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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id z19sm2369237wma.0.2021.09.11.09.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SlXQUNKS3c3ZKazmS/+w3RMtDhurrxUzxhSxeew26+k=; b=FbiVsXj3FAZx5ZjncQN9iEIfsVeLqeBuwOPoqI6UQ63fHO+/83LFAhS7XD3vY+Brzw Yqa0kWbTn545ks2TCE47BkEDx+3Kb3sVS4u/F6e4iZmu8Ez8h10W5Mjf3bx73dKDyhhm 16mWBuKeqNAFz6UCKmRBTDjjXYq/eQZ3PJX19S45DSQp71m218kuT3pdHVZvWGc7eGV/ XMUB9V5ujtfiBgDPgioFwIavDkZEFJ+wYRTvVKGk8YlZhslcngjh8YRqSq7gyZd/fo76 Wno12siEhYPLD3bpDAtPs9FlhcO9kGC926wkUbeUXViecJeJDvKLH+pevpAokEF5F04u z+Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SlXQUNKS3c3ZKazmS/+w3RMtDhurrxUzxhSxeew26+k=; b=6yz32BTE0nLkN+wPhmDplS+0Mtkc12QKUOelxupe4Jm/fKDxSF3UTHMuWOWJ9ghgkj VTdnULx/9gUzrbP9uUD3UTQb1Mr3zdBkAndkv/9ktjS4fwnun/uwk3lo+JG46b58XJCx BJWACPwcmL+GaMbxhH3kH+jwdU6jVhnDXi3Kme3pvmq1GInfW9dBbXOdChkwI1/Hrvpb IGaaO94zNdSHmu4jGIi7ka5u99JCQpp2jSU0vysPbj3ptYUZbCGVJG1qSDmfoQMZboij HkNw8bp74RYa2H+zlzLpCyIHiiacUf7gg1xBICP0YvjFOa5W89xsSNxfdrRzZPkMfzmZ OqAA== X-Gm-Message-State: AOAM532Gyq7DtWzc+O1dSdwhRxnHqA5e6Tc5X4nlnkxkJzhcOCjUl6LZ EPhNV58Ruw0I4hSsCMVsd44= X-Google-Smtp-Source: ABdhPJxK+oCZiehRlNPyQF2hLSkfA1CxPBnch9PQF5ryk0EIJOTHvHhl0uHXcZyP//yh8kc+sLuN2g== X-Received: by 2002:a5d:48c5:: with SMTP id p5mr3745013wrs.303.1631379355868; Sat, 11 Sep 2021 09:55:55 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH v3 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:26 +0200 Message-Id: <20210911165434.531552-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379358424100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/cpu.h | 5 +++-- target/openrisc/cpu.c | 2 +- target/openrisc/interrupt.c | 2 -- target/openrisc/meson.build | 6 ++++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..be6df81a810 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -312,8 +312,6 @@ struct OpenRISCCPU { =20 =20 void cpu_openrisc_list(void); -void openrisc_cpu_do_interrupt(CPUState *cpu); -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; =20 +void openrisc_cpu_do_interrupt(CPUState *cpu); +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index bd34e429ecb..27cb04152f9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, - .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3eab771dcda..19223e3f25b 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -28,7 +28,6 @@ =20 void openrisc_cpu_do_interrupt(CPUState *cs) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); CPUOpenRISCState *env =3D &cpu->env; int exception =3D cs->exception_index; @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } -#endif =20 cs->exception_index =3D -1; } diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index 9774a583065..e445dec4a00 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -9,7 +9,6 @@ 'exception_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'interrupt.c', 'interrupt_helper.c', 'mmu.c', 'sys_helper.c', @@ -17,7 +16,10 @@ )) =20 openrisc_softmmu_ss =3D ss.source_set() -openrisc_softmmu_ss.add(files('machine.c')) +openrisc_softmmu_ss.add(files( + 'interrupt.c', + 'machine.c', +)) =20 target_arch +=3D {'openrisc': openrisc_ss} target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} --=20 2.31.1