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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id s14sm1912541wmc.25.2021.09.11.09.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KmrmQJKuuxtvSWhjZHiSYnfiuVq11gAlW4sC8tAjXUk=; b=NAxzEVkDy77sPBxEMuLmND+N75WXUMp66ryBeqNrWMnnPhMOFSD7noSrN+cUwgdQMb wC+VMcgru4KhuIm3IfzuZ1ACwyoi2aF7m4ZqM9d3oWSSaypwBgM8b+u69F6lal0oA0+w AWqZ8A3QUof+B2613/IRqlghg12h5ybXoCQ3y0EMre/cLBnc8wuwrqDHGf29iWmhbgNW O4LJaoSvUYyXu5oKKjmXcfrHVjkWoyJ5sdLIDVtrKfUTNS96XvWF1x5C0tf/jXzp56/g q8yohhrt9fs7KIYY7n+8486BsFFP3WNfrweENNiH9SJ20tRLtBWFRelnn316xqbYN2Ds x8kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KmrmQJKuuxtvSWhjZHiSYnfiuVq11gAlW4sC8tAjXUk=; b=qhMgTLCgK8TWV8w8oFCoE2PYwVqlwUFdI40v3KjfomGlDp7ULMAlKDhfECiB47gytv fxtekVQ1WvG2DRmqtAdfUfYKNZi8Ogj5gBFPVf0yB9xvYwocj+NNp+JfIuTZzZzySvpm zbpO77kt9/kJbzEucfB+u/pXq1FSrnGyLFi7q+mH6KHISRiH0BJx52itSMxYbwMwuSmd d/rYyTo+bGh8P9Rl8i7mmXT2tCYbK4EIWrFm5Dut1sLSpfGq6ugw9NN0nlwkQHqKKN1e O6c6i4TP2LMIT0orByQWfxfcZAu6wUCJB/8vXGFrBJdSWrxeXv+xAiIQaVIPVHwalNB+ QYPQ== X-Gm-Message-State: AOAM5333C29Ys/PXWJDHM7eo7JEl9hICMrHCp9tMumW4DMuUrc3nJNa1 BNNsKylsolQ2fjWcf3ex30Y= X-Google-Smtp-Source: ABdhPJz+JC5O2lLLbpJobtASucneZLg/TgPVXZlhkb7xv67RcBYks6QuSh82sPN89d7R84Gx3gRoUw== X-Received: by 2002:adf:c501:: with SMTP id q1mr3846189wrf.150.1631379331059; Sat, 11 Sep 2021 09:55:31 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Warner Losh Subject: [PATCH v3 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Date: Sat, 11 Sep 2021 18:54:21 +0200 Message-Id: <20210911165434.531552-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1631379333218100001 Following the logic of commit 30493a030ff ("i386: split seg_helper into user-only and sysemu parts"), move x86_cpu_exec_interrupt() under sysemu/seg_helper.c. Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/tcg/seg_helper.c | 64 ---------------------------- target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 64 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 13c6e6ee62e..baa905a0cd6 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int = intno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 -#ifndef CONFIG_USER_ONLY -bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int intno; - - interrupt_request =3D x86_cpu_pending_interrupt(cs, interrupt_request); - if (!interrupt_request) { - return false; - } - - /* Don't process multiple interrupt requests in a single call. - * This is required to make icount-driven execution deterministic. - */ - switch (interrupt_request) { - case CPU_INTERRUPT_POLL: - cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; - apic_poll_irq(cpu->apic_state); - break; - case CPU_INTERRUPT_SIPI: - do_cpu_sipi(cpu); - break; - case CPU_INTERRUPT_SMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; - do_smm_enter(cpu); - break; - case CPU_INTERRUPT_NMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; - env->hflags2 |=3D HF2_NMI_MASK; - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); - break; - case CPU_INTERRUPT_MCE: - cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); - break; - case CPU_INTERRUPT_HARD: - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); - cs->interrupt_request &=3D ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); - intno =3D cpu_get_pic_interrupt(env); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing hardware INT=3D0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - break; - case CPU_INTERRUPT_VIRQ: - /* FIXME: this should respect TPR */ - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); - intno =3D x86_ldl_phys(cs, env->vm_vmcb - + offsetof(struct vmcb, control.int_vector)); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing virtual hardware INT=3D0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; - break; - } - - /* Ensure that no TB jump will be modified as the program flow was cha= nged. */ - return true; -} -#endif /* CONFIG_USER_ONLY */ - void helper_lldt(CPUX86State *env, int selector) { SegmentCache *dt; diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/s= eg_helper.c index 82c0856c417..b425b930f9d 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -125,6 +125,71 @@ void x86_cpu_do_interrupt(CPUState *cs) } } =20 +bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int intno; + + interrupt_request =3D x86_cpu_pending_interrupt(cs, interrupt_request); + if (!interrupt_request) { + return false; + } + + /* + * Don't process multiple interrupt requests in a single call. + * This is required to make icount-driven execution deterministic. + */ + switch (interrupt_request) { + case CPU_INTERRUPT_POLL: + cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + apic_poll_irq(cpu->apic_state); + break; + case CPU_INTERRUPT_SIPI: + do_cpu_sipi(cpu); + break; + case CPU_INTERRUPT_SMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); + cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + do_smm_enter(cpu); + break; + case CPU_INTERRUPT_NMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); + cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + env->hflags2 |=3D HF2_NMI_MASK; + do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); + break; + case CPU_INTERRUPT_MCE: + cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; + do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); + break; + case CPU_INTERRUPT_HARD: + cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); + cs->interrupt_request &=3D ~(CPU_INTERRUPT_HARD | + CPU_INTERRUPT_VIRQ); + intno =3D cpu_get_pic_interrupt(env); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing hardware INT=3D0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + break; + case CPU_INTERRUPT_VIRQ: + /* FIXME: this should respect TPR */ + cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); + intno =3D x86_ldl_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, control.int_vector)); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing virtual hardware INT=3D0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; + break; + } + + /* + * Ensure that no TB jump will be modified as the program flow was cha= nged. + */ + return true; +} + /* check if Port I/O is allowed in TSS */ void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) { --=20 2.31.1