From nobody Tue Feb 10 20:09:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219912822428.4212018911263; Thu, 9 Sep 2021 13:38:32 -0700 (PDT) Received: from localhost ([::1]:60536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQoZ-0001iU-HP for importer@patchew.org; Thu, 09 Sep 2021 16:38:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdb-0007Qf-Ep; Thu, 09 Sep 2021 16:27:14 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:38860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdX-0000Qk-WE; Thu, 09 Sep 2021 16:27:11 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 10 Sep 2021 04:26:52 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 13:03:26 -0700 Received: from unknown (HELO hulk.wdc.com) ([10.225.167.73]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Sep 2021 13:26:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631219227; x=1662755227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yTfoB+9JP9qQfT0r1fE8CrNRPuCwx/KG8+8TZYb44Po=; b=NvLl4rDLccR/9gWFnqujPtWAuHpzQpcybMvFRBdtnxw4wq1wXnZRLcEK 44j74Sjqo3kU6cZoS6tFWgG+VdHPht6zQ522OWVEd4g/nzXUjSV9yDJ0g 5yPgo4uWYd5DUlj+9lTqCpBB7r4ndEYto7AOLYGfqjDJsV9dldeuwmkAq qP5vCmSYrPShEwdQQUkVTxo/Zdk6bE8zeJ2kib8hGTyY2cVmMBlp8sjSO 9bJ0Ht3MThWaYOMNPYWJ1xR0ib52nu0XJKD7AXcHtTOs1GSRFyth8bGa+ N/D4gJXdjLvy465o03BswbJ6FuTZmGOoHNmmx81L7SznNDtvvs1JraF6b Q==; X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="178710307" IronPort-SDR: OxqFsXOxI4c211fxeObOBMsGaBCjE8zuZCBKfB8Fv9JYhMP4zIiLodASOZH7euaMtWMTPFJmie LBKivztjVZJGPCC+dcvadZPcriJvNGvXF01FVDT8b3kIT2kI3TnEQoyEgnLRUSlZlttBWYN7tf Cm2EThKY9jaKFVdLJfVeHG2WMj1Uib1haIcxKwGUF8AhCuQ2CncvsFVHPQi97vxU9OO7dkJH0e 8RdQuPJPU+xqXjYB2JIYtahvd+R3ULdi7qvGBR3QF3X9nThNyIxSK4Fy5s+NcREqmyV5TFFHOb 2cbzyUwif1TBAc/qtgTMrQ/m IronPort-SDR: 5HjpyaM2mkwvL2t/VWczRsNVPc9VXKhlrGQ26xf8vklh50jezxAw8fnyW9UKGgEINOdu+q3dDe Be7mK1oE1hC2SDlDc8Rwy0bl1e2QgwUJvYj3RAdRiMufw1Tq/xEKPuzGEis4myW97QKS8uiZ5m SeSR15S7L+LVjFFDRLHuzAwd0exCpUL0M3cXvxH8XOJ9hlF2GITJDucLp3IJ+7W2IgWwyAg8rD cgl/rUqUNTNy8SBH5DY3Fycs1Xp96eszarN/HwMEIQqkx0DZgNiHmzriOxDZCMMA6zTOXFSccM tWw= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation Date: Thu, 9 Sep 2021 13:26:36 -0700 Message-Id: <20210909202639.1230170-7-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219913828100001 Content-Type: text/plain; charset="utf-8" mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 24 +++++-- target/riscv/csr.c | 144 ++++++++++++++++++++++++++------------- target/riscv/machine.c | 26 ++++++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 +++++++++ target/riscv/pmu.h | 28 ++++++++ 6 files changed, 200 insertions(+), 55 deletions(-) create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd1c6425ac9e..179c587d8634 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 -#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 =20 FIELD(VTYPE, VLMUL, 0, 2) @@ -114,6 +114,19 @@ FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 +typedef struct PMUCTRState PMUCTRState; +struct PMUCTRState { + /* Current value of a counter */ + target_ulong mhpmcounter_val; + /* Current value of a counter in RV32*/ + target_ulong mhpmcounterh_val; + /* Snapshot values of counter */ + target_ulong mhpmcounter_prev; + /* Snapshort value of a counter in RV32 */ + target_ulong mhpmcounterh_prev; + bool started; +}; + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ @@ -224,13 +237,10 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 - /* PMU counter configured values */ - target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; - - /* for RV32 */ - target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + /* PMU counter state */ + PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values */ + /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 27614408e52a..7e3d4c6e0a10 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 @@ -423,41 +424,33 @@ static RISCVException write_vstart(CPURISCVState *env= , int csrno, } =20 /* User Timers and Counters */ -static RISCVException read_instret(CPURISCVState *env, int csrno, - target_ulong *val) +static target_ulong get_icount_ticks(bool brv32) { + int64_t val; + target_ulong result; + #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - *val =3D icount_get(); + val =3D icount_get(); } else { - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); } #else - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); #endif =20 - return RISCV_EXCP_NONE; -} - -static RISCVException read_instreth(CPURISCVState *env, int csrno, - target_ulong *val) -{ -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - *val =3D icount_get() >> 32; + if (brv32) { + result =3D val >> 32; } else { - *val =3D cpu_get_host_ticks() >> 32; + result =3D val; } -#else - *val =3D cpu_get_host_ticks() >> 32; -#endif =20 - return RISCV_EXCP_NONE; + return result; } =20 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 *val =3D env->mhpmevent_val[evt_index]; =20 @@ -466,7 +459,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno= , target_ulong *val) =20 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 env->mhpmevent_val[evt_index] =3D val; =20 @@ -475,52 +468,99 @@ static int write_mhpmevent(CPURISCVState *env, int cs= rno, target_ulong val) =20 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + int ctr_idx =3D csrno - CSR_MCYCLE; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 - env->mhpmcounter_val[ctr_index] =3D val; + counter->mhpmcounter_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounter_prev =3D get_icount_ticks(false); + } else { + /* Other counters can keep incrementing from the given value */ + counter->mhpmcounter_prev =3D val; + } =20 - return RISCV_EXCP_NONE; + return RISCV_EXCP_NONE; } =20 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + int ctr_idx =3D csrno - CSR_MCYCLEH; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + counter->mhpmcounterh_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounterh_prev =3D get_icount_ticks(false); + } else { + counter->mhpmcounterh_prev =3D val; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, + bool is_uh, uint32_t ctr_idx) +{ + PMUCTRState counter =3D env->pmu_ctrs[ctr_idx]; + target_ulong ctr_prev =3D is_uh ? counter.mhpmcounterh_prev : + counter.mhpmcounter_prev; + target_ulong ctr_val =3D is_uh ? counter.mhpmcounterh_val : + counter.mhpmcounter_val; =20 - env->mhpmcounterh_val[ctr_index] =3D val; + if (get_field(env->mcountinhibit, BIT(ctr_idx))) { + /** + * Counter should not increment if inhibit bit is set. We can't re= ally + * stop the icount counting. Just return the previous value to ind= icate + * that counter was not incremented. + */ + if (!counter.started) { + *val =3D ctr_val; + return RISCV_EXCP_NONE; + } else { + /* Mark that the counter has been stopped */ + counter.started =3D false; + } + } + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + *val =3D get_icount_ticks(is_uh); + } else { + *val =3D ctr_val; + } + + /* No need to handle the overflow here */ + *val =3D *val - ctr_prev + ctr_val; =20 return RISCV_EXCP_NONE; } =20 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_MCYCLE; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_CYCLE; } - *val =3D env->mhpmcounter_val[ctr_index]; =20 - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, false, ctr_index); } =20 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_MCYCLEH; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_CYCLEH; } =20 - *val =3D env->mhpmcounterh_val[ctr_index]; - - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 - #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -857,11 +897,23 @@ static RISCVException read_mcountinhibit(CPURISCVStat= e *env, int csrno, static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong val) { + int cidx; + PMUCTRState *counter; + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -RISCV_EXCP_ILLEGAL_INST; } =20 env->mcountinhibit =3D val; + + /* Check if any other counter is also monitoring cycles/instructions */ + for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { + if (!get_field(env->mcountinhibit, BIT(cidx))) { + counter =3D &env->pmu_ctrs[cidx]; + counter->started =3D true; + } + } + return RISCV_EXCP_NONE; } =20 @@ -1709,10 +1761,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VL] =3D { "vl", vs, read_vl }, [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, - [CSR_INSTRET] =3D { "instret", ctr, read_instret }, - [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, - [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, + [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, + [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_hpmcounterh }, + [CSR_INSTRETH] =3D { "instreth", ctr32, read_hpmcounterh }, =20 /* * In privileged mode, the monitor will have to emulate TIME CSRs only= if @@ -1723,10 +1775,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, - [CSR_MINSTRET] =3D { "minstret", any, read_instret }, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a2b32064b07a..e0a489c20e67 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,13 @@ static bool vector_needed(void *opaque) return riscv_has_ext(env, RVV); } =20 +static bool pmu_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_pmu; +} + static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", .version_id =3D 1, @@ -138,6 +145,21 @@ static const VMStateDescription vmstate_hyper =3D { } }; =20 +static const VMStateDescription vmstate_pmu_ctr_state =3D { + .name =3D "cpu/pmu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmu_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_BOOL(started, PMUCTRState), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -178,8 +200,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), - VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, + vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea9c..992122c4d6f5 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,6 +24,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'pmu.c', 'monitor.c', 'machine.c' )) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c new file mode 100644 index 000000000000..000fe8da45ef --- /dev/null +++ b/target/riscv/pmu.c @@ -0,0 +1,32 @@ +/* + * RISC-V PMU file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "pmu.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr) +{ + return (target_ctr =3D=3D 0) ? true : false; +} + +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) +{ + return (target_ctr =3D=3D 2) ? true : false; +} diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h new file mode 100644 index 000000000000..58a5bc3a4089 --- /dev/null +++ b/target/riscv/pmu.h @@ -0,0 +1,28 @@ +/* + * RISC-V PMU header file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr); +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, + uint32_t target_ctr); --=20 2.31.1