From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219327691945.8716289330209; Thu, 9 Sep 2021 13:28:47 -0700 (PDT) Received: from localhost ([::1]:35046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQf8-0001Ti-0d for importer@patchew.org; Thu, 09 Sep 2021 16:28:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdP-0007Fy-0I; Thu, 09 Sep 2021 16:26:59 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:38860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdM-0000Qk-QP; Thu, 09 Sep 2021 16:26:58 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 10 Sep 2021 04:26:51 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 13:03:25 -0700 Received: from unknown (HELO hulk.wdc.com) ([10.225.167.73]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Sep 2021 13:26:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631219216; x=1662755216; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OUpxuQwgM63cpijDUX+aSzm40706iupwmIz2OuxTpCc=; b=lQatOevammF9/nB9c+oiEed7EZjda9exLdIk2LJPKWOUMl/7ei3DNMFy KmUSahtOJ/BidCozgASBcbrk+NB2vqRyKEZhFx5jBqmISYCjHJFMvB0lc D/+jv6jxUP7vJJOpxPTfoIMV1dFcM7JflorENFoK/w8Fe0bQUVmR6A8J1 +FA10qqwfUlqx87EDGMKwrgwDpjrb/cvgO82pZlfZsXhY1R3Q3xkwzWH5 UKxcfJpLD4VKQi6e+KKTKllbUjFA69wGPQ1tDYtgWGLWQj0MMAnAw/Sgs R1vHe/ptnTUGjwmRTllUJLmyrS6yP3PAWC1h9zaGRniPcrS+qzsTS6+d7 Q==; X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="178710290" IronPort-SDR: WgGzA9hl5CZxZw8ijrM73oMSgBEujkjUuRJ2WRswR2FN895xFsSO45v1SwkTFlA2WBFDOoET9B Ou25D8EI0S5PRBrPpZp7p9YxF8ke/Mvv/xzyaC3JvBAptGc6UyVdPKYgJD1daN/UXbsES3ziHc C4h3bPsWoEELd1x6wjknew5fVw2/Anlu42M987e7JpZNWLNa6yM5bTV+cFqHMAppBxAB23Vzdh bFTOV6i2mCLfwpBiwgulOxd6iPOWBYuq4rfM/hJu06K/X6Dwr+bZIyQGuLUtCOVOo71G1LlVaF yg5ygE9iSqxurwUdydFsfME8 IronPort-SDR: ebjzbzG2gJL7pZdtHd9V3hbd0Y4dgRRpwLNdVY6mvql/uZXkabMr8zl6vioZJY6nDyc8FmE956 /vGi8Awbpv/XKe+PDV5bQ+iQ861ih3WDynjiaYMezcI7HOp0Q4eQJVX3xOpxra86AgmF3NOnj/ fFW+TEyQa9OFiSpuzq83ypZ2dg4h68W+9AFiZe0ORSmLytt5aFZ2fKW7RUQhenDNo3Qyo9vTk9 Lo4Em2Chk3xjSzJ1IaTb1ugqpBbT3buNjBpDgHMNPambZmtjyiu0UQp7H6ZR13aAnzRK7snvxc JVk= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function Date: Thu, 9 Sep 2021 13:26:31 -0700 Message-Id: <20210909202639.1230170-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219328236100001 Content-Type: text/plain; charset="utf-8" Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. Ideally, they should check the mcountern bits before cycle/minstret/hpmcounterx access. The predicate function also calculates the counter index incorrectly for hpmcounterx. Signed-off-by: Atish Patra --- target/riscv/csr.c | 62 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9a4ed18ac597..0515d851b948 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } =20 + if (env->priv =3D=3D PRV_S) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->mcounteren, HCOUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIME: + if (!get_field(env->mcounteren, HCOUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRET: + if (!get_field(env->mcounteren, HCOUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + if (riscv_cpu_is_32bit(env)) { + switch (csrno) { + case CSR_CYCLEH: + if (!get_field(env->mcounteren, HCOUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIMEH: + if (!get_field(env->mcounteren, HCOUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRETH: + if (!get_field(env->mcounteren, HCOUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + } + } + if (riscv_cpu_virt_enabled(env)) { switch (csrno) { case CSR_CYCLE: @@ -89,8 +141,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; @@ -116,8 +169,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNT= ER3H)) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTE= R3H))) { + ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219328711332.0146815845843; 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09 Sep 2021 13:26:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631219219; x=1662755219; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KlVm9ArR4IJetr50BN064+0SmCXOWsrWRCRAaqdEjFA=; b=RJ0yG5WVBfwlhCi0zd5OwJ3u7h+gKLY6zpKX3hHV8t4gcUNnSRD577w6 rms+7ggqtz+WXa8/2LL0GylqHoHMnCB90t2A4QA3yAtie+pd0sdq6ucOS FnsO0M6RvntvbbVa+VRFl0L7F9OPxS/V6CMG+nAPk4kmG6GlDYcdwVIpe HaWBTsLp8GWNxsJTl7l+/qjbk7ajwFx/k7iOTOP4FD0mFIIHNSk6gh1ix uea2hRk7UnYQUHAVXSxTufaxCdsCw+a7coc7ftmRdTjxy/UxSDhQq0J5V gRpWuBQezGGa6TBiIEu6KsyMrzqPxwkYxUgYvjz8pWgXGC0QbKFowMYaR w==; X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="178710295" IronPort-SDR: EiQPClv4bbG0LppVZ7dCUxaPZD+PkpbyJ02T7QPlIc6IGqfLgHYlWLoASWLFq7VJ6/KmaRXNBj WYWYl/4Z4KaxJDtiyALzrNNh49OzdHWJBvP0ius2P/6nIVBxD02RQM/PwvEr2bm04OiGKbgM57 tFDEoCccEJe2DGknixqsuPh3IGy15S2TsCo0WCBBlBBcmLvH8E5F7rnz/Rp76rZcrc6giI5vvW 2mgrlH1kdg38i8w1x4BmnjL79LWRURqNNAfU9uV+W7n3T3c0os938XAzCzVB2dw3sxqtCVCXAI zZaubtvOyrdxAUVDXfMnczdo IronPort-SDR: EvX5IFeQwuz66jqqGJiykoXzZ9WeP4TzcZjMxExBRCVklKudfK4/Zbkmw+KqfiGiRTuuo7dAhi Tk14TmZSC6UHPs/uPiGEk8HnC2wFKj3Rfhk5SCkbHd5hT5KYdpyW3OkgyxBOaHEFWELoarKEoP wLQaSiqpnsize89/YsxFQOsA2crU21uWeXXzrGdqvCfgkl4wq+3PRq6ny/RmVrHlbg2T36fntx CaD/0xocZ7LUe9VTuT+cI4smHdlPbtkEFMJSWyd9uBimzM9teT5teKXh9DAFjVArv2zJHNFVaY MbU= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu Date: Thu, 9 Sep 2021 13:26:32 -0700 Message-Id: <20210909202639.1230170-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219330057100003 Content-Type: text/plain; charset="utf-8" The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM architecture as well. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb7604f..7a486450ebc6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,7 +587,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00b8..5e67003e58a3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,7 +293,7 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; - bool ext_counters; + bool ext_pmu; bool ext_ifencei; bool ext_icsr; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0515d851b948..c3ce7d83a6b2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; =20 - if (!cpu->cfg.ext_counters) { + if (!cpu->cfg.ext_pmu) { /* The Counters extensions is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219524152215.28879311786739; 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09 Sep 2021 13:26:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631219221; x=1662755221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JALfc7yTud5jrpLgmge3WaiVZ/AdoqGrtD4FSaDRcPU=; b=J77b9tfz1cYhpP46CfVqOGd3CJC+b89PsMfge0h4eG9gbIDE+xjLmY+1 nYpDepreuVN8KYgT91nPpc3tBOJnalrLSBa4g6/hybtmdNorA0ZJ8/+/j 6t3z4YUjdTtxXL8vHG4KHoBaAJCP4wgsRsjS1FubZKGHz0kMUeZrv4Jfq Z8yh8NQFnPgsy9wFzcgb8NksVWZkyCg2ckpGlvR1bF0me0frj7Nw2avJu zi70KC7YgAErS+BO+uZSBlP2Pmm6hxcSiBZgrtZr1zoEpsCwP4EP+xSgo JkdSO0sQIkic0KJEG4D2lgoV03HQ0p1MXyicZyM/ZqsdmdVR8VYEF+v9D Q==; X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="178710297" IronPort-SDR: nQU/UuXv0eL9KEkbU7I2w4UuvZgklSBlAdqTHNcv9UqOR8fegcSQu+AK6zZjuZs4qJxPLQIj/j C7bruCEoFBY7k9AqdrNqN5CCj0UA+yJXV8mOzVCDJO0r5Ub/7ryGaUUnI2jeZbCvE1E3x7bw/y WlbqmIj3bX+J+j9WmJyNueLnTONpOODqH+d/N0Bma2fm62yddn/cIJEsTwepIGDCCI/eQq3yk0 sSApA2/WgtR34Teu1uY9lDcibbKS+1ntPqzXmIMqwzIinX+RM36316sFqhWQ/JgD3wNIxBXmoY 4M+7idbkDPPqQeYpTcpngqju IronPort-SDR: 7TdEC/C+ZXj6HtMu8RY7yDrD4whfzzb/v5FS3yfYf8uVZX7FGwTDrOJqc8wWLtrh1nTwTWpvWw +MyY0PCRCfmepEWkGcKZe8DQOWxUpJflQCgCq78Q/DcOGxGyglITpb65oDOXO385k4rzJkVt7X FRCrEF5kaanOH3dGw8HpbFAJDDMurAno1xdvs9UoIbhgAFQIlcetRy/ro35fE4txA0rIkc1epV dkvcM732CBmPrQ/iaNqeudYCtE+AiEqEgVBjgIbnbQyWGX7MKlTwIe91O4hpeVs02RdNsllhBa B2U= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable Date: Thu, 9 Sep 2021 13:26:33 -0700 Message-Id: <20210909202639.1230170-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219526192100001 Content-Type: text/plain; charset="utf-8" The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the Qemu implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++---------------- 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7a486450ebc6..eba6050324a0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,7 +587,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), + DEFINE_PROP_UINT16("pmu", RISCVCPU, cfg.ext_pmu, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5e67003e58a3..0e2e88f3bbea 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,9 +293,9 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; - bool ext_pmu; bool ext_ifencei; bool ext_icsr; + uint16_t ext_pmu; =20 char *priv_spec; char *user_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c3ce7d83a6b2..fa014bac72ab 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -57,15 +57,45 @@ static RISCVException vs(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static RISCVException mctr(CPURISCVState *env, int csrno) +{ +#if !defined(CONFIG_USER_ONLY) + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; + int base_csrno =3D CSR_MHPMCOUNTER3; + + if (riscv_cpu_is_32bit(env) && csrno >=3D CSR_MCYCLEH) { + /* Offset for RV32 hpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; + if (!cpu->cfg.ext_pmu || ctr_index > cpu->cfg.ext_pmu) { + /* The Counters extensions is not enabled or out of range*/ + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +#endif +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + int base_csrno =3D CSR_CYCLE; + bool brv32 =3D riscv_cpu_is_32bit(env); + + if (brv32 && csrno >=3D CSR_CYCLEH) { + /* Offset for RV32 hpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.ext_pmu) { - /* The Counters extensions is not enabled */ + if (!cpu->cfg.ext_pmu || ctr_index > (cpu->cfg.ext_pmu + 3)) { + /* The Counters extensions is not enabled or out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -93,7 +123,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (brv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->mcounteren, HCOUNTEREN_CY)) { @@ -148,7 +178,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (brv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, HCOUNTEREN_CY) && @@ -1721,35 +1751,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, =20 - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219457749237.48508601239598; Thu, 9 Sep 2021 13:30:57 -0700 (PDT) Received: from localhost ([::1]:41916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQhE-00060s-Gb for importer@patchew.org; Thu, 09 Sep 2021 16:30:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46520) by lists.gnu.org with esmtps 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+PG0fEBA8wwRHj0RZzYFBmZQulYESvbGdswVKbUFYfu2ho30hMfNiw5JkbBhFphUVddplc0tQ8 IkllhD06KL7IfkphkI3NBLyn90TIp2YybD1T7tJgSFF/OCSJCIi1Wco+B5l9aAOYhQ3GHcwkyt psk= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR Date: Thu, 9 Sep 2021 13:26:34 -0700 Message-Id: <20210909202639.1230170-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219459550100001 Content-Type: text/plain; charset="utf-8" As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/csr.c | 25 +++++++++++++++++++++++++ target/riscv/machine.c | 5 +++-- 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0e2e88f3bbea..bdb488cdbccc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -219,6 +219,8 @@ struct CPURISCVState { target_ulong scounteren; target_ulong mcounteren; =20 + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7330ff5a194c..ac519dcdc4df 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -275,6 +275,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fa014bac72ab..a155a4370d6b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -766,6 +766,28 @@ static RISCVException write_mtvec(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D env->mcountinhibit; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return -RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit =3D val; + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1781,6 +1803,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibi", any, read_mcountinhibi= t, + write_mcountinhibit= }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302daff..20dea0843604 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -177,6 +177,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219686357720.1001024340829; Thu, 9 Sep 2021 13:34:46 -0700 (PDT) Received: from localhost ([::1]:49858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQkv-0002x1-9z for importer@patchew.org; Thu, 09 Sep 2021 16:34:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQda-0007QR-V0; Thu, 09 Sep 2021 16:27:14 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:38857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdX-0000PU-52; Thu, 09 Sep 2021 16:27:10 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219687545100001 Content-Type: text/plain; charset="utf-8" With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 12 ++ target/riscv/csr.c | 468 ++++++++++++++++++++++++++++------------- target/riscv/machine.c | 3 + 3 files changed, 331 insertions(+), 152 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bdb488cdbccc..bd1c6425ac9e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,6 +105,9 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 +#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMCOUNTERS 32 + FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) @@ -221,6 +224,15 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 + /* PMU counter configured values */ + target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; + + /* for RV32 */ + target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + + /* PMU event selector configured values */ + target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a155a4370d6b..27614408e52a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -79,6 +79,15 @@ static RISCVException mctr(CPURISCVState *env, int csrno) #endif } =20 +static RISCVException mctr32(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_is_32bit(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return mctr(env, csrno); +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -426,6 +435,7 @@ static RISCVException read_instret(CPURISCVState *env, = int csrno, #else *val =3D cpu_get_host_ticks(); #endif + return RISCV_EXCP_NONE; } =20 @@ -441,9 +451,76 @@ static RISCVException read_instreth(CPURISCVState *env= , int csrno, #else *val =3D cpu_get_host_ticks() >> 32; #endif + + return RISCV_EXCP_NONE; +} + +static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + *val =3D env->mhpmevent_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3; + + env->mhpmevent_val[evt_index] =3D val; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + + env->mhpmcounter_val[ctr_index] =3D val; + return RISCV_EXCP_NONE; } =20 +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +{ + int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + + env->mhpmcounterh_val[ctr_index] =3D val; + + return RISCV_EXCP_NONE; +} + +static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + } + *val =3D env->mhpmcounter_val[ctr_index]; + + return RISCV_EXCP_NONE; +} + +static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + int ctr_index; + + if (env->priv =3D=3D PRV_M) { + ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + } else { + ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + } + + *val =3D env->mhpmcounterh_val[ctr_index]; + + return RISCV_EXCP_NONE; +} + + #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -1743,157 +1820,244 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 /* Performance Counters */ - [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_zero }, - [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_zero }, - [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_zero }, - [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_zero }, - [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_zero }, - [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_zero }, - [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_zero }, - [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_zero }, - [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_zero }, - [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_zero }, - [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_zero }, - [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_zero }, - [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_zero }, - [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_zero }, - [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_zero }, - [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_zero }, - [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_zero }, - [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_zero }, - [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_zero }, - [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_zero }, - [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_zero }, - [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_zero }, - [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_zero }, - [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_zero }, - [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_zero }, - [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_zero }, - [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_zero }, - [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, - [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, - - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, - - [CSR_MCOUNTINHIBIT] =3D { "mcountinhibi", any, read_mcountinhibi= t, - write_mcountinhibit= }, - - [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, - [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, - [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, - [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_zero }, - [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_zero }, - [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_zero }, - [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_zero }, - [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_zero }, - [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_zero }, - [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_zero }, - [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_zero }, - [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_zero }, - [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_zero }, - [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_zero }, - [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_zero }, - [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_zero }, - [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_zero }, - [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_zero }, - [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_zero }, - [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_zero }, - [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_zero }, - [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_zero }, - [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_zero }, - [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_zero }, - [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_zero }, - [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_zero }, - [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_zero }, - [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_zero }, - [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_zero }, - - [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_zero }, - [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_zero }, - [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_zero }, - [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_zero }, - [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_zero }, - [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_zero }, - [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_zero }, - [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_zero }, - [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_zero }, - [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_zero }, - [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_zero }, - [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_zero }, - [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_zero }, - [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_zero }, - [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_zero }, - [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_zero }, - [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_zero }, - [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_zero }, - [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_zero }, - [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_zero }, - [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_zero }, - [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_zero }, - [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_zero }, - [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_zero }, - [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_zero }, - [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_zero }, - [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_zero }, - [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_zero }, - [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_zero }, - - [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", any32, read_zero }, - [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", any32, read_zero }, - [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", any32, read_zero }, - [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", any32, read_zero }, - [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", any32, read_zero }, - [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", any32, read_zero }, - [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", any32, read_zero }, - [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", any32, read_zero }, - [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", any32, read_zero }, - [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", any32, read_zero }, - [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", any32, read_zero }, - [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", any32, read_zero }, - [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", any32, read_zero }, - [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", any32, read_zero }, - [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", any32, read_zero }, - [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", any32, read_zero }, - [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", any32, read_zero }, - [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", any32, read_zero }, - [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", any32, read_zero }, - [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", any32, read_zero }, - [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", any32, read_zero }, - [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", any32, read_zero }, - [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", any32, read_zero }, - [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", any32, read_zero }, - [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", any32, read_zero }, - [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", any32, read_zero }, - [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, - [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, - [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, + [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_hpmcounter }, + [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_hpmcounter }, + + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_hpmcounter, + write_mhpmcounter }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_hpmcounter, + write_mhpmcounter }, + + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhibit, + write_mcountinhibit }, + + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_mhpmevent, + write_mhpmevent }, + [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, + write_mhpmevent }, + + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_hpmcounterh = }, + [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_hpmcounterh = }, + + [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, + [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, + write_mhpmcounterh = }, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 20dea0843604..a2b32064b07a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,6 +178,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="178710307" IronPort-SDR: OxqFsXOxI4c211fxeObOBMsGaBCjE8zuZCBKfB8Fv9JYhMP4zIiLodASOZH7euaMtWMTPFJmie LBKivztjVZJGPCC+dcvadZPcriJvNGvXF01FVDT8b3kIT2kI3TnEQoyEgnLRUSlZlttBWYN7tf Cm2EThKY9jaKFVdLJfVeHG2WMj1Uib1haIcxKwGUF8AhCuQ2CncvsFVHPQi97vxU9OO7dkJH0e 8RdQuPJPU+xqXjYB2JIYtahvd+R3ULdi7qvGBR3QF3X9nThNyIxSK4Fy5s+NcREqmyV5TFFHOb 2cbzyUwif1TBAc/qtgTMrQ/m IronPort-SDR: 5HjpyaM2mkwvL2t/VWczRsNVPc9VXKhlrGQ26xf8vklh50jezxAw8fnyW9UKGgEINOdu+q3dDe Be7mK1oE1hC2SDlDc8Rwy0bl1e2QgwUJvYj3RAdRiMufw1Tq/xEKPuzGEis4myW97QKS8uiZ5m SeSR15S7L+LVjFFDRLHuzAwd0exCpUL0M3cXvxH8XOJ9hlF2GITJDucLp3IJ+7W2IgWwyAg8rD cgl/rUqUNTNy8SBH5DY3Fycs1Xp96eszarN/HwMEIQqkx0DZgNiHmzriOxDZCMMA6zTOXFSccM tWw= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation Date: Thu, 9 Sep 2021 13:26:36 -0700 Message-Id: <20210909202639.1230170-7-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219913828100001 Content-Type: text/plain; charset="utf-8" mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 24 +++++-- target/riscv/csr.c | 144 ++++++++++++++++++++++++++------------- target/riscv/machine.c | 26 ++++++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 +++++++++ target/riscv/pmu.h | 28 ++++++++ 6 files changed, 200 insertions(+), 55 deletions(-) create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd1c6425ac9e..179c587d8634 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 -#define RV_MAX_MHPMEVENTS 29 +#define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 =20 FIELD(VTYPE, VLMUL, 0, 2) @@ -114,6 +114,19 @@ FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 +typedef struct PMUCTRState PMUCTRState; +struct PMUCTRState { + /* Current value of a counter */ + target_ulong mhpmcounter_val; + /* Current value of a counter in RV32*/ + target_ulong mhpmcounterh_val; + /* Snapshot values of counter */ + target_ulong mhpmcounter_prev; + /* Snapshort value of a counter in RV32 */ + target_ulong mhpmcounterh_prev; + bool started; +}; + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ @@ -224,13 +237,10 @@ struct CPURISCVState { =20 target_ulong mcountinhibit; =20 - /* PMU counter configured values */ - target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS]; - - /* for RV32 */ - target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS]; + /* PMU counter state */ + PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values */ + /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 27614408e52a..7e3d4c6e0a10 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 @@ -423,41 +424,33 @@ static RISCVException write_vstart(CPURISCVState *env= , int csrno, } =20 /* User Timers and Counters */ -static RISCVException read_instret(CPURISCVState *env, int csrno, - target_ulong *val) +static target_ulong get_icount_ticks(bool brv32) { + int64_t val; + target_ulong result; + #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - *val =3D icount_get(); + val =3D icount_get(); } else { - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); } #else - *val =3D cpu_get_host_ticks(); + val =3D cpu_get_host_ticks(); #endif =20 - return RISCV_EXCP_NONE; -} - -static RISCVException read_instreth(CPURISCVState *env, int csrno, - target_ulong *val) -{ -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - *val =3D icount_get() >> 32; + if (brv32) { + result =3D val >> 32; } else { - *val =3D cpu_get_host_ticks() >> 32; + result =3D val; } -#else - *val =3D cpu_get_host_ticks() >> 32; -#endif =20 - return RISCV_EXCP_NONE; + return result; } =20 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 *val =3D env->mhpmevent_val[evt_index]; =20 @@ -466,7 +459,7 @@ static int read_mhpmevent(CPURISCVState *env, int csrno= , target_ulong *val) =20 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { - int evt_index =3D csrno - CSR_MHPMEVENT3; + int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 env->mhpmevent_val[evt_index] =3D val; =20 @@ -475,52 +468,99 @@ static int write_mhpmevent(CPURISCVState *env, int cs= rno, target_ulong val) =20 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + int ctr_idx =3D csrno - CSR_MCYCLE; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 - env->mhpmcounter_val[ctr_index] =3D val; + counter->mhpmcounter_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounter_prev =3D get_icount_ticks(false); + } else { + /* Other counters can keep incrementing from the given value */ + counter->mhpmcounter_prev =3D val; + } =20 - return RISCV_EXCP_NONE; + return RISCV_EXCP_NONE; } =20 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) { - int ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + int ctr_idx =3D csrno - CSR_MCYCLEH; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + counter->mhpmcounterh_val =3D val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounterh_prev =3D get_icount_ticks(false); + } else { + counter->mhpmcounterh_prev =3D val; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, + bool is_uh, uint32_t ctr_idx) +{ + PMUCTRState counter =3D env->pmu_ctrs[ctr_idx]; + target_ulong ctr_prev =3D is_uh ? counter.mhpmcounterh_prev : + counter.mhpmcounter_prev; + target_ulong ctr_val =3D is_uh ? counter.mhpmcounterh_val : + counter.mhpmcounter_val; =20 - env->mhpmcounterh_val[ctr_index] =3D val; + if (get_field(env->mcountinhibit, BIT(ctr_idx))) { + /** + * Counter should not increment if inhibit bit is set. We can't re= ally + * stop the icount counting. Just return the previous value to ind= icate + * that counter was not incremented. + */ + if (!counter.started) { + *val =3D ctr_val; + return RISCV_EXCP_NONE; + } else { + /* Mark that the counter has been stopped */ + counter.started =3D false; + } + } + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + *val =3D get_icount_ticks(is_uh); + } else { + *val =3D ctr_val; + } + + /* No need to handle the overflow here */ + *val =3D *val - ctr_prev + ctr_val; =20 return RISCV_EXCP_NONE; } =20 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *va= l) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_MCYCLE; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3 + 3; + ctr_index =3D csrno - CSR_CYCLE; } - *val =3D env->mhpmcounter_val[ctr_index]; =20 - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, false, ctr_index); } =20 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *v= al) { - int ctr_index; + uint16_t ctr_index; =20 if (env->priv =3D=3D PRV_M) { - ctr_index =3D csrno - CSR_MHPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_MCYCLEH; } else { - ctr_index =3D csrno - CSR_HPMCOUNTER3H + 3; + ctr_index =3D csrno - CSR_CYCLEH; } =20 - *val =3D env->mhpmcounterh_val[ctr_index]; - - return RISCV_EXCP_NONE; + return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 - #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -857,11 +897,23 @@ static RISCVException read_mcountinhibit(CPURISCVStat= e *env, int csrno, static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, target_ulong val) { + int cidx; + PMUCTRState *counter; + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -RISCV_EXCP_ILLEGAL_INST; } =20 env->mcountinhibit =3D val; + + /* Check if any other counter is also monitoring cycles/instructions */ + for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { + if (!get_field(env->mcountinhibit, BIT(cidx))) { + counter =3D &env->pmu_ctrs[cidx]; + counter->started =3D true; + } + } + return RISCV_EXCP_NONE; } =20 @@ -1709,10 +1761,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VL] =3D { "vl", vs, read_vl }, [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, - [CSR_INSTRET] =3D { "instret", ctr, read_instret }, - [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, - [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, + [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, + [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_hpmcounterh }, + [CSR_INSTRETH] =3D { "instreth", ctr32, read_hpmcounterh }, =20 /* * In privileged mode, the monitor will have to emulate TIME CSRs only= if @@ -1723,10 +1775,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, - [CSR_MINSTRET] =3D { "minstret", any, read_instret }, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a2b32064b07a..e0a489c20e67 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,13 @@ static bool vector_needed(void *opaque) return riscv_has_ext(env, RVV); } =20 +static bool pmu_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_pmu; +} + static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", .version_id =3D 1, @@ -138,6 +145,21 @@ static const VMStateDescription vmstate_hyper =3D { } }; =20 +static const VMStateDescription vmstate_pmu_ctr_state =3D { + .name =3D "cpu/pmu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmu_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), + VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), + VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), + VMSTATE_BOOL(started, PMUCTRState), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -178,8 +200,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOU= NTERS), - VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCO= UNTERS), + VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, + vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), diff --git a/target/riscv/meson.build b/target/riscv/meson.build index d5e0bc93ea9c..992122c4d6f5 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,6 +24,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'pmu.c', 'monitor.c', 'machine.c' )) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c new file mode 100644 index 000000000000..000fe8da45ef --- /dev/null +++ b/target/riscv/pmu.c @@ -0,0 +1,32 @@ +/* + * RISC-V PMU file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "pmu.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr) +{ + return (target_ctr =3D=3D 0) ? true : false; +} + +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) +{ + return (target_ctr =3D=3D 2) ? true : false; +} diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h new file mode 100644 index 000000000000..58a5bc3a4089 --- /dev/null +++ b/target/riscv/pmu.h @@ -0,0 +1,28 @@ +/* + * RISC-V PMU header file. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" + +bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, + uint32_t target_ctr); +bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, + uint32_t target_ctr); --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219791769436.48006489556985; Thu, 9 Sep 2021 13:36:31 -0700 (PDT) Received: from localhost ([::1]:53672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQmc-0005aW-MA for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219792974100001 Content-Type: text/plain; charset="utf-8" The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++++++ target/riscv/csr.c | 152 +++++++++++++++++- target/riscv/pmu.c | 343 +++++++++++++++++++++++++++++++++++++++- target/riscv/pmu.h | 9 ++ 6 files changed, 589 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eba6050324a0..0d77756c58d7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "internals.h" #include "exec/exec-all.h" #include "qapi/error.h" @@ -557,6 +558,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_misa(env, target_misa); } =20 + if (cpu->cfg.ext_pmu) { + if (!riscv_pmu_init(cpu, cpu->cfg.ext_pmu) && cpu->cfg.ext_sscof) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + if (!cpu->pmu_timer) { + cpu->cfg.ext_sscof =3D false; + } + } + } + riscv_cpu_register_gdb_regs_for_features(cs); =20 qemu_init_vcpu(cs); @@ -588,6 +599,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT16("pmu", RISCVCPU, cfg.ext_pmu, 16), + DEFINE_PROP_BOOL("sscof", RISCVCPU, cfg.ext_sscof, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 179c587d8634..4c756783e72d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,8 @@ struct PMUCTRState { /* Snapshort value of a counter in RV32 */ target_ulong mhpmcounterh_prev; bool started; + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ + target_ulong irq_overflow_left; }; =20 struct CPURISCVState { @@ -243,6 +245,9 @@ struct CPURISCVState { /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 + /* PMU event selector configured values for RV32*/ + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 @@ -320,6 +325,7 @@ struct RISCVCPU { bool ext_ifencei; bool ext_icsr; uint16_t ext_pmu; + bool ext_sscof; =20 char *priv_spec; char *user_spec; @@ -332,6 +338,12 @@ struct RISCVCPU { bool epmp; uint64_t resetvec; } cfg; + + QEMUTimer *pmu_timer; + /* A bitmask of Available programmable counters */ + uint32_t pmu_avail_ctrs; + /* Mapping of events to counters */ + GHashTable *pmu_event_ctr_map; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -525,6 +537,19 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 +/** + * The event id are encoded based on the encoding specified in the + * SBI specification v0.3 + */ + +enum riscv_pmu_event_idx { + RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +}; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ac519dcdc4df..60596fbb6bda 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -308,6 +308,37 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f + +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 @@ -338,6 +369,8 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 +#define CSR_SCOUNTOVF 0xd33 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -508,6 +541,7 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_PMU_OVF 13 =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -522,11 +556,13 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_LCOFIP (1 << IRQ_PMU_OVF) =20 /* sip masks */ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +#define SIP_LCOFIP MIP_LCOFIP =20 /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) @@ -535,4 +571,23 @@ typedef enum RISCVException { #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) +#define MIE_LCOFIE (1 << IRQ_PMU_OVF) + +#define MHPMEVENT_BIT_OF BIT(63) +#define MHPMEVENTH_BIT_OF BIT(31) +#define MHPMEVENT_BIT_MINH BIT(62) +#define MHPMEVENTH_BIT_MINH BIT(30) +#define MHPMEVENT_BIT_SINH BIT(61) +#define MHPMEVENTH_BIT_SINH BIT(29) +#define MHPMEVENT_BIT_UINH BIT(60) +#define MHPMEVENTH_BIT_UINH BIT(28) +#define MHPMEVENT_BIT_VSINH BIT(59) +#define MHPMEVENTH_BIT_VSINH BIT(27) +#define MHPMEVENT_BIT_VUINH BIT(58) +#define MHPMEVENTH_BIT_VUINH BIT(26) + +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_RESVD 16 + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7e3d4c6e0a10..5f4abe965d5e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -89,6 +89,19 @@ static RISCVException mctr32(CPURISCVState *env, int csr= no) return mctr(env, csrno); } =20 +static RISCVException sscof(CPURISCVState *env, int csrno) +{ + #if !defined(CONFIG_USER_ONLY) + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sscof) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif + return RISCV_EXCP_NONE; +} + static RISCVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -104,11 +117,18 @@ static RISCVException ctr(CPURISCVState *env, int csr= no) } ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.ext_pmu || ctr_index > (cpu->cfg.ext_pmu + 3)) { - /* The Counters extensions is not enabled or out of range */ + if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || + (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { + goto skip_ext_pmu_check; + } + + if ((!cpu->cfg.ext_pmu || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + /* The Counters extension is not enabled or out of range*/ return RISCV_EXCP_ILLEGAL_INST; } =20 +skip_ext_pmu_check: + if (env->priv =3D=3D PRV_S) { switch (csrno) { case CSR_CYCLE: @@ -424,7 +444,7 @@ static RISCVException write_vstart(CPURISCVState *env, = int csrno, } =20 /* User Timers and Counters */ -static target_ulong get_icount_ticks(bool brv32) +target_ulong get_icount_ticks(bool brv32) { int64_t val; target_ulong result; @@ -461,11 +481,36 @@ static int write_mhpmevent(CPURISCVState *env, int cs= rno, target_ulong val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; =20 + if (!riscv_cpu_is_32bit(env)) { + riscv_pmu_update_event_map(env, val, evt_index); + } env->mhpmevent_val[evt_index] =3D val; =20 return RISCV_EXCP_NONE; } =20 +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + + *val =3D env->mhpmevent_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint64_t mhpmevth_val =3D val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + env->mhpmeventh_val[evt_index] =3D val; + + return RISCV_EXCP_NONE; +} + static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { int ctr_idx =3D csrno - CSR_MCYCLE; @@ -475,6 +520,9 @@ static int write_mhpmcounter(CPURISCVState *env, int cs= rno, target_ulong val) if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounter_prev =3D get_icount_ticks(false); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, val, ctr_idx); + } } else { /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D val; @@ -487,11 +535,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int= csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D counter->mhpmcounter_val; + uint64_t mhpmctrh_val =3D val; =20 counter->mhpmcounterh_val =3D val; + mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounterh_prev =3D get_icount_ticks(false); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } } else { counter->mhpmcounterh_prev =3D val; } @@ -561,6 +615,32 @@ static int read_hpmcounterh(CPURISCVState *env, int cs= rno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) +{ + int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; + int i; + *val =3D 0; + target_ulong *mhpm_evt_val; + uint64_t of_bit_mask; + + if (riscv_cpu_is_32bit(env)) { + mhpm_evt_val =3D env->mhpmeventh_val; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpm_evt_val =3D env->mhpmevent_val; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + for (i =3D mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { + if ((get_field(env->mcounteren, BIT(i))) && + (mhpm_evt_val[i] & of_bit_mask)) { + *val |=3D BIT(i); + } + } + + return RISCV_EXCP_NONE; +} + #if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) @@ -607,7 +687,7 @@ static RISCVException read_timeh(CPURISCVState *env, in= t csrno, /* Machine constants */ =20 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP | MIP_LCOFIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) =20 static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | @@ -645,7 +725,8 @@ static const target_ulong vs_delegable_excps =3D DELEGA= BLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; +static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | + SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; @@ -2023,6 +2104,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscof, read_mhpmeventh, + write_mhpmeventh}, + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, @@ -2111,5 +2251,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh = }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh = }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscof, read_scountovf }, + #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 000fe8da45ef..a4c0044ff822 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -20,13 +20,352 @@ #include "cpu.h" #include "pmu.h" =20 +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ + +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || + !get_field(env->mcounteren, BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + target_ulong max_val =3D UINT32_MAX; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && (env->mhpmeventh_val[ctr_idx] & MHPMEVE= NTH_BIT_MINH)) || + (env->priv =3D=3D PRV_S && (env->mhpmeventh_val[ctr_idx] & MHPMEVEN= TH_BIT_SINH)) || + (env->priv =3D=3D PRV_U && (env->mhpmeventh_val[ctr_idx] & MHPMEVEN= TH_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + if (counter->mhpmcounterh_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + counter->mhpmcounterh_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { + env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounterh_val++; + } + } else { + counter->mhpmcounter_val++; + } + + return 0; +} + +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t max_val =3D UINT64_MAX; + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && (env->mhpmevent_val[ctr_idx] & MHPMEVEN= T_BIT_MINH)) || + (env->priv =3D=3D PRV_S && (env->mhpmevent_val[ctr_idx] & MHPMEVENT= _BIT_SINH)) || + (env->priv =3D=3D PRV_U && (env->mhpmevent_val[ctr_idx] & MHPMEVENT= _BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounter_val++; + } + return 0; +} + +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +{ + uint32_t ctr_idx; + int ret; + CPURISCVState *env =3D &cpu->env; + gpointer value; + + value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx)); + if (!value) { + return -1; + } + + ctr_idx =3D GPOINTER_TO_UINT(value); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || + get_field(env->mcountinhibit, BIT(ctr_idx))) { + return -1; + } + + if (riscv_cpu_is_32bit(env)) { + ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + } else { + ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + } + + return ret; +} + bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 0) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed instret counter */ + if (target_ctr =3D=3D 2) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + if (!ctr_idx) { + return false; + } + + return target_ctr =3D=3D ctr_idx ? true : false; } =20 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 2) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed mcycle counter */ + if (target_ctr =3D=3D 0) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + + /* Counter zero is not used for event_ctr_map */ + if (!ctr_idx) { + return false; + } + + return (target_ctr =3D=3D ctr_idx) ? true : false; +} + +static gboolean pmu_remove_event_map(gpointer key, gpointer value, + gpointer udata) +{ + return (GPOINTER_TO_UINT(value) =3D=3D GPOINTER_TO_UINT(udata)) ? true= : false; +} + +static int64_t pmu_icount_ticks_to_ns(int64_t value) +{ + int64_t ret =3D 0; + + if (icount_enabled()) { + ret =3D icount_to_ns(value); + } else { + ret =3D (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; + } + + return ret; +} + +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx) +{ + uint32_t event_idx; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + + if (!riscv_pmu_counter_valid(cpu, ctr_idx)) { + return -1; + } + + /** + * Expected mhpmevent value is zero for reset case. Remove the current + * mapping. + */ + if (!value) { + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, + pmu_remove_event_map, + GUINT_TO_POINTER(ctr_idx)); + return 0; + } + + event_idx =3D value & MHPMEVENT_IDX_MASK; + if (g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx))) { + return 0; + } + + switch (event_idx) { + case RISCV_PMU_EVENT_HW_CPU_CYCLES: + case RISCV_PMU_EVENT_HW_INSTRUCTIONS: + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + break; + default: + /* We don't support any raw events right now */ + return -1; + } + g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + GUINT_TO_POINTER(ctr_idx)); + + return 0; +} + +static void pmu_timer_trigger_irq(RISCVCPU *cpu, + enum riscv_pmu_event_idx evt_idx) +{ + uint32_t ctr_idx; + CPURISCVState *env =3D &cpu->env; + target_ulong curr_val =3D 0, currh_val =3D 0, delta; + PMUCTRState *counter; + target_ulong *mhpmevent_val; + uint64_t of_bit_mask; + + if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + return; + } + + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(evt_idx))); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { + return; + } + + curr_val =3D get_icount_ticks(false); + if (riscv_cpu_is_32bit(env)) { + mhpmevent_val =3D &env->mhpmeventh_val[ctr_idx]; + currh_val =3D get_icount_ticks(true); + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpmevent_val =3D &env->mhpmevent_val[ctr_idx]; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->irq_overflow_left > 0) { + timer_mod_anticipate_ns(cpu->pmu_timer, counter->irq_overflow_left= ); + counter->irq_overflow_left =3D 0; + return; + } + + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { + delta =3D curr_val - counter->mhpmcounter_prev; + counter->mhpmcounter_val +=3D delta; + if (riscv_cpu_is_32bit(env)) { + delta =3D currh_val - counter->mhpmcounterh_prev; + counter->mhpmcounterh_val +=3D delta; + } + /* Generate interrupt only if OF bit is clear */ + if (!(*mhpmevent_val & of_bit_mask)) { + *mhpmevent_val |=3D of_bit_mask; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } +} + +/* Timer callback for instret and cycle counter overflow */ +void riscv_pmu_timer_cb(void *priv) +{ + RISCVCPU *cpu =3D priv; + + /* Timer event was triggered only for these events */ + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); +} + +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) +{ + uint64_t overflow_delta, overflow_at; + int64_t overflow_ns, overflow_left =3D 0; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscof) { + return -1; + } + + if (value) { + overflow_delta =3D UINT64_MAX - value + 1; + } else { + overflow_delta =3D UINT64_MAX - value; + } + + /** + * QEMU supports only int64_t timers while RISC-V counters are uint64_= t. + * Compute the leftover and save it so that it can be reprogrammed aga= in + * when timer expires. + */ + if (overflow_delta > INT64_MAX) { + overflow_left =3D overflow_delta - INT64_MAX; + } + + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + overflow_ns =3D pmu_icount_ticks_to_ns((int64_t)overflow_delta); + overflow_left =3D pmu_icount_ticks_to_ns(overflow_left) ; + } else { + return -1; + } + overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns; + + if (overflow_at > INT64_MAX) { + overflow_left +=3D overflow_at - INT64_MAX; + counter->irq_overflow_left =3D overflow_left; + overflow_at =3D INT64_MAX; + } + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + + return 0; +} + + +int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +{ + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { + return -1; + } + + cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + if (!cpu->pmu_event_ctr_map) { + /* PMU support can not be enabled */ + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); + cpu->cfg.ext_pmu =3D 0; + return -1; + } + + /* Create a bitmask of available programmable counters */ + cpu->pmu_avail_ctrs =3D ~(-1 << (num_counters + 3)) & ~(0x07); + return 0; } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 58a5bc3a4089..af78da92e820 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -26,3 +26,12 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *e= nv, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); +void riscv_pmu_timer_cb(void *priv); +int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name); +target_ulong get_icount_ticks(bool brv32); +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219448633632.5969973444473; Thu, 9 Sep 2021 13:30:48 -0700 (PDT) Received: from localhost ([::1]:41754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOQh5-0005tK-Gw for importer@patchew.org; Thu, 09 Sep 2021 16:30:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdR-0007IL-0m; Thu, 09 Sep 2021 16:27:01 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:36123) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOQdM-0000RO-Pg; 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X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="179620288" IronPort-SDR: u2eWsdwEK0dBnLfXV8mz/mDKRHp+2J1hPadsT5ODjqDERHIzwq+4aot8HEfrfHb4iVbx92qeFN ZacSf79RVowox5rziK6PNQXcu+QlFdOskP3RQMdTCyueb+fWWyzo2VkGeBzc4G48Y5pBN9cyPE O7UoC3MQsSX+U96dVbUEsP6G+BTOfLXKBRGFbrvKPzwd/Wto7NHivhXoQysKRhLWUnXnbNbLgu bRrKu4/A88OFVcXGIMB6pEnA/Tneup2OXUw6Rv9YR2s4MMmeIG+YJhKhIupSy46lAJthtJ0s6B AY37L28RXIAi3mkYVuInAhCR IronPort-SDR: aNBCTYGmCBIOV+h3e74ZYjbuSI7OG3yAZsSa/AKgukczhD1l9sl/Lw/hfDyGzuzLBVF8CdaRGZ 6Uk2GFFMF+ntBGitXIpOkzQgWmBCEhviXnvInhoBx2Oxg+8jBjIMWan8n2h8h9WLSGM2+5DrG8 YK5H4ek8YDYMZiI4VQr7rs6jI3AKDzWJWnF77G1i42iAmKzjlUpDqzaOiUl0a3a8ZJHiXeuKCI 8EXgQO3Ap6ufZYxrk3VC/t8pbBmpnhbot2ce1CGHSPenv31va8QLjjcN9ktM8h4iRivuX3zIF1 sHg= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 8/9] target/riscv: Add few cache related PMU events Date: Thu, 9 Sep 2021 13:26:38 -0700 Message-Id: <20210909202639.1230170-9-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219450511100001 Content-Type: text/plain; charset="utf-8" Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f49..c86250e1aada 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,10 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu.h" +#include "cpu_bits.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -754,6 +757,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, } #endif /* !CONFIG_USER_ONLY */ =20 + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -851,6 +876,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, fals= e); --=20 2.31.1 From nobody Wed May 8 00:22:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631219371469496.4033906600324; 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09 Sep 2021 13:26:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631219220; x=1662755220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Tq2p/Ll2dVmYe8pNo+bw4oH6NsBrSJPfOEeR4S1sJs=; b=TrgYaTO8Y8JThBaT5EwUmxAHW0lQUiFLzzdVsxHobxku1+YCjGtYOZSm Lxx2lW6n7lo8Y1/Y2Em7Unj2tO0WPHAQlBs4YP8gFYe25vz4H9M6IPK/y 3fg5A02Y7bRfz1nfAT5SWmQetzcPBZW9q71U46RrCqSFiEdSX7Ri6VE0l DpJ7xg7gzECBdXtuKVsi7QhwAkgKrmosvU9sJEegq4XfGGKOf3f4Tzmr8 u7I9SdavtWPMZwlPk0KNNaEj3MMNMFIE/4FgzuzFNmbxiFh7OcNKRuYrV fHtAbJKdjUuSoZZ1dS+jFxxWs95G8Q7eZwLR9kcvTrEcIgArCj0okiIzY A==; X-IronPort-AV: E=Sophos;i="5.85,281,1624291200"; d="scan'208";a="179620290" IronPort-SDR: 7AC4yI81b0bRIjZcIE7O6VJi4AA9KasVYOf6YPOo0eL5Qx7qosoEmy43nAVZ4nktH/UzbHu7Ui WeAxJjhYHy/76DVzIUYfBAPXOSZjRnzklHJVKam7uVGiMzJkjHQE1bqavegnWveDcWnZB90NxN 3LbBa8207mSbNnJWZ9kc7xiUozEGlbHPgNJkzx0eIOEUSsfQwtWT3XBa/dJxbtXRzTL2GoWirc 1wCpcJZz2oLRizss/rIuYtcAOgTNzums3/R86BI2ZgYa6aoph/SswJ6zhSnfk7NkUyiPQ2ZK7k 7Imn4DmBYbHl2pW/PdH/VoPB IronPort-SDR: lULnzqMuyJ5lGFqOliLHQdZHKcUtmuyvuEX02A0hioCRdHbLYfI14oTPRiDtvLXnRjG+lCnSQg BopWk4/gkeqsSW7I2ZKszxpQJkUcISFb2MG+vIJlu5SACC/X9amyH/Boxsd78nLMqM62mmjOOZ PpmUSnNyRX60BvXjM5sWxk+xxRAfgz3oMR08xhnYS5C/CvJS8DhiGWzdK+X+oq9z0uyemzA/3+ 0QiGuTy+Byw0qs1hh+3RZqht7h2QYMYQDuSrbBzdNVGrbKzHY24bUW7NLqunr5fJINoOuWuFMR fJ0= WDCIronportException: Internal From: Atish Patra To: qemu-devel@nongnu.org Subject: [ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree Date: Thu, 9 Sep 2021 13:26:39 -0700 Message-Id: <20210909202639.1230170-10-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com> References: <20210909202639.1230170-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=87996f883=atish.patra@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Bin Meng , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631219372051100001 Content-Type: text/plain; charset="utf-8" Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. Signed-off-by: Atish Patra --- hw/riscv/virt.c | 25 +++++++++++++++++++-- target/riscv/pmu.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a3cd2599a5e..197390fe5627 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -42,6 +43,7 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include =20 static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, @@ -184,14 +186,14 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, int i, cpu, socket; MachineState *mc =3D MACHINE(s); uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; + uint32_t *clint_cells, *plic_cells, *pmu_int_cells; unsigned long clint_addr, plic_addr; uint32_t plic_phandle[MAX_NODES]; uint32_t cpu_phandle, intc_phandle, test_phandle; uint32_t phandle =3D 1, plic_mmio_phandle =3D 1; uint32_t plic_pcie_phandle =3D 1, plic_virtio_phandle =3D 1; char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; + char *name, *clint_name, *plic_name, *clust_name, *pmu_name; hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; static const char * const clint_compat[2] =3D { @@ -240,6 +242,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, =20 plic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + pmu_int_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { cpu_phandle =3D phandle++; @@ -282,6 +285,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, plic_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); plic_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); =20 + pmu_int_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandle); + pmu_int_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_PMU_OVF); + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); qemu_fdt_add_subnode(fdt, core_name); qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); @@ -291,6 +297,21 @@ static void create_fdt(RISCVVirtState *s, const MemMap= Entry *memmap, g_free(cpu_name); } =20 + pmu_name =3D g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(fdt, pmu_name); + qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); + RISCVCPU cpu =3D s->soc[0].harts[0]; + if (cpu.cfg.ext_sscof) { + qemu_fdt_setprop_cell(fdt, pmu_name, "#interrupt-cells", 1); + qemu_fdt_setprop(fdt, pmu_name, "interrupts-extended", + pmu_int_cells, + s->soc[socket].num_harts * sizeof(uint32_t) *= 2); + } + + riscv_pmu_generate_fdt_node(fdt, pmu_name); + g_free(pmu_int_cells); + g_free(pmu_name); + addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, sock= et); size =3D riscv_socket_mem_size(mc, socket); mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a4c0044ff822..a93b61daf00a 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,9 +19,64 @@ #include "qemu/osdep.h" #include "cpu.h" #include "pmu.h" +#include "sysemu/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ =20 +/** + * To keep it simple, any event can be mapped to any programmable counters= in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must conti= nue + * to provide the correct value as well. + */ +void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name) +{ + uint32_t fdt_event_map[6] =3D {}; + uint32_t fdt_event_ctr_map[20] =3D {}; + uint32_t fdt_raw_event_ctr_map[6] =3D {}; + + fdt_event_map[0] =3D cpu_to_be32(0x00000009); + fdt_event_map[1] =3D cpu_to_be32(0x00000000); + fdt_event_map[2] =3D cpu_to_be32(0x00000200); + fdt_event_map[3] =3D cpu_to_be32(0x00010000); + fdt_event_map[4] =3D cpu_to_be32(0x00000100); + fdt_event_map[5] =3D cpu_to_be32(0x00000002); + qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmevent", + fdt_event_map, sizeof(fdt_event_map)); + + fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] =3D cpu_to_be32(0x00000FF9); + fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] =3D cpu_to_be32(0x00000FFC); + + fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] =3D cpu_to_be32(0x00001F0); + + fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] =3D cpu_to_be32(0x00001F0); + + fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] =3D cpu_to_be32(0x00001F0); + + qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); + + fdt_raw_event_ctr_map[0] =3D cpu_to_be32(0x00000000); + fdt_raw_event_ctr_map[1] =3D cpu_to_be32(0x00020002); + fdt_raw_event_ctr_map[2] =3D cpu_to_be32(0x00000F00); + fdt_raw_event_ctr_map[3] =3D cpu_to_be32(0x00000000); + fdt_raw_event_ctr_map[4] =3D cpu_to_be32(0x00020003); + fdt_raw_event_ctr_map[5] =3D cpu_to_be32(0x000000F0); + qemu_fdt_setprop(fdt, pmu_name, "pmu,raw-event-to-mhpmcounters", + fdt_raw_event_ctr_map, + sizeof(fdt_raw_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || --=20 2.31.1