From nobody Tue Feb 10 14:43:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631102861714715.8488195690634; Wed, 8 Sep 2021 05:07:41 -0700 (PDT) Received: from localhost ([::1]:55260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNwMd-0007rl-Ot for importer@patchew.org; Wed, 08 Sep 2021 08:07:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNwB4-0006VK-QZ for qemu-devel@nongnu.org; Wed, 08 Sep 2021 07:55:42 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59068 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNwB3-0005dH-AM for qemu-devel@nongnu.org; Wed, 08 Sep 2021 07:55:42 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mNwAx-0009u6-Te; Wed, 08 Sep 2021 12:55:40 +0100 From: Mark Cave-Ayland To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Wed, 8 Sep 2021 12:54:49 +0100 Message-Id: <20210908115451.9821-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210908115451.9821-1-mark.cave-ayland@ilande.co.uk> References: <20210908115451.9821-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 10/12] escc: remove register changes from escc_reset_chn() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1631102863175100001 Content-Type: text/plain; charset="utf-8" Now that register values at reset are handled elsewhere for all of device r= eset, soft reset and hard reset, escc_reset_chn() only needs to handle initialisa= tion of internal device state. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 80f1d1b8fc..22c97414a1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -139,7 +139,6 @@ #define MISC2_PLLCMD0 0x20 #define MISC2_PLLCMD1 0x40 #define MISC2_PLLCMD2 0x80 -#define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 #define EXTINT_SYNCINT 0x10 @@ -279,31 +278,7 @@ static void escc_update_irq(ESCCChannelState *s) =20 static void escc_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ - s->wregs[W_CLOCK] =3D CLOCK_TRXC; - /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; - /* Enable most interrupts */ - s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; - if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; - } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; - s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; s->rxint_under_svc =3D s->txint_under_svc =3D 0; --=20 2.20.1