From nobody Mon Feb 9 15:11:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631089616982143.65349367328588; Wed, 8 Sep 2021 01:26:56 -0700 (PDT) Received: from localhost ([::1]:52954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNsv1-0005Xa-Lo for importer@patchew.org; Wed, 08 Sep 2021 04:26:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNstb-0002qt-3T for qemu-devel@nongnu.org; Wed, 08 Sep 2021 04:25:27 -0400 Received: from mga14.intel.com ([192.55.52.115]:13016) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNstZ-0003pF-IT for qemu-devel@nongnu.org; Wed, 08 Sep 2021 04:25:26 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 01:25:19 -0700 Received: from icx-2s.bj.intel.com ([10.240.192.119]) by FMSMGA003.fm.intel.com with ESMTP; 08 Sep 2021 01:25:18 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="220102701" X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="220102701" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="538450903" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH 4/7] bitops: Support 32 and 64 bit mask macro Date: Wed, 8 Sep 2021 16:19:34 +0800 Message-Id: <20210908081937.77254-5-yang.zhong@intel.com> X-Mailer: git-send-email 2.29.2.334.gfaefdd61ec In-Reply-To: <20210908081937.77254-1-yang.zhong@intel.com> References: <20210908081937.77254-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, pbonzini@redhat.com, eblake@redhat.com, seanjc@google.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1631089619051100001 Content-Type: text/plain; charset="utf-8" The Qemu should enable bit mask macro like Linux did in the kernel, the GENMASK(h, l) and GENMASK_ULL(h, l) will set the bit to 1 from l to h bit in the 32 bit or 64 bit long type. Signed-off-by: Yang Zhong --- include/qemu/bitops.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952..04dec60670 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -18,6 +18,7 @@ =20 #define BITS_PER_BYTE CHAR_BIT #define BITS_PER_LONG (sizeof (unsigned long) * BITS_PER_BYTE) +#define BITS_PER_LONG_LONG 64 =20 #define BIT(nr) (1UL << (nr)) #define BIT_ULL(nr) (1ULL << (nr)) @@ -28,6 +29,12 @@ #define MAKE_64BIT_MASK(shift, length) \ (((~0ULL) >> (64 - (length))) << (shift)) =20 +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + /** * set_bit - Set a bit in memory * @nr: the bit to set