From nobody Tue Feb 10 21:40:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630998296978895.2636954033972; Tue, 7 Sep 2021 00:04:56 -0700 (PDT) Received: from localhost ([::1]:38148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNVA8-0001zr-7O for importer@patchew.org; Tue, 07 Sep 2021 03:04:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNV41-0001Rc-44; Tue, 07 Sep 2021 02:58:37 -0400 Received: from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]:36719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNV3y-0001Iq-Om; Tue, 07 Sep 2021 02:58:36 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.108.1.114]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 60964BCB54E0; Tue, 7 Sep 2021 08:58:25 +0200 (CEST) Received: from kaod.org (37.59.142.97) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Tue, 7 Sep 2021 08:58:24 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-97G002b076d2f1-fe67-481e-91df-00cce9b53478, 984F41D2D9692A95DAA6D5E609006558D983FB00) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell , Andrew Jeffery , Joel Stanley Subject: [PATCH 02/10] aspeed/smc: Introduce aspeed_smc_error() helper Date: Tue, 7 Sep 2021 08:58:14 +0200 Message-ID: <20210907065822.1152443-3-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907065822.1152443-1-clg@kaod.org> References: <20210907065822.1152443-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [37.59.142.97] X-ClientProxiedBy: DAG8EX1.mxp5.local (172.16.2.71) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: aa32182f-0359-446b-8179-91b90df68028 X-Ovh-Tracer-Id: 977281122754136937 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrudefgedgudduudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvffufffkofgjfhggtgfgihesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeehheefgeejiedtffefteejudevjeeufeeugfdtfeeuleeuteevleeihffhgfdtleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddrleejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.32.125.2; envelope-from=clg@kaod.org; helo=smtpout1.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630998298652100001 It unifies the errors reported by the Aspeed SMC model and also removes some use of ctrl->name which will help us for the next patches. Signed-off-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 97 +++++++++++++++++++++------------------------ 1 file changed, 45 insertions(+), 52 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index c9990f069ea4..b4d92d75a694 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -512,6 +512,9 @@ static void aspeed_2600_smc_reg_to_segment(const Aspeed= SMCState *s, } } =20 +#define aspeed_smc_error(fmt, ...) \ + qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS= __) + static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, const AspeedSegments *new, int cs) @@ -528,11 +531,11 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCS= tate *s, =20 if (new->addr + new->size > seg.addr && new->addr < seg.addr + seg.size) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%" - HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " - "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", - s->ctrl->name, cs, new->addr, new->addr + new->s= ize, - i, seg.addr, seg.addr + seg.size); + aspeed_smc_error("new segment CS%d [ 0x%" + HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps wi= th " + "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]= ", + cs, new->addr, new->addr + new->size, + i, seg.addr, seg.addr + seg.size); return true; } } @@ -567,9 +570,8 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState= *s, int cs, =20 /* The start address of CS0 is read-only */ if (cs =3D=3D 0 && seg.addr !=3D s->ctrl->flash_window_base) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Tried to change CS0 start address to 0x%" - HWADDR_PRIx "\n", s->ctrl->name, seg.addr); + aspeed_smc_error("Tried to change CS0 start address to 0x%" + HWADDR_PRIx, seg.addr); seg.addr =3D s->ctrl->flash_window_base; new =3D s->ctrl->segment_to_reg(s, &seg); } @@ -583,9 +585,8 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState= *s, int cs, cs =3D=3D s->ctrl->max_peripherals && seg.addr + seg.size !=3D s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Tried to change CS%d end address to 0x%" - HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.= size); + aspeed_smc_error("Tried to change CS%d end address to 0x%" + HWADDR_PRIx, cs, seg.addr + seg.size); seg.size =3D s->ctrl->segments[cs].addr + s->ctrl->segments[cs].si= ze - seg.addr; new =3D s->ctrl->segment_to_reg(s, &seg); @@ -595,17 +596,17 @@ static void aspeed_smc_flash_set_segment(AspeedSMCSta= te *s, int cs, if (seg.size && (seg.addr + seg.size <=3D s->ctrl->flash_window_base || seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_siz= e)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invali= d : " - "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", - s->ctrl->name, cs, seg.addr, seg.addr + seg.size); + aspeed_smc_error("new segment for CS%d is invalid : " + "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", + cs, seg.addr, seg.addr + seg.size); return; } =20 /* Check start address vs. alignment */ if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not " - "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n= ", - s->ctrl->name, cs, seg.addr, seg.addr + seg.size); + aspeed_smc_error("new segment for CS%d is not " + "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" = ]", + cs, seg.addr, seg.addr + seg.size); } =20 /* And segments should not overlap (in the specs) */ @@ -618,16 +619,15 @@ static void aspeed_smc_flash_set_segment(AspeedSMCSta= te *s, int cs, static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, unsigned size) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u" - PRIx64 "\n", __func__, addr, size); + aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u" PRIx64, addr, size= ); return 0; } =20 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: = 0x%" - PRIx64 "\n", __func__, addr, size, data); + aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, + addr, size, data); } =20 static const MemoryRegionOps aspeed_smc_flash_default_ops =3D { @@ -670,8 +670,8 @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCF= lash *fl) } =20 if (!cmd) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: no command defined for mode %d= \n", - __func__, aspeed_smc_flash_mode(fl)); + aspeed_smc_error("no command defined for mode %d", + aspeed_smc_flash_mode(fl)); } =20 return cmd; @@ -715,11 +715,9 @@ static uint32_t aspeed_smc_check_segment_addr(const As= peedSMCFlash *fl, =20 s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg); if ((addr % seg.size) !=3D addr) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid address 0x%08x for CS%d segment : " - "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", - s->ctrl->name, addr, fl->id, seg.addr, - seg.addr + seg.size); + aspeed_smc_error("invalid address 0x%08x for CS%d segment : " + "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", + addr, fl->id, seg.addr, seg.addr + seg.size); addr %=3D seg.size; } =20 @@ -795,8 +793,7 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwa= ddr addr, unsigned size) aspeed_smc_flash_unselect(fl); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n", - __func__, aspeed_smc_flash_mode(fl)); + aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl= )); } =20 trace_aspeed_smc_flash_read(fl->id, addr, size, ret, @@ -913,8 +910,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr= addr, uint64_t data, aspeed_smc_flash_mode(fl)); =20 if (!aspeed_smc_is_writable(fl)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%" - HWADDR_PRIx "\n", __func__, addr); + aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); return; } =20 @@ -939,8 +935,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr= addr, uint64_t data, aspeed_smc_flash_unselect(fl); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n", - __func__, aspeed_smc_flash_mode(fl)); + aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl= )); } } =20 @@ -1066,7 +1061,7 @@ static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_m= ask) } } =20 - qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask); + aspeed_smc_error("invalid HCLK mask %x", hclk_mask); return 0; } =20 @@ -1146,8 +1141,7 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) uint32_t data; =20 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid direction for DMA checksum\n", __func_= _); + aspeed_smc_error("invalid direction for DMA checksum"); return; } =20 @@ -1159,8 +1153,8 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) data =3D address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_AD= DR], MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n", - __func__, s->regs[R_DMA_FLASH_ADDR]); + aspeed_smc_error("Flash read failed @%08x", + s->regs[R_DMA_FLASH_ADDR]); return; } trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); @@ -1195,32 +1189,32 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) data =3D address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_= ADDR], MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x= \n", - __func__, s->regs[R_DMA_DRAM_ADDR]); + aspeed_smc_error("DRAM read failed @%08x", + s->regs[R_DMA_DRAM_ADDR]); return; } =20 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], data, MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%0= 8x\n", - __func__, s->regs[R_DMA_FLASH_ADDR]); + aspeed_smc_error("Flash write failed @%08x", + s->regs[R_DMA_FLASH_ADDR]); return; } } else { data =3D address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLAS= H_ADDR], MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08= x\n", - __func__, s->regs[R_DMA_FLASH_ADDR]); + aspeed_smc_error("Flash read failed @%08x", + s->regs[R_DMA_FLASH_ADDR]); return; } =20 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], data, MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08= x\n", - __func__, s->regs[R_DMA_DRAM_ADDR]); + aspeed_smc_error("DRAM write failed @%08x", + s->regs[R_DMA_DRAM_ADDR]); return; } } @@ -1280,7 +1274,7 @@ static void aspeed_smc_dma_ctrl(AspeedSMCState *s, ui= nt32_t dma_ctrl) } =20 if (aspeed_smc_dma_in_progress(s)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__); + aspeed_smc_error("DMA in progress !"); return; } =20 @@ -1302,7 +1296,7 @@ static inline bool aspeed_smc_dma_granted(AspeedSMCSt= ate *s) } =20 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + aspeed_smc_error("DMA not granted"); return false; } =20 @@ -1327,7 +1321,7 @@ static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *= s, uint32_t dma_ctrl) } =20 if (!aspeed_smc_dma_granted(s)) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + aspeed_smc_error("DMA not granted"); return; } =20 @@ -1433,8 +1427,7 @@ static void aspeed_smc_realize(DeviceState *dev, Erro= r **errp) =20 /* Enforce some real HW limits */ if (s->num_cs > s->ctrl->max_peripherals) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n", - __func__, s->ctrl->max_peripherals); + aspeed_smc_error("num_cs cannot exceed: %d", s->ctrl->max_peripher= als); s->num_cs =3D s->ctrl->max_peripherals; } =20 --=20 2.31.1