From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688700658336.76054598434655; Fri, 3 Sep 2021 10:05:00 -0700 (PDT) Received: from localhost ([::1]:41868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCcd-0004Jx-Jj for importer@patchew.org; Fri, 03 Sep 2021 13:04:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYy-0007HA-92 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:12 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]:46979) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYv-0004z4-8o for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:11 -0400 Received: by mail-lf1-x133.google.com with SMTP id t19so12967610lfe.13 for ; Fri, 03 Sep 2021 10:01:08 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gw4LvlnxnnY6EO7Y13J17phqBUMt7B/+5TuFjvc41YA=; b=HlXsjpi3wJFwDqWVolQAC7/Q+8Qqf9yltQ+pCIN35IrvwYkxKselHnKw559B6DIXjA R+soXKPqgO2NT2xbV2Ihg8tgVElguN9zHhVSNZ9/btdhzlORkLDJd0Yd22JLMdPSFsHx tJ7yuq/328V2EvlEv9Oy0UOCrx9OGu9i3pTiPVYziHbpy/2shAeWcgs1WyWxEPhXSPqY 9aTAR1hMrrJ3PXuk2e7itktKSChksWsYCgn9rDsXhyU0mZFWZU7sgT6CHURlrEu5oPK4 cTae43NMjxrBE5L4cBBG7BBEjQKRLbNfJHHefDnJ3f4L/gVljPn3hCDkZj3Eg1RFB7Bj yTDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gw4LvlnxnnY6EO7Y13J17phqBUMt7B/+5TuFjvc41YA=; b=NMzdVKy9mI+YQeNN/RZH8DDdEI2ujKBw4fAskvbf3Y3frOKyjaqrqh5SnRp3OASbjA hSLv0YXvMA4jk/W7Dwoyw3ogwhIZVmfrW5wdm5Jvsg3zt1O/bbiLb5o3sq/SDwABBNL1 WqZiGScppLNNWhRCjqidYztLANZ2J/kprFftTFjm8NCCecDZXdSVp72iWgeuQMAFge1r 61CBeLHf1ytCrOE+d8W4kXl2xnVR/YrkK/02dUi3fiJ/ePjNtcUGDcIiX/hcQs/7bIJE QLCJpqs+M+691R1M82O5bFXf0E4pWNsJn6nbxR+pU7R5ocsIMl9y8JOWISq+piDJ7T81 qYaA== X-Gm-Message-State: AOAM530MoUh5cfrRjmXfaPhtQIItNKzjgflFoyF/eqCm7DlApyyBWiYl 2mjQYmcvv9lMAp9EfQfRDg9cIsBQBl7LTBm6xvQ= X-Google-Smtp-Source: ABdhPJwu3awEr901GQ6OXdcHMaQkKIey8RFnxVgZDXvsG8fNSRozc6iFdnx8jz+33q0T4PmnYCCXaw== X-Received: by 2002:ac2:4d10:: with SMTP id r16mr3050772lfi.546.1630688465846; Fri, 03 Sep 2021 10:01:05 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Date: Fri, 3 Sep 2021 19:00:47 +0200 Message-Id: <20210903170100.2529121-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x133.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688702310100001 Content-Type: text/plain; charset="utf-8" The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Split off removal of 'x-b' property and 'ext_b' field into a separate patch to ensure bisectability. target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579..ceb7e01810 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,6 +587,10 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), + DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), + DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), + DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), + DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..7c4cd8ea89 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,6 +293,10 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; bool ext_counters; bool ext_ifencei; bool ext_icsr; --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688638100647.7732018584159; Fri, 3 Sep 2021 10:03:58 -0700 (PDT) Received: from localhost ([::1]:38198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCbc-0001j2-RL for importer@patchew.org; Fri, 03 Sep 2021 13:03:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYy-0007Ik-Um for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:12 -0400 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]:39653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYv-0004z5-8k for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:12 -0400 Received: by mail-lf1-x12d.google.com with SMTP id m28so13013108lfj.6 for ; Fri, 03 Sep 2021 10:01:08 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JfntyVVXMEu7zVQPLwpnP4WZtNnfaQJsxSeK0jAz7GY=; b=MI6Q2lUuztLMsTJRna09PB09GEaif4JqijODE5L3uWYlY/ol+mOx77it0boEhNJgnk T2STQb0289SgIthppGzTYcWKeK3SGbzYu7EZirwnxpbfuELwy3jb+Tj/Mdl1vFLNqC9N 404BZv5QAcZzLNCBdl75qUVcfkmhHAtoN051ssbxE0qk2uovnOcCPHSfeNzNUVxKRrlb R7cgok3AD7a9ECj1XDvmPbqZlmnmaQDYgqWzaVuKygwVt6A7M8I5KDNSyoklPnV/izgX fOWshYWInxPPNwfCVAznElif4mEYT7MisJ+cLxXqRHIigR7Sw04YYhPRKB2fvrHwm/iG tYnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JfntyVVXMEu7zVQPLwpnP4WZtNnfaQJsxSeK0jAz7GY=; b=qCrkX8rlhxU3L9KyZIyNMIVZYaaAQqU5oJJtKi0hQIIB8qexbgSzgvu7ZOx1ZRpeeO 2LJ6r7I1B6Lwq+s+6jUiMcO6L/Y2k1A180GJy8y4bEzlK8NI6joRIq6WK9hTE8VvXoAK FTLpGFRlqj38zI5gIF34yW51bZsY4JQLs8xdHNpFZLoTaTO2NqQtme6sL++R/6XwI5vj jq12YXpEM79pDQRf7zmyoQG/jduIBTtFse7dLhn6Vr+6bFa9Liex0NgqnHb6zrGp21kD zIcfHidlMlOchNHqxGj1/XEv21jbdTVBHazHUjab944/hZ7y8g2h+D4GISWqC/jMZ1gV PITg== X-Gm-Message-State: AOAM530SMKACweG9viBgmTUNwEuBgOBFEBwZSyxx061nTCV37nHTKAed Erne43KsRH5iJ4g1LhTxsE5mqpRTlBOzA2mM19o= X-Google-Smtp-Source: ABdhPJzyFgeBqi/WtQcVkGF90DVoBIeFszrjxJM2ojo98bX0wZD5bVYO8s/MdG2wUYOQhqP696SK6Q== X-Received: by 2002:ac2:5c46:: with SMTP id s6mr3536508lfp.78.1630688466603; Fri, 03 Sep 2021 10:01:06 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 02/14] target/riscv: Reassign instructions to the Zba-extension Date: Fri, 3 Sep 2021 19:00:48 +0200 Message-Id: <20210903170100.2529121-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688640569100001 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis fix add_uw -- deserves note --- Changes in v9: - Rebased to 8880cc4362. - Update gen_add_uw() to use a temporary instead of messing with arg1 (fixes a regression after rebase on CF3 and SPEC2017). Changes in v3: - The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro and its use for qualifying the Zba instructions) are moved into a separate commit. target/riscv/insn32.decode | 20 ++++++++++++-------- target/riscv/insn_trans/trans_rvb.c.inc | 22 +++++++++++++++------- 2 files changed, 27 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2cd921d51c..86f1166dab 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -660,6 +660,18 @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 010111= 1 @r_wdvm vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm =20 +# *** RV32 Zba Standard Extension *** +sh1add 0010000 .......... 010 ..... 0110011 @r +sh2add 0010000 .......... 100 ..... 0110011 @r +sh3add 0010000 .......... 110 ..... 0110011 @r + +# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** +add_uw 0000100 .......... 000 ..... 0111011 @r +sh1add_uw 0010000 .......... 010 ..... 0111011 @r +sh2add_uw 0010000 .......... 100 ..... 0111011 @r +sh3add_uw 0010000 .......... 110 ..... 0111011 @r +slli_uw 00001 ............ 001 ..... 0011011 @sh + # *** RV32B Standard Extension *** clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 @@ -687,9 +699,6 @@ ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r -sh1add 0010000 .......... 010 ..... 0110011 @r -sh2add 0010000 .......... 100 ..... 0110011 @r -sh3add 0010000 .......... 110 ..... 0110011 @r =20 bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -718,10 +727,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sh1add_uw 0010000 .......... 010 ..... 0111011 @r -sh2add_uw 0010000 .......... 100 ..... 0111011 @r -sh3add_uw 0010000 .......... 110 ..... 0111011 @r -add_uw 0000100 .......... 000 ..... 0111011 @r =20 bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -732,4 +737,3 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 -slli_uw 00001. ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index b72e76255c..91da7c5853 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,8 +1,9 @@ /* - * RISC-V translation routines for the RVB Standard Extension. + * RISC-V translation routines for the RVB draft and Zba Standard Extensio= n. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,6 +18,11 @@ * this program. If not, see . */ =20 +#define REQUIRE_ZBA(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \ + return false; \ + } \ +} while (0) =20 static void gen_clz(TCGv ret, TCGv arg1) { @@ -339,7 +345,7 @@ GEN_SHADD(3) #define GEN_TRANS_SHADD(SHAMT) = \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ - REQUIRE_EXT(ctx, RVB); = \ + REQUIRE_ZBA(ctx); = \ return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); = \ } =20 @@ -614,7 +620,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, = \ arg_sh##SHAMT##add_uw *a) \ { \ REQUIRE_64BIT(ctx); \ - REQUIRE_EXT(ctx, RVB); \ + REQUIRE_ZBA(ctx); \ return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \ } =20 @@ -624,14 +630,16 @@ GEN_TRANS_SHADD_UW(3) =20 static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) { - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_add_tl(ret, arg1, arg2); + TCGv t =3D tcg_temp_new(); + tcg_gen_ext32u_tl(t, arg1); + tcg_gen_add_tl(ret, t, arg2); + tcg_temp_free(t); } =20 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } =20 @@ -643,6 +651,6 @@ static void gen_slli_uw(TCGv dest, TCGv src, target_lon= g shamt) static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688860544682.1199086493464; Fri, 3 Sep 2021 10:07:40 -0700 (PDT) Received: from localhost ([::1]:49300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCfD-00016z-HF for importer@patchew.org; Fri, 03 Sep 2021 13:07:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYy-0007ID-Kj for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:12 -0400 Received: from mail-lf1-x12b.google.com ([2a00:1450:4864:20::12b]:36655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYv-0004zs-9L for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:12 -0400 Received: by mail-lf1-x12b.google.com with SMTP id c8so13012046lfi.3 for ; Fri, 03 Sep 2021 10:01:08 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sSQEPWASEFCKIe8qVM7WpjgOoUbV16zrv4O67np4u9E=; b=nxuq+4M93792aY5QcZcfmcjiTCZ1ICARrURrfdkRIPt5le6v635RciwOStnn0ION9r JQtmeJEDCWDTQ4bCeybxhzNYNNjJiim/ozA/TyUR+Vb3xu4o3SlRVpc4zTd2eEHgZN7y t2cpnWtyEBX0pXPGRwdiFt9ylUXD5U42m2I77iLEGSUJaCgodlrPshialAE/Nq8KjSVu VVLqhJLZOA/3l8MEdu7liqUB/SnLNKgjsvFME/NFqeWf6S5b0eifQYyxhZcjsGnbZhko iSI7I7ODyW/UwNZd4qWqJFFFNyuVJSFvVklnpKvpxgtzQwINd1srYurj/XFy1sqOXJO1 EkNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sSQEPWASEFCKIe8qVM7WpjgOoUbV16zrv4O67np4u9E=; b=ISilYmqpED6a8tv/1cDCVFogEKmK3RDqUu8uSZFrjyANFlFwBUk/QZikYN95+6cmHm 2GbMxWAePrOFnRcanGwU4vfmlhBg+T8iyse6XTFPORl8twZMhI2EIcwH73lbimK4CjyX jJ7ZiYYi0qCgehyw6Ny/etDu8Oi2GJikgCS8cDPx5Jj5n4x1oJ6ZNmGEZWJHPcZFJKvW co4tQQUC55GXvogPXXk2qyaXq62eXIW3VXWsUuso1rqAxFnsLCrjxKbR1Fl3ikXsZ8Fj TIWK8aicfvyaJjUftVUcCtmCEqiQKYOw2ElJS38EuI07+cqni5cWjMBchvU2y5/J8z+q UfEA== X-Gm-Message-State: AOAM53108Lp6nqzG3h39bI3VfmJ7XCoutq+RNnQMlbBgsGGBpyB/OV+p kbapUvOUgNqbXjoOKMk8/Qk0Di+xGoEmVB5FjqU= X-Google-Smtp-Source: ABdhPJwNZx0NeyFvKMu/FRXZoDG5ruph7OEJfQJBGu7U9Jou9H9U6KiecsyPQKYQ83wUGrBNNFmd9g== X-Received: by 2002:a05:6512:1586:: with SMTP id bp6mr3517298lfb.509.1630688467467; Fri, 03 Sep 2021 10:01:07 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Date: Fri, 3 Sep 2021 19:00:49 +0200 Message-Id: <20210903170100.2529121-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12b.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688860882100001 Content-Type: text/plain; charset="utf-8" For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding space currently reserves a wider shamt-field (for use is a future RV128 ISA), setting the additional bit to 1 will not map to slli.uw for RV64 and needs to be treated as an illegal instruction. Note that this encoding being reserved for a future RV128 does not imply that no other instructions for RV64-only could be added in this encoding space in the future. As the implementation is separate from the gen_shifti helpers, we keep it that way and add the check for the shamt-width here. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v9: - Rebased to 8880cc4362. Changes in v3: - Instead of defining a new decoding format, we treat slli.uw as if it had a 7bit-wide field for shamt (the 7th bit is reserved for RV128) and check for validity of the encoding in C code. target/riscv/insn_trans/trans_rvb.c.inc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 91da7c5853..77114889de 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_= uw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBA(ctx); + + /* + * The shamt field is only 6 bits for RV64 (with the 7th bit + * remaining reserved for RV128). If the reserved bit is set + * on RV64, the encoding is illegal. + */ + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688975199494.2304552934586; Fri, 3 Sep 2021 10:09:35 -0700 (PDT) Received: from localhost ([::1]:54730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCh4-0004qA-4O for importer@patchew.org; Fri, 03 Sep 2021 13:09:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYz-0007Jf-MJ for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: from mail-lj1-x22b.google.com ([2a00:1450:4864:20::22b]:33743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYx-000534-Lh for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: by mail-lj1-x22b.google.com with SMTP id s12so10572615ljg.0 for ; Fri, 03 Sep 2021 10:01:11 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MlvZycGLKdvFwSDPG1Qq4HAJkbFd1XEZk3GKCDbKdoY=; b=Tj+cfKFMfYtFHRjGIXh03FDK+rX7QtmG5lvjZNrGhtjT2hjsYUCYZRkgy8Xl/XUtl6 UnPWXcGUsmsjU/oPJ7nD4XiCDKRy/YTxPkDPZPfdn3ZvfxxbMXhjmK2ZDZZDwpDjopgF HdvkxmzXBAWhpsRUz07Mjv2YGotXCJZyIMiIaix38yE7juGxkE3+AFAYtiJ4TEYvg9oD BTkOlvqRLhKJHAdhBhirH+JGzGLzZDj3FwkyrpEjc8o+02bNXrHd0LUA58aGtFayvG2E k3s/0YMjbGYkb0Bq6qm3rxArUBlTRKdAbH4u/0aPNZ93hHuvTvJSiSwyNiv4OTC/xXVG CCag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MlvZycGLKdvFwSDPG1Qq4HAJkbFd1XEZk3GKCDbKdoY=; b=cBkTBbTj7PjxEf/SUxNN/0Dr3DkntVmnsvdqnn5QhwfxZisooP9eGLTvJGCp4SBHg0 Cu5j/aQeX1ls0e7rt5KbnkjZ89rdWUixRi2HTJqMKEGyRr2ryv9x6bD6hP8QkOO/yzlU fY7YbmPbH/hqqJkWK4nQYavdB00XJiwdZsQXnMdGtWMlv4WVXMYy2PnE+FiSAMtNXTSe 2J2ou9/AcLf8AhQT9cBPF10KbycAR3gu22DTnaQPl3XypuxtGFT1/+/bESCB7Bz+c/H1 Gdvs2qFp9OMomiSirL5FPYc+IWrb/EFGA29c6+2riSvkBrFYJTuOSXRdL7Ubxbie604q I4Sw== X-Gm-Message-State: AOAM533MzNmZFHeu7LA1FtCbnB6m6Xb7rNAE76Fq2Yum6ZwKGcRjBihA KHoMNK37za+asj+XPNM/3E3jgjLLSiUO4ckrYVM= X-Google-Smtp-Source: ABdhPJyMat31uGB9NTEwLlXVBrTZCnCVgTThX1gFA0LYi+5+RXbavqL6kDwEjep51WeTVdOSbQhUrg== X-Received: by 2002:a2e:8457:: with SMTP id u23mr18050ljh.3.1630688468289; Fri, 03 Sep 2021 10:01:08 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 04/14] target/riscv: Remove the W-form instructions from Zbs Date: Fri, 3 Sep 2021 19:00:50 +0200 Message-Id: <20210903170100.2529121-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688976307100003 Content-Type: text/plain; charset="utf-8" Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extenstion and have not been present in the binutils patches circulating in January 2021. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove the W-form instructions from Zbs in a separate commit. target/riscv/insn32.decode | 7 ---- target/riscv/insn_trans/trans_rvb.c.inc | 56 ------------------------- 2 files changed, 63 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 86f1166dab..b499691a9e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -717,10 +717,6 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 =20 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -bsetw 0010100 .......... 001 ..... 0111011 @r -bclrw 0100100 .......... 001 ..... 0111011 @r -binvw 0110100 .......... 001 ..... 0111011 @r -bextw 0100100 .......... 101 ..... 0111011 @r slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r @@ -728,9 +724,6 @@ rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -bsetiw 0010100 .......... 001 ..... 0011011 @sh5 -bclriw 0100100 .......... 001 ..... 0011011 @sh5 -binviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 77114889de..0763d0f836 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -418,62 +418,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw= *a) return gen_arith(ctx, a, EXT_NONE, gen_packuw); } =20 -static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_NONE, gen_bset); -} - -static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset); -} - -static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_NONE, gen_bclr); -} - -static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr); -} - -static bool trans_binvw(DisasContext *ctx, arg_binvw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_NONE, gen_binv); -} - -static bool trans_binviw(DisasContext *ctx, arg_binviw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv); -} - -static bool trans_bextw(DisasContext *ctx, arg_bextw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_NONE, gen_bext); -} - static bool trans_slow(DisasContext *ctx, arg_slow *a) { REQUIRE_64BIT(ctx); --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688813795923.155980911375; Fri, 3 Sep 2021 10:06:53 -0700 (PDT) Received: from localhost ([::1]:46580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCeS-0007eB-Ca for importer@patchew.org; Fri, 03 Sep 2021 13:06:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYz-0007Ju-T6 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:40935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYx-00052Y-Ld for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: by mail-lf1-x131.google.com with SMTP id bq28so12976329lfb.7 for ; Fri, 03 Sep 2021 10:01:10 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VvgWOZqK8pNWtJT1QOLtHEj6PXlVf5p9ZZ9y5BHBbi0=; b=JmZZgQJtQOwFNUv1AeAXX7LzKkgDV/gaJD4MZwpibiilAcUrRdQii/VQRyahz6V7LD kpaw/rcJ2kiQ5EH1SgZbtBzEmn5Bx+g58+qRNUc4MaeG+UiTygGlOmNu6BmGPzYiKVds 5wA38cCpC/R/Sb5Iz5Ri43kB+ohMkO674GLt4uPhk8yDkJiGPyQZG8v/q8XCzWaqFr1C 27EfZzay9ydill3peWFYtemQu/R+Owv8MzyXSKYjlnwXZ4vzwydhHHEtzly0GsKmCSNF pqevaYQlETOAZ9wyXNTe5EAPDURHTEsxedYVEzx7o2z8V3mERlqS8imlpiLWA8WFhM7U K5Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VvgWOZqK8pNWtJT1QOLtHEj6PXlVf5p9ZZ9y5BHBbi0=; b=DTaoh2xzSzpdHA1s6qUHHwaXZS00YZR5yUYuBJvGoOMygIJ8Swandh0bwR9Zi2/7Yt E6OcI3zmgGQYEDdQL1Zwa4U5HvKvDPh/tyZ3c3TyWM0+OiNIm1mtxO0EKPJpBHtxuDXd 4gAUYyG7Hn3S+KX7sa3q49np1p225GekQz0/HEJC8XnUYkRghl279GVerPoJPp2yWOhe czU9iGOi+aaVolpnmsjtan3D0cSO9D9a0KR+MPoY9n5iLiWh15408TFcB5qYhvptxcAp JjGL3VVq2XgaB2XuiqhuAEU5/SOsO6bNrS4N6qobBt+RWtlEGDYtSWXt4SF0XlTeBbe9 FrYA== X-Gm-Message-State: AOAM533HolBOLhB6fRXHkeSdTFQnn1c+gw6yj5IXuge6lvTTeFHjarPi edvM1ze2qlyDL2o14TUw7aE64aJRGTffZbNw1Ng= X-Google-Smtp-Source: ABdhPJywAyDVsrWi6N0g4vBMpiAEG5iePX6c11tlJA/8qDHvKaRXCJ4/lrJEgbkmDH0stDs+wjsldg== X-Received: by 2002:a05:6512:23a0:: with SMTP id c32mr3474192lfv.55.1630688469044; Fri, 03 Sep 2021 10:01:09 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Date: Fri, 3 Sep 2021 19:00:51 +0200 Message-Id: <20210903170100.2529121-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688814579100001 Content-Type: text/plain; charset="utf-8" The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove shift-one instructions in a separate commit. target/riscv/insn32.decode | 8 --- target/riscv/insn_trans/trans_rvb.c.inc | 70 ------------------------- 2 files changed, 78 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b499691a9e..e0f6e315a2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -693,8 +693,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -704,8 +702,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -717,15 +713,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 =20 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 0763d0f836..860fbc3775 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *= a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } =20 -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -418,38 +380,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw= *a) return gen_arith(ctx, a, EXT_NONE, gen_packuw); } =20 -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 =3D tcg_temp_new_i32(); --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688815182955.3250674084977; Fri, 3 Sep 2021 10:06:55 -0700 (PDT) Received: from localhost ([::1]:46722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCeU-0007jk-1x for importer@patchew.org; Fri, 03 Sep 2021 13:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ1-0007Mv-8q for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:15 -0400 Received: from mail-lj1-x22b.google.com ([2a00:1450:4864:20::22b]:34814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYz-00054U-5v for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:14 -0400 Received: by mail-lj1-x22b.google.com with SMTP id f2so10570998ljn.1 for ; Fri, 03 Sep 2021 10:01:12 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yMMCcuXLdyaBPmCUgPPerhqNmkQPKptjtBMuOYzNvJs=; b=IMbGo6Bhtj/hDuBsuwl0DgAKHW8OnHXFbvQYen7AL2c2r2VAJY0WxiNB1OdNiXcr0B xCvmq+7vHXFFQJZKn2Xp1d9lrTB4i62NY1wKKRIu8AjZPYZFb2PnPD86+wPwbuDlNsmq lSq2EGugXTBfdydEJNvPcZQzBK9JdSIEsGuqykpxlN7tiVwqDLtksMI1SoZWLV80gorg 7ihtweuX4VjhgMVFvNAv6WJj3goavGyOhmzmTw2SRSvG4OLKaJAMYrRELfsF8vFUlRAl KjEYy75qb9xVNlH0yFtNMJ4BYA/6Fq9TaTuURhK/hFfCFcHSQdqB+jM6PwRyzi12B0oM s1tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yMMCcuXLdyaBPmCUgPPerhqNmkQPKptjtBMuOYzNvJs=; b=ZqM//wV3/IbXq99CrETHgJCOXkcw6VTvp2O5qxWMxUMKJorejsyLfILt+uNLlF4U21 iGsbiKe+O4frepZ1O9k5xsDZZG2l6TEEiFDwN4TH/Uzdx88YEBomGLGwwic+DyNyWfr8 7pEgV3DYcU4iPoiN+xPnRr1p15d60P2cUdo3HX0K91/QpDqWVxO6P0Sdoj5Hs1ef/qYh xGdXcBv5cS36b0Y8iqkyM/menQrhW28PQFTr6sj+ljPDjKSbwnN+3bEY9soHrPWaVUaR y9Ehwfx+TcAW44PG2fkKobTkLrCkiDpP1EJjfM5sqQHwTA7TR5oL8J0oK+hTjz4oaabr 2tpA== X-Gm-Message-State: AOAM531AtkiR+HW+P2vB7QjlHAAFKW4n+UL2B9spw6cS31CjmD5sIJLJ ZLuzdsUG26rbXqnK56fVinCXCwS4dlkfPX1JIGk= X-Google-Smtp-Source: ABdhPJxW+0H9EMjC/NmC0e+kkwL9Bp/g+UdQoT1Op83YPp9XbjEgqWlpHgG05zu35rTkNOhMV3YJig== X-Received: by 2002:a05:651c:490:: with SMTP id s16mr30365ljc.214.1630688469819; Fri, 03 Sep 2021 10:01:09 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 06/14] target/riscv: Reassign instructions to the Zbs-extension Date: Fri, 3 Sep 2021 19:00:52 +0200 Message-Id: <20210903170100.2529121-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688816598100003 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and its use for qualifying the Zba instructions) are moved into a separate commit. target/riscv/insn32.decode | 17 +++++++++-------- target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++---------- 2 files changed, 24 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e0f6e315a2..35a3563ff4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -689,19 +689,11 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r -bset 0010100 .......... 001 ..... 0110011 @r -bclr 0100100 .......... 001 ..... 0110011 @r -binv 0110100 .......... 001 ..... 0110011 @r -bext 0100100 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r =20 -bseti 00101. ........... 001 ..... 0010011 @sh -bclri 01001. ........... 001 ..... 0010011 @sh -binvi 01101. ........... 001 ..... 0010011 @sh -bexti 01001. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -722,3 +714,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 +# *** RV32 Zbs Standard Extension *** +bclr 0100100 .......... 001 ..... 0110011 @r +bclri 01001. ........... 001 ..... 0010011 @sh +bext 0100100 .......... 101 ..... 0110011 @r +bexti 01001. ........... 101 ..... 0010011 @sh +binv 0110100 .......... 001 ..... 0110011 @r +binvi 01101. ........... 001 ..... 0010011 @sh +bset 0010100 .......... 001 ..... 0110011 @r +bseti 00101. ........... 001 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 860fbc3775..ee8bc7435f 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the RVB draft and Zba Standard Extensio= n. + * RISC-V translation routines for the RVB draft Zb[as] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,11 +24,16 @@ } \ } while (0) =20 +#define REQUIRE_ZBS(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ + return false; \ + } \ +} while (0) + static void gen_clz(TCGv ret, TCGv arg1) { tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } - static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); @@ -165,13 +170,13 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) =20 static bool trans_bset(DisasContext *ctx, arg_bset *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, EXT_NONE, gen_bset); } =20 static bool trans_bseti(DisasContext *ctx, arg_bseti *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset); } =20 @@ -187,13 +192,13 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) =20 static bool trans_bclr(DisasContext *ctx, arg_bclr *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, EXT_NONE, gen_bclr); } =20 static bool trans_bclri(DisasContext *ctx, arg_bclri *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr); } =20 @@ -209,13 +214,13 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) =20 static bool trans_binv(DisasContext *ctx, arg_binv *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, EXT_NONE, gen_binv); } =20 static bool trans_binvi(DisasContext *ctx, arg_binvi *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv); } =20 @@ -227,13 +232,13 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) =20 static bool trans_bext(DisasContext *ctx, arg_bext *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, EXT_NONE, gen_bext); } =20 static bool trans_bexti(DisasContext *ctx, arg_bexti *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } =20 --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688890671974.4767352047586; Fri, 3 Sep 2021 10:08:10 -0700 (PDT) Received: from localhost ([::1]:50358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCfh-0001pB-KN for importer@patchew.org; Fri, 03 Sep 2021 13:08:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ1-0007PG-TX for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:15 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]:37857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYy-00053o-GO for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:15 -0400 Received: by mail-lf1-x132.google.com with SMTP id l10so12990125lfg.4 for ; Fri, 03 Sep 2021 10:01:11 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pxdueKs5pACRF4frC+TAZoaDfUvLv6Pw06AO0YA55Iw=; b=mm6Obmv8xbkfEPsGXZOUFzk3uB70ouVZvmsHc07GxVyY26XeyL6aKaiZnwBW8AWyOx mGeXdtsZexCzMDOuAleFT8zbtsyMwUQT1HDVSs7VaW3EFcC36aZXDyycOArGffnnjWsg UXRSxKmUbfOQhPMC14Q9Pc3mhh3YrBocntPZqQhInZuYV71w7gU8e36yyqyc180amjzg cdwgdAeUp6ywKO67RWPDN3u0wUpFb8qzvNxcEesNeoDYyEK03ZUcQpoPAqLH6zsVUGQw 0z8xDH/5qUYll3VkIpI2GhedQia13+C+4HZdb2/lzUtprm6UFBOE/jxODnKU0Etnwnw0 otsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pxdueKs5pACRF4frC+TAZoaDfUvLv6Pw06AO0YA55Iw=; b=Ho4Z74HUPXlDIdU8stW6LGROHEHYDDPMJZcwbyZHxvaOqo24Rbwn1Byn+FgR0K4vYJ fVvsgeTjYJSO40mzowWS/H/nYgIiVeVm7k8iYMVOZmh9UZcUuRmj9jrYacrhkBc7nf/A 4JBsKz5KtrZOJvkTvYMMoMmFBTPBETaKnWFEuE9BquLWx7eQ5Pvdfvpzogpj89X67kX5 0SBRSrzKg8OyvVuPBjibuxMJ7BSVIJdRvkTYVXCjNTck+2+ze7TGgREXC94dOsvzjlCh jNKDiVVSxMSvRVueXhUHjR3awO/yaWsb3CGfKuu5DKf4WECo6kNkTFowhhveaQkaIYYF CuIA== X-Gm-Message-State: AOAM530M9zti7ZMFiFvKWADkW/mJPIS+lqlPPoGk4uS+nVykgFAklvth EiY8kCJgvDZXugrtwSdrFFSl9HaEOIq1r9s1pPA= X-Google-Smtp-Source: ABdhPJwluweCpK7+4U3plnwr6DTCn3wcE3MNwEc3D0A4FKlGeuxiwQbuJb8KY1qXwpa87IyDqz5vAg== X-Received: by 2002:a19:3804:: with SMTP id f4mr3441831lfa.81.1630688470598; Fri, 03 Sep 2021 10:01:10 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 07/14] target/riscv: Add instructions of the Zbc-extension Date: Fri, 3 Sep 2021 19:00:53 +0200 Message-Id: <20210903170100.2529121-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x132.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688890977100001 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v9: - Rebased to 8880cc4362. Changes in v6: - Move gen_clmulh to trans_rvb.c.inc, as per Richard H's request. Changes in v5: - Introduce gen_clmulh (as suggested by Richard H) and use to simplify trans_clmulh(). Changes in v3: - This adds the Zbc instructions as a spearate commit. - Uses a helper for clmul/clmulr instead of inlining the calculation of the result (addressing a comment from Richard Henderson). target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++ target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 5 ++++ target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++- 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 5b2f795d03..73be5a81c7 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -3,6 +3,7 @@ * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulon= g rs2) { return do_gorc(rs1, rs2, 32); } + +target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) +{ + target_ulong result =3D 0; + + for (int i =3D 0; i < TARGET_LONG_BITS; i++) { + if ((rs2 >> i) & 1) { + result ^=3D (rs1 << i); + } + } + + return result; +} + +target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) +{ + target_ulong result =3D 0; + + for (int i =3D 0; i < TARGET_LONG_BITS; i++) { + if ((rs2 >> i) & 1) { + result ^=3D (rs1 >> (TARGET_LONG_BITS - i - 1)); + } + } + + return result; +} diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 460eee9988..8a318a2dbc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 35a3563ff4..1658bb4217 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -714,6 +714,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 +# *** RV32 Zbc Standard Extension *** +clmul 0000101 .......... 001 ..... 0110011 @r +clmulh 0000101 .......... 011 ..... 0110011 @r +clmulr 0000101 .......... 010 ..... 0110011 @r + # *** RV32 Zbs Standard Extension *** bclr 0100100 .......... 001 ..... 0110011 @r bclri 01001. ........... 001 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index ee8bc7435f..a940441ae1 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the RVB draft Zb[as] Standard Extension. + * RISC-V translation routines for the Zb[acs] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) =20 +#define REQUIRE_ZBC(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZBS(ctx) do { \ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ return false; \ @@ -543,3 +549,27 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_= uw *a) =20 return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } + +static bool trans_clmul(DisasContext *ctx, arg_clmul *a) +{ + REQUIRE_ZBC(ctx); + return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul); +} + +static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_clmulr(dst, src1, src2); + tcg_gen_shri_tl(dst, dst, 1); +} + +static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a) +{ + REQUIRE_ZBC(ctx); + return gen_arith(ctx, a, EXT_NONE, gen_clmulh); +} + +static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a) +{ + REQUIRE_ZBC(ctx); + return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr); +} --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630689064861153.84050468278951; Fri, 3 Sep 2021 10:11:04 -0700 (PDT) Received: from localhost ([::1]:58600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCiV-0007gx-Lx for importer@patchew.org; Fri, 03 Sep 2021 13:11:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ2-0007SD-U4 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:16 -0400 Received: from mail-lf1-x12f.google.com ([2a00:1450:4864:20::12f]:37855) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ0-00055f-JX for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:16 -0400 Received: by mail-lf1-x12f.google.com with SMTP id l10so12990312lfg.4 for ; Fri, 03 Sep 2021 10:01:14 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bbPt960q2YowtYuudfgv+XFdnmCjrjr8N9JIOHBeHtI=; b=vMfK6JwrIYeMsLOP4jXgkCE5Vu189IwVafulmd7jvd1EHxD00XmQgQzrv23b0tP7AF ky0bb9u0GOcOYig+uA2RB1CJEosk8I6kibrcExrti8hzzsm4xyeCDDLt8JAAmj+Ma3Ak DcKSxtlnvgd3iW2Z6z/sMIsJvvrme7778Iy/Qc1TiorUuiU/Ph7Efuiv8uxtAPA5yZ/H 9QeDahlaoTDLkXCsWIFtQD1tW/jbT1LMYsfYXlbdFikYqdjCeukf1AmmUq1TqRiZjcYz UZ3O4LScF/3qs50NudBZ+J0yZmDOQt8BMle6299b3A3uwdB3rLQOF+apZ3/O+iLLgQIF C2Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bbPt960q2YowtYuudfgv+XFdnmCjrjr8N9JIOHBeHtI=; b=P93E8bps+l6S022aiIJjul84NuZoRkd3bvTRA7VpLaE6Q9FcDkV/Ws/UxUhqAIB8IA nTgEfJzQ/rvf5SHzzSqaCx0Atk5gvAc8MvY4pCKWsasCsDrNd7f+/lYGu7pk67ss7L05 w7GfMqrE/7T9hwv48EH5dC5f3k6J+kuoZQGg89dEXn1KpzfMX5LlZfOOKmVb220VT8dx MdiYJhAiTehnQkCm/SCHwa4q9intIx0h0clUSY8yvFUnawT854S3N7NWQRar1wIY23Rs zMHeEDm5dNkP5s8FZnIqtfbgCcNLirPE5/3cSGRl5EOmmWbM2rJo2fQeopTCEsC6xQ+W uVdw== X-Gm-Message-State: AOAM532UVS1ocmh2kn/b13avelam2sUp8Yp6OE4YZHldXonyQLpo9NHC 6Wc8DBsfXNA5XzsL5e/NRkvOXHWFMj9SVnAKAeQ= X-Google-Smtp-Source: ABdhPJx4rEpd+wb0SREpbR0a9XWEHAbxqSjYmPGACCAMzFE7DNi8AlVTBM2YFC2iKa5tea3FswXLaA== X-Received: by 2002:ac2:5498:: with SMTP id t24mr880471lfk.367.1630688471409; Fri, 03 Sep 2021 10:01:11 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 08/14] target/riscv: Reassign instructions to the Zbb-extension Date: Fri, 3 Sep 2021 19:00:54 +0200 Message-Id: <20210903170100.2529121-9-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630689065371100002 Content-Type: text/plain; charset="utf-8" This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - The changes to the Zbb instructions (i.e. use the REQUIRE_ZBB macro) are now in a separate commit. target/riscv/insn32.decode | 40 ++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++----------- 2 files changed, 50 insertions(+), 41 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1658bb4217..a509cfee11 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -672,45 +672,47 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r sh3add_uw 0010000 .......... 110 ..... 0111011 @r slli_uw 00001 ............ 001 ..... 0011011 @sh =20 -# *** RV32B Standard Extension *** +# *** RV32 Zbb Standard Extension *** +andn 0100000 .......... 111 ..... 0110011 @r clz 011000 000000 ..... 001 ..... 0010011 @r2 -ctz 011000 000001 ..... 001 ..... 0010011 @r2 cpop 011000 000010 ..... 001 ..... 0010011 @r2 +ctz 011000 000001 ..... 001 ..... 0010011 @r2 +max 0000101 .......... 110 ..... 0110011 @r +maxu 0000101 .......... 111 ..... 0110011 @r +min 0000101 .......... 100 ..... 0110011 @r +minu 0000101 .......... 101 ..... 0110011 @r +orn 0100000 .......... 110 ..... 0110011 @r +rol 0110000 .......... 001 ..... 0110011 @r +ror 0110000 .......... 101 ..... 0110011 @r +rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 - -andn 0100000 .......... 111 ..... 0110011 @r -orn 0100000 .......... 110 ..... 0110011 @r xnor 0100000 .......... 100 ..... 0110011 @r + +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 +rolw 0110000 .......... 001 ..... 0111011 @r +roriw 0110000 .......... 101 ..... 0011011 @sh5 +rorw 0110000 .......... 101 ..... 0111011 @r + +# *** RV32B Standard Extension *** pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r -min 0000101 .......... 100 ..... 0110011 @r -minu 0000101 .......... 101 ..... 0110011 @r -max 0000101 .......... 110 ..... 0110011 @r -maxu 0000101 .......... 111 ..... 0110011 @r -ror 0110000 .......... 101 ..... 0110011 @r -rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r =20 -rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** -clzw 0110000 00000 ..... 001 ..... 0011011 @r2 -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 - packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -rorw 0110000 .......... 101 ..... 0111011 @r -rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index a940441ae1..02f2913063 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zb[acs] Standard Extension. + * RISC-V translation routines for the Zb[abcs] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) =20 +#define REQUIRE_ZBB(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZBC(ctx) do { \ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ return false; \ @@ -40,9 +46,10 @@ static void gen_clz(TCGv ret, TCGv arg1) { tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } + static bool trans_clz(DisasContext *ctx, arg_clz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_ZERO, gen_clz); } =20 @@ -53,31 +60,31 @@ static void gen_ctz(TCGv ret, TCGv arg1) =20 static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_ZERO, gen_ctz); } =20 static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } =20 static bool trans_andn(DisasContext *ctx, arg_andn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl); } =20 static bool trans_orn(DisasContext *ctx, arg_orn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl); } =20 static bool trans_xnor(DisasContext *ctx, arg_xnor *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl); } =20 @@ -124,37 +131,37 @@ static bool trans_packh(DisasContext *ctx, arg_packh = *a) =20 static bool trans_min(DisasContext *ctx, arg_min *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl); } =20 static bool trans_max(DisasContext *ctx, arg_max *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl); } =20 static bool trans_minu(DisasContext *ctx, arg_minu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl); } =20 static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl); } =20 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); } =20 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); } =20 @@ -250,19 +257,19 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti = *a) =20 static bool trans_ror(DisasContext *ctx, arg_ror *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); } =20 static bool trans_rori(DisasContext *ctx, arg_rori *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); } =20 static bool trans_rol(DisasContext *ctx, arg_rol *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } =20 @@ -335,7 +342,7 @@ static void gen_clzw(TCGv ret, TCGv arg1) static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_ZERO, gen_clzw); } =20 @@ -348,14 +355,14 @@ static void gen_ctzw(TCGv ret, TCGv arg1) static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, EXT_NONE, gen_ctzw); } =20 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); ctx->w =3D true; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } @@ -412,7 +419,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); ctx->w =3D true; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } @@ -420,7 +427,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); ctx->w =3D true; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } @@ -446,7 +453,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); ctx->w =3D true; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688686643805.2535735417666; Fri, 3 Sep 2021 10:04:46 -0700 (PDT) Received: from localhost ([::1]:41112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCcP-0003oc-L8 for importer@patchew.org; Fri, 03 Sep 2021 13:04:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ2-0007QN-AI for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:16 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]:41655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ0-00055E-4h for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:16 -0400 Received: by mail-lf1-x134.google.com with SMTP id y34so12970281lfa.8 for ; Fri, 03 Sep 2021 10:01:13 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dFXolZKt0nDbC1saRJW1HJvG5PiI8fg5A/41EL/oZeQ=; b=Hm0BaW6QP0/gnWQ+CXwHys9lTDYvfxr7HgOd9398QVjXSO+OV+IBOtzc8wICxNOfxc 6YFWysmbghnvp5rxAax5f+/Vm4gCSBSrTeFoNvPU86DXr/r0FfVVjVlQUfZ8YBBoYGjw vv2mqBLzEeDKlG2MhcMVfL8cAsy18btkPwmd4xu596QsJwIT8ynNipJh0QuQ5qTCgb7d NwhwrCt6HpILUgvwaxWK2vWlcUnHA6+DCpYwbjNXpCwc5G8aLxyJpRbK/EU9H7r3leCc OQgBptXJgVmVDnpP+VbpJZ2Lu5RPomRrTj4/O0J7Jy7K/BMEjpT0TBRCKbF6Ht5KaA8E gjUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dFXolZKt0nDbC1saRJW1HJvG5PiI8fg5A/41EL/oZeQ=; b=rtzTel49gBiKB3gOijgkPYcVSTOUohb4lpzdYuydjM3UdpesmJ76nBeuh6nsMFKaIU GWRoWQusjDNw8oRvUQfZL0YmOjCmaoyE1Z98enuAepLbfCJ6q5scdfXLqiPcoDJIYXrH zrqy3+nHocBuaq1bNWpLfdMUsHVhiAe96ngCvw1k+lMfqymYvI7JUkYAA6Vy81WfGu7T DJBUH5wltDLKiPLfoAeQwsZXKWAytfvj4DDy4hJfgCDipESzvgh0+dMttE36Pp+ynjUm Ovv6sAm99qEgxz/2ZCRt42ZFdQcagw3ZaPw4RQANwpIF0MAoiEPHZBg9LOONeqBbufh/ uNvw== X-Gm-Message-State: AOAM531pxqeA5jGEKc0KLMDdhICVyeTEXm+lCgWnpFo86e9S3rlq/qSA rIubxwy19TTeZkiLr/AibA43fAComQeOLl4pBV4= X-Google-Smtp-Source: ABdhPJzSZicyqI0cZ3ykyrH1SzGiEfIq2PjMW8QeNvFYjdsyMTKNtuz1p+nzTE1rtYeiLWUqI3tdYQ== X-Received: by 2002:a05:6512:241:: with SMTP id b1mr3468676lfo.99.1630688472256; Fri, 03 Sep 2021 10:01:12 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Date: Fri, 3 Sep 2021 19:00:55 +0200 Message-Id: <20210903170100.2529121-10-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688688936100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v9: - Picked up Alistair's Reviewed-by, after patman had failed to catch it for v8. Changes in v8: - Optimize orc.b further by reordering the shift/and, updating the comment to reflect that we put the truth-value into the LSB, and putting the (now only) constant in a temporary - Fold the final bitwise-not into the second and, using and andc. Changes in v7: - Free TCG temporary in gen_orc_b(). Changes in v6: - Fixed orc.b (now passes SPEC w/ optimized string functions) by adding the missing final negation. Changes in v4: - Change orc.b to implementation suggested by Richard Henderson Changes in v3: - Moved orc.b and gorc/gorci changes into separate commit. - Using the simpler orc.b implementation suggested by Richard Henderson target/riscv/bitmanip_helper.c | 26 ----------------- target/riscv/helper.h | 2 -- target/riscv/insn32.decode | 6 +--- target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++-------------- 4 files changed, 18 insertions(+), 55 deletions(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 73be5a81c7..bb48388fcd 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -64,32 +64,6 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulon= g rs2) return do_grev(rs1, rs2, 32); } =20 -static target_ulong do_gorc(target_ulong rs1, - target_ulong rs2, - int bits) -{ - target_ulong x =3D rs1; - int i, shift; - - for (i =3D 0, shift =3D 1; shift < bits; i++, shift <<=3D 1) { - if (rs2 & shift) { - x |=3D do_swap(x, adjacent_masks[i], shift); - } - } - - return x; -} - -target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2) -{ - return do_gorc(rs1, rs2, TARGET_LONG_BITS); -} - -target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2) -{ - return do_gorc(rs1, rs2, 32); -} - target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) { target_ulong result =3D 0; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 8a318a2dbc..a9bda2c8ac 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -61,8 +61,6 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) /* Bitmanip */ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a509cfee11..59202196dc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -681,6 +681,7 @@ max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r +orc_b 001010 000111 ..... 101 ..... 0010011 @r2 orn 0100000 .......... 110 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r @@ -702,19 +703,14 @@ pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r -gorc 0010100 .......... 101 ..... 0110011 @r - grevi 01101. ........... 101 ..... 0010011 @sh -gorci 00101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r -gorcw 0010100 .......... 101 ..... 0111011 @r =20 greviw 0110100 .......... 101 ..... 0011011 @sh5 -gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 02f2913063..311174ea40 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -295,16 +295,27 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi = *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi); } =20 -static bool trans_gorc(DisasContext *ctx, arg_gorc *a) +static void gen_orc_b(TCGv ret, TCGv source1) { - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc); + TCGv tmp =3D tcg_temp_new(); + TCGv ones =3D tcg_constant_tl(dup_const(MO_8, 0x01)); + + /* Set lsb in each byte if the byte was zero. */ + tcg_gen_sub_tl(tmp, source1, ones); + tcg_gen_andc_tl(tmp, tmp, source1); + tcg_gen_shri_tl(tmp, tmp, 7); + tcg_gen_andc_tl(tmp, ones, tmp); + + /* Replicate the lsb of each byte across the byte. */ + tcg_gen_muli_tl(ret, tmp, 0xff); + + tcg_temp_free(tmp); } =20 -static bool trans_gorci(DisasContext *ctx, arg_gorci *a) +static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a) { - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_ZERO, gen_orc_b); } =20 #define GEN_SHADD(SHAMT) \ @@ -474,22 +485,6 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw= *a) return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev); } =20 -static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc); -} - -static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc); -} - #define GEN_SHADD_UW(SHAMT) \ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ { \ --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630689183454208.66367813923353; Fri, 3 Sep 2021 10:13:03 -0700 (PDT) Received: from localhost ([::1]:34838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCkQ-0002Ro-5e for importer@patchew.org; Fri, 03 Sep 2021 13:13:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ5-0007W4-9g for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:19 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]:44816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ1-00056j-4y for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:17 -0400 Received: by mail-lf1-x129.google.com with SMTP id s10so12953697lfr.11 for ; Fri, 03 Sep 2021 10:01:14 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Byfy05ziqCgv95xzCHpZBdafCiVDPBMWHY7L07p6tOg=; b=b951w8h3y9Cy1bZpH2Zh0v4UMaaNZ4zC/CyC2/CntVz3GnBbmfkjkARGZiMec2Od61 lhGAE/r14+Qsok68Vv0nPV4wlYXhrsMqgeocVtygUzTsJx+Fne5wiUNTkAw0Z4kIDkns IwkAt404MlCy856Q4G4Lng5cH3Uos/Omc9aVkkQ+ID/YopI9aMorXbBWDCvoJwBRYr8y +VXoRQZRUun/YU/0jaqh2vngZzIhAzkHD3J/+yrsk+ivRr2PkJLELFnesKl7vlA14xWQ 9ogl4MFAPf8bGJQ3t2ZRRbs1wgld6LFydG+ODW7L/hQ7+uFkls2BYSzD+ch5dc0xW8Q0 +How== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Byfy05ziqCgv95xzCHpZBdafCiVDPBMWHY7L07p6tOg=; b=s1oQnVOaMDPtCWjmiAFTPfCt4T9tupn7a3jaRhY9JphcTjZaVn7d3N3d2/L/uWV6XU t+jd5iRrOlRGw+6Xz+TE5GLklKltcy21RFh8L2wdfpgeFPjhB0sOBzsWbx2EYWqKKgJN y3gO/k4swvbsWHb6N14ChwL/JENG0xHBNyLPM7HMmMccX08tnh/PxI5ydrh1omsNXUuz Gc+Fgl9sCjhRk56ob7dSZbBFW7rlm3DWeN5q57IMXykwdO5y1O0y9PycRW5U7YgQZ/rc tYblvL1lNvuv7xAlXwCmTj8s/1Z0/i6/KLcap/Zj0Hd6SzBQHd/ueOv6UaVBR4IBdzt5 QS4Q== X-Gm-Message-State: AOAM530nSmSyu6MCVE3aIKi85Etzs4P3DrRuAAPAOPRpraG2eNh6LRpU 1xguuuv56cZlt5SyaC0ye/F8pJDVUyBnfBvY2k4= X-Google-Smtp-Source: ABdhPJx2a0dOJylIUEOFvqITiZrvM6yIUnTebOrudRGIXESxpqrRSiUrnLv9aP8GZEhkyo0z6D0DUA== X-Received: by 2002:a05:6512:401a:: with SMTP id br26mr3392203lfb.23.1630688473064; Fri, 03 Sep 2021 10:01:13 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 10/14] target/riscv: Add a REQUIRE_32BIT macro Date: Fri, 3 Sep 2021 19:00:56 +0200 Message-Id: <20210903170100.2529121-11-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630689183954100001 Content-Type: text/plain; charset="utf-8" With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Moved the REQUIRE_32BIT macro into a separate commit. target/riscv/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..7562b2f87c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -337,6 +337,12 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_32BIT(ctx) do { \ + if (!is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_64BIT(ctx) do { \ if (is_32bit(ctx)) { \ return false; \ --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630688978800690.0758151207901; Fri, 3 Sep 2021 10:09:38 -0700 (PDT) Received: from localhost ([::1]:55000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCh7-00052f-Lm for importer@patchew.org; Fri, 03 Sep 2021 13:09:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ4-0007V6-S9 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:18 -0400 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:43853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ1-00057O-Py for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:17 -0400 Received: by mail-lf1-x131.google.com with SMTP id h16so10126147lfk.10 for ; Fri, 03 Sep 2021 10:01:15 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NEEaIX0LvJEEMBShlhj2iDp242T4MN8HluiORAvdLpU=; b=lE/Lv+lqxRMPY195ZqEDFS86fXAxJPJiF4+q6pEsB/rK/sNshj78as/Jjm8icKjyNu oZi/IU4TsvQ8GgtxXjFozat7Y/Sk6RWx3MiPJziTwkyhNEcejynFYkypbsd/9THxZQST p39ClbeMAtXsqfvhbfv/vRK7XIZ+41Se+9bghuzebK1Me4wi78PswdPZ+JwojSwDZLkO lFixQ0z6UsuZEsauZDymzIYmAPzPLnTfhE8rzuAAqOle6V7o1JmttW6P9swja7l/rAJ3 g/p6YshKx4dvwRMIFsnb0gQLBUsKzHxmnU2CJEvyAnO09tPsJrmxwyBPAC+qQ9oO7h1S W4rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NEEaIX0LvJEEMBShlhj2iDp242T4MN8HluiORAvdLpU=; b=tkT9nFrYlKT8XkZtB8hkj/VAhZYR/KIqJ2vz/5cGTV/iyobH+/t7UxTwkLE4KfV/0n Nvc4rQkuMbSXlpVskVWtOG6mSM8dbPajKBEG57z2MmTGpDuyPY8FYdTERdsCUevCq9Cz y3/MywZE3Fly2Gr5rBAZIet1MdXt55f4lqtMhB4yqOfgGPTZtConbJuZQ6YW3NLC3HcE GYutrkTrGQNbCZAhsBbqygjazSW9mlhXLZaeMFydoxrYD0IPLCUvGp7mPYgRPNk9knNq Sj2m+OKwfS5Jfd6e5zpnF7YwLGvtvQrk8HNKozJ90fzmQH5ViXPzqk6OYu3P/fpDhx5Q PQSA== X-Gm-Message-State: AOAM532hzhqBqsfi/0i5ZUwOaLJ2W2XplS2R0KofZMFarZLSelrQG0OF qRH95qARuwgDcfYDRj+xFn7qcbCSuJ4Z1MqpLco= X-Google-Smtp-Source: ABdhPJyDeK619jAlMCVAJbdpYQxDKjBtW27WMvJU6khYnNLnAERLXH32Aqmrgq62F20PkuKkvI1nHg== X-Received: by 2002:a05:6512:3b9b:: with SMTP id g27mr3411277lfv.556.1630688473941; Fri, 03 Sep 2021 10:01:13 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Date: Fri, 3 Sep 2021 19:00:57 +0200 Message-Id: <20210903170100.2529121-12-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630688980724100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v9: - Rebased to 8880cc4362. - Fixes a whitespace-at-the-end-of-line warning for the rev8 comment in insn32.decode Changes in v4: - reorder trans_rev8* functions to be sequential - rename rev8 to rev8_32 in decoder Changes in v3: - rev8-addition & grevi*-removal moved to a separate commit target/riscv/bitmanip_helper.c | 40 ------------------------- target/riscv/helper.h | 2 -- target/riscv/insn32.decode | 12 ++++---- target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++-------------------- 4 files changed, 15 insertions(+), 79 deletions(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index bb48388fcd..f1b5e5549f 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -24,46 +24,6 @@ #include "exec/helper-proto.h" #include "tcg/tcg.h" =20 -static const uint64_t adjacent_masks[] =3D { - dup_const(MO_8, 0x55), - dup_const(MO_8, 0x33), - dup_const(MO_8, 0x0f), - dup_const(MO_16, 0xff), - dup_const(MO_32, 0xffff), - UINT32_MAX -}; - -static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shif= t) -{ - return ((x & mask) << shift) | ((x & ~mask) >> shift); -} - -static target_ulong do_grev(target_ulong rs1, - target_ulong rs2, - int bits) -{ - target_ulong x =3D rs1; - int i, shift; - - for (i =3D 0, shift =3D 1; shift < bits; i++, shift <<=3D 1) { - if (rs2 & shift) { - x =3D do_swap(x, adjacent_masks[i], shift); - } - } - - return x; -} - -target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2) -{ - return do_grev(rs1, rs2, TARGET_LONG_BITS); -} - -target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2) -{ - return do_grev(rs1, rs2, 32); -} - target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) { target_ulong result =3D 0; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a9bda2c8ac..c7a5376227 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -59,8 +59,6 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, = tl) DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Bitmanip */ -DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 59202196dc..901a66c0f5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -683,6 +683,9 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r orc_b 001010 000111 ..... 101 ..... 0010011 @r2 orn 0100000 .......... 110 ..... 0110011 @r +# The encoding for rev8 differs between RV32 and RV64. +# rev8_32 denotes the RV32 variant. +rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 rol 0110000 .......... 001 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rori 01100 ............ 101 ..... 0010011 @sh @@ -694,6 +697,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 +# The encoding for rev8 differs between RV32 and RV64. +# When executing on RV64, the encoding used in RV32 is an illegal +# instruction, so we use different handler functions to differentiate. +rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 rolw 0110000 .......... 001 ..... 0111011 @r roriw 0110000 .......... 101 ..... 0011011 @sh5 rorw 0110000 .......... 101 ..... 0111011 @r @@ -702,15 +709,10 @@ rorw 0110000 .......... 101 ..... 0111011 @r pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r -grev 0110100 .......... 101 ..... 0110011 @r -grevi 01101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -grevw 0110100 .......... 101 ..... 0111011 @r - -greviw 0110100 .......... 101 ..... 0011011 @sh5 =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 311174ea40..55251a52a5 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -273,26 +273,18 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } =20 -static bool trans_grev(DisasContext *ctx, arg_grev *a) +static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_NONE, gen_helper_grev); -} - -static void gen_grevi(TCGv dest, TCGv src, target_long shamt) -{ - if (shamt =3D=3D TARGET_LONG_BITS - 8) { - /* rev8, byte swaps */ - tcg_gen_bswap_tl(dest, src); - } else { - gen_helper_grev(dest, src, tcg_constant_tl(shamt)); - } + REQUIRE_32BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); } =20 -static bool trans_grevi(DisasContext *ctx, arg_grevi *a) +static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a) { - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi); + REQUIRE_64BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); } =20 static void gen_orc_b(TCGv ret, TCGv source1) @@ -469,22 +461,6 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) return gen_shift(ctx, a, EXT_NONE, gen_rolw); } =20 -static bool trans_grevw(DisasContext *ctx, arg_grevw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev); -} - -static bool trans_greviw(DisasContext *ctx, arg_greviw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w =3D true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev); -} - #define GEN_SHADD_UW(SHAMT) \ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ { \ --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630689051619168.31403970879774; Fri, 3 Sep 2021 10:10:51 -0700 (PDT) Received: from localhost ([::1]:57620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCiI-0006vx-LM for importer@patchew.org; Fri, 03 Sep 2021 13:10:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ6-0007bA-5h for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:20 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]:43851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ3-00058M-Pp for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:19 -0400 Received: by mail-lf1-x12e.google.com with SMTP id h16so10126343lfk.10 for ; Fri, 03 Sep 2021 10:01:17 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pY58uScBbn/vSWM6Uw5kG51iB+LRATIh/xl8JG0DaRA=; b=ahmDkkeINGHZRhtOSJaxmtnfG/Eb1s8ItCxdPaNTZDhRTbpMk6/sVkpD4um23fGZ7i an39U54QzO9duMEMsY0/PAa8ABIXjbEMSTZ0n4aT6Z9HtKsESdO9fHabCnn3xYI2Tbvq oJc+t8pnG1ctxchLNfpWuXM4bhdox0NofV0mcN7Itm+Lo+y4ZV7jf3FGOV0xPYPmw9Lt tFP4qcwuZPiJ2ug5r+NJfhItpI1QSuAE9f5upyYSbwUJZY8OaNVLXPE/6yYS8HdxbVvE alR5brBAgICzgcmWpexfn7vOgGdH/D9sPoNIKym2axhIbxvmEC7paIVYtzRWvSUQIT/d obBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pY58uScBbn/vSWM6Uw5kG51iB+LRATIh/xl8JG0DaRA=; b=Fxv7mgh2VGkv/UgxsFc94zIJWRLuujmQL//Q+tWpRNbs0IBNq2VUrXzJqTpP3gsjDO 2ZqFA1z8dgZSuLNjTjufi9tURZRQ8BGnjMbOOiBgUpH4iVhn75xwLYmxJgvZBL0vV9K9 JTCFeG+G2296ublueFkPKn98X6B+XwHZpY2qBwzMFHoRmD+j4qoC0txfe0Fp4sEqfjlz cdwnhdUeVte+HgR+GBXbeJ21TlgIkGy40omc2Iu1mR7jo+q8vUjvv6jHR2eWKiiNlZuM gtNm7XDDmVxWyxXSdU3AK94v7w9nWYvZMvTalzM0qNxwwZiYih6Co9hOWkOomiy65SiH JgDQ== X-Gm-Message-State: AOAM533CwXBmKs1PD6eIBOUQlN0LR5jdGq2zSUHKHnQfN25D5GwHa6zy IyPK7mTEi+cJS6US7+PMNCOx+5AK5qwU2IUy0Oo= X-Google-Smtp-Source: ABdhPJyQq/EZff+KZsDGGTASxvZb7A77qZMc6qTmC6IzcOjgW7f0cV76KC/qSN1nchcrpTowOjd37A== X-Received: by 2002:ac2:51d9:: with SMTP id u25mr3587686lfm.541.1630688474822; Fri, 03 Sep 2021 10:01:14 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Date: Fri, 3 Sep 2021 19:00:58 +0200 Message-Id: <20210903170100.2529121-13-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630689053707100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v9: - Rebased to 8880cc4362. Changes in v4: - Renamed RV32 variant to zext_h_32. - Reordered trans_zext_h_{32,64} to be next to each other. Changes in v3: - Moved zext.h-addition & pack*-removal to a separate commit. target/riscv/insn32.decode | 12 ++-- target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++--------------------- 2 files changed, 21 insertions(+), 77 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 901a66c0f5..affb99b3e6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -692,6 +692,9 @@ rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 xnor 0100000 .......... 100 ..... 0110011 @r +# The encoding for zext.h differs between RV32 and RV64. +# zext_h_32 denotes the RV32 variant. +zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 =20 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -704,15 +707,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 rolw 0110000 .......... 001 ..... 0111011 @r roriw 0110000 .......... 101 ..... 0011011 @sh5 rorw 0110000 .......... 101 ..... 0111011 @r +# The encoding for zext.h differs between RV32 and RV64. +# When executing on RV64, the encoding used in RV32 is an illegal +# instruction, so we use different handler functions to differentiate. +zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 =20 # *** RV32B Standard Extension *** -pack 0000100 .......... 100 ..... 0110011 @r -packu 0100100 .......... 100 ..... 0110011 @r -packh 0000100 .......... 111 ..... 0110011 @r =20 # *** RV64B Standard Extension (in addition to RV32B) *** -packw 0000100 .......... 100 ..... 0111011 @r -packuw 0100100 .......... 100 ..... 0111011 @r =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 55251a52a5..f412c2a9ce 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -88,47 +88,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl); } =20 -static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_deposit_tl(ret, arg1, arg2, - TARGET_LONG_BITS / 2, - TARGET_LONG_BITS / 2); -} - -static bool trans_pack(DisasContext *ctx, arg_pack *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, EXT_NONE, gen_pack); -} - -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); - tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); - tcg_temp_free(t); -} - -static bool trans_packu(DisasContext *ctx, arg_packu *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, EXT_NONE, gen_packu); -} - -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext8u_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); - tcg_temp_free(t); -} - -static bool trans_packh(DisasContext *ctx, arg_packh *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, EXT_NONE, gen_packh); -} - static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_ZBB(ctx); @@ -336,6 +295,20 @@ GEN_TRANS_SHADD(1) GEN_TRANS_SHADD(2) GEN_TRANS_SHADD(3) =20 +static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); +} + +static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); +} + static void gen_clzw(TCGv ret, TCGv arg1) { tcg_gen_clzi_tl(ret, ret, 64); @@ -370,37 +343,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *= a) return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } =20 -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext16s_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 16, 48); - tcg_temp_free(t); -} - -static bool trans_packw(DisasContext *ctx, arg_packw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, EXT_NONE, gen_packw); -} - -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, 16); - tcg_gen_deposit_tl(ret, arg2, t, 0, 16); - tcg_gen_ext32s_tl(ret, ret); - tcg_temp_free(t); -} - -static bool trans_packuw(DisasContext *ctx, arg_packuw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, EXT_NONE, gen_packuw); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 =3D tcg_temp_new_i32(); --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630689340656482.72014069047384; Fri, 3 Sep 2021 10:15:40 -0700 (PDT) Received: from localhost ([::1]:41086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCmx-0006mj-9t for importer@patchew.org; Fri, 03 Sep 2021 13:15:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ7-0007cV-0g for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:21 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]:43857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ4-00059A-S4 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:20 -0400 Received: by mail-lf1-x134.google.com with SMTP id h16so10126466lfk.10 for ; Fri, 03 Sep 2021 10:01:18 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wqsox9YYOmlgC9q1wk77cPlvcrhfgMZHFkpAaB6PE3A=; b=0hYjte02UaHZs4XvtRHo6gqIw0e5vhMTDoHFrE6rZ0h+ZYIeYWg0OdFFt9HjL7cghe R6uKh9DLunoagEw7klyrFp8uJsgwRChlrgLRetuzqkCDKLnIr92seSd/qXG0ypC58Rl9 yMadWv7q0iL2VnvURg4FFds5nP11O2Mosud3JPXq1YSnHzfC4lVctLk3xrFNXFzcuekB onq7d2HkTo9v2j6pcfPWilA1d6zcSbH5fz8iOFX29xq7/tpGC6vWr1YrTbo+iyW59sqW 3as9DulGUegegzk4Sw+tSIXLzXbjhKMawvmEQtMpmlzaFXH/neLV0/GLMV0dXMCykG82 j9Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wqsox9YYOmlgC9q1wk77cPlvcrhfgMZHFkpAaB6PE3A=; b=KkVyAZ6EhvKhKdJHcNrzoWCqtthukElzb9fnSK1z1Z3evrnuIUdWPTFyuX1xw0nQkx +xj7JRxlB2IaRKcI+9w1a7LurLJ8E/afN06gbs05Dp9EUT6XuHh2xcdXcWFDgPD9yQx3 BfQZj6uOXKcLstgLTDQJ1D4VkbddanWnGpd4X5Jn8B2rHkCj8OjUZ+FVmv4mJnWrmACc o0aFmaxkuahjRA2oPFB8cbXlK83XWGVwqgeokgkiAJn29Yygt8kuwnx81ud0PWkpivJc o9SSgzDdKxUW0ZhXTGm6fEVJJyEG6rjvB0IJivZcpKTDCWoxQdQ8165xqO6BhnGxuZB+ N7Iw== X-Gm-Message-State: AOAM531I54zUFp4gqzc+1YM1J5z0/kSzDvqTtUaj+asWyRoaDCGy0APu rAB/w6ZJYhwaY3sSwN0V5UmQhXjUVIpRBCI4l5s= X-Google-Smtp-Source: ABdhPJzE/gPuOmT/bgJRqvWVLsgiPaWLOlbMh52FWfoQv1+Zv5PonpCtxhoxBWy8k/Sje/uoXqgWeQ== X-Received: by 2002:a05:6512:2202:: with SMTP id h2mr3594288lfu.494.1630688475573; Fri, 03 Sep 2021 10:01:15 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 13/14] target/riscv: Remove RVB (replaced by Zb[abcs] Date: Fri, 3 Sep 2021 19:00:59 +0200 Message-Id: <20210903170100.2529121-14-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630689342334100001 Content-Type: text/plain; charset="utf-8" With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/message/532 Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Removing RVB moved into a separate commit at the tail-end of the series. target/riscv/cpu.c | 26 -------------------------- target/riscv/cpu.h | 3 --- target/riscv/insn32.decode | 4 ---- 3 files changed, 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ceb7e01810..3a56836f1c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_bext_version(CPURISCVState *env, int bext_ver) -{ - env->bext_ver =3D bext_ver; -} - static void set_vext_version(CPURISCVState *env, int vext_ver) { env->vext_ver =3D vext_ver; @@ -496,25 +491,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_h) { target_misa |=3D RVH; } - if (cpu->cfg.ext_b) { - int bext_version =3D BEXT_VERSION_0_93_0; - target_misa |=3D RVB; - - if (cpu->cfg.bext_spec) { - if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) { - bext_version =3D BEXT_VERSION_0_93_0; - } else { - error_setg(errp, - "Unsupported bitmanip spec version '%s'", - cpu->cfg.bext_spec); - return; - } - } else { - qemu_log("bitmanip version is not specified, " - "use the default value v0.93\n"); - } - set_bext_version(env, bext_version); - } if (cpu->cfg.ext_v) { int vext_version =3D VEXT_VERSION_0_07_1; target_misa |=3D RVV; @@ -586,7 +562,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), @@ -597,7 +572,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4cd8ea89..77e8b06106 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,7 +67,6 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVB RV('B') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -83,7 +82,6 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 -#define BEXT_VERSION_0_93_0 0x00009300 #define VEXT_VERSION_0_07_1 0x00000701 =20 enum { @@ -288,7 +286,6 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; - bool ext_b; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index affb99b3e6..2f251dac1b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -712,10 +712,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r # instruction, so we use different handler functions to differentiate. zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 =20 -# *** RV32B Standard Extension *** - -# *** RV64B Standard Extension (in addition to RV32B) *** - # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r clmulh 0000101 .......... 011 ..... 0110011 @r --=20 2.25.1 From nobody Sat Apr 27 16:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630689244159178.62438381978677; Fri, 3 Sep 2021 10:14:04 -0700 (PDT) Received: from localhost ([::1]:37116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMClP-000467-3Z for importer@patchew.org; Fri, 03 Sep 2021 13:14:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCZ7-0007ck-Aw for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:21 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]:37861) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCZ4-000592-T7 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:20 -0400 Received: by mail-lf1-x134.google.com with SMTP id l10so12990627lfg.4 for ; Fri, 03 Sep 2021 10:01:18 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xjHbcU4jd4/FFyGkcPZC0fU+deSURo/V2puvaJZ+g/s=; b=HwB9c+/nucCCa7T31W4zd6nrUHN/VSQK+iXjUcayo3M74t54ova+OYIkjz9Uo4++qU fJkcZ2WbRBsqlw+U1hf6rQvyq/WcOJ3avt4e5M1k+5bdaoyoO+3dJN7PxP+2S2Rk4l2N vwHzfjxnfmzOcKegz5ssXOs0vWqgmW3YqN+J6PJ8W2UiwQAb2wyCJ1elGpFsQSupt50l Vvv/vs6sApgCM51EbmSh6KwwGe0RAtGuyIagYLpQpFMRpQy3bUZOVWzTs3eNRfqOXbK6 BFyCieTSn7P7lbu+ztiEYRus9jvkjyepCEaSXLbPiz6Nsu+JeHNL/q5jGCKluWG83HpX LGfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xjHbcU4jd4/FFyGkcPZC0fU+deSURo/V2puvaJZ+g/s=; b=hBe214NAvTFjccR/fC59O6+Jy7Axkjvo6rkGRMlMb+pr19s/PlbovoaizpX5dgV6nz fufYK/xsFsvAkIbiWfRzb0SiXlOohXtOnGj8ReyV5N75K/ECjxW1bn29FA2Mx5JVfP9V nNgaHSFsdIhXW1kCmiKDJyn8K6lVxgVFXW/Md8S+ewvmjyB8hikMVeyVQMa4yXBMGt2S zshjIEVkSaWKCqkLAPa8sP9R9Ai0PyG2O8QPBPyM/V6A99N/Rk3i8Df4YbtEYSzsa8wZ B1QjvjeXJSJHR8C4LViud7QTdoRAjXweYhHzxF1osxtN8F50cmIGDcgLtvUzhkEYLLIA 56kQ== X-Gm-Message-State: AOAM531RSdzfFleAJQaAU7KKN8vw1Lcf9DGP42F74xFMkEwVyGl51/D0 Vuqe33U9S9nLE9KmcGpK4QuhfogG+8hj1uqv600= X-Google-Smtp-Source: ABdhPJzvbLSErTlkcMttzIKF39KydMYcUELOB6vWYh/lINm03fsyUKjZz1zdbvcRoguwZZrytpzkLg== X-Received: by 2002:a05:6512:1088:: with SMTP id j8mr3695747lfg.74.1630688476664; Fri, 03 Sep 2021 10:01:16 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 14/14] disas/riscv: Add Zb[abcs] instructions Date: Fri, 3 Sep 2021 19:01:00 +0200 Message-Id: <20210903170100.2529121-15-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630689245267100001 Content-Type: text/plain; charset="utf-8" With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich Acked-by: Alistair Francis --- (no changes since v2) Changes in v2: - Fix missing ';' from last-minute whitespace cleanups. disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 278d9be924..793ad14c27 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -478,6 +478,49 @@ typedef enum { rv_op_fsflags =3D 316, rv_op_fsrmi =3D 317, rv_op_fsflagsi =3D 318, + rv_op_bseti =3D 319, + rv_op_bclri =3D 320, + rv_op_binvi =3D 321, + rv_op_bexti =3D 322, + rv_op_rori =3D 323, + rv_op_clz =3D 324, + rv_op_ctz =3D 325, + rv_op_cpop =3D 326, + rv_op_sext_h =3D 327, + rv_op_sext_b =3D 328, + rv_op_xnor =3D 329, + rv_op_orn =3D 330, + rv_op_andn =3D 331, + rv_op_rol =3D 332, + rv_op_ror =3D 333, + rv_op_sh1add =3D 334, + rv_op_sh2add =3D 335, + rv_op_sh3add =3D 336, + rv_op_sh1add_uw =3D 337, + rv_op_sh2add_uw =3D 338, + rv_op_sh3add_uw =3D 339, + rv_op_clmul =3D 340, + rv_op_clmulr =3D 341, + rv_op_clmulh =3D 342, + rv_op_min =3D 343, + rv_op_minu =3D 344, + rv_op_max =3D 345, + rv_op_maxu =3D 346, + rv_op_clzw =3D 347, + rv_op_ctzw =3D 348, + rv_op_cpopw =3D 349, + rv_op_slli_uw =3D 350, + rv_op_add_uw =3D 351, + rv_op_rolw =3D 352, + rv_op_rorw =3D 353, + rv_op_rev8 =3D 354, + rv_op_zext_h =3D 355, + rv_op_roriw =3D 356, + rv_op_orc_b =3D 357, + rv_op_bset =3D 358, + rv_op_bclr =3D 359, + rv_op_binv =3D 360, + rv_op_bext =3D 361, } rv_op; =20 /* structures */ @@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] =3D { { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, + { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 0: op =3D rv_op_addi; break; case 1: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_slli; break; + case 0b00000: op =3D rv_op_slli; break; + case 0b00101: op =3D rv_op_bseti; break; + case 0b01001: op =3D rv_op_bclri; break; + case 0b01101: op =3D rv_op_binvi; break; + case 0b01100: + switch (((inst >> 20) & 0b1111111)) { + case 0b0000000: op =3D rv_op_clz; break; + case 0b0000001: op =3D rv_op_ctz; break; + case 0b0000010: op =3D rv_op_cpop; break; + /* 0b0000011 */ + case 0b0000100: op =3D rv_op_sext_b; break; + case 0b0000101: op =3D rv_op_sext_h; break; + } + break; } break; case 2: op =3D rv_op_slti; break; @@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 4: op =3D rv_op_xori; break; case 5: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_srli; break; - case 8: op =3D rv_op_srai; break; + case 0b00000: op =3D rv_op_srli; break; + case 0b00101: op =3D rv_op_orc_b; break; + case 0b01000: op =3D rv_op_srai; break; + case 0b01001: op =3D rv_op_bexti; break; + case 0b01100: op =3D rv_op_rori; break; + case 0b01101: + switch ((inst >> 20) & 0b1111111) { + case 0b0111000: op =3D rv_op_rev8; break; + } + break; } break; case 6: op =3D rv_op_ori; break; @@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) case 1: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_slliw; break; + case 4: op =3D rv_op_slli_uw; break; + case 48: + switch ((inst >> 20) & 0b11111) { + case 0b00000: op =3D rv_op_clzw; break; + case 0b00001: op =3D rv_op_ctzw; break; + case 0b00010: op =3D rv_op_cpopw; break; + } + break; } break; case 5: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_srliw; break; case 32: op =3D rv_op_sraiw; break; + case 48: op =3D rv_op_roriw; break; } break; } @@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divu; break; case 14: op =3D rv_op_rem; break; case 15: op =3D rv_op_remu; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 41: op =3D rv_op_clmul; break; + case 42: op =3D rv_op_clmulr; break; + case 43: op =3D rv_op_clmulh; break; + case 44: op =3D rv_op_min; break; + case 45: op =3D rv_op_minu; break; + case 46: op =3D rv_op_max; break; + case 47: op =3D rv_op_maxu; break; + case 130: op =3D rv_op_sh1add; break; + case 132: op =3D rv_op_sh2add; break; + case 134: op =3D rv_op_sh3add; break; + case 161: op =3D rv_op_bset; break; case 256: op =3D rv_op_sub; break; + case 260: op =3D rv_op_xnor; break; case 261: op =3D rv_op_sra; break; + case 262: op =3D rv_op_orn; break; + case 263: op =3D rv_op_andn; break; + case 289: op =3D rv_op_bclr; break; + case 293: op =3D rv_op_bext; break; + case 385: op =3D rv_op_rol; break; + case 386: op =3D rv_op_ror; break; + case 417: op =3D rv_op_binv; break; } break; case 13: op =3D rv_op_lui; break; @@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divuw; break; case 14: op =3D rv_op_remw; break; case 15: op =3D rv_op_remuw; break; + case 32: op =3D rv_op_add_uw; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 130: op =3D rv_op_sh1add_uw; break; + case 132: op =3D rv_op_sh2add_uw; break; + case 134: op =3D rv_op_sh3add_uw; break; case 256: op =3D rv_op_subw; break; case 261: op =3D rv_op_sraw; break; + case 385: op =3D rv_op_rolw; break; + case 389: op =3D rv_op_rorw; break; } break; case 16: --=20 2.25.1