From nobody Sat Apr 27 23:33:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630682238; cv=none; d=zohomail.com; s=zohoarc; b=EkN3aRhgNaKmoYCjo7uZyxFXEwr0SXTA4AnUSrvmcw0n+PU1oD3s7IA2zfoWcWFlAo7dzSVC8EBHJ8VuGA2G5AQZNYg5ET2iW6UMWa7BpWKJxX/VxcXYYpbUxYp0/hSQjxXDL9IrQPXwCG+QP+guuevlMtexhsgUexPDOcCPPPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630682238; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SL90VPTxtLLYwhekzrWcwoaOEJbVtGKH8Xq7EIDvL2c=; b=m4mrmM5SGQhRNwrn3yXat2QeJ2n4v3mORC3iIhqwjFly+Z5Ysi81bG8UTnzlz7S/MsXDPsQnV7CFg7RLp0N2f6RdCZ2dY9Br9j6SEFP/yW1OhShCjwiTW9g3lSeXJOl4yW4R02EgzBC+cBemABArQ221aftvCv1RNbvtbY9RRkk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630682238785296.3619917586459; Fri, 3 Sep 2021 08:17:18 -0700 (PDT) Received: from localhost ([::1]:47978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMAwP-0007RI-FC for importer@patchew.org; Fri, 03 Sep 2021 11:17:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMAtv-0004ZH-HE for qemu-devel@nongnu.org; Fri, 03 Sep 2021 11:14:43 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:53072) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMAts-0007N5-MW for qemu-devel@nongnu.org; Fri, 03 Sep 2021 11:14:43 -0400 Received: by mail-wm1-x32d.google.com with SMTP id e26so3741977wmk.2 for ; Fri, 03 Sep 2021 08:14:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y21sm4737780wmc.11.2021.09.03.08.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 08:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SL90VPTxtLLYwhekzrWcwoaOEJbVtGKH8Xq7EIDvL2c=; b=pYAYb9U1+SsSWmzd6H40H1A2jLg9KAssZe44momZuONP7U0IyDa3RAdVZfO6ivnsn4 zQRMQwOEcwR0i/ILz1BJUZdZhAEv+cByMJc2bhIZ2nTAtx84ZMaGVmPsX6Z7vSGOJcWz KVevJ4x3hLtvXmzNuy8qxHyE289GZN37YXmARjmJsRTDmWnk3zM6y1NzmBP186retWgm NuDlKpZuEMRD7jQaNQ+yMxVqVAHnn7iHOWNuPR2fjUvHgN9UqTEsPAKv/pHpg5jtmOsL oMzdKzJbJLHh1NGOpAsV0l7ik2K8HHAIC2J87C4cjoti3ZSJ13KJX/gXxoNDFITc40BB xohw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SL90VPTxtLLYwhekzrWcwoaOEJbVtGKH8Xq7EIDvL2c=; b=uk8+Wp9MTERkmYznMxJA05NEM4k50XYaC9aZ5CEiCrdC5X3+w8MXGSphrofv/KFw2a YmZKeUQ07UG6DxN4bujPrLVzlHo81tYz9KoSAiWt3sOtypVFcSIhW+/ZK7aAztL/aaKy H2nrz5c1AwpCdmOXMg1otTxA+sMH2itSnYCixGg8Z+doB3W5NQPyGRTLCyCDtjj0XUm/ p0nb5ffBV7C5JqGfmjbRK4rHLYhrULp9Tc+RLLJu3YeaNeyLi8qq0zCA+abNzhfgOI+l LAAMFATA94EuvEfvwiKY3mCDc+8icdRZCexDA3oZ61Y/7E0ARKwScGf2eTOOEzdbybSW Ul3A== X-Gm-Message-State: AOAM530sHgIvHoPAb508nD3ZU7pCGyGfqhvoVI4Mmbbz+A4x84gBC5VO N94rTjU2a04O8DrKQJyTtUQlQg== X-Google-Smtp-Source: ABdhPJwjH4sxI5gz2lmeIyZObD9Jj2SDexCt+v3r5BWNxvMF2C3dupdWslOlqL3wBZZKbfST24ED/Q== X-Received: by 2002:a05:600c:2215:: with SMTP id z21mr9057262wml.47.1630682079233; Fri, 03 Sep 2021 08:14:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/4] qdev: Support marking individual buses as 'full' Date: Fri, 3 Sep 2021 16:14:32 +0100 Message-Id: <20210903151435.22379-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903151435.22379-1-peter.maydell@linaro.org> References: <20210903151435.22379-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630682240352100002 Content-Type: text/plain; charset="utf-8" By default, QEMU will allow devices to be plugged into a bus up to the bus class's device count limit. If the user creates a device on the command line or via the monitor and doesn't explicitly specify the bus to plug it in, QEMU will plug it into the first non-full bus that it finds. This is fine in most cases, but some machines have multiple buses of a given type, some of which are dedicated to on-board devices and some of which have an externally exposed connector for user-pluggable devices. One example is I2C buses. Provide a new function qbus_mark_full() so that a machine model can mark this kind of "internal only" bus as 'full' after it has created all the devices that should be plugged into that bus. The "find a non-full bus" algorithm will then skip the internal-only bus when looking for a place to plug in user-created devices. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/qdev-core.h | 24 ++++++++++++++++++++++++ softmmu/qdev-monitor.c | 7 ++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index bafc311bfa1..762f9584dde 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -264,6 +264,7 @@ struct BusState { HotplugHandler *hotplug_handler; int max_index; bool realized; + bool full; int num_children; =20 /* @@ -798,6 +799,29 @@ static inline bool qbus_is_hotpluggable(BusState *bus) return bus->hotplug_handler; } =20 +/** + * qbus_mark_full: Mark this bus as full, so no more devices can be attach= ed + * @bus: Bus to mark as full + * + * By default, QEMU will allow devices to be plugged into a bus up + * to the bus class's device count limit. Calling this function + * marks a particular bus as full, so that no more devices can be + * plugged into it. In particular this means that the bus will not + * be considered as a candidate for plugging in devices created by + * the user on the commandline or via the monitor. + * If a machine has multiple buses of a given type, such as I2C, + * where some of those buses in the real hardware are used only for + * internal devices and some are exposed via expansion ports, you + * can use this function to mark the internal-only buses as full + * after you have created all their internal devices. Then user + * created devices will appear on the expansion-port bus where + * guest software expects them. + */ +static inline void qbus_mark_full(BusState *bus) +{ + bus->full =3D true; +} + void device_listener_register(DeviceListener *listener); void device_listener_unregister(DeviceListener *listener); =20 diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c index a304754ab91..0705f008466 100644 --- a/softmmu/qdev-monitor.c +++ b/softmmu/qdev-monitor.c @@ -435,7 +435,12 @@ static DeviceState *qbus_find_dev(BusState *bus, char = *elem) =20 static inline bool qbus_is_full(BusState *bus) { - BusClass *bus_class =3D BUS_GET_CLASS(bus); + BusClass *bus_class; + + if (bus->full) { + return true; + } + bus_class =3D BUS_GET_CLASS(bus); return bus_class->max_dev && bus->num_children >=3D bus_class->max_dev; } =20 --=20 2.20.1 From nobody Sat Apr 27 23:33:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630682242; cv=none; d=zohomail.com; s=zohoarc; b=jieiaNxd1HdSQof//ewe/dUKNB8KJ04dIH3iNcn3kA2OIaopP+zTUEnxE/Ds1cHNAnZlq/OqVLLdBHeeczlZMNPLCeVyIKF9Gf72DdEIF/V+lJDtQTL3GDyW/h+1Qcc/ufLLhTKalQ3n+UWXCFsAfstV+EJFgLN6ku0SA8+RqX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630682242; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sE2ls29dfSsN30EdvESz1JIj1pUVIWRUf+dXCYAoZ+w=; b=dnisBwKe0vlvFxzlYLFtglz1yELkt/sjR1UW2mtv+mAt+XKa4pC2bCXI0DgZjodRKEI0STs1syPfeeoflUumdrOJD+pgvO9MVzDQrWG3i8HZdBwdnTtS0ob/lyN5zNCbtV3wElAmmAws8JC4UbIsjunfA836dWyEcjNXoL1Adpc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163068224243077.41516016526873; Fri, 3 Sep 2021 08:17:22 -0700 (PDT) Received: from localhost ([::1]:48140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMAwT-0007Xa-9n for importer@patchew.org; Fri, 03 Sep 2021 11:17:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMAtw-0004bk-Mk for qemu-devel@nongnu.org; Fri, 03 Sep 2021 11:14:44 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:38712) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMAtu-0007O1-85 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 11:14:44 -0400 Received: by mail-wm1-x32a.google.com with SMTP id k5-20020a05600c1c8500b002f76c42214bso4011668wms.3 for ; Fri, 03 Sep 2021 08:14:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y21sm4737780wmc.11.2021.09.03.08.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 08:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sE2ls29dfSsN30EdvESz1JIj1pUVIWRUf+dXCYAoZ+w=; b=P1UAWB2PZcnkZWO3PUTJ+XYo/vvtBJHl0ITqJrtK6OmgZt/+dlOLaYF+HsyEYs4rHC umSh2+BJyLqpLPEUF4kGYDAVMDk9hQ/Jm2684x78oO6N7ZS1qEjhdQ4XIjFspJewncUK oOqhcz7F1AYHpmjRlAsFQ+GSFkRJm8cPTyMVwxWtqRdmce5KeqGcqGV+MXVC/bR8zM8P wqY4hJReejmUKZPw8BFiJkuJb2jxAs5sZ/MrhgFwcsNxlkza3eO8BPIgrfJnQHy4E9LD xRQlO0fDlUA/fh0OPKMJKq9l9aVBMmBupo/9C/Teg6FRlcstDtfZH7y6iX7mEpllkbpo WDCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sE2ls29dfSsN30EdvESz1JIj1pUVIWRUf+dXCYAoZ+w=; b=lBsNYQcRQw//SdIWHO3J8WvObadxhpOHVO3A5UEDTmGjZZcq8sZnGBnMoQfQcXokju kA0bxh1SBDitA7f4T/tpzxj7/AI+D1+LhyQKl94J9TePm22PHo9fdSq0Alj3P2VahKkJ pCaHgU4buXKn4OuoKhrU4qiDP+hbSDKbva7J/Feo+c7JNCD3x1WdSV7Ph04nl1tixtIe lOgAyMCB2wEZs3gkjekyiNLaoIchEgADbFgzqWugLi2/CJVQziE2yYUsx5xbsj9Ojboy mj3QmfypS2+BOeYFxBcGbybmHQ/GKPBjhyVTmmm/Vry09erlvFwDzaNrLosz02Wbujk7 XMWA== X-Gm-Message-State: AOAM5335HyXgzAzm/Dxi6XnYqsiz8niVQ6IEawp8N8OUfeXykZ5Lngy+ rPMsQdWB/pLC85c4sL+DdUcNlg== X-Google-Smtp-Source: ABdhPJzqztgYFBjzcDPk7CTMX409SaT8FIRgRpGCwATe0mVvooBzCPDE0Z0UKCsQuxrdA2Po2G+x4g== X-Received: by 2002:a1c:a747:: with SMTP id q68mr8929730wme.149.1630682080442; Fri, 03 Sep 2021 08:14:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/4] hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn Date: Fri, 3 Sep 2021 16:14:33 +0100 Message-Id: <20210903151435.22379-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903151435.22379-1-peter.maydell@linaro.org> References: <20210903151435.22379-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630682243036100001 Content-Type: text/plain; charset="utf-8" The mps2-tz boards use a data-driven structure to create the devices that sit behind peripheral protection controllers. Currently the functions which create these devices are passed an 'opaque' pointer which is always the address within the machine struct of the device to create, and some "all devices need this" information like irqs and addresses. If a specific device needs more information than this, it is currently not possible to pass that through from the PPCInfo data structure. Add support for passing an extra data parameter, so that we can more flexibly handle the needs of specific device types. To provide some type-safety we make this extra parameter a pointer to a union (which initially has no members). In particular, we would like to be able to indicate which of the i2c controllers are for on-board devices only and which are connected to the external 'shield' expansion port; a subsequent patch will use this mechanism for that purpose. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index e23830f4b7d..746ba3cc59e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -373,6 +373,10 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms= , int irqno) } } =20 +/* Union describing the device-specific extra data we pass to the devfn. */ +typedef union PPCExtraData { +} PPCExtraData; + /* Most of the devices in the AN505 FPGA image sit behind * Peripheral Protection Controllers. These data structures * define the layout of which devices sit behind which PPCs. @@ -382,7 +386,8 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs); + const int *irqs, + const PPCExtraData *extradata); =20 typedef struct PPCPortInfo { const char *name; @@ -391,6 +396,7 @@ typedef struct PPCPortInfo { hwaddr addr; hwaddr size; int irqs[3]; /* currently no device needs more IRQ lines than this */ + PPCExtraData extradata; /* to pass device-specific info to the devfn */ } PPCPortInfo; =20 typedef struct PPCInfo { @@ -401,7 +407,8 @@ typedef struct PPCInfo { static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -417,7 +424,7 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState = *mms, =20 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrad= ata) { /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -441,7 +448,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, =20 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { MPS2SCC *scc =3D opaque; DeviceState *sccdev; @@ -465,7 +472,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extr= adata) { MPS2FPGAIO *fpgaio =3D opaque; MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -480,7 +487,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, =20 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { SysBusDevice *s; NICInfo *nd =3D &nd_table[0]; @@ -500,7 +508,8 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, =20 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, + const PPCExtraData *extradata) { /* * The AN524 makes the ethernet and USB share a PPC port. @@ -543,7 +552,7 @@ static MemoryRegion *make_eth_usb(MPS2TZMachineState *m= ms, void *opaque, =20 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { TZMPC *mpc =3D opaque; int i =3D mpc - &mms->mpc[0]; @@ -615,7 +624,7 @@ static void remap_irq_fn(void *opaque, int n, int level) =20 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma =3D opaque; @@ -672,7 +681,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { /* * The AN505 has five PL022 SPI controllers. @@ -694,7 +703,7 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { ArmSbconI2CState *i2c =3D opaque; SysBusDevice *s; @@ -707,7 +716,7 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, = void *opaque, =20 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, - const int *irqs) + const int *irqs, const PPCExtraData *extrada= ta) { PL031State *pl031 =3D opaque; SysBusDevice *s; @@ -1084,7 +1093,7 @@ static void mps2tz_common_init(MachineState *machine) } =20 mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze, - pinfo->irqs); + pinfo->irqs, &pinfo->extradata); portname =3D g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); --=20 2.20.1 From nobody Sat Apr 27 23:33:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y21sm4737780wmc.11.2021.09.03.08.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 08:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=12HaYXUuKoS6T5PuKGowDR0/v6+2hx1VPdfHK6j3uyM=; b=gLo448uVa127kt9ci4nDcabjel7q1SrgbziE/oxAZlGYy3DproYUQF+hrFuQAlPfNq smRqyzX7asHgMrPCOzXCF3UaD4s7yUsJ3oduFRt30tmLzQ4ivFQQoWglsZHF9nP+jwYm t5E4zh4nChELj0DgRJEN31xqbJDgNPO3iQpG9/JnntidqC/aFBxrNCtzArdd+LMZn09+ Xl5eOQShrjPW0wvBC4KHKc3YUfO2+lFAfMXpRWbOGNpBAiWXCLLrqfmzopS0AknekwFF tKiyfcWxfT8y9Ux1smDLDS1cqBTfZdc0vgXAIga2QmkjKM/18Tg0pOMyeTfAPUM5o/0X 8uZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=12HaYXUuKoS6T5PuKGowDR0/v6+2hx1VPdfHK6j3uyM=; b=hKtZ7ui2HOvtgRfalL9iB74mQQGV5whxf+jfYG3zYysvfvqYIuEaskB5Lv+Nvsz7vI xTFwy4ALBHfpE3up7WeGB6fEXRJJ6p5hT1xlg/gHpjSbSSPUyKGu52igA+Hl6Ixjcodj b6QYMHP8olWX1hyo6IE+V5AVwyGWqBnTsZYkl/TRhwZ39ty4Pbg5JqE9e1AA06xVCzV+ 8SXgw6GMgdqOtcTPaLnGEY0pWmULqx5YZxv8JF/EG5NhnyQsWJbibKL/BuEaMJ4cdL+e HC3hTxERUfWl1qdxdNsjSSLkCWLTdYrAjJAcjM4/H9YOq+RXW6pAC25PrftMhXstV4PF t3mw== X-Gm-Message-State: AOAM532U5oE5PVE9WXtcH/5qz96xMMelJQ+VwHgkCaGTgYCMcyy4kOP2 jYYMEPCq2yxJtlM0xpV9G5UP6g== X-Google-Smtp-Source: ABdhPJwOnbLBIT3lHS8UYzDUFb1DAm/CTurMyO5Esmism8XtsF64JQX2QAmhaKDDX7RYxyXEamfWZg== X-Received: by 2002:adf:f9cb:: with SMTP id w11mr4857297wrr.382.1630682081522; Fri, 03 Sep 2021 08:14:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/4] hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' Date: Fri, 3 Sep 2021 16:14:34 +0100 Message-Id: <20210903151435.22379-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903151435.22379-1-peter.maydell@linaro.org> References: <20210903151435.22379-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630682396939100003 Content-Type: text/plain; charset="utf-8" The various MPS2 boards have multiple I2C buses: typically a bus dedicated to the audio configuration, one for the LCD touchscreen controller, one for a DDR4 EEPROM, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 57 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 746ba3cc59e..f40e854dec7 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -375,6 +375,7 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms,= int irqno) =20 /* Union describing the device-specific extra data we pass to the devfn. */ typedef union PPCExtraData { + bool i2c_internal; } PPCExtraData; =20 /* Most of the devices in the AN505 FPGA image sit behind @@ -711,6 +712,20 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,= void *opaque, object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); s =3D SYS_BUS_DEVICE(i2c); sysbus_realize(s, &error_fatal); + + /* + * If this is an internal-use-only i2c bus, mark it full + * so that user-created i2c devices are not plugged into it. + * If we implement models of any on-board i2c devices that + * plug in to one of the internal-use-only buses, then we will + * need to create and plugging those in here before we mark the + * bus as full. + */ + if (extradata->i2c_internal) { + BusState *qbus =3D qdev_get_child_bus(DEVICE(i2c), "i2c"); + qbus_mark_full(qbus); + } + return sysbus_mmio_get_region(s, 0); } =20 @@ -921,10 +936,14 @@ static void mps2tz_common_init(MachineState *machine) { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, {= 36, 37, 44 } }, { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, {= 38, 39, 45 } }, { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, {= 40, 41, 46 } }, - { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, - { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, }, }, { .name =3D "apb_ppcexp2", @@ -965,15 +984,20 @@ static void mps2tz_common_init(MachineState *machine) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52= } }, { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53= } }, { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54= } }, - { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, { /* port 7 reserved */ }, - { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, }, }, { .name =3D "apb_ppcexp2", @@ -1015,15 +1039,20 @@ static void mps2tz_common_init(MachineState *machin= e) }, { .name =3D "apb_ppcexp1", .ports =3D { - { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, - { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, - { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, - { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, { /* port 7 reserved */ }, - { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, }, }, { .name =3D "apb_ppcexp2", --=20 2.20.1 From nobody Sat Apr 27 23:33:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y21sm4737780wmc.11.2021.09.03.08.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 08:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mxdg4WBcVbUdsRcZMoLQ96Hj5pGJaTJATreG10LOYTE=; b=HWaGAy+ODu+VetBKHsWRZ8RzjD91FDOkTsBg2bYVP/KIDBIUG2e05pHCyaE2tyxFzV OIBjmt4TxquIeRdWDw+dSthE0O+iGynN2XD+6AVFdXCWb2FB7Ngx8SscIOr94bVQCFiP iyOLwUapHA86iCe989KP53u+eE3AYPxGcSFKbMqii1HnAf7ae2rP+KiE53d32mx+xA/D Grbtza//f5WV39WfpVgZ+aU0KQj1ZBpJLvc4tWwVk7pZ9Um32g7osSPOHc3TuX5kn2SB KEZmdTIqTvL8t7aOZMH6GJ+b4rfhMcx75tnuVUKTXJ8Ns2cd20hv0q9S7VSocuahqLLW oLmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mxdg4WBcVbUdsRcZMoLQ96Hj5pGJaTJATreG10LOYTE=; b=JIJOWXOYvimlcqYPUsjBfshbkE1y1BJ+0qOhz7zs+eBVotIAzG7H3SrpwMMkSVPqbR am8B0eO/ABbSxo85WtHJiiD075N0pZNT3s+4z5X3WTQ7ormHqMeCaguq2bvTz79clZpV Lsl3C/kcsclXXlR2q6+ptG8DPXPLxYqhzEVsKSFWsV5KOyofJuuaHJgCt0u6Mi3uxCZe iG8SJbOhDtlPe+Ph93APP/FixK5mJtJ2z1249GR/EjwZs0O8y59R8XKVEkUJbHPdXGX+ ipDOc7PlTgq9DW3O9m9a9/kz3KIieL4/ZYyteduD/0dG0KNnZhEX3TuPS33CXB1pgGs8 0LTw== X-Gm-Message-State: AOAM533IL48QqJMYdjRNivXKdjOB4o/rEU8xPS+YiJcFU2wjuOENPmzU ZAlmfQh/9Xhs976ohLdwZgZK/MNSADzyCA== X-Google-Smtp-Source: ABdhPJwEy9ffu5603o1YH/W2hKjy/xunf78BBuDcHLX/Feun334FL53q0dF9AVepvyxblXvEefhMkw== X-Received: by 2002:a5d:4285:: with SMTP id k5mr4829659wrq.131.1630682082344; Fri, 03 Sep 2021 08:14:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/4] hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Date: Fri, 3 Sep 2021 16:14:35 +0100 Message-Id: <20210903151435.22379-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903151435.22379-1-peter.maydell@linaro.org> References: <20210903151435.22379-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Markus Armbruster Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630682394796100001 Content-Type: text/plain; charset="utf-8" The various MPS2 boards implemented in mps2.c have multiple I2C buses: a bus dedicated to the audio configuration, one for the LCD touchscreen controller, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 4634aa1a1ca..bb76fa68890 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -428,7 +428,17 @@ static void mps2_common_init(MachineState *machine) 0x40023000, /* Audio */ 0x40029000, /* Shield0 */ 0x4002a000}; /* Shield1 */ - sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); + DeviceState *dev; + + dev =3D sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); + if (i < 2) { + /* + * internal-only bus: mark it full to avoid user-created + * i2c devices being plugged into it. + */ + BusState *qbus =3D qdev_get_child_bus(dev, "i2c"); + qbus_mark_full(qbus); + } } create_unimplemented_device("i2s", 0x40024000, 0x400); =20 --=20 2.20.1