From nobody Wed Feb 11 00:36:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630669470966236.38236278266174; Fri, 3 Sep 2021 04:44:30 -0700 (PDT) Received: from localhost ([::1]:58816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7cT-0001mt-2a for importer@patchew.org; Fri, 03 Sep 2021 07:44:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RC-0002Cn-D4 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:50 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59842 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RA-0005r3-Qf for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:50 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qk-0009kl-L3; Fri, 03 Sep 2021 12:32:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:18 +0100 Message-Id: <20210903113223.19551-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630669471873100001 Content-Type: text/plain; charset="utf-8" This new hardware reset function is to be called for both channels when the hardware reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Add a new trace event when the guest initiates a hard reset via the WR9 reg= ister to help diagnose guest reset issues. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 38 +++++++++++++++++++++++++++++++++++++- hw/char/trace-events | 1 + 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 697f15f383..806f593738 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -331,6 +331,40 @@ static void escc_soft_reset_chn(ESCCChannelState *s) clear_queue(s); } =20 +static void escc_hard_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg =3D 0; + for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] =3D 0; + s->wregs[i] =3D 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; + s->wregs[W_MINTR] =3D MINTR_RST_ALL; + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + + s->rx =3D s->tx =3D 0; + s->rxint =3D s->txint =3D 0; + s->rxint_under_svc =3D s->txint_under_svc =3D 0; + s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); @@ -589,7 +623,9 @@ static void escc_mem_write(void *opaque, hwaddr addr, escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: - escc_reset(DEVICE(serial)); + trace_escc_hard_reset(); + escc_hard_reset_chn(&serial->chn[0]); + escc_hard_reset_chn(&serial->chn[1]); return; } break; diff --git a/hw/char/trace-events b/hw/char/trace-events index 073f98ebe8..b774832af4 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t valu= e) "addr 0x%"PRIx64" va grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 =20 # escc.c +escc_hard_reset(void) "hard reset" escc_soft_reset_chn(char channel) "soft reset channel %c" escc_put_queue(char channel, int b) "channel %c put: 0x%02x" escc_get_queue(char channel, int val) "channel %c get 0x%02x" --=20 2.20.1