From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630670259354283.1896400684659; Fri, 3 Sep 2021 04:57:39 -0700 (PDT) Received: from localhost ([::1]:37468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7pC-0000NE-BJ for importer@patchew.org; Fri, 03 Sep 2021 07:57:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7R0-0001ta-OD for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:40 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59822 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7Qy-0005kB-Rm for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:38 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7QY-0009kl-0y; Fri, 03 Sep 2021 12:32:14 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:15 +0100 Message-Id: <20210903113223.19551-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 1/9] escc: checkpatch fixes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670259977100001 Content-Type: text/plain; charset="utf-8" Also fix a couple of spelling mistakes in comments. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 162 +++++++++++++++++++++++++++++-------------------- 1 file changed, 97 insertions(+), 65 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 52e7978287..c87ecd59d8 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -230,20 +230,23 @@ static uint32_t get_queue(void *opaque) q->count--; } trace_escc_get_queue(CHN_C(s), val); - if (q->count > 0) + if (q->count > 0) { serial_receive_byte(s, 0); + } return val; } =20 static int escc_update_irq_chn(ESCCChannelState *s) { if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint =3D=3D 1)) || - // tx ints enabled, pending - ((((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINT1ST) || - ((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINTALL)) && - s->rxint =3D=3D 1) || // rx ints enabled, pending - ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && - (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p + /* tx ints enabled, pending */ + ((((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINT1ST) || + ((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINTALL)) && + s->rxint =3D=3D 1) || + /* rx ints enabled, pending */ + ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && + (s->rregs[R_STATUS] & STATUS_BRK)))) { + /* break int e&p */ return 1; } return 0; @@ -269,17 +272,22 @@ static void escc_reset_chn(ESCCChannelState *s) s->rregs[i] =3D 0; s->wregs[i] =3D 0; } - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no p= arity + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; s->wregs[W_MINTR] =3D MINTR_RST_ALL; - s->wregs[W_CLOCK] =3D CLOCK_TRXC; // Synch mode tx clock =3D TRxC - s->wregs[W_MISC2] =3D MISC2_PLLDIS; // PLL disabled + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts - if (s->disabled) + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - else + STATUS_CTS | STATUS_TXUNDRN; + } else { s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; =20 s->rx =3D s->tx =3D 0; @@ -300,21 +308,25 @@ static void escc_reset(DeviceState *d) static inline void set_rxint(ESCCChannelState *s) { s->rxint =3D 1; - /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower prio= rity - than chn_a rx/tx/special_condition service*/ + /* + * XXX: missing daisy chaining: escc_chn_b rx should have a lower prio= rity + * than chn_a rx/tx/special_condition service + */ s->rxint_under_svc =3D 1; if (s->chn =3D=3D escc_chn_a) { s->rregs[R_INTR] |=3D INTR_RXINTA; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HIRXINTA; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LORXINTA; + } } else { s->otherchn->rregs[R_INTR] |=3D INTR_RXINTB; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HIRXINTB; - else + } else { s->rregs[R_IVEC] =3D IVEC_LORXINTB; + } } escc_update_irq(s); } @@ -328,17 +340,18 @@ static inline void set_txint(ESCCChannelState *s) if (s->wregs[W_INTR] & INTR_TXINT) { s->rregs[R_INTR] |=3D INTR_TXINTA; } - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HITXINTA; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LOTXINTA; + } } else { s->rregs[R_IVEC] =3D IVEC_TXINTB; if (s->wregs[W_INTR] & INTR_TXINT) { s->otherchn->rregs[R_INTR] |=3D INTR_TXINTB; } } - escc_update_irq(s); + escc_update_irq(s); } } =20 @@ -347,20 +360,23 @@ static inline void clr_rxint(ESCCChannelState *s) s->rxint =3D 0; s->rxint_under_svc =3D 0; if (s->chn =3D=3D escc_chn_a) { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->rregs[R_INTR] &=3D ~INTR_RXINTA; } else { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->otherchn->rregs[R_INTR] &=3D ~INTR_RXINTB; } - if (s->txint) + if (s->txint) { set_txint(s); + } escc_update_irq(s); } =20 @@ -369,21 +385,24 @@ static inline void clr_txint(ESCCChannelState *s) s->txint =3D 0; s->txint_under_svc =3D 0; if (s->chn =3D=3D escc_chn_a) { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->rregs[R_INTR] &=3D ~INTR_TXINTA; } else { s->otherchn->rregs[R_INTR] &=3D ~INTR_TXINTB; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->otherchn->rregs[R_INTR] &=3D ~INTR_TXINTB; } - if (s->rxint) + if (s->rxint) { set_rxint(s); + } escc_update_irq(s); } =20 @@ -392,21 +411,24 @@ static void escc_update_parameters(ESCCChannelState *= s) int speed, parity, data_bits, stop_bits; QEMUSerialSetParams ssp; =20 - if (!qemu_chr_fe_backend_connected(&s->chr) || s->type !=3D escc_seria= l) + if (!qemu_chr_fe_backend_connected(&s->chr) || s->type !=3D escc_seria= l) { return; + } =20 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { - if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) + if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) { parity =3D 'E'; - else + } else { parity =3D 'O'; + } } else { parity =3D 'N'; } - if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) =3D=3D TXCTRL1_2STOP) + if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) =3D=3D TXCTRL1_2STOP) { stop_bits =3D 2; - else + } else { stop_bits =3D 1; + } switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { case TXCTRL2_5BITS: data_bits =3D 5; @@ -523,10 +545,11 @@ static void escc_mem_write(void *opaque, hwaddr addr, default: break; } - if (s->reg =3D=3D 0) + if (s->reg =3D=3D 0) { s->reg =3D newreg; - else + } else { s->reg =3D 0; + } break; case SERIAL_DATA: trace_escc_mem_writeb_data(CHN_C(s), val); @@ -538,17 +561,19 @@ static void escc_mem_write(void *opaque, hwaddr addr, s->txint =3D 0; escc_update_irq(s); s->tx =3D val; - if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled + if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */ if (qemu_chr_fe_backend_connected(&s->chr)) { - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ qemu_chr_fe_write_all(&s->chr, &s->tx, 1); } else if (s->type =3D=3D escc_kbd && !s->disabled) { handle_kbd_command(s, val); } } - s->rregs[R_STATUS] |=3D STATUS_TXEMPTY; // Tx buffer empty - s->rregs[R_SPEC] |=3D SPEC_ALLSENT; // All sent + s->rregs[R_STATUS] |=3D STATUS_TXEMPTY; /* Tx buffer empty */ + s->rregs[R_SPEC] |=3D SPEC_ALLSENT; /* All sent */ set_txint(s); break; default: @@ -606,12 +631,13 @@ static int serial_can_receive(void *opaque) ESCCChannelState *s =3D opaque; int ret; =20 - if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) =3D=3D 0) // Rx not enabled - || ((s->rregs[R_STATUS] & STATUS_RXAV) =3D=3D STATUS_RXAV)) - // char already available + if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) =3D=3D 0) /* Rx not enabled */ + || ((s->rregs[R_STATUS] & STATUS_RXAV) =3D=3D STATUS_RXAV)) { + /* char already available */ ret =3D 0; - else + } else { ret =3D 1; + } return ret; } =20 @@ -638,12 +664,13 @@ static void serial_receive1(void *opaque, const uint8= _t *buf, int size) static void serial_event(void *opaque, QEMUChrEvent event) { ESCCChannelState *s =3D opaque; - if (event =3D=3D CHR_EVENT_BREAK) + if (event =3D=3D CHR_EVENT_BREAK) { serial_receive_break(s); + } } =20 static const VMStateDescription vmstate_escc_chn =3D { - .name =3D"escc_chn", + .name =3D "escc_chn", .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { @@ -662,7 +689,7 @@ static const VMStateDescription vmstate_escc_chn =3D { }; =20 static const VMStateDescription vmstate_escc =3D { - .name =3D"escc", + .name =3D "escc", .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { @@ -734,21 +761,21 @@ static QemuInputHandler sunkbd_handler =3D { static void handle_kbd_command(ESCCChannelState *s, int val) { trace_escc_kbd_command(val); - if (s->led_mode) { // Ignore led byte + if (s->led_mode) { /* Ignore led byte */ s->led_mode =3D 0; return; } switch (val) { - case 1: // Reset, return type code + case 1: /* Reset, return type code */ clear_queue(s); put_queue(s, 0xff); - put_queue(s, 4); // Type 4 + put_queue(s, 4); /* Type 4 */ put_queue(s, 0x7f); break; - case 0xe: // Set leds + case 0xe: /* Set leds */ s->led_mode =3D 1; break; - case 7: // Query layout + case 7: /* Query layout */ case 0xf: clear_queue(s); put_queue(s, 0xfe); @@ -768,34 +795,39 @@ static void sunmouse_event(void *opaque, trace_escc_sunmouse_event(dx, dy, buttons_state); ch =3D 0x80 | 0x7; /* protocol start byte, no buttons pressed */ =20 - if (buttons_state & MOUSE_EVENT_LBUTTON) + if (buttons_state & MOUSE_EVENT_LBUTTON) { ch ^=3D 0x4; - if (buttons_state & MOUSE_EVENT_MBUTTON) + } + if (buttons_state & MOUSE_EVENT_MBUTTON) { ch ^=3D 0x2; - if (buttons_state & MOUSE_EVENT_RBUTTON) + } + if (buttons_state & MOUSE_EVENT_RBUTTON) { ch ^=3D 0x1; + } =20 put_queue(s, ch); =20 ch =3D dx; =20 - if (ch > 127) + if (ch > 127) { ch =3D 127; - else if (ch < -127) + } else if (ch < -127) { ch =3D -127; + } =20 put_queue(s, ch & 0xff); =20 ch =3D -dy; =20 - if (ch > 127) + if (ch > 127) { ch =3D 127; - else if (ch < -127) + } else if (ch < -127) { ch =3D -127; + } =20 put_queue(s, ch & 0xff); =20 - // MSC protocol specify two extra motion bytes + /* MSC protocol specifies two extra motion bytes */ =20 put_queue(s, 0); put_queue(s, 0); --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630670301150125.12305011906597; Fri, 3 Sep 2021 04:58:21 -0700 (PDT) Received: from localhost ([::1]:41352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7ps-0002z2-1k for importer@patchew.org; Fri, 03 Sep 2021 07:58:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7R3-0001uS-ST for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:42 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59830 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7R2-0005nn-D9 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:41 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qc-0009kl-8N; Fri, 03 Sep 2021 12:32:18 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:16 +0100 Message-Id: <20210903113223.19551-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 2/9] escc: reset register values to zero in escc_reset() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670303022100001 Content-Type: text/plain; charset="utf-8" This is to ensure that a device reset always returns the ESCC to a known st= ate. Note that this is currently redundant with the same code in escc_reset_chn() but that will change shortly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index c87ecd59d8..b0d3b92dc1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -300,9 +300,24 @@ static void escc_reset_chn(ESCCChannelState *s) static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); + int i, j; =20 - escc_reset_chn(&s->chn[0]); - escc_reset_chn(&s->chn[1]); + for (i =3D 0; i < 2; i++) { + ESCCChannelState *cs =3D &s->chn[i]; + + /* + * According to the ESCC datasheet "Miscellaneous Questions" secti= on + * on page 384, the values of the ESCC registers are not guarantee= d on + * power-on until an explicit hardware or software reset has been + * issued. For now we zero the registers so that a device reset al= ways + * returns the emulated device to a fixed state. + */ + for (j =3D 0; j < ESCC_SERIAL_REGS; j++) { + cs->rregs[j] =3D 0; + cs->wregs[j] =3D 0; + } + escc_reset_chn(cs); + } } =20 static inline void set_rxint(ESCCChannelState *s) --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16306703903351011.2948032192686; Fri, 3 Sep 2021 04:59:50 -0700 (PDT) Received: from localhost ([::1]:46012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7rG-0006ED-3e for importer@patchew.org; Fri, 03 Sep 2021 07:59:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7R8-0001yw-GL for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:46 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59834 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7R6-0005pA-Ur for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:46 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qg-0009kl-Ei; Fri, 03 Sep 2021 12:32:22 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:17 +0100 Message-Id: <20210903113223.19551-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 3/9] escc: introduce escc_soft_reset_chn() for software reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670390890100001 Content-Type: text/plain; charset="utf-8" This new software reset function is to be called when the appropriate chann= el software reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Add a new trace event when the guest initiates a soft reset via the WR9 reg= ister to help diagnose guest reset issues. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 40 ++++++++++++++++++++++++++++++++++++++-- hw/char/trace-events | 1 + 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index b0d3b92dc1..697f15f383 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -297,6 +297,40 @@ static void escc_reset_chn(ESCCChannelState *s) clear_queue(s); } =20 +static void escc_soft_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg =3D 0; + for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] =3D 0; + s->wregs[i] =3D 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; + s->wregs[W_MINTR] =3D MINTR_RST_ALL; + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + + s->rx =3D s->tx =3D 0; + s->rxint =3D s->txint =3D 0; + s->rxint_under_svc =3D s->txint_under_svc =3D 0; + s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); @@ -547,10 +581,12 @@ static void escc_mem_write(void *opaque, hwaddr addr, default: break; case MINTR_RST_B: - escc_reset_chn(&serial->chn[0]); + trace_escc_soft_reset_chn(CHN_C(&serial->chn[0])); + escc_soft_reset_chn(&serial->chn[0]); return; case MINTR_RST_A: - escc_reset_chn(&serial->chn[1]); + trace_escc_soft_reset_chn(CHN_C(&serial->chn[1])); + escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: escc_reset(DEVICE(serial)); diff --git a/hw/char/trace-events b/hw/char/trace-events index 1436fb462d..073f98ebe8 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t valu= e) "addr 0x%"PRIx64" va grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 =20 # escc.c +escc_soft_reset_chn(char channel) "soft reset channel %c" escc_put_queue(char channel, int b) "channel %c put: 0x%02x" escc_get_queue(char channel, int val) "channel %c get 0x%02x" escc_update_irq(int irq) "IRQ =3D %d" --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630669470966236.38236278266174; Fri, 3 Sep 2021 04:44:30 -0700 (PDT) Received: from localhost ([::1]:58816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7cT-0001mt-2a for importer@patchew.org; Fri, 03 Sep 2021 07:44:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RC-0002Cn-D4 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:50 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59842 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RA-0005r3-Qf for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:50 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qk-0009kl-L3; Fri, 03 Sep 2021 12:32:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:18 +0100 Message-Id: <20210903113223.19551-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630669471873100001 Content-Type: text/plain; charset="utf-8" This new hardware reset function is to be called for both channels when the hardware reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Add a new trace event when the guest initiates a hard reset via the WR9 reg= ister to help diagnose guest reset issues. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 38 +++++++++++++++++++++++++++++++++++++- hw/char/trace-events | 1 + 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 697f15f383..806f593738 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -331,6 +331,40 @@ static void escc_soft_reset_chn(ESCCChannelState *s) clear_queue(s); } =20 +static void escc_hard_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg =3D 0; + for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] =3D 0; + s->wregs[i] =3D 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; + s->wregs[W_MINTR] =3D MINTR_RST_ALL; + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + + s->rx =3D s->tx =3D 0; + s->rxint =3D s->txint =3D 0; + s->rxint_under_svc =3D s->txint_under_svc =3D 0; + s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); @@ -589,7 +623,9 @@ static void escc_mem_write(void *opaque, hwaddr addr, escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: - escc_reset(DEVICE(serial)); + trace_escc_hard_reset(); + escc_hard_reset_chn(&serial->chn[0]); + escc_hard_reset_chn(&serial->chn[1]); return; } break; diff --git a/hw/char/trace-events b/hw/char/trace-events index 073f98ebe8..b774832af4 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t valu= e) "addr 0x%"PRIx64" va grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 =20 # escc.c +escc_hard_reset(void) "hard reset" escc_soft_reset_chn(char channel) "soft reset channel %c" escc_put_queue(char channel, int b) "channel %c put: 0x%02x" escc_get_queue(char channel, int val) "channel %c get 0x%02x" --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630669777367929.4311585675296; Fri, 3 Sep 2021 04:49:37 -0700 (PDT) Received: from localhost ([::1]:38534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7hQ-0007UG-1G for importer@patchew.org; Fri, 03 Sep 2021 07:49:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RG-0002Uo-VW for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:55 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59850 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RF-0005t2-5S for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:54 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qo-0009kl-SK; Fri, 03 Sep 2021 12:32:31 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:19 +0100 Message-Id: <20210903113223.19551-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 5/9] escc: implement soft reset as described in the datasheet X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630669779574100001 Content-Type: text/plain; charset="utf-8" The software reset differs from a device reset in that it only changes the = contents of specific registers. Remove the code that resets all the registers to zer= o during soft reset and implement the default values listed in the table in the "Z85= C30 Reset" section. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 48 +++++++++++++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 806f593738..d5c7136e97 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -86,9 +86,11 @@ #define W_INTR 1 #define INTR_INTALL 0x01 #define INTR_TXINT 0x02 +#define INTR_PAR_SPEC 0x04 #define INTR_RXMODEMSK 0x18 #define INTR_RXINT1ST 0x08 #define INTR_RXINTALL 0x10 +#define INTR_WTRQ_TXRX 0x20 #define W_IVEC 2 #define W_RXCTRL 3 #define RXCTRL_RXEN 0x01 @@ -105,6 +107,7 @@ #define TXCTRL1_CLK64X 0xc0 #define TXCTRL1_CLKMSK 0xc0 #define W_TXCTRL2 5 +#define TXCTRL2_TXCRC 0x01 #define TXCTRL2_TXEN 0x08 #define TXCTRL2_BITMSK 0x60 #define TXCTRL2_5BITS 0x00 @@ -116,16 +119,24 @@ #define W_TXBUF 8 #define W_MINTR 9 #define MINTR_STATUSHI 0x10 +#define MINTR_SOFTIACK 0x20 #define MINTR_RST_MASK 0xc0 #define MINTR_RST_B 0x40 #define MINTR_RST_A 0x80 #define MINTR_RST_ALL 0xc0 #define W_MISC1 10 +#define MISC1_ENC_MASK 0x60 #define W_CLOCK 11 #define CLOCK_TRXC 0x08 #define W_BRGLO 12 #define W_BRGHI 13 #define W_MISC2 14 +#define MISC2_BRG_EN 0x01 +#define MISC2_BRG_SRC 0x02 +#define MISC2_LCL_LOOP 0x10 +#define MISC2_PLLCMD0 0x20 +#define MISC2_PLLCMD1 0x40 +#define MISC2_PLLCMD2 0x80 #define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 @@ -170,6 +181,7 @@ #define R_RXBUF 8 #define R_RXCTRL 9 #define R_MISC 10 +#define MISC_2CLKMISS 0x40 #define R_MISC1 11 #define R_BRGLO 12 #define R_BRGHI 13 @@ -299,30 +311,32 @@ static void escc_reset_chn(ESCCChannelState *s) =20 static void escc_soft_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ - s->wregs[W_CLOCK] =3D CLOCK_TRXC; + s->wregs[W_CMD] =3D 0; + s->wregs[W_INTR] &=3D INTR_PAR_SPEC | INTR_WTRQ_TXRX; + s->wregs[W_RXCTRL] &=3D ~RXCTRL_RXEN; + /* 1 stop bit */ + s->wregs[W_TXCTRL1] |=3D TXCTRL1_1STOP; + s->wregs[W_TXCTRL2] &=3D TXCTRL2_TXCRC | TXCTRL2_8BITS; + s->wregs[W_MINTR] &=3D ~MINTR_SOFTIACK; + s->wregs[W_MISC1] &=3D MISC1_ENC_MASK; /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; + s->wregs[W_MISC2] &=3D MISC2_BRG_EN | MISC2_BRG_SRC | + MISC2_PLLCMD1 | MISC2_PLLCMD2; + s->wregs[W_MISC2] |=3D MISC2_PLLCMD0; /* Enable most interrupts */ s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | EXTINT_TXUNDRN | EXTINT_BRKINT; + + s->rregs[R_STATUS] &=3D STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS= _BRK; + s->rregs[R_STATUS] |=3D STATUS_TXEMPTY | STATUS_TXUNDRN; if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + s->rregs[R_STATUS] |=3D STATUS_DCD | STATUS_SYNC | STATUS_CTS; } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + s->rregs[R_SPEC] &=3D SPEC_ALLSENT; + s->rregs[R_SPEC] |=3D SPEC_BITS8; + s->rregs[R_INTR] =3D 0; + s->rregs[R_MISC] &=3D MISC_2CLKMISS; =20 s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630670648161743.0025155923088; Fri, 3 Sep 2021 05:04:08 -0700 (PDT) Received: from localhost ([::1]:54030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7vT-0004Do-1g for importer@patchew.org; Fri, 03 Sep 2021 08:04:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RH-0002VB-31 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:55 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59856 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RF-0005t8-Jn for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:32:54 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qt-0009kl-41; Fri, 03 Sep 2021 12:32:31 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:20 +0100 Message-Id: <20210903113223.19551-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 6/9] escc: implement hard reset as described in the datasheet X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670650460100001 Content-Type: text/plain; charset="utf-8" The hardware reset differs from a device reset in that it only changes the = contents of specific registers. Remove the code that resets all the registers to zer= o during hardware reset and implement the default values using the existing soft res= et code with the additional changes listed in the table in the "Z85C30 Reset" secti= on. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 41 +++++++++++++---------------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index d5c7136e97..80f1d1b8fc 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -118,6 +118,8 @@ #define W_SYNC2 7 #define W_TXBUF 8 #define W_MINTR 9 +#define MINTR_VIS 0x01 +#define MINTR_NV 0x02 #define MINTR_STATUSHI 0x10 #define MINTR_SOFTIACK 0x20 #define MINTR_RST_MASK 0xc0 @@ -347,36 +349,19 @@ static void escc_soft_reset_chn(ESCCChannelState *s) =20 static void escc_hard_reset_chn(ESCCChannelState *s) { - int i; + escc_soft_reset_chn(s); =20 - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ + /* + * Hard reset is almost identical to soft reset above, except that the + * values of WR9 (W_MINTR), WR10 (W_MISC1), WR11 (W_CLOCK) and WR14 + * (W_MISC2) have extra bits forced to 0/1 + */ + s->wregs[W_MINTR] &=3D MINTR_VIS | MINTR_NV; + s->wregs[W_MINTR] |=3D MINTR_RST_B | MINTR_RST_A; + s->wregs[W_MISC1] =3D 0; s->wregs[W_CLOCK] =3D CLOCK_TRXC; - /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; - /* Enable most interrupts */ - s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; - if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; - } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; - - s->rx =3D s->tx =3D 0; - s->rxint =3D s->txint =3D 0; - s->rxint_under_svc =3D s->txint_under_svc =3D 0; - s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; - clear_queue(s); + s->wregs[W_MISC2] &=3D MISC2_PLLCMD1 | MISC2_PLLCMD2; + s->wregs[W_MISC2] |=3D MISC2_LCL_LOOP | MISC2_PLLCMD0; } =20 static void escc_reset(DeviceState *d) --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630669946330632.4223382400374; Fri, 3 Sep 2021 04:52:26 -0700 (PDT) Received: from localhost ([::1]:47268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7k8-000507-NM for importer@patchew.org; Fri, 03 Sep 2021 07:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RN-0002b4-Is for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:02 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59860 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RK-0005us-Cl for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:00 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qt-0009kl-EL; Fri, 03 Sep 2021 12:32:35 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:21 +0100 Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 7/9] escc: remove register changes from escc_reset_chn() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630669948559100001 Content-Type: text/plain; charset="utf-8" Now that register values at reset are handled elsewhere for all of device r= eset, soft reset and hard reset, escc_reset_chn() only needs to handle initialisa= tion of internal device state. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 80f1d1b8fc..22c97414a1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -139,7 +139,6 @@ #define MISC2_PLLCMD0 0x20 #define MISC2_PLLCMD1 0x40 #define MISC2_PLLCMD2 0x80 -#define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 #define EXTINT_SYNCINT 0x10 @@ -279,31 +278,7 @@ static void escc_update_irq(ESCCChannelState *s) =20 static void escc_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ - s->wregs[W_CLOCK] =3D CLOCK_TRXC; - /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; - /* Enable most interrupts */ - s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; - if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; - } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; - s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; s->rxint_under_svc =3D s->txint_under_svc =3D 0; --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16306700539141005.2048993991303; Fri, 3 Sep 2021 04:54:13 -0700 (PDT) Received: from localhost ([::1]:55936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7ls-0002Ee-RI for importer@patchew.org; Fri, 03 Sep 2021 07:54:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RP-0002bW-2L for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59868 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RN-0005wj-Mr for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:02 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7Qx-0009kl-KK; Fri, 03 Sep 2021 12:32:39 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:22 +0100 Message-Id: <20210903113223.19551-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 8/9] escc: re-use escc_reset_chn() for soft reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670055206100001 Content-Type: text/plain; charset="utf-8" This removes duplication of the internal device state initialisation between device reset and soft reset. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 22c97414a1..9283ed70a6 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -288,7 +288,8 @@ static void escc_reset_chn(ESCCChannelState *s) =20 static void escc_soft_reset_chn(ESCCChannelState *s) { - s->reg =3D 0; + escc_reset_chn(s); + s->wregs[W_CMD] =3D 0; s->wregs[W_INTR] &=3D INTR_PAR_SPEC | INTR_WTRQ_TXRX; s->wregs[W_RXCTRL] &=3D ~RXCTRL_RXEN; @@ -314,12 +315,6 @@ static void escc_soft_reset_chn(ESCCChannelState *s) s->rregs[R_SPEC] |=3D SPEC_BITS8; s->rregs[R_INTR] =3D 0; s->rregs[R_MISC] &=3D MISC_2CLKMISS; - - s->rx =3D s->tx =3D 0; - s->rxint =3D s->txint =3D 0; - s->rxint_under_svc =3D s->txint_under_svc =3D 0; - s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; - clear_queue(s); } =20 static void escc_hard_reset_chn(ESCCChannelState *s) --=20 2.20.1 From nobody Tue May 7 17:49:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630670236420659.5592263658605; Fri, 3 Sep 2021 04:57:16 -0700 (PDT) Received: from localhost ([::1]:36330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM7op-000845-Cd for importer@patchew.org; Fri, 03 Sep 2021 07:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RS-0002dE-Q5 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:07 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:59872 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM7RR-0005yj-DT for qemu-devel@nongnu.org; Fri, 03 Sep 2021 07:33:06 -0400 Received: from host86-140-11-91.range86-140.btcentralplus.com ([86.140.11.91] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mM7R1-0009kl-Pp; Fri, 03 Sep 2021 12:32:43 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 3 Sep 2021 12:32:23 +0100 Message-Id: <20210903113223.19551-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> References: <20210903113223.19551-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.140.11.91 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 9/9] escc: fix STATUS_SYNC bit in R_STATUS register X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630670237631100001 Content-Type: text/plain; charset="utf-8" After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should= remain high until the flag byte has been detected. Whilst the ESCC device doesn't = yet implement SDLC mode, without this change the active low STATUS_SYNC is cons= tantly asserted causing the MacOS OpenTransport extension to hang on startup as it= thinks it is constantly receiving LocalTalk responses during its initial negotiati= on phase. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 9283ed70a6..0fce4f6324 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -94,6 +94,7 @@ #define W_IVEC 2 #define W_RXCTRL 3 #define RXCTRL_RXEN 0x01 +#define RXCTRL_HUNT 0x10 #define W_TXCTRL1 4 #define TXCTRL1_PAREN 0x01 #define TXCTRL1_PAREV 0x02 @@ -561,7 +562,13 @@ static void escc_mem_write(void *opaque, hwaddr addr, break; } break; - case W_INTR ... W_RXCTRL: + case W_RXCTRL: + s->wregs[s->reg] =3D val; + if (val & RXCTRL_HUNT) { + s->rregs[R_STATUS] |=3D STATUS_SYNC; + } + break; + case W_INTR ... W_IVEC: case W_SYNC1 ... W_TXBUF: case W_MISC1 ... W_CLOCK: case W_MISC2 ... W_EXTINT: --=20 2.20.1