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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id f18sm2080257wmc.6.2021.09.02.09.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:17:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DdBo63POokH5fIMDIDGd3vZfaCJQwybOZKNS3BGh4nM=; b=SdUILgJd3l3KkosL5d+GJCCbjxa1kuvIi2eQH+QhbRZsxGZZeyT8B45EfAvb4vDqID Hvz12f+uLhG2sxeYjZh1eHobRoGFGmx8Vwc0IlXnnkf2IX5bx+BVhSr1cY3Ej8rlB7KC YO8ak4ncoqL6BecyY/e6YiTBs4ooYjlzwmmJGuU0TYXlpRik+gmohfcoQGfINeBVNh7H gfydQO5CesTCgYv9jzBSAmfhKaEn9YTmVKuXA9R7D2QLLI+i2p5DKESCrSigkULnbdYP q+rTwC0UOLH6fDszBS6ixFPljdENz9/dOQt5v2rlttm82OpvBLF+yYDt5s7Pj/jtLcYS Xgng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DdBo63POokH5fIMDIDGd3vZfaCJQwybOZKNS3BGh4nM=; b=YMuKqICZSHnMYbc5a2OH9Y+hzY9zR1daxu+G0MXHvt7DMUjQkzmQYsWAMpQFjMEc+O 9FPAeQ2Uorf4SCrvLF+Ey2DRCxLH/2w0Tf0vwn0o19rbPs8YZ41XzIfXtUcNnJ/aQuEK XFH/kjrW9ZiJUNCxYx9mD0emjIV5WALuvFkQZsaD3PbpjkT6b6ZIhu6iXqG0O59ufUGw Txkat+rr7KZh5/LKue7K7qiyj0xqoNtcSvMGefmG08pt2PjR4i+XRAo0mm7NOEyZViy1 Gwq9UYhw+qn6tiMpKZ4euWNDXjIuO8gATEDDiIblnfow+zEXf1eTS1SFpAirnYNJaq0E 7OIw== X-Gm-Message-State: AOAM530P6TsYjsdwkYkFM5aL0w4QowfreedNSZO3E8u3hBgn3BryLhZZ ukbz8N9/8qvR3GNxlQM36j4= X-Google-Smtp-Source: ABdhPJxeXOWsxsq5sHAGX+bjrNwp1kbgUUARJY9Fvv8rdRD0ZNZFO5Z6zZ0qv0LrIPXbrhuPF3RRHw== X-Received: by 2002:a1c:a50c:: with SMTP id o12mr4082621wme.4.1630599447661; Thu, 02 Sep 2021 09:17:27 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 16/30] target/microblaze: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:29 +0200 Message-Id: <20210902161543.417092-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630599451633100001 Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925f..74fbb5d201a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -92,12 +92,15 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 +#ifndef CONFIG_USER_ONLY + +#ifdef CONFIG_TCG static bool mb_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } +#endif /* CONFIG_TCG */ =20 -#ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { MicroBlazeCPU *cpu =3D opaque; @@ -142,7 +145,7 @@ static void microblaze_cpu_set_irq(void *opaque, int ir= q, int level) cpu_reset_interrupt(cs, type); } } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 static void mb_cpu_reset(DeviceState *dev) { @@ -368,6 +371,7 @@ static const struct TCGCPUOps mb_tcg_ops =3D { .tlb_fill =3D mb_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .has_work =3D mb_cpu_has_work, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, @@ -386,8 +390,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mb_cpu_class_by_name; - cc->has_work =3D mb_cpu_has_work; - cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; --=20 2.31.1