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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id d24sm1844328wmb.35.2021.09.02.08.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J1dcdIQ9CGWzlsg5Dn15xdm5h+WWHlgv9y5poU7SILU=; b=nmHWhKQc4cQ8poiZOsBSVna/+IcTO76/Xgy6htZ11++IGvST+0vsj0Yb7T3Y89mA+Z Ffse1o14BVN8xQOzx9UrVrpulHJEIbxJo+VhEDYcG4roPcXCNeWBCGzS0+ZqG2PKRoJp re1il8Yv50undaZa04WF33qAcSwcJDW1gW4zjfHLEwJlPNsBllGQR10uHMurMAme+Wu7 dFOwtQ/73yXO+wgQoWR8acLVbUZadySXnfEB1iUNfHJu/NwOxSSvj+DpSi0d+fLM4F+T zGhDfAOOBkk+j/NeBeQhgE/JQ9yMtol8kcN+rCUNSZhAl6Xn0nDC1r6GKNff9D3WAikU NnHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J1dcdIQ9CGWzlsg5Dn15xdm5h+WWHlgv9y5poU7SILU=; b=FgJj0JoUtbpJDr0Nh+jE8gl+U6Tm/8vDjmBWVS1m4A6rmxF/iH/MMuys/x05S71e3C PRXGZj0X6j5YBF+GYnEspRav+XhA/6Pnf/HwJzseuqa2srLO8bPWzu2qOuEsMnMzow/+ L4QeZRqaYwmAnwHcxUUG/WxvW05W0/Sr4/6sa47QDrhLG3FS3QfrXPxVghYpE5eSdiU7 NoUwlXcQBEE3mlKpqNmvDae3Mb3qDgSGa2D1Gn6IxoJIDi4sd+GjvxPHA4NnXZhzyJR+ W2dqxokCxQbuta96DzwHhxS3RkzYcrpLElvdWC2m6D/IFyQqPSX/QJrHLsS327vOJT6G LMRQ== X-Gm-Message-State: AOAM530psEvQcCXCmyW3kBZ1tHnrEbqHzye7x8R8A77J5vbcfSJrHiTV um/zQpgTjopfXHKw4mJe6Qc= X-Google-Smtp-Source: ABdhPJz7sxKzV5VkLGVMCrMgJ5rFnNDYqoRSnoIdz+9dydA+a9qoHCb3bjm9MTLJEtE5jEYVwPeO+g== X-Received: by 2002:a7b:c5d2:: with SMTP id n18mr3773265wmk.97.1630595962055; Thu, 02 Sep 2021 08:19:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Jiaxun Yang , qemu-arm@nongnu.org, Palmer Dabbelt , Max Filippov , Warner Losh , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Richard Henderson , Alistair Francis Subject: [PATCH 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Date: Thu, 2 Sep 2021 17:17:14 +0200 Message-Id: <20210902151715.383678-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org> References: <20210902151715.383678-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630595965311100001 All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded and remove the user-mode assertion. Also restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 4 ++-- accel/tcg/cpu-exec.c | 13 +++++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 600f0349659..bbec7760f48 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,8 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -68,6 +66,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5f4836946c1..7a6dd9049f0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -685,6 +685,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) return false; } =20 +#ifndef CONFIG_USER_ONLY /* * CPU_INTERRUPT_POLL is a virtual event which gets converted into a * "real" interrupt event later. It does not need to be recorded for @@ -698,12 +699,11 @@ static inline bool need_replay_interrupt(int interrup= t_request) return true; #endif } +#endif /* !CONFIG_USER_ONLY */ =20 static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or @@ -725,9 +725,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } -#if defined(CONFIG_USER_ONLY) - g_assert_not_reached(); -#endif +#if !defined(CONFIG_USER_ONLY) if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { /* Do nothing */ } else if (interrupt_request & CPU_INTERRUPT_HALT) { @@ -756,12 +754,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } -#endif +#endif /* !TARGET_I386 */ /* The target hook has 3 exit conditions: False when the interrupt isn't processed, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + if (cc->tcg_ops->cpu_exec_interrupt && cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { @@ -780,6 +780,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request =3D cpu->interrupt_request; } +#endif /* !CONFIG_USER_ONLY */ if (interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as --=20 2.31.1