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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id t5sm2171265wra.95.2021.09.02.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NjpYoE1+3YFnM0F4QDL6LEotiNFdmLxhe/DUiCLHaJM=; b=OE2IJqZijkuAu/dtbUlP6NrY1EsKCVCfz038HJYOXGJ8EDulteUPVw6555LSquq8R6 UyBKsyS8TbxCG0tsSFJvYB9ADJXpRn70/xtWLjcmzdXfF7x/a5hVHd20QXgWS8llqbvf RQfWoj9R/B+AWCxkrIr1BZvlzLejShTHQ+YSmEdC+u9eoEHoOc8rShzTgKV2UztPduyH vKYYjTOxemAwBu9hCc1RW8h+NqDRzfy3q8VqTvyxqN1YiXtUBK/Y/vT5Cs4ZwKZBSpGD jfyBQyX4dtNCXA6loITIiM3OL24aV4kpGFstbBz9jIIxjgf5jpPsl389IKvPiDBZC5i3 TFpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NjpYoE1+3YFnM0F4QDL6LEotiNFdmLxhe/DUiCLHaJM=; b=GmL7ZwzmUdbPD/l6cjLXf3RGPubki3HbkxnzV5+HSafxKCtql0Cf+6UAmLNXmBs8oY QAqEKsJLKmUXNThOy4rut1wCdjuRjo8TiNV+DtL/stKx1FNNxjD//57oNCFEiFDuqi1f sc1ZaUDB87H8YpjZE67gWtuu2eu7ONUreoounQan66QFReg4U82hFUvRH9ciN29ys28D co7ffgF17swVuVjqx11shF/+805cw+S4bMgenXUOCtIsxGEW7W/uszmhZAL8C4ULWix4 Mo6mKeZoyM6C1HHpU9R5MLdG2KPNAaKRjAOF3XVnecKFVs6WB+utXPnJedSjOidtHMXp lznA== X-Gm-Message-State: AOAM533sBAGIY2xpckse1dKxic+cXVmF/Tq6YrC7R2mDZOsgZmskhu7z zLTLnRi91PqUbeXA4fw94C0= X-Google-Smtp-Source: ABdhPJxHGkPXjKBYhlTr35f7CR7AMmKVY8Al83O7nq6m8XUpAKzCtMrlY8MqhAltIqo0aoW6RI9a5A== X-Received: by 2002:a5d:638b:: with SMTP id p11mr4313614wru.257.1630595934445; Thu, 02 Sep 2021 08:18:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Jiaxun Yang , qemu-arm@nongnu.org, Palmer Dabbelt , Max Filippov , Warner Losh , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Richard Henderson , Alistair Francis Subject: [PATCH 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu Date: Thu, 2 Sep 2021 17:17:09 +0200 Message-Id: <20210902151715.383678-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org> References: <20210902151715.383678-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630595938319100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 5 ----- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00b..e735e53e26c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); @@ -362,6 +361,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579c..13575c14085 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f4..701858d670c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *en= v) return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } -#endif =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return true; } } -#endif return false; } =20 -#if !defined(CONFIG_USER_ONLY) - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { --=20 2.31.1