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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id 17sm1830515wmj.20.2021.09.02.08.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qOhbKOMLJQTnP4opOKzKRsGwickHkRFQACXPCZkwzZ4=; b=MVdpwWPCgzsfVptRrLWGxJCKhgwtHmICPzS+494nVY58reKdXIcLJv+nFCR2fBuT1c EjD/e/B480ZHjRxYaeZYH1BzttEuTjVRPsxJF7w9Kccd0dazIjJBO/v824FVwQi4SF/2 jPMOcbajzTFpJLAsqEhBGLKlZcWOkxIQPgQT1iMo3axxsNyT5tEHTnWQSsgnVAjKccwp 2Ahm0ebcztLvCmzqqJggnwUKp860fyqXzCaSmQkCSNNyIBLStSA5MyHENKpNYQ2c0soE jbhOrcKT278czFzvKqt4yZOM3QGSxResVes+LfOyb4cbpvhNkwOdnkSvXuK7E+talVC8 6N6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qOhbKOMLJQTnP4opOKzKRsGwickHkRFQACXPCZkwzZ4=; b=jZtXA2/1cDxr3J4PrsCujY6UWv5bXtUvqPicgiAtNextOk0wIOEbeno5Mf+s+Ys/3/ EYPWCS95tX221NS9hs+Sg1bxryE0MZiLe3hjbGEmkzQ9XJ9Xj81Tah9cSSNh2V0ueSCH w9k+O2DPDE1imb7Imbngacf4WbccrgmacHSSHwoRgfxEAsT0cV9CL31zgUrZp4B3HYyR spu+k/iSe6Ajm2cZLTyDRgSbGzcVMByTSwtvnhXg2iFZZiSoZRlp8gCyhJiprAaXN+/i cqcWcD1mTeoOTn1YeQKaNKeI+lOwDjrE5bVu/tsvN7xvZ5LYht0rDZI1oO0wqLVADTqv Ue2A== X-Gm-Message-State: AOAM533zp4m8swI+cLEpFDNHmdSx1DYPivO9Bx2uD6fDhhZ5o7jjzn/r yIW+6hi+mNtplB38F71SomA= X-Google-Smtp-Source: ABdhPJysv/O1nATy+Iu5ULEGo2DtI3bT2Rsk+0/uZ+uSNrF4KOuKlIytm6Z9sf/zOU+f6QI7ieRRvw== X-Received: by 2002:adf:c3c8:: with SMTP id d8mr4413659wrg.143.1630595912991; Thu, 02 Sep 2021 08:18:32 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Jiaxun Yang , qemu-arm@nongnu.org, Palmer Dabbelt , Max Filippov , Warner Losh , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Richard Henderson , Alistair Francis Subject: [PATCH 14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu Date: Thu, 2 Sep 2021 17:17:05 +0200 Message-Id: <20210902151715.383678-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org> References: <20210902151715.383678-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630595915550100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 5 +++-- target/mips/cpu.c | 2 +- target/mips/tcg/exception.c | 18 ------------------ target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++ target/mips/tcg/user/tlb_helper.c | 5 ----- 5 files changed, 22 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219e..c7a77ddccdd 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,8 +18,6 @@ void mips_tcg_init(void); =20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -41,6 +39,9 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMI= PSState *env, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); + void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d426918291a..00e0c55d0e4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D { static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .tlb_fill =3D mips_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 4fb8b00711d..7b3026b105b 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tr= anslationBlock *tb) env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } =20 -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index a150a014ec1..73254d19298 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D EXCP_NONE; } =20 +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index b835144b820..210c6d529ef 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, raise_mmu_exception(env, address, access_type); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } - -void mips_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D EXCP_NONE; -} --=20 2.31.1