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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id i68sm2187724wri.26.2021.09.02.08.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fcD3NEKxqm51zeSb+lOjnaiMKTAZvQ5t+y/MQ7dqNn4=; b=SoWG2/wQj0ymZnxrkfnJDZKSuaHnBEMFz8bj97s4TV8NBQ32xc7+kcPUd2yLDhsC5w CegLWLfFZOULB2qsUNRjw+d2r+k3oF5emn6c+qVl/cYK5dAaqAfGfOr63WsjWUXmblZe 8lAXQg76gUsp7/QeheJxgFIDlfA3lzhHP8vaadbZZy65HaXI0jSTTilO+xsyM0ObpCaI 1WZYFfdRQSUI+DQiDYLuB3JRb6b+9HRuSpiCvCksshLQ9/SAHDt+4b2ts7wdAmx7LI/b aXd8JGK6rh9NXMW4PAkUxBdyjcCdcZFrQRWxuxxsnQZyyVx1N6Bq3sj1VDFaA8/6sewn fSIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fcD3NEKxqm51zeSb+lOjnaiMKTAZvQ5t+y/MQ7dqNn4=; b=PjT/yWtMd21vb+RPZxRRs6dg5222KCdoeyltzaYRvr71diEzpC4sNV//h/YC8bPD8Z he/gNjO1ZDijSqRRWG8VQD6kbQKs54Bezf/hOY8aya/eCSs50PGMd1sLntlz+x7Inbuq kzzxmEjnIMKQxQ0qjTuGhtWP1ikJXejNKHbH+93CQA9Ks1zJWsrLFnlZ68JbJCJX89A9 K62rNwCWutZ0n1b+xZQ67gAw2dddsP5VB5ntBIRbRpcR4J5cDPLczHEGFhLBalJC8xDR VROSASCO/6rQe1zkWijuabrd2iu1mtZDgQWtFMt0UT5+HTw4DRvAGhS6KyTNxbj3dDrP RzBA== X-Gm-Message-State: AOAM533NSufMpL/9nlMP+cJBTiD4gaup90kY8xlw2sNMcLy9v2J3pedu x7bdZa7tJ9RwTcYwXlMqo2c= X-Google-Smtp-Source: ABdhPJyMdX6G1vQy+2o7TKZglcvYLmKGkf97DRaIkpPbJyZVsKwfU5KX+Ng4s35R1vCWNozyEXOtYA== X-Received: by 2002:a7b:c94c:: with SMTP id i12mr3769142wml.111.1630595897048; Thu, 02 Sep 2021 08:18:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Jiaxun Yang , qemu-arm@nongnu.org, Palmer Dabbelt , Max Filippov , Warner Losh , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Richard Henderson , Alistair Francis Subject: [PATCH 11/24] target/i386: Restrict cpu_exec_interrupt() handler to sysemu Date: Thu, 2 Sep 2021 17:17:02 +0200 Message-Id: <20210902151715.383678-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org> References: <20210902151715.383678-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630595900182100001 Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- target/i386/tcg/helper-tcg.h | 2 ++ target/i386/tcg/seg_helper.c | 10 ++-------- target/i386/tcg/tcg-cpu.c | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 2510cc244e9..60ca09e95eb 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_S= PACE_BITS); * @cpu: vCPU the interrupt is to be handled by. */ void x86_cpu_do_interrupt(CPUState *cpu); +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif =20 /* helper.c */ bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index dee7bef68c6..13c6e6ee62e 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int i= ntno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) * This is required to make icount-driven execution deterministic. */ switch (interrupt_request) { -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_POLL: cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); break; -#endif case CPU_INTERRUPT_SIPI: do_cpu_sipi(cpu); break; case CPU_INTERRUPT_SMI: cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; -#ifdef CONFIG_USER_ONLY - cpu_abort(CPU(cpu), "SMI interrupt: cannot enter SMM in user-mode"= ); -#else do_smm_enter(cpu); -#endif /* CONFIG_USER_ONLY */ break; case CPU_INTERRUPT_NMI: cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); @@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) "Servicing hardware INT=3D0x%02x\n", intno); do_interrupt_x86_hardirq(env, intno, 1); break; -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_VIRQ: /* FIXME: this should respect TPR */ cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); @@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) do_interrupt_x86_hardirq(env, intno, 1); cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; break; -#endif } =20 /* Ensure that no TB jump will be modified as the program flow was cha= nged. */ return true; } +#endif /* CONFIG_USER_ONLY */ =20 void helper_lldt(CPUX86State *env, int selector) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index dce800a8953..fd86daf93d2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, - .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .tlb_fill =3D x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_exception =3D x86_cpu_do_interrupt, #else .do_interrupt =3D x86_cpu_do_interrupt, + .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ --=20 2.31.1