From nobody Fri May 3 07:14:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630595531; cv=none; d=zohomail.com; s=zohoarc; b=jzvmN0DRlDnC7PCMgRUWScZ+tinV46mooTx4bRFtDnWnUqfGEMQl3IsqAWAgHGHrzztawiftZFq/uQ7O023r9GIhSDTe8Tqvz7uKe+PEVqaNT8kmEKfWKmM3BRTHUbBpKTBpUCiTePImBOv/QuDbCOukn24WBZyPs4FPGDYc4ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630595531; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1GDIll3Av4qQx8oCwKBUtu2UrHTCpi3Blkr0Kr5nmJg=; b=jwKiszxmlLi/moH4xKHtet0JpmHRIYC9SO+y+2QP7jSNQFjpR08lyslcbr2Esjgavn9SNZ/ZitIYy03JKBjpXsNYachXMz2BW/abKkwXOqOecMQF7FlmUkTEnILJ7mcznzKMbwfEThL29Py2aI4nbmHwEFXTTh138192UTRHTbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630595531370286.9464029016601; Thu, 2 Sep 2021 08:12:11 -0700 (PDT) Received: from localhost ([::1]:45698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLoNu-0005U5-5D for importer@patchew.org; Thu, 02 Sep 2021 11:12:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLoL7-0000R4-AU for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:17 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:54898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLoL4-0003Of-Sz for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:17 -0400 Received: by mail-wm1-x330.google.com with SMTP id g138so1512672wmg.4 for ; Thu, 02 Sep 2021 08:09:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c24sm2107842wrb.57.2021.09.02.08.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:09:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1GDIll3Av4qQx8oCwKBUtu2UrHTCpi3Blkr0Kr5nmJg=; b=asQzEQcvty1KByuCZjXGLEW2Ezsw8VDK/HEzIonZkHcN+fzZZ/yGoQDEP/GlihlEt6 P7eYYqA3+ur9ejxvSgD9zGLxVmvQEz8gxAQdGz26dzLSC9hXbWxK6UczIVmnAO1NHRpe y3upnhOO4R8wv30cBfWFZDQWz7Wo8CObEjchfHqG1OJnUhl8/vKxK8v+wP9ylq5tUEY3 u51OIhvENneRNNn43HMk/8i3KBAmOKrTD1uxGV28KFs4voJGbVjh8QDal0pgG35kE31e +Nzv+ID9BEDkYO07XoI+5rDks9CkX2gGGxE+IxXy1XJhC1TK2GSdnyOjlRRn+Knhh9z1 utvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GDIll3Av4qQx8oCwKBUtu2UrHTCpi3Blkr0Kr5nmJg=; b=FsRmYKd7tFaPPkELdbxDcK/AWE/F4Y6vR9tjVp5/65c0P91M2Smdx0gBoZO+/pI8FT YBajzX2i9bbIs8wz7ILTIt8TwKxpS173aNnkI83lSR4+lQP2IBdxPy7rodLRJ50Mw2H3 ZycSVmsUfhMumTWy60VIwMzW6vlb9YdwCzd+9RZUVgZKToRTse6s10jcCLsw39vc6bSj 2ioBQeSWSnE45pYYNun7bXzULk4sYJ3XbIQ5PCPHlEumWx6F6oYIJzgVvk6fWk41xKlm yB7+zV4+yiNoWYhZnhp8z5xnYybbMaICX/tjsJ0i/q0gVMOo6VIeZNxaEv0Mz6o4n7jj psow== X-Gm-Message-State: AOAM530wvY6ShJv1iVAWjnsZr+YnAbEiw+6rVZ/UP/MRTxrgNLvuo6jd 95RdFLu+DXHfSO4szAwrSaooWw== X-Google-Smtp-Source: ABdhPJzPRUtME3bEuGybo9N+TiIH4FGx2+4WjEvIg3Fao3BVyL/x/g6Xm2Q+uYa9zgEJCalLXsaiRQ== X-Received: by 2002:a7b:cb01:: with SMTP id u1mr3624272wmj.152.1630595353529; Thu, 02 Sep 2021 08:09:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/4] target/arm: Add TB flag for "MVE insns not predicated" Date: Thu, 2 Sep 2021 16:09:07 +0100 Message-Id: <20210902150910.15748-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902150910.15748-1-peter.maydell@linaro.org> References: <20210902150910.15748-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630595533192100001 Content-Type: text/plain; charset="utf-8" Our current codegen for MVE always calls out to helper functions, because some byte lanes might be predicated. The common case is that in fact there is no predication active and all lanes should be updated together, so we can produce better code by detecting that and using the TCG generic vector infrastructure. Add a TB flag that is set when we can guarantee that there is no active MVE predication, and a bool in the DisasContext. Subsequent patches will use this flag to generate improved code for some instructions. Signed-off-by: Peter Maydell --- Another of those awkward-to-review patches where the interesting question is "did I miss anywhere where we set v7m.vpr to non-0 or v7m.ltpsize to non-4 while in the middle of a TB ?" ... I've left the TB flag as non-cached because there seemed to be an irritatingly large set of places where we'd have to do an hflags recomputation. --- target/arm/cpu.h | 4 +++- target/arm/translate.h | 2 ++ target/arm/helper.c | 23 +++++++++++++++++++++++ target/arm/translate-m-nocp.c | 8 ++++++++ target/arm/translate-mve.c | 9 ++++++++- target/arm/translate-vfp.c | 3 +++ target/arm/translate.c | 4 ++++ 7 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a987f65e41..460d611e65e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3440,7 +3440,7 @@ typedef ARMCPU ArchCPU; * | TBFLAG_AM32 | +-----+----------+ * | | |TBFLAG_M32| * +-------------+----------------+----------+ - * 31 23 5 4 0 + * 31 23 6 5 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3497,6 +3497,8 @@ FIELD(TBFLAG_M32, LSPACT, 2, 1) /* No= t cached. */ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ +/* Set if MVE insns are definitely not predicated */ +FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ =20 /* * Bit usage when in AArch64 state diff --git a/target/arm/translate.h b/target/arm/translate.h index 8636c20c3b4..908b8ded8ee 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -98,6 +98,8 @@ typedef struct DisasContext { bool hstr_active; /* True if memory operations require alignment */ bool align_mem; + /* True if MVE insns are definitely not predicated for any reason */ + bool mve_no_pred; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index a7ae78146d4..cf41b746b64 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13673,6 +13673,25 @@ static inline void assert_hflags_rebuild_correctly= (CPUARMState *env) #endif } =20 +static bool mve_no_predication(CPUARMState *env) +{ + /* + * Return true if there is definitely no predication of MVE + * instructions for any reason. (Returning false even if there + * isn't any predication is OK; generated code will just be + * a little worse.) + * We do not account here for partial insn execution due to + * ECI bits as those are already in the TB flags elsewhere. + */ + if (env->v7m.vpr) { + return false; + } + if (env->v7m.ltpsize < 4) { + return false; + } + return true; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -13712,6 +13731,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { DP_TBFLAG_M32(flags, LSPACT, 1); } + + if (mve_no_predication(env)) { + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); + } } else { /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 5eab04832cd..79613fc150a 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -92,6 +92,8 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) gen_helper_v7m_vlstm(cpu_env, fptr); } tcg_temp_free_i32(fptr); + /* VLLDM or VLSTM helpers might have updated vpr or ltpsize */ + s->mve_no_pred =3D false; =20 clear_eci_state(s); =20 @@ -326,6 +328,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, case ARM_VFP_FPSCR: tmp =3D loadfn(s, opaque, true); gen_helper_vfp_set_fpscr(cpu_env, tmp); + s->mve_no_pred =3D false; tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; @@ -397,6 +400,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, store_cpu_field(control, v7m.control[M_REG_S]); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); gen_helper_vfp_set_fpscr(cpu_env, tmp); + s->mve_no_pred =3D false; tcg_temp_free_i32(tmp); tcg_temp_free_i32(sfpa); break; @@ -409,6 +413,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, } tmp =3D loadfn(s, opaque, true); store_cpu_field(tmp, v7m.vpr); + s->mve_no_pred =3D false; break; case ARM_VFP_P0: { @@ -418,6 +423,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_deposit_i32(vpr, vpr, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); store_cpu_field(vpr, v7m.vpr); + s->mve_no_pred =3D false; tcg_temp_free_i32(tmp); break; } @@ -500,6 +506,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, store_cpu_field(control, v7m.control[M_REG_S]); fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); + s->mve_no_pred =3D false; tcg_temp_free_i32(fpscr); lookup_tb =3D true; break; @@ -549,6 +556,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, zero =3D tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); + s->mve_no_pred =3D false; tcg_temp_free_i32(zero); tcg_temp_free_i32(sfpa); tcg_temp_free_i32(fpdscr); diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2ed91577ec8..d95807541b1 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -810,7 +810,11 @@ DO_LOGIC(VORR, gen_helper_mve_vorr) DO_LOGIC(VORN, gen_helper_mve_vorn) DO_LOGIC(VEOR, gen_helper_mve_veor) =20 -DO_LOGIC(VPSEL, gen_helper_mve_vpsel) +static bool trans_VPSEL(DisasContext *s, arg_2op *a) +{ + s->mve_no_pred =3D false; + return do_2op(s, a, gen_helper_mve_vpsel); +} =20 #define DO_2OP(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ @@ -1366,6 +1370,7 @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) } =20 gen_helper_mve_vpnot(cpu_env); + s->mve_no_pred =3D false; mve_update_eci(s); return true; } @@ -1852,6 +1857,7 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVE= GenCmpFn *fn) /* VPT */ gen_vpst(s, a->mask); } + s->mve_no_pred =3D false; mve_update_eci(s); return true; } @@ -1883,6 +1889,7 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_= scalar *a, /* VPT */ gen_vpst(s, a->mask); } + s->mve_no_pred =3D false; mve_update_eci(s); return true; } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index e2eb797c829..155ca69075b 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -128,6 +128,8 @@ static void gen_preserve_fp_state(DisasContext *s) * any further FP insns in this TB. */ s->v7m_lspact =3D false; + /* Helper might have updated vpr or ltpsize */ + s->mve_no_pred =3D false; } } =20 @@ -164,6 +166,7 @@ static void gen_update_fp_context(DisasContext *s) =20 fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); + s->mve_no_pred =3D false; tcg_temp_free_i32(fpscr); if (dc_isar_feature(aa32_mve, s)) { TCGv_i32 z32 =3D tcg_const_i32(0); diff --git a/target/arm/translate.c b/target/arm/translate.c index 24b7f49d767..54c31ad6dec 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8464,6 +8464,7 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) /* DLSTP: set FPSCR.LTPSIZE */ tmp =3D tcg_const_i32(a->size); store_cpu_field(tmp, v7m.ltpsize); + s->mve_no_pred =3D false; } return true; } @@ -8529,6 +8530,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) assert(ok); tmp =3D tcg_const_i32(a->size); store_cpu_field(tmp, v7m.ltpsize); + s->mve_no_pred =3D false; } gen_jmp_tb(s, s->base.pc_next, 1); =20 @@ -8711,6 +8713,7 @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a) gen_helper_mve_vctp(cpu_env, masklen); tcg_temp_free_i32(masklen); tcg_temp_free_i32(rn_shifted); + s->mve_no_pred =3D false; mve_update_eci(s); return true; } @@ -9370,6 +9373,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->v7m_new_fp_ctxt_needed =3D EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); dc->v7m_lspact =3D EX_TBFLAG_M32(tb_flags, LSPACT); + dc->mve_no_pred =3D EX_TBFLAG_M32(tb_flags, MVE_NO_PRED) && dc->ec= i =3D=3D 0; } else { dc->debug_target_el =3D EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); dc->sctlr_b =3D EX_TBFLAG_A32(tb_flags, SCTLR__B); --=20 2.20.1 From nobody Fri May 3 07:14:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630595493; cv=none; d=zohomail.com; s=zohoarc; b=DZA5XPly7ZT0h1L+d83HmjQovVmetINAlXWfKVnxfLcHCQXuccUxOcKfRscHhJ0ZLYpfUl1P313o+PQ53Bkt9JNYHACmNUTwcg1ZYkHqlIeqdEmjNjutiuZhnPdYDkcmhG3iVtF71BHjFXbleduUG9JbJ4UgpYqZpDcU1E6Ruvo= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c24sm2107842wrb.57.2021.09.02.08.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:09:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IOs+ybtxzQvBd0zTnc8h9eQMrze7nEv95Ct+IYf1dzY=; b=TTQVdtRMl79lUFvi/5MnSRHMqI4lwLDMAuQ3QwZCzd1D/omBeMZ9W5pPQIoJ/36fhn AVjt3f2CUz7ea959LqNR0PkxwWUPCQyv19EBQVGCHEoNxUiVkLGobINtZafPagFOvCPR me4qRVa686byFU9xQ5G2UqgWPKMyQd75s13qA9Tv/r6nxpBRiEThrFTDu05FsGFChH0y wKrizWiKyH5D5SC9IG+/rfUdTFySCnV+pTJcyv9MgMdyDHItx4auEgUCPIvDL1EowM3+ RJnOJ2TUg+re5e3iVCFCfvUlRhR/2542QDhXKHzqWtq+wR0LunXyBxoGM+kTy0M47QXp BK1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IOs+ybtxzQvBd0zTnc8h9eQMrze7nEv95Ct+IYf1dzY=; b=TcIH/djlmB5UNKx0M7vvoqZ9XEkPkZv9PHVR3yrnLQUARNgIO4p398kb9QxPWCJYxq 7p/C0qGIli/haBY4es+L3G09OhHV7XbOh+hudNYxmiz1cWGBkwYMCR4/E3Lw9T80hpzx R+6zafHw4VYZaQ9kkpyumEOrDv5EczVhAjVign0TYncPlo6fSeST8PadpvJo2xd1H6Cc gRQAVGTB1nx/QYG2J/wF/mTOoqPKu105qfxWDFwL0zLq3OwbcjJUOomKp6/FQZ79vGcS 09qc9HqasO7uLPW3EYEhkGPbKA6Cf9auiNwqSGDGtMWH8kg+S5Z5Qi38Rv37r1S4cOam z2KQ== X-Gm-Message-State: AOAM533oB2d+wiDlebc6NuzTBGFtB/fhphcXcBTD/9k8nyElztfbKhVJ pH3h5/tkXQx9+4ld1XcPPiTQuA== X-Google-Smtp-Source: ABdhPJyKxWsjYQ1lT/7oxxAxdRo7OUCBVdWOxTGG0gHPcZNZu/9yrDBMMc0hA80Nqxlns2s3Uh7S7Q== X-Received: by 2002:a1c:f405:: with SMTP id z5mr3681019wma.33.1630595354213; Thu, 02 Sep 2021 08:09:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/4] target/arm: Optimize MVE logic ops Date: Thu, 2 Sep 2021 16:09:08 +0100 Message-Id: <20210902150910.15748-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902150910.15748-1-peter.maydell@linaro.org> References: <20210902150910.15748-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630595494869100001 Content-Type: text/plain; charset="utf-8" When not predicating, implement the MVE bitwise logical insns directly using TCG vector operations. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 41 ++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d95807541b1..087d60f0d81 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -774,7 +774,8 @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) return do_1op(s, a, fns[a->size]); } =20 -static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) +static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn, + GVecGen3Fn *vecfn) { TCGv_ptr qd, qn, qm; =20 @@ -787,28 +788,38 @@ static bool do_2op(DisasContext *s, arg_2op *a, MVEGe= nTwoOpFn fn) return true; } =20 - qd =3D mve_qreg_ptr(a->qd); - qn =3D mve_qreg_ptr(a->qn); - qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qn, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); + if (vecfn && s->mve_no_pred) { + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn), + mve_qreg_offset(a->qm), 16, 16); + } else { + qd =3D mve_qreg_ptr(a->qd); + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qn, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + } mve_update_eci(s); return true; } =20 -#define DO_LOGIC(INSN, HELPER) \ +static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn) +{ + return do_2op_vec(s, a, fn, NULL); +} + +#define DO_LOGIC(INSN, HELPER, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ { \ - return do_2op(s, a, HELPER); \ + return do_2op_vec(s, a, HELPER, VECFN); \ } =20 -DO_LOGIC(VAND, gen_helper_mve_vand) -DO_LOGIC(VBIC, gen_helper_mve_vbic) -DO_LOGIC(VORR, gen_helper_mve_vorr) -DO_LOGIC(VORN, gen_helper_mve_vorn) -DO_LOGIC(VEOR, gen_helper_mve_veor) +DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and) +DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc) +DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or) +DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc) +DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor) =20 static bool trans_VPSEL(DisasContext *s, arg_2op *a) { --=20 2.20.1 From nobody Fri May 3 07:14:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630595810; cv=none; d=zohomail.com; s=zohoarc; b=c3odfW6jIBKrb2g8CjxQhTZYzfMhpXJEqvPixgrNnI3m3DbduHEuL28891Twl4f7SLivA8ucbHwZMwvTKURl86eGw7taqTYcJWrVOIjqf4OvTMn/9d6xrNqOzqvHk4bwskX5l7ra9pqDXay9lA79I8r+FLVnUcPR+6XF3QyhG8o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630595810; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zzmLZYqNkL0qfTbdS2xsSiJj4fXt0+iIGVR8nAz1VxA=; b=lZojAJQIp4enYqFTFO3HBURoBh/y25q7N79WdjtPEgaZDIDJHXyX5WF70ZAuW+ROxkHI+EeOdE0mYDAwQBUG3YdmG0Vju4ZE2DSV61SeoaLLRplvMu8vEz3lHBunSTFUqRyDiP/CCJcUbsShKGxnFT0KfDMYPQvbVcq8B8l8rnw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630595810825356.62199093481854; Thu, 2 Sep 2021 08:16:50 -0700 (PDT) Received: from localhost ([::1]:51990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLoSP-0001bl-Mu for importer@patchew.org; Thu, 02 Sep 2021 11:16:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLoL9-0000WO-2R for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:19 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:35397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLoL6-0003QQ-PR for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:18 -0400 Received: by mail-wr1-x42b.google.com with SMTP id i6so3485752wrv.2 for ; Thu, 02 Sep 2021 08:09:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c24sm2107842wrb.57.2021.09.02.08.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:09:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zzmLZYqNkL0qfTbdS2xsSiJj4fXt0+iIGVR8nAz1VxA=; b=OXsDlD8uEnyvc9weEuttBAmWjGT9tUr7KFFDKESQ8eEGUTNqKlhGaqAACkWg4Zgtx2 x4kQ+TesPuE5rT/0vk/Khz+50Aatzk9Dhm8jqOOXmxICrFJIUDIjPR4K3PMhjWBKEJQi ivFppqa/vuDAI4JYzNaMErmaeSMfcUUpkK8Rl0G6cRhzAn/acTgEs8IRw/IqekP8wuXk fzJulKY11ekwuBUDoWG07/sv9HMuv46NmAUXF8d0NbsZZPjuYzHa39TSz3B2RADylB4z 0E8F/s4QbzMwRvvf2gpWWmwKied9KekZQG+wS32/DJl3MA7r0K1VXvFrKEKAVB6opXZA jiqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zzmLZYqNkL0qfTbdS2xsSiJj4fXt0+iIGVR8nAz1VxA=; b=it744Q0tt2I7MPWaXhGOjEXK97UBhdV3Oa2wNCXEwL06meJ7Xd2nbdGwgdnj8XfLSj RD8ZiDO94SgHZhaPjNyf6D0vxYofRofh+isLRxF0gNMJ+SWU9lonekPiZbr8awo3xl9+ UweqQARE5Rngqj6COMxUbxggbSBzoefn47d5c4EvvyVQhglGu6Eiqo6BQXHxr3wQpQez d+UigmaoOBeaIhzJE41wxeQSbReaZcRVN7IFIqCyxnst9eg4oZzLE5zVfsoSpJgNc4c9 veHCLDDYGqrQjqEFdA4+Jf4/ZQKbMeKmFPi9gHfAo4P+pQx8Mju5QJBrWXZGbmJ5VIMs HZHw== X-Gm-Message-State: AOAM532e67DXXuV9+rUplw6WTRI4TxlDkblndyMoboxDs7FRgmj5fAUL 9xrCAp80MQSkAHB8f6WfbcpioA== X-Google-Smtp-Source: ABdhPJxekN3GJEzFeAygb1vYAGYrCcIMIxQAwMCwMg0EJGLd5qMiKi+oUvpNZ/iF4K1r395i74Sekw== X-Received: by 2002:adf:9e49:: with SMTP id v9mr4269020wre.39.1630595355226; Thu, 02 Sep 2021 08:09:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/4] target/arm: Optimize MVE arithmetic ops Date: Thu, 2 Sep 2021 16:09:09 +0100 Message-Id: <20210902150910.15748-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902150910.15748-1-peter.maydell@linaro.org> References: <20210902150910.15748-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630595812027100001 Content-Type: text/plain; charset="utf-8" Optimize MVE arithmetic ops when we have a TCG vector operation we can use. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 087d60f0d81..5bc5a3a2063 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -827,7 +827,7 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) return do_2op(s, a, gen_helper_mve_vpsel); } =20 -#define DO_2OP(INSN, FN) \ +#define DO_2OP_VEC(INSN, FN, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ { \ static MVEGenTwoOpFn * const fns[] =3D { \ @@ -836,20 +836,22 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) gen_helper_mve_##FN##w, \ NULL, \ }; \ - return do_2op(s, a, fns[a->size]); \ + return do_2op_vec(s, a, fns[a->size], VECFN); \ } =20 -DO_2OP(VADD, vadd) -DO_2OP(VSUB, vsub) -DO_2OP(VMUL, vmul) +#define DO_2OP(INSN, FN) DO_2OP_VEC(INSN, FN, NULL) + +DO_2OP_VEC(VADD, vadd, tcg_gen_gvec_add) +DO_2OP_VEC(VSUB, vsub, tcg_gen_gvec_sub) +DO_2OP_VEC(VMUL, vmul, tcg_gen_gvec_mul) DO_2OP(VMULH_S, vmulhs) DO_2OP(VMULH_U, vmulhu) DO_2OP(VRMULH_S, vrmulhs) DO_2OP(VRMULH_U, vrmulhu) -DO_2OP(VMAX_S, vmaxs) -DO_2OP(VMAX_U, vmaxu) -DO_2OP(VMIN_S, vmins) -DO_2OP(VMIN_U, vminu) +DO_2OP_VEC(VMAX_S, vmaxs, tcg_gen_gvec_smax) +DO_2OP_VEC(VMAX_U, vmaxu, tcg_gen_gvec_umax) +DO_2OP_VEC(VMIN_S, vmins, tcg_gen_gvec_smin) +DO_2OP_VEC(VMIN_U, vminu, tcg_gen_gvec_umin) DO_2OP(VABD_S, vabds) DO_2OP(VABD_U, vabdu) DO_2OP(VHADD_S, vhadds) --=20 2.20.1 From nobody Fri May 3 07:14:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630595779; cv=none; d=zohomail.com; s=zohoarc; b=YnycshDG00zRH9ADT3EVGTc8q/OZwD6vmwrWthIcpJ36JvV4CTi6qyH/YWuSEbsMpKZEvvZpemZaYGbjH5vUx9s3Kh/ObeWYHDyF0770izT6rrkHzZYe4GSPw+1hq4mMcE1L99Y0VA6f6boMWZScpF40TcEA52ubDV5CExMhzls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630595779; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hTL0YVceSstDhE4eWuPfHB9Yy35Pz6ourVXwIf0vsMU=; b=c8AaO/IanqhrJjTvgg8yyoxyj8Vgn+UF0dYKOe4/nwKuyakQqmRuxCkB+zACpSlmQIumA6k+3blE1Ti2X1Qg0oI7ePHur5mC95wrlzNfK2WNcJR8bzSermEFx/c4WVbnvbSkQuO0WWieyFz0w/a8m8e4bfkK6VNYRmx/iT8Yecc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16305957799501009.69062842086; Thu, 2 Sep 2021 08:16:19 -0700 (PDT) Received: from localhost ([::1]:51040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLoRu-0000wd-DU for importer@patchew.org; Thu, 02 Sep 2021 11:16:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLoL9-0000Z3-TB for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:19 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39439) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLoL7-0003Rr-Lm for qemu-devel@nongnu.org; Thu, 02 Sep 2021 11:09:19 -0400 Received: by mail-wr1-x42d.google.com with SMTP id z4so3469702wrr.6 for ; Thu, 02 Sep 2021 08:09:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c24sm2107842wrb.57.2021.09.02.08.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 08:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hTL0YVceSstDhE4eWuPfHB9Yy35Pz6ourVXwIf0vsMU=; b=jHnvrAQYtPjAbycusOsjeAnyyqrreIFryg49SAPe4voxb0izxn5ES0syNU2FNpZ2qy CT22RkgtvNV2I3tvqx9p5u5t0uH4Z8NY7zPc3o7eIES2cpXCnZr5gSFffyFgJJMXjLpH YgAAF+spvWMpdMcpuSf3AyF6XWJJU+kEkuccqwV2hS+r+ZphqcMPJ80CeHE6kYbbwzTb Bz9AngrzlMLY3peHe+ReR9UIkZ1QvTRSDMnscQ45gn4BMQAYpogu7OJdYryVW3OH5/Cy wPiaZt1r7Cehs5zSj9W/WlMMdDa8geZy2xubDosQuP35YOkW6wbBr8Ioe3w6J2GoaFv0 2gsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hTL0YVceSstDhE4eWuPfHB9Yy35Pz6ourVXwIf0vsMU=; b=N8DpcISZQTYecYjVrUnwY2+/H3Mbbfv9XKfoDhr4MY8jkHKj35sSRynKg6CcpPVsQU 7mc5KPiP9yIro4KJnJM/nT+0nhcjk4C4e3TyzIp7vois5dmYBr0EiafxuO+DW/i/TeuK io4IEKvnnfBMNFBpGdWbr/jn4eCigyPookyyezmtO7sYPaDlCH3furDUOZtVPJ+MazGg nAKAT2e9rdh2InMvau4dKZO1OoG3VeTqRyqvZ+nvOjs4/vygIs1UFxENT6Y61z9f22ol d0wveiestJMX95/YZ1RUu6esUtXLQRFi21VVN7EkH8Tc1gs5dS2kpddBsa9SOGjI5lw3 uv8Q== X-Gm-Message-State: AOAM532j2tCCO838tlXdfLijOsYgvrGxHGk3fI4RqWPNf1e9DmL4/oHP A1nE/69eeoN3vt/f1/N1HPGCCQ== X-Google-Smtp-Source: ABdhPJxgvd0Z5HvsFahw6WKE7cPvCBYp+js863wKPEnJhskiGdZFOE+NZMmnn0SQdAUkftl4rk4nXQ== X-Received: by 2002:a5d:4e51:: with SMTP id r17mr4532791wrt.308.1630595356307; Thu, 02 Sep 2021 08:09:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/4] target/arm: Optimize MVE VNEG, VABS Date: Thu, 2 Sep 2021 16:09:10 +0100 Message-Id: <20210902150910.15748-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902150910.15748-1-peter.maydell@linaro.org> References: <20210902150910.15748-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630595782203100001 Content-Type: text/plain; charset="utf-8" Optimize the MVE VNEG and VABS insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 5bc5a3a2063..32c5ff6ea06 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -500,7 +500,8 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } =20 -static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) +static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn, + GVecGen2Fn vecfn) { TCGv_ptr qd, qm; =20 @@ -514,16 +515,25 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGe= nOneOpFn fn) return true; } =20 - qd =3D mve_qreg_ptr(a->qd); - qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); + if (vecfn && s->mve_no_pred) { + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16,= 16); + } else { + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + } mve_update_eci(s); return true; } =20 -#define DO_1OP(INSN, FN) \ +static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) +{ + return do_1op_vec(s, a, fn, NULL); +} + +#define DO_1OP_VEC(INSN, FN, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ { \ static MVEGenOneOpFn * const fns[] =3D { \ @@ -532,13 +542,15 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGe= nOneOpFn fn) gen_helper_mve_##FN##w, \ NULL, \ }; \ - return do_1op(s, a, fns[a->size]); \ + return do_1op_vec(s, a, fns[a->size], VECFN); \ } =20 +#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL) + DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) -DO_1OP(VABS, vabs) -DO_1OP(VNEG, vneg) +DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs) +DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg) DO_1OP(VQABS, vqabs) DO_1OP(VQNEG, vqneg) DO_1OP(VMAXA, vmaxa) --=20 2.20.1