From nobody Thu May 2 04:38:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1630570759; cv=none; d=zohomail.com; s=zohoarc; b=EAAXx+a5z6/Er7UjmEBI7ZMDxA3OLPNq+DzLsK35v+V/p3eSgrKD8rSmZZQkBT4hF4Z42hKk7H7UGRGs3GDssVp9GTDG8JwKR16vA9ugfvaIIQijljLGSD/i8pmWwqqSA5eyseegWueW4dhTanZ+CX2IDrXns1Q9ZFKmh4m05Z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630570759; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/yNj1h9GzI+Vv9ZQFvPMnor4HRV6PcYbRxJpOhgF/1E=; b=YLn2qCykJ1hIbpR27aI5ZXF2p0nR4vdQo4Efekx+KtelBA5seSfaUOI1ZB1dedIXkQ+HzDfjHtKJZBSDPsi8t2z+ACuarAe2tDSB2RGwvf+2gtnh3RQwtGVniGsyVVNfgizfRHeqwO/njK5WXkOm/L/usI2VtHMitHm3g78oA6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630570759406224.55907725918848; Thu, 2 Sep 2021 01:19:19 -0700 (PDT) Received: from localhost ([::1]:46118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLhwM-00084T-Ax for importer@patchew.org; Thu, 02 Sep 2021 04:19:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLhsJ-0001kT-Jt; Thu, 02 Sep 2021 04:15:09 -0400 Received: from m12-16.163.com ([220.181.12.16]:52785) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLhsD-0002je-83; Thu, 02 Sep 2021 04:15:06 -0400 Received: from lcm-VirtualBox.verisilicon.com (unknown [182.148.13.201]) by smtp12 (Coremail) with SMTP id EMCowABXMRDmhzBhan7BAQ--.86S5; Thu, 02 Sep 2021 16:14:44 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=/yNj1 h9GzI+Vv9ZQFvPMnor4HRV6PcYbRxJpOhgF/1E=; b=gG9t82nkiZZBtGuQdMayS 3jwUIbgINeQLaBhRD/jaUN4AmSA7PTTJa3w5zAYAdAtb+dBPNojM+BORc1pvxfrf EvaJazmZq/Jiz2OLzjrkg/TiTLmbP81LCtsr/uwKmwZ0UhOWfP2mA1HObP0BJlX7 8qBltWS4uLPow7vmhdxHmI= From: chunming To: eric.auger@redhat.com, peter.maydell@linaro.org Subject: [PATCH v6 1/4] hw/arm/smmuv3: Support non PCI/PCIe device connect with SMMU v3 Date: Thu, 2 Sep 2021 16:14:26 +0800 Message-Id: <20210902081429.140293-2-chunming_li1234@163.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210902081429.140293-1-chunming_li1234@163.com> References: <20210902081429.140293-1-chunming_li1234@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: EMCowABXMRDmhzBhan7BAQ--.86S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxWr13ZF15XryxWFW7WF1rZwb_yoWrWF1Upa 95JF15Kr4UGF4fCwn3Xr4a9F15W3W8GF1rKr1xGr93AayUJryrXr4kK3WYqrWDGrWkZF43 uaySga15ur17Z3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07bFSdgUUUUU= X-Originating-IP: [182.148.13.201] X-CM-SenderInfo: xfkx0zplqjszjlrsjki6rwjhhfrp/1tbiMBQCdlWBy2Y2jgAAsR Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.181.12.16; envelope-from=chunming_li1234@163.com; helo=m12-16.163.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: renwei.liu@verisilicon.com, qemu-arm@nongnu.org, jianxian.wen@verisilicon.com, qemu-devel@nongnu.org, chunming Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1630570760362100001 Content-Type: text/plain; charset="utf-8" From: chunming . Add peri-sid-map property to store non PCI/PCIe devices SID . Create IOMMU memory regions for non PCI/PCIe devices based on their SID . Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices Signed-off-by: chunming --- hw/arm/smmuv3.c | 46 ++++++++++++++++++++++++++++++++++++ include/hw/arm/smmu-common.h | 9 ++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 01b60bee4..557d24ec6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ #include "hw/arm/smmuv3.h" #include "smmuv3-internal.h" #include "smmu-internal.h" +#include "hw/qdev-properties.h" =20 /** * smmuv3_trigger_irq - pulse @irq if enabled and update @@ -913,6 +914,19 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, gp= ointer user_data) return true; } =20 +static SMMUDevice *smmu_find_peri_sdev(SMMUState *s, uint16_t sid) +{ + SMMUDevice *sdev; + + QLIST_FOREACH(sdev, &s->peri_sdev_list, next) { + if (smmu_get_sid(sdev) =3D=3D sid) { + return sdev; + } + } + + return NULL; +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -1437,6 +1451,9 @@ static void smmu_realize(DeviceState *d, Error **errp) SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; + SMMUDevice *sdev; + char *name =3D NULL; + uint16_t sid =3D 0; =20 c->parent_realize(d, &local_err); if (local_err) { @@ -1454,6 +1471,28 @@ static void smmu_realize(DeviceState *d, Error **err= p) sysbus_init_mmio(dev, &sys->iomem); =20 smmu_init_irq(s, dev); + + /* Create IOMMU memory region for peripheral devices based on their SI= D */ + for (int i =3D 0; i < sys->peri_num_sid; i++) { + sid =3D sys->peri_sid_map[i]; + sdev =3D smmu_find_peri_sdev(sys, sid); + if (sdev) { + continue; + } + + sdev =3D g_new0(SMMUDevice, 1); + sdev->smmu =3D sys; + sdev->bus =3D NULL; + sdev->devfn =3D sid; + + name =3D g_strdup_printf("%s-peri-%d", sys->mrtypename, sid); + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + sys->mrtypename, + OBJECT(sys), name, 1ULL << SMMU_MAX_VA_BI= TS); + + QLIST_INSERT_HEAD(&sys->peri_sdev_list, sdev, next); + g_free(name); + } } =20 static const VMStateDescription vmstate_smmuv3_queue =3D { @@ -1506,6 +1545,12 @@ static void smmuv3_instance_init(Object *obj) /* Nothing much to do here as of now */ } =20 +static Property smmuv3_properties[] =3D { + DEFINE_PROP_ARRAY("peri-sid-map", SMMUState, peri_num_sid, peri_sid_ma= p, + qdev_prop_uint16, uint16_t), + DEFINE_PROP_END_OF_LIST(), +}; + static void smmuv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1515,6 +1560,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset); c->parent_realize =3D dc->realize; dc->realize =3D smmu_realize; + device_class_set_props(dc, smmuv3_properties); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 706be3c6d..2902eb13c 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -117,6 +117,9 @@ struct SMMUState { QLIST_HEAD(, SMMUDevice) devices_with_notifiers; uint8_t bus_num; PCIBus *primary_bus; + QLIST_HEAD(, SMMUDevice) peri_sdev_list; + uint32_t peri_num_sid; + uint16_t *peri_sid_map; }; =20 struct SMMUBaseClass { @@ -138,7 +141,11 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_= t bus_num); /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { - return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); + if (sdev->bus =3D=3D NULL) { + return sdev->devfn; + } else { + return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); + } } =20 /** --=20 2.30.2 From nobody Thu May 2 04:38:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1630570662; cv=none; d=zohomail.com; s=zohoarc; b=X16L5l4Ne2dUWZVer/buptaRORHgB+NM5IVePZnXmPqZsugezbu1Vo//5AD2gi2etAyFG/lrOaaNalqPUYyOqvzC4RJCB9vBZ3yq2NKGAiP+T/uAVjHS12+AFeGdU8eF5g34FrCNA/DvrzzotlN9uDryBx+INSakCr0fRaOIoAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630570662; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 02 Sep 2021 04:15:09 -0400 Received: from m12-16.163.com ([220.181.12.16]:52783) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLhsD-0002jL-Rs; Thu, 02 Sep 2021 04:15:05 -0400 Received: from lcm-VirtualBox.verisilicon.com (unknown [182.148.13.201]) by smtp12 (Coremail) with SMTP id EMCowABXMRDmhzBhan7BAQ--.86S6; Thu, 02 Sep 2021 16:14:44 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=sxT4f Ng/5jw852mPUItD0wtKQXXXp9s6gNNw/pABRQs=; b=hNqshChi3TlTe2w4/TBU1 552gLiqRaMQBGlLzpuWzbukh8rhlF+Flo2Yh6ttkhuxJWnnSpsIWoVYFARXgBI5q kM4CSlqEsxzcwlywZx8q0LgyvJrr6hcCgoQ3eKOojH+//wuyiFZM0o6GW9E45gjL JdXC+DYoJ54aOYvE8DYjXE= From: chunming To: eric.auger@redhat.com, peter.maydell@linaro.org Subject: [PATCH v6 2/4] hw/arm/smmuv3: Update CFGI commands to support non PCI/PCIe devices Date: Thu, 2 Sep 2021 16:14:27 +0800 Message-Id: <20210902081429.140293-3-chunming_li1234@163.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210902081429.140293-1-chunming_li1234@163.com> References: <20210902081429.140293-1-chunming_li1234@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: EMCowABXMRDmhzBhan7BAQ--.86S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7KrW3Aw1kJFyxZr4kKrWktFb_yoW8KrW3pr 42kFn0gr18Gw1SkrsIyr4I9FZxJ3ZY9F1jgr1UWa93C3WDAryrXryDKw1fJr9rWFW0vr47 uayrWF45Xr12v3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07bFEfOUUUUU= X-Originating-IP: [182.148.13.201] X-CM-SenderInfo: xfkx0zplqjszjlrsjki6rwjhhfrp/1tbivxUCdlWBveQstQAAsK Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: chunming "smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe d= evices. Look up in the platform device list: peri_sdev_list for non PCI/PCIe devi= ces. Signed-off-by: chunming --- hw/arm/smmuv3.c | 29 ++++++++++++++++++----------- include/hw/arm/smmu-common.h | 5 ++++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 557d24ec6..615a6c904 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -985,14 +985,17 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; } =20 - if (!mr) { - break; + if (mr) { + trace_smmuv3_cmdq_cfgi_ste(sid); + sdev =3D container_of(mr, SMMUDevice, iommu); + smmuv3_flush_config(sdev); } =20 - trace_smmuv3_cmdq_cfgi_ste(sid); - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); - + sdev =3D smmu_find_peri_sdev(bs, sid); + if (sdev) { + trace_smmuv3_cmdq_cfgi_ste(sid); + smmuv3_flush_config(sdev); + } break; } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ @@ -1027,13 +1030,17 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; } =20 - if (!mr) { - break; + if (mr) { + trace_smmuv3_cmdq_cfgi_cd(sid); + sdev =3D container_of(mr, SMMUDevice, iommu); + smmuv3_flush_config(sdev); } =20 - trace_smmuv3_cmdq_cfgi_cd(sid); - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); + sdev =3D smmu_find_peri_sdev(bs, sid); + if (sdev) { + trace_smmuv3_cmdq_cfgi_cd(sid); + smmuv3_flush_config(sdev); + } break; } case SMMU_CMD_TLBI_NH_ASID: diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 2902eb13c..be12b93c5 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -161,7 +161,10 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMU= AccessFlags perm, */ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); =20 -/* Return the iommu mr associated to @sid, or NULL if none */ +/** + * Return the iommu mr associated to @sid, or NULL if none + * Only for PCI device, check smmu_find_peri_sdev for peripheral device + */ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); =20 #define SMMU_IOTLB_MAX_SIZE 256 --=20 2.30.2 From nobody Thu May 2 04:38:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 02 Sep 2021 16:14:45 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=/Uyc5 PzT8EKt6zmEc25VFAwVDkD1qIMpvvkUsu5fmg4=; b=HLEzstvFiv9lZvR+tM2BU Ax6pxpx0Xqc7IRSBymPbl9g6rvvMjZtzBW5gRxgft/s7PJ/2EFpRZZF8a3CE+eH2 t0w41iKZ83e4zw4fCf2m0/Gkq1W1ZnQSkqmNBy7Tvge5Kgd8+OQ6MsJp4F6ODMQV Nxq4jQO46lqBMzMr5IYqD8= From: chunming To: eric.auger@redhat.com, peter.maydell@linaro.org Subject: [PATCH v6 3/4] hw/arm/virt: Update SMMU v3 creation to support non PCI/PCIe device connection Date: Thu, 2 Sep 2021 16:14:28 +0800 Message-Id: <20210902081429.140293-4-chunming_li1234@163.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210902081429.140293-1-chunming_li1234@163.com> References: <20210902081429.140293-1-chunming_li1234@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: EMCowABXMRDmhzBhan7BAQ--.86S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7WFyDCr1fWr4rKF4kKw1kuFg_yoW8Cw1xpF s5tFykGryY93W3Z392vF13u3WrGws2gw1UKr4xWrZ3Aw1Ut34UWr1kKa1YkFWUuF1kCF43 ZFn2gF47Wr17XrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07bsVbkUUUUU= X-Originating-IP: [182.148.13.201] X-CM-SenderInfo: xfkx0zplqjszjlrsjki6rwjhhfrp/1tbivxUCdlWBveQstQABsL Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: chunming . Add "smmuv3_sidmap" to set non PCI/PCIe devices SID value . Pass non PCI/PCIe devices SID value to SMMU v3 model creation Signed-off-by: chunming --- hw/arm/virt.c | 14 ++++++++++++++ include/hw/arm/virt.h | 1 + 2 files changed, 15 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 81eda46b0..9373d20e9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,9 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("max"), }; =20 +static const uint16_t smmuv3_peri_sidmap[] =3D { +}; + static bool cpu_type_valid(const char *cpu) { int i; @@ -1244,6 +1247,15 @@ static void create_smmu(const VirtMachineState *vms, =20 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); + + qdev_prop_set_uint32(dev, "len-peri-sid-map", + ARRAY_SIZE(smmuv3_peri_sidmap)); + + for (i =3D 0; i < ARRAY_SIZE(smmuv3_peri_sidmap); i++) { + g_autofree char *propname =3D g_strdup_printf("peri-sid-map[%d]", = i); + qdev_prop_set_uint16(dev, propname, smmuv3_peri_sidmap[i]); + } + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { @@ -2762,6 +2774,8 @@ static void virt_instance_init(Object *obj) =20 vms->irqmap =3D a15irqmap; =20 + vms->peri_sidmap =3D smmuv3_peri_sidmap; + virt_flash_create(vms); =20 vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9661c4669..fb00118b3 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -167,6 +167,7 @@ struct VirtMachineState { PCIBus *bus; char *oem_id; char *oem_table_id; + const uint16_t *peri_sidmap; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.30.2 From nobody Thu May 2 04:38:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1630570863; cv=none; d=zohomail.com; s=zohoarc; b=JSbib6DLG2bvthqW+c4wRap3CwSXD67/uly4gAcO11DkE5YOF4/FnQSv/XmJpjmhhv62sp9lr0ZoMjhZnKHDtCAiN/SabpVuBcahd7ebirYr6LFO3/IkpNqmRUMw+ro8n39MedU99y7ZsJVKClt7o3qS9wOeikETP3DBKyAjUWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630570863; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t0eqM+VjeNRK3yuIBq2YaS6dv/za6U8pHx3UcchABys=; b=hpFHIHDyqcwEO8lKxSBPSb4Vkn2RP3mBxMdTC6Tfey7Gpf/j3IeY1obYnT7aT7srcT3P5458TabfsHh6mNgLCHsVNVdmSTuaWY733lQCbuJsNDWiZ4hmvTmZvItdw8RGmRCEhPnfaM9ulneYPFtlXWKHE+c8mePSy5SDGhfCYe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630570863221159.6077722426079; Thu, 2 Sep 2021 01:21:03 -0700 (PDT) Received: from localhost ([::1]:48598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLhy2-0001HV-3c for importer@patchew.org; Thu, 02 Sep 2021 04:21:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLhsR-0001oG-9H; Thu, 02 Sep 2021 04:15:15 -0400 Received: from m12-16.163.com ([220.181.12.16]:53078) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLhsJ-0002mw-5x; Thu, 02 Sep 2021 04:15:14 -0400 Received: from lcm-VirtualBox.verisilicon.com (unknown [182.148.13.201]) by smtp12 (Coremail) with SMTP id EMCowABXMRDmhzBhan7BAQ--.86S8; Thu, 02 Sep 2021 16:14:45 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=t0eqM +VjeNRK3yuIBq2YaS6dv/za6U8pHx3UcchABys=; b=MTHbYOvoaJK27J9g3oNNF CIrv5ex26TY59uaVrbLvi7Xkgn6cNzeKHnXJxB9xyAK6WNuTa+oH8TXRB4K5+iIk xzdEEXdQfFVf0rCV9UhLe9iMMQbflBtsRkmdlIbuqFIGKKRAJQLzM1FjBQKV8kPQ VzgHt17QtPjd6THHZYoMeg= From: chunming To: eric.auger@redhat.com, peter.maydell@linaro.org Subject: [PATCH v6 4/4] hw/arm/virt: Add PL330 DMA controller and connect with SMMU v3 Date: Thu, 2 Sep 2021 16:14:29 +0800 Message-Id: <20210902081429.140293-5-chunming_li1234@163.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210902081429.140293-1-chunming_li1234@163.com> References: <20210902081429.140293-1-chunming_li1234@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: EMCowABXMRDmhzBhan7BAQ--.86S8 X-Coremail-Antispam: 1Uf129KBjvJXoWxtw4ftw4xCF45tw4UCrW7Arb_yoWxGw1kpF WrCFs8Wr4ftr1SqrZI9F1FkF1rAw1vk3WDGr4I9w4Sk3W8WryrXr48tasrKrWUW34kZ3W5 Xa1DWF9Fgw1xWr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07bYzuZUUUUU= X-Originating-IP: [182.148.13.201] X-CM-SenderInfo: xfkx0zplqjszjlrsjki6rwjhhfrp/1tbiNRUCdlrPdKxYFwAAsW Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.181.12.16; envelope-from=chunming_li1234@163.com; helo=m12-16.163.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: renwei.liu@verisilicon.com, qemu-arm@nongnu.org, jianxian.wen@verisilicon.com, qemu-devel@nongnu.org, chunming Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1630570864465100001 Content-Type: text/plain; charset="utf-8" From: chunming . Store SMMU v3 device in virtual machine then non PCI/PCIe can get its m= emory region later . Add PL330 DMA controller to test SMMU v3 connection and function . The default SID for PL330 is 1 but we test other values, it works well Signed-off-by: chunming --- hw/arm/virt.c | 96 ++++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 2 + 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9373d20e9..564b0a109 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -143,6 +143,7 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_GIC_REDIST] =3D { 0x080A0000, 0x00F60000 }, [VIRT_UART] =3D { 0x09000000, 0x00001000 }, [VIRT_RTC] =3D { 0x09010000, 0x00001000 }, + [VIRT_DMA] =3D { 0x09011000, 0x00001000 }, [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, [VIRT_GPIO] =3D { 0x09030000, 0x00001000 }, [VIRT_SECURE_UART] =3D { 0x09040000, 0x00001000 }, @@ -188,6 +189,7 @@ static const int a15irqmap[] =3D { [VIRT_GPIO] =3D 7, [VIRT_SECURE_UART] =3D 8, [VIRT_ACPI_GED] =3D 9, + [VIRT_DMA] =3D 10, [VIRT_MMIO] =3D 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] =3D 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_SMMU] =3D 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ @@ -205,6 +207,7 @@ static const char *valid_cpus[] =3D { }; =20 static const uint16_t smmuv3_peri_sidmap[] =3D { + [VIRT_DMA] =3D 1, }; =20 static bool cpu_type_valid(const char *cpu) @@ -792,6 +795,93 @@ static void create_uart(const VirtMachineState *vms, i= nt uart, g_free(nodename); } =20 +static void create_dma(const VirtMachineState *vms) +{ + int i; + char *nodename; + hwaddr base =3D vms->memmap[VIRT_DMA].base; + hwaddr size =3D vms->memmap[VIRT_DMA].size; + int irq =3D vms->irqmap[VIRT_DMA]; + int sid =3D vms->peri_sidmap[VIRT_DMA]; + const char compat[] =3D "arm,pl330\0arm,primecell"; + const char irq_names[] =3D "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\= 0dma6\0dma7"; + DeviceState *dev; + MachineState *ms =3D MACHINE(vms); + SysBusDevice *busdev; + DeviceState *smmuv3_dev; + SMMUState *smmuv3_sys; + Object *smmuv3_memory; + + dev =3D qdev_new("pl330"); + + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3 && vms->iommu_phandle) { + smmuv3_dev =3D vms->smmuv3; + smmuv3_sys =3D ARM_SMMU(smmuv3_dev); + g_autofree char *memname =3D g_strdup_printf("%s-peri-%d[0]", + smmuv3_sys->mrtypename, + sid); + + smmuv3_memory =3D object_property_get_link(OBJECT(smmuv3_dev), + memname, &error_abort); + + object_property_set_link(OBJECT(dev), "memory", + OBJECT(smmuv3_memory), + &error_fatal); + } else { + object_property_set_link(OBJECT(dev), "memory", + OBJECT(get_system_memory()), + &error_fatal); + } + + qdev_prop_set_uint8(dev, "num_chnls", 8); + qdev_prop_set_uint8(dev, "num_periph_req", 4); + qdev_prop_set_uint8(dev, "num_events", 16); + qdev_prop_set_uint8(dev, "data_width", 64); + qdev_prop_set_uint8(dev, "wr_cap", 8); + qdev_prop_set_uint8(dev, "wr_q_dep", 16); + qdev_prop_set_uint8(dev, "rd_cap", 8); + qdev_prop_set_uint8(dev, "rd_q_dep", 16); + qdev_prop_set_uint16(dev, "data_buffer_dep", 256); + + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); + + for (i =3D 0; i < 9; ++i) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(vms->gic, irq + i)); + } + + nodename =3D g_strdup_printf("/pl330@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 4, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 5, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 6, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 7, GIC_FDT_IRQ_FLAGS_LEVEL= _HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 8, GIC_FDT_IRQ_FLAGS_LEVEL= _HI); + + qemu_fdt_setprop(ms->fdt, nodename, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); + + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3 && vms->iommu_phandle) { + qemu_fdt_setprop_cells(ms->fdt, nodename, "iommus", + vms->iommu_phandle, sid); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + } + + g_free(nodename); +} + static void create_rtc(const VirtMachineState *vms) { char *nodename; @@ -1226,7 +1316,7 @@ static void create_pcie_irq_map(const MachineState *m= s, 0x7 /* PCI irq */); } =20 -static void create_smmu(const VirtMachineState *vms, +static void create_smmu(VirtMachineState *vms, PCIBus *bus) { char *node; @@ -1248,6 +1338,8 @@ static void create_smmu(const VirtMachineState *vms, object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); =20 + vms->smmuv3 =3D dev; + qdev_prop_set_uint32(dev, "len-peri-sid-map", ARRAY_SIZE(smmuv3_peri_sidmap)); =20 @@ -2079,6 +2171,8 @@ static void machvirt_init(MachineState *machine) =20 create_pcie(vms); =20 + create_dma(vms); + if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); } else { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index fb00118b3..09a56d95b 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -72,6 +72,7 @@ enum { VIRT_UART, VIRT_MMIO, VIRT_RTC, + VIRT_DMA, VIRT_FW_CFG, VIRT_PCIE, VIRT_PCIE_MMIO, @@ -168,6 +169,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; const uint16_t *peri_sidmap; + DeviceState *smmuv3; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.30.2