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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v5pPz7UFQ9KY/Khb5OGJwbmVXcY4XGfYcfxtdVJ4joA=; b=G2FfmPAp38pdx4wiK2aMWBzx3AuW+CJjPAU76FgsJthEXjiQARyurch7HC0u0aUmzU +9cFWTlTMIdCmSS6+zWQm/j1hEPSt1WFW9C5KtcOKddGLLYJv7IruhdpS16OEn2sJcDC qfKjg2in9FPnmsnikaxuJ4BYrQaEuABplGXIAtVXE7eF3saq+qe7qW9YFKrzVsutixOF 1kBFn/FHYbO3u41+bz+I36CDSBQkY+60bloWn8sDDCbkcWiN4ojFjb88GR3xGzLrKvzl eWjdbJV0eD4z2g+CXgbKOX/qBHNNsPGiiUUXwx5qupd5Cgf0BDrgZ/J6Y5vT7VFRxXqt g03g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v5pPz7UFQ9KY/Khb5OGJwbmVXcY4XGfYcfxtdVJ4joA=; b=KtaeAauAz63c1O8RHQyyGuKAN6W/2tKgIIQY9XQ0r/AiRmwbMF/LHkcSuZfrGG/I5A 4pPgnr2Euyv7kpnqcfJeZwhbjHPavdkuu7Dyv1hC9FvhbGnVL57fiXXWaOxBV72heiLF OudbK17A5SWz1UEYVK1XxkXTJmzvJltf6BHRcUxGhISBUY97E+zuy3Y3U46Nl2HuCuAI 0Gdex3jfCD5WdVx+DTudLRSf3Y0HROMmt+YSt7HElLa1hIqp7cQIW2DtPM1WULsoYE5c cMXBveIdgbi7/dBA9aQNYy0UJkHl+Sm7X1qtDZ62lMfAYXVhNo2VG6xhzHczGCUpI7ax VD0Q== X-Gm-Message-State: AOAM5311GWGKv7o4Cjs3bdN0QSXjC3uyBnTugdLCYsauTvx3L5ASjEDW bG4+GDvBpEfMzUtHLIab1uW+rH8CLmyo9w== X-Google-Smtp-Source: ABdhPJyiqBrqeVa7C6cDgK18FaGMJuw7h5pHIjqTfQrNhGBUSoRJhu4F1kdHXhmKv+TM3FbXk6g4dg== X-Received: by 2002:adf:e809:: with SMTP id o9mr36900062wrm.425.1630492627748; Wed, 01 Sep 2021 03:37:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/51] target/arm: Implement MVE fp scalar comparisons Date: Wed, 1 Sep 2021 11:36:19 +0100 Message-Id: <20210901103653.13435-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492912246100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp scalar comparisons VCMP and VPT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 18 +++++++++++ target/arm/mve.decode | 61 +++++++++++++++++++++++++++++-------- target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++-------- target/arm/translate-mve.c | 14 +++++++++ 4 files changed, 131 insertions(+), 24 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 0c15c531641..9ee841cdf01 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -831,6 +831,24 @@ DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void,= env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmple_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 49b7ef35937..f1b8afb4778 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -127,6 +127,11 @@ @vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ qm=3D%qm size=3D%2op_fp_scalar_size mask=3D%mask_22_13 =20 +# Bit 28 is a 2op_fp_scalar_size bit, but we do not decode it in this +# format to avoid complicated overlapping-instruction-groups +@vcmp_fp_scalar .... .... .... qn:3 . .... .... .... rm:4 &vcmp_scalar \ + mask=3D%mask_22_13 + @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 @2op_fp .... .... .... .... .... .... .... .... &2op \ @@ -400,8 +405,10 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 = 0 1 0000 @vdup size=3D2 VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup } { - VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup - VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup + VCMPGT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_s= calar size=3D2 + VCMPLE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_s= calar size=3D2 + VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup + VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup } =20 # multiply-add long dual accumulate @@ -480,8 +487,17 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 = . 0 ... 1 @vmladav_nosz =20 # Scalar operations =20 -VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar -VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +{ + VCMPEQ_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VCMPNE_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar +} + +{ + VCMPLT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VCMPGE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +} =20 { VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar @@ -711,17 +727,38 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1= 100 rdm:4 qd=3D%qd } =20 { - VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 - VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask= _22_13 - VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_sca= lar + VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 + VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mas= k_22_13 + VCMPEQ_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0100 .... @vcmp_scalar } -VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_sca= lar + +{ + VCMPNE_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1100 .... @vcmp_scalar +} + +{ + VCMPGT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_sc= alar size=3D1 + VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0110 .... @vcmp_scalar +} + +{ + VCMPLE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_sc= alar size=3D1 + VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1110 .... @vcmp_scalar +} + +{ + VCMPGE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0100 .... @vcmp_scalar +} +{ + VCMPLT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1100 .... @vcmp_scalar +} + VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_sca= lar VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_sca= lar -VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_sca= lar -VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar -VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar -VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar =20 # 2-operand FP VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 07a1ab88814..891926c124d 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3191,6 +3191,44 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_= minnum) mve_advance_vpt(env); \ } =20 +#define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + uint32_t rm) \ + { \ + TYPE *n =3D vn; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + bool r; \ + for (e =3D 0; e < 16 / ESIZE; e++, emask <<=3D ESIZE) { = \ + if ((mask & emask) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & (1 << (e * ESIZE)))) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +#define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) + /* * Some care is needed here to get the correct result for the unordered ca= se. * Architecturally EQ, GE and GT are defined to be false for unordered, but @@ -3203,20 +3241,20 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32= _minnum) #define DO_GT16(X, Y, S) float16_lt(Y, X, S) #define DO_GT32(X, Y, S) float32_lt(Y, X, S) =20 -DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq) -DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq) +DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) +DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) =20 -DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq) -DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq) +DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) +DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) =20 -DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16) -DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32) +DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) +DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) =20 -DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16) -DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32) +DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) +DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) =20 -DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16) -DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32) +DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) +DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) =20 -DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16) -DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32) +DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) +DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index da14a6f790e..e8a3dec6683 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1771,6 +1771,20 @@ DO_VCMP(VCMPLE, vcmple) return false; \ } \ return do_vcmp(s, a, fns[a->size]); \ + } \ + static bool trans_##INSN##_scalar(DisasContext *s, \ + arg_vcmp_scalar *a) \ + { \ + static MVEGenScalarCmpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##_scalarh, \ + gen_helper_mve_##FN##_scalars, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vcmp_scalar(s, a, fns[a->size]); \ } =20 DO_VCMP_FP(VCMPEQ_fp, vfcmpeq) --=20 2.20.1