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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=q4iGGhRYQhOQk9djF/szEwzePdZg1DYDBM0aOmT7RLM=; b=hbaEar2X1EMt1eHchMo4QTCCgXgsv+QSeVkqr643AjXmezXzExIwonqmNkkwUrqcoA SkKzLhlrhVTpFwsxkK0FTlEI9Ji0iytvQ9ZT0XFBjeuQyYTmVmuG6lPzVXtFdrXaCTLp rjCPk/asCAdswVi4Iui6z1Ohr35HmSXNJspo9j/+DFvIlA8W5RP4LD5vFKMRcWWgE9hU tMPGcLEuzbbNbtdmRR4WwRCvVL5jW/JtX19ISLf0L3rXMgBrz7fAOe8YlocFokt55Naw mfCkWoLhqSt7q3sC5JiWg3Pj/H9Wn6kHRF90h8RoIP0LBJgyfje+A7h5Uxd9V9Vc78fp aWOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q4iGGhRYQhOQk9djF/szEwzePdZg1DYDBM0aOmT7RLM=; b=Lw6dtA5lE+Qp8HxRrrta2LsbCV5+J1d5lXtBEI6OqMFrGA7SBy/zJh9R7AmUpmM+sj vxgI/Xu+tMspXt8e/guZH1tuSVVKotPPwgHBxSzSX+b8ra1xOUH1Fr2KTp2NlZ6kG/JY 43zCejlOrlF+b3Di+s/G4KgUud7ojsdAieKxkqv0245dbcxpxbEelg9AOO7ZpjKAjEU+ 2LkEGQabCaIFfw4v6iqcThN0e6IPvSX0XF+yP79Vg2W6zAmDX1TP3ghyRRpo0OQK2dDp UpZqXuV6r6c6szDgeaQq5O5JPtIgmVnv25freeA+GljIwIqq7WtqcpGMczj9YiVxwnpP N+PA== X-Gm-Message-State: AOAM533RGYbv8stNOtLeUJ4EcnYNRAmd1rSHIxwwk4YUihL3A//lq2SY XCLs32F5+nqVuWzW2aK1gG0gJ5AgEDKqQg== X-Google-Smtp-Source: ABdhPJz/rR99E+wwygfSY2WY2ZQV9TZZlUGEPFD0211TVnWR0mgIoy15kO/RdANkxdYEgjSsMkZZjQ== X-Received: by 2002:a1c:6a14:: with SMTP id f20mr9016137wmc.142.1630492616843; Wed, 01 Sep 2021 03:36:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/51] tests: Remove uses of deprecated raspi2/raspi3 machine names Date: Wed, 1 Sep 2021 11:36:03 +0100 Message-Id: <20210901103653.13435-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492921109100001 From: Philippe Mathieu-Daud=C3=A9 Commit 155e1c82ed0 deprecated the raspi2/raspi3 machine names. Use the recommended new names: raspi2b and raspi3b. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Reviewed-by: Willian Rampazzo Message-id: 20210827060815.2384760-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- docs/devel/qgraph.rst | 38 ++++++++++++------------- tests/qtest/libqos/qgraph.h | 6 ++-- tests/qtest/libqos/qgraph_internal.h | 2 +- tests/qtest/boot-serial-test.c | 2 +- tests/qtest/libqos/arm-raspi2-machine.c | 8 +++--- tests/unit/test-qgraph.c | 2 +- tests/acceptance/boot_linux_console.py | 6 ++-- 7 files changed, 32 insertions(+), 32 deletions(-) diff --git a/docs/devel/qgraph.rst b/docs/devel/qgraph.rst index 39e293687e6..c2882c3a334 100644 --- a/docs/devel/qgraph.rst +++ b/docs/devel/qgraph.rst @@ -41,7 +41,7 @@ Nodes =20 A node can be of four types: =20 -- **QNODE_MACHINE**: for example ``arm/raspi2`` +- **QNODE_MACHINE**: for example ``arm/raspi2b`` - **QNODE_DRIVER**: for example ``generic-sdhci`` - **QNODE_INTERFACE**: for example ``sdhci`` (interface for all ``-sdhci`` drivers). @@ -119,12 +119,12 @@ It is possible to troubleshoot unavailable tests by r= unning:: # |-> dest=3D'i440FX-pcihost' type=3D0 (node=3D0x5591421117f0) # src=3D'' # |-> dest=3D'x86_64/pc' type=3D0 (node=3D0x559142111600) - # |-> dest=3D'arm/raspi2' type=3D0 (node=3D0x559142110740) + # |-> dest=3D'arm/raspi2b' type=3D0 (node=3D0x559142110740) ... # } # ALL QGRAPH NODES: { # name=3D'virtio-net-tests/announce-self' type=3D3 cmd_line=3D'(null)'= [available] - # name=3D'arm/raspi2' type=3D0 cmd_line=3D'-M raspi2 ' [UNAVAILABLE] + # name=3D'arm/raspi2b' type=3D0 cmd_line=3D'-M raspi2b ' [UNAVAILABLE] ... # } =20 @@ -135,8 +135,8 @@ qgraph path in the "ALL QGRAPH EDGES" output as follows= : '' -> 'x86_64/pc' -> 'virtio-net'. The root of the qgraph is '' and the depth first search begi= ns there. =20 -The ``arm/raspi`` machine node is listed as "UNAVAILABLE". Although it is -reachable from the root via '' -> 'arm/raspi2' the node is unavailable bec= ause +The ``arm/raspi2b`` machine node is listed as "UNAVAILABLE". Although it is +reachable from the root via '' -> 'arm/raspi2b' the node is unavailable be= cause the QEMU binary did not list it when queried by the framework. This is exp= ected because we used the ``qemu-system-x86_64`` binary which does not support A= RM machine types. @@ -158,7 +158,7 @@ Here we continue the ``sdhci`` use case, with the follo= wing scenario: - ``sdhci-test`` aims to test the ``read[q,w], writeq`` functions offered by the ``sdhci`` drivers. - The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``AR= M`` - (in this example we focus on the ``arm-raspi2``) machines. + (in this example we focus on the ``arm-raspi2b``) machines. - QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``ARM`` and ``QSDHCI_PCI`` for ``x86_64/pc``. Both implement the ``read[q,w], writeq`` functions. @@ -180,11 +180,11 @@ In order to implement such scenario in qgraph, the te= st developer needs to: all the pci drivers available) =20 ``sdhci-pci --consumes--> pci-bus`` -- Create an ``arm/raspi2`` machine node. This machine ``contains`` +- Create an ``arm/raspi2b`` machine node. This machine ``contains`` a ``generic-sdhci`` memory mapped ``sdhci`` driver node, representing ``QSDHCI_MemoryMapped``. =20 - ``arm/raspi2 --contains--> generic-sdhci`` + ``arm/raspi2b --contains--> generic-sdhci`` - Create the ``sdhci`` interface node. This interface offers the functions that are shared by all ``sdhci`` devices. The interface is produced by ``sdhci-pci`` and ``generic-sdhci``, @@ -199,7 +199,7 @@ In order to implement such scenario in qgraph, the test= developer needs to: =20 ``sdhci-test --consumes--> sdhci`` =20 -``arm-raspi2`` machine, simplified from +``arm-raspi2b`` machine, simplified from ``tests/qtest/libqos/arm-raspi2-machine.c``:: =20 #include "qgraph.h" @@ -217,7 +217,7 @@ In order to implement such scenario in qgraph, the test= developer needs to: return &machine->alloc; } =20 - fprintf(stderr, "%s not present in arm/raspi2\n", interface); + fprintf(stderr, "%s not present in arm/raspi2b\n", interface); g_assert_not_reached(); } =20 @@ -229,7 +229,7 @@ In order to implement such scenario in qgraph, the test= developer needs to: return &machine->sdhci.obj; } =20 - fprintf(stderr, "%s not present in arm/raspi2\n", device); + fprintf(stderr, "%s not present in arm/raspi2b\n", device); g_assert_not_reached(); } =20 @@ -253,10 +253,10 @@ In order to implement such scenario in qgraph, the te= st developer needs to: =20 static void raspi2_register_nodes(void) { - /* arm/raspi2 --contains--> generic-sdhci */ - qos_node_create_machine("arm/raspi2", + /* arm/raspi2b --contains--> generic-sdhci */ + qos_node_create_machine("arm/raspi2b", qos_create_machine_arm_raspi2); - qos_node_contains("arm/raspi2", "generic-sdhci", NULL); + qos_node_contains("arm/raspi2b", "generic-sdhci", NULL); } =20 libqos_init(raspi2_register_nodes); @@ -470,7 +470,7 @@ In the above example, all possible types of relations a= re created:: | +--produces-- + | - arm/raspi2 --contains--> generic-sdhci + arm/raspi2b --contains--> generic-sdhci =20 or inverting the consumes edge in consumed_by:: =20 @@ -486,7 +486,7 @@ or inverting the consumes edge in consumed_by:: | +--produces-- + | - arm/raspi2 --contains--> generic-sdhci + arm/raspi2b --contains--> generic-sdhci =20 Adding a new test """"""""""""""""" @@ -536,7 +536,7 @@ Final graph will be like this:: | +--produces-- + | - arm/raspi2 --contains--> generic-sdhci + arm/raspi2b --contains--> generic-sdhci =20 or inverting the consumes edge in consumed_by:: =20 @@ -552,7 +552,7 @@ or inverting the consumes edge in consumed_by:: | +--produces-- + | - arm/raspi2 --contains--> generic-sdhci + arm/raspi2b --contains--> generic-sdhci =20 Assuming there the binary is ``QTEST_QEMU_BINARY=3D./qemu-system-x86_64`` @@ -561,7 +561,7 @@ a valid test path will be: =20 and for the binary ``QTEST_QEMU_BINARY=3D./qemu-system-arm``: =20 -``/arm/raspi2/generic-sdhci/sdhci/sdhci-test`` +``/arm/raspi2b/generic-sdhci/sdhci/sdhci-test`` =20 Additional examples are also in ``test-qgraph.c`` =20 diff --git a/tests/qtest/libqos/qgraph.h b/tests/qtest/libqos/qgraph.h index 54672350c8f..871740c0dc8 100644 --- a/tests/qtest/libqos/qgraph.h +++ b/tests/qtest/libqos/qgraph.h @@ -252,17 +252,17 @@ void qos_node_create_driver_named(const char *name, c= onst char *qemu_name, * This function can be useful when there are multiple devices * with the same node name contained in a machine/other node * - * For example, if ``arm/raspi2`` contains 2 ``generic-sdhci`` + * For example, if ``arm/raspi2b`` contains 2 ``generic-sdhci`` * devices, the right commands will be: * * .. code:: * - * qos_node_create_machine("arm/raspi2"); + * qos_node_create_machine("arm/raspi2b"); * qos_node_create_driver("generic-sdhci", constructor); * // assume rest of the fields are set NULL * QOSGraphEdgeOptions op1 =3D { .edge_name =3D "emmc" }; * QOSGraphEdgeOptions op2 =3D { .edge_name =3D "sdcard" }; - * qos_node_contains("arm/raspi2", "generic-sdhci", &op1, &op2, NULL); + * qos_node_contains("arm/raspi2b", "generic-sdhci", &op1, &op2, NULL); * * Of course this also requires that the @container's get_device function * should implement a case for "emmc" and "sdcard". diff --git a/tests/qtest/libqos/qgraph_internal.h b/tests/qtest/libqos/qgra= ph_internal.h index c0025f5ab9b..7d62fd17af7 100644 --- a/tests/qtest/libqos/qgraph_internal.h +++ b/tests/qtest/libqos/qgraph_internal.h @@ -230,7 +230,7 @@ void qos_graph_foreach_test_path(QOSTestCallback fn); /** * qos_get_machine_type(): return QEMU machine type for a machine node. * This function requires every machine @name to be in the form - * /, like "arm/raspi2" or "x86_64/pc". + * /, like "arm/raspi2b" or "x86_64/pc". * * The function will validate the format and return a pointer to * @machine to . For example, when passed "x86_64/pc" diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index 96849cec915..83828ba2707 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -173,7 +173,7 @@ static testdef_t tests[] =3D { sizeof(kernel_pls3adsp1800), kernel_pls3adsp1800 }, { "microblazeel", "petalogix-ml605", "", "TT", sizeof(kernel_plml605), kernel_plml605 }, - { "arm", "raspi2", "", "TT", sizeof(bios_raspi2), 0, bios_raspi2 }, + { "arm", "raspi2b", "", "TT", sizeof(bios_raspi2), 0, bios_raspi2 }, /* For hppa, force bios to output to serial by disabling graphics. */ { "hppa", "hppa", "-vga none", "SeaBIOS wants SYSTEM HALT" }, { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64), diff --git a/tests/qtest/libqos/arm-raspi2-machine.c b/tests/qtest/libqos/a= rm-raspi2-machine.c index 35bb4709a45..09ca863c103 100644 --- a/tests/qtest/libqos/arm-raspi2-machine.c +++ b/tests/qtest/libqos/arm-raspi2-machine.c @@ -42,7 +42,7 @@ static void *raspi2_get_driver(void *object, const char *= interface) return &machine->alloc; } =20 - fprintf(stderr, "%s not present in arm/raspi2\n", interface); + fprintf(stderr, "%s not present in arm/raspi2b\n", interface); g_assert_not_reached(); } =20 @@ -53,7 +53,7 @@ static QOSGraphObject *raspi2_get_device(void *obj, const= char *device) return &machine->sdhci.obj; } =20 - fprintf(stderr, "%s not present in arm/raspi2\n", device); + fprintf(stderr, "%s not present in arm/raspi2b\n", device); g_assert_not_reached(); } =20 @@ -85,8 +85,8 @@ static void *qos_create_machine_arm_raspi2(QTestState *qt= s) =20 static void raspi2_register_nodes(void) { - qos_node_create_machine("arm/raspi2", qos_create_machine_arm_raspi2); - qos_node_contains("arm/raspi2", "generic-sdhci", NULL); + qos_node_create_machine("arm/raspi2b", qos_create_machine_arm_raspi2); + qos_node_contains("arm/raspi2b", "generic-sdhci", NULL); } =20 libqos_init(raspi2_register_nodes); diff --git a/tests/unit/test-qgraph.c b/tests/unit/test-qgraph.c index f819430e2cc..334c76c8e71 100644 --- a/tests/unit/test-qgraph.c +++ b/tests/unit/test-qgraph.c @@ -21,7 +21,7 @@ #include "../qtest/libqos/qgraph_internal.h" =20 #define MACHINE_PC "x86_64/pc" -#define MACHINE_RASPI2 "arm/raspi2" +#define MACHINE_RASPI2 "arm/raspi2b" #define I440FX "i440FX-pcihost" #define PCIBUS_PC "pcibus-pc" #define SDHCI "sdhci" diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py index 5248c8097df..0a49c0e2760 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -475,7 +475,7 @@ def do_test_arm_raspi2(self, uart_id): def test_arm_raspi2_uart0(self): """ :avocado: tags=3Darch:arm - :avocado: tags=3Dmachine:raspi2 + :avocado: tags=3Dmachine:raspi2b :avocado: tags=3Ddevice:pl011 :avocado: tags=3Daccel:tcg """ @@ -484,7 +484,7 @@ def test_arm_raspi2_uart0(self): def test_arm_raspi2_initrd(self): """ :avocado: tags=3Darch:arm - :avocado: tags=3Dmachine:raspi2 + :avocado: tags=3Dmachine:raspi2b """ deb_url =3D ('http://archive.raspberrypi.org/debian/' 'pool/main/r/raspberrypi-firmware/' @@ -971,7 +971,7 @@ def test_arm_orangepi_uboot_netbsd9(self): def test_aarch64_raspi3_atf(self): """ :avocado: tags=3Darch:aarch64 - :avocado: tags=3Dmachine:raspi3 + :avocado: tags=3Dmachine:raspi3b :avocado: tags=3Dcpu:cortex-a53 :avocado: tags=3Ddevice:pl011 :avocado: tags=3Datf --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9C9/PrAdyP+yrPG+bQavBhq69GwpxQyLDrPvOrD8adM=; b=tL1GFsQ9lXUycCLaSArCcnno1GgJxKj8SOX2PBtII81krLHdexsTjeVuFTOm51QuF1 0X/rCvQm9b/HHrophdJsYZfkaaNOzv59legk1ExiqDefvEuFVpUkNnfUOqiPqEVXDyvF AuPySas8taoKTQzafME6I/FvAdSjAbQxBiXHvvjq7MDy55rW+bZSSIvPePiJ4sCot8wR N8ZERhbmEw2UGTvQGFYUciojkiCtyI2Mt+iyjXGO4m3qnoVitl+9qGPC/dIyS3m0o5pY GMUXk4j1NbBngsh9oIjE6Fhr6tlXSw8TgxtcT/LnupfjuUXg/7ag1pvpfjrypvLtw8yD JSQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9C9/PrAdyP+yrPG+bQavBhq69GwpxQyLDrPvOrD8adM=; b=KQL3sx0byhZX+BtFtQK7GmI7o6f3fPHfbJxXu5Xd+AvVJPQuTscvFeqGF4l3VcwByI 2zuilr03EIxqdKtEFAtC0mMB7k5mPyjHPWiHbqKxGOhh9jty6TLOEmM34flQ9Fw4OrNa 62hSxjEG/R6+0FGOOkSYkmfRUucSkkp3se+rLx6JI3KJZB8/DnEqaGG14xLkIyoqjmVS wdd338afg6vcsnOXyKu6h+SniAHY6mFSgycHOS6qVnal3i/SNI/3r0O6aN0FQ3peMlkP RVVpNQr5Rs6kM/GEFfxbkamqp7UsMbQy+1S3FDtLDdakLtmgycv08RanKM4Y7rTGI9cU F8PA== X-Gm-Message-State: AOAM532SWaDeGQ+OETcWHvYuDxCuKr7XXCb2NaZ2Z8dyeFZcYGVzg07K 5MTwqvVBcRyoqpsFuZcVkE0Oy5h+D1x6tw== X-Google-Smtp-Source: ABdhPJxbacU6pb8aqrWSiYP79+2g32dOdcCfhMyMhaqyAEI17IbEQmXfzyACLz2HLnKp2xsGDYtLVw== X-Received: by 2002:a1c:e904:: with SMTP id q4mr9121875wmc.26.1630492617426; Wed, 01 Sep 2021 03:36:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/51] hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases Date: Wed, 1 Sep 2021 11:36:04 +0100 Message-Id: <20210901103653.13435-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492764216100001 From: Philippe Mathieu-Daud=C3=A9 Remove the raspi2/raspi3 machine aliases, deprecated since commit 155e1c82ed0. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210827060815.2384760-3-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/about/deprecated.rst | 7 ------- docs/about/removed-features.rst | 7 +++++++ hw/arm/raspi.c | 2 -- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 8d4fd384a59..1e1a5e96ad4 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -207,13 +207,6 @@ this CPU is also deprecated. System emulator machines ------------------------ =20 -Raspberry Pi ``raspi2`` and ``raspi3`` machines (since 5.2) -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -The Raspberry Pi machines come in various models (A, A+, B, B+). To be able -to distinguish which model QEMU is implementing, the ``raspi2`` and ``rasp= i3`` -machines have been renamed ``raspi2b`` and ``raspi3b``. - Aspeed ``swift-bmc`` machine (since 6.1) '''''''''''''''''''''''''''''''''''''''' =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 08f9e625ce6..9d0d90c90d9 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -574,6 +574,13 @@ This machine has been renamed ``fuloong2e``. These machine types were very old and likely could not be used for live migration from old QEMU versions anymore. Use a newer machine type instead. =20 +Raspberry Pi ``raspi2`` and ``raspi3`` machines (removed in 6.2) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The Raspberry Pi machines come in various models (A, A+, B, B+). To be able +to distinguish which model QEMU is implementing, the ``raspi2`` and ``rasp= i3`` +machines have been renamed ``raspi2b`` and ``raspi3b``. + =20 linux-user mode CPUs -------------------- diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 0ada91c05e9..146d35382bf 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -340,7 +340,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc,= void *data) MachineClass *mc =3D MACHINE_CLASS(oc); RaspiMachineClass *rmc =3D RASPI_MACHINE_CLASS(oc); =20 - mc->alias =3D "raspi2"; rmc->board_rev =3D 0xa21041; raspi_machine_class_common_init(mc, rmc->board_rev); }; @@ -360,7 +359,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc,= void *data) MachineClass *mc =3D MACHINE_CLASS(oc); RaspiMachineClass *rmc =3D RASPI_MACHINE_CLASS(oc); =20 - mc->alias =3D "raspi3"; rmc->board_rev =3D 0xa02082; raspi_machine_class_common_init(mc, rmc->board_rev); }; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630492918; cv=none; d=zohomail.com; s=zohoarc; b=iH2nr2lBsXPzrYfW/bV+YObes26yfLseXqVed7fAv4qnUIyndtLn56QZw1mjf7nWm2AEk+hV/CYKrGPMATW+/pkbbvZKNiCPfdIj51J/CeWF36207TBmq61pcjtlBtxcBO01PEpFQbrXCtGedhApxj5XzOe4qdLpSy7J1fvw//Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630492918; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h50eayBgkaoAxyuO40I1PnRhLt568bidBUOZ4ZiBi7A=; b=oJEvoed7nGBSDFesD/WT0FeYJc7en+FqXVnpr3AtNut7oo9x9ejoDiX13TnqDQTOwtwnXLT1objiww/nUlYpv7ACTSBHwnQZjMhTSJei/qdu9PSy4YcjKkXc7hCMB/yMziPEqRFr4APiRWbO2Q5rShMi42awqXUhf/uys33KyJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630492918027749.9227202438482; Wed, 1 Sep 2021 03:41:58 -0700 (PDT) Received: from localhost ([::1]:56840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNgq-0007Ap-Vu for importer@patchew.org; Wed, 01 Sep 2021 06:41:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNc8-0006kO-Ku for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:04 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:42871) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc3-0005bo-9b for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:04 -0400 Received: by mail-wr1-x42f.google.com with SMTP id q11so3714414wrr.9 for ; Wed, 01 Sep 2021 03:36:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h50eayBgkaoAxyuO40I1PnRhLt568bidBUOZ4ZiBi7A=; b=YhaoXsBZIU/65LnVFS5j1UYR2qIqV6sbbJ/48cZPK2r2Wx4NqhZhAQexVS8mfT7YKa 7Nk36ofIUA2KwNUvhhVBeNGCc5Hw9/7+YElPZuGeSpj83mcHuwB7dTuw6TVw7hWdQAt/ AjR/geadvFiS/fxDfofxf4E9yzXhGy+Qyxr1XleCl3Fcy45F5TKr6VSL6fXkmslLgG1n gWDpvOdp/1+KBDcv7UqVAihRzQp+uNaQVFwrVQMFQRe+5q6qZLXZ7+CAPJcYXRfFghcP iPstm/VZ8zO4A+xmik8X62VEz1HsBMdHb9mfMK9cyS/n5kMFmBDe6CblE+2MiVCoYFDS RKRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h50eayBgkaoAxyuO40I1PnRhLt568bidBUOZ4ZiBi7A=; b=FNKQSo8315D0TWYvNRsyD6rX7grJBqNCgznpz6/B8GyBoLIshk0nMEbbG42+sSSunf lSEuu83lswR0erdXmExFLH2ZRzRDH2VRHBPIMDiLn2n9hgWBeAXa0XKp8k9h4MCEmri1 n6ylaxhNlTaz7i0BOflI07jirIf/SHE5BW44XGLYqKJR9jz+paI2vVIr6kfAwJmPpJwd J9emLU3xHoiVccPw1cNCQCUzartf0QfncoaRHOS2u2H7BPaHramGFnatv8VOWyTSZL5Q sPup0sUp41AxCWCqdgdjqKUIZX5AavRA/DKO7CCtiYuldLuKdbHlv5X5Ko4/H3mXtDAA gGPA== X-Gm-Message-State: AOAM531XrpVrPhruMPk4xwfMHHGDsE03yEo7aAhWR5BzSHe54tN+FmmO oMQP8HOy90qSMOrY+C13u7pgcUfb4YuRlw== X-Google-Smtp-Source: ABdhPJyw+R5mL5M3jU3cU91lluVqkFwxy8Nw2UtKrKyuF0fnCxk5DJJNKPVH1Bl8ZRV/1Q0ZZTFnAg== X-Received: by 2002:adf:e809:: with SMTP id o9mr36899276wrm.425.1630492618034; Wed, 01 Sep 2021 03:36:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix Date: Wed, 1 Sep 2021 11:36:05 +0100 Message-Id: <20210901103653.13435-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492918700100003 From: Philippe Mathieu-Daud=C3=A9 QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q' suffix for 64-bit accesses. Rename the current 'll' suffix to have the GIC dist accessors better match the rest of the codebase. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210826180704.2131949-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_dist.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index b65f56f9035..7e9b393d9ab 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -763,8 +763,8 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, } } =20 -static MemTxResult gicd_writell(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -779,8 +779,8 @@ static MemTxResult gicd_writell(GICv3State *s, hwaddr o= ffset, } } =20 -static MemTxResult gicd_readll(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static MemTxResult gicd_readq(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -812,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset= , uint64_t *data, r =3D gicd_readl(s, offset, data, attrs); break; case 8: - r =3D gicd_readll(s, offset, data, attrs); + r =3D gicd_readq(s, offset, data, attrs); break; default: r =3D MEMTX_ERROR; @@ -854,7 +854,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offse= t, uint64_t data, r =3D gicd_writel(s, offset, data, attrs); break; case 8: - r =3D gicd_writell(s, offset, data, attrs); + r =3D gicd_writeq(s, offset, data, attrs); break; default: r =3D MEMTX_ERROR; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493106; cv=none; d=zohomail.com; s=zohoarc; b=XkeNflTwBgckfiZgMLSr7+FER9K3K7t7EbpsX0doM+4DukwMdbVYEsBFqUXNb881Zrc8+cFCIO/qVr5bCCngmAGj4K/zSP5ETXvvGQUIgMQOBIA8+57zcumVpVtCPUNHtTRz7i1BWhkNln6SENFh6vp8w6B7g7CtoO7Un5w0rho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493106; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hrL7wY7FeSozFPbmJ1hgaWugx0ZzntiXknL52DAZLEI=; b=i30OrW68KET7DKKAzODIqT+Fad8wSGAN4WXZwMBrg+y6Q5udXwl0M1GCLMeaHTx5/+1DBZ/ZEvxSlRkoTJYmaMIZ4XhqWFbcEl7V5osvl499oJUe/PwL0rGTVs+gOmvuJAyDId3u8wro9T8BLvdAy2ywwFZcSFEi0+nh0ucczDI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16304931063241016.4146811383825; Wed, 1 Sep 2021 03:45:06 -0700 (PDT) Received: from localhost ([::1]:36980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNjt-0004HM-17 for importer@patchew.org; Wed, 01 Sep 2021 06:45:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcA-0006pZ-Kv for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:06 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:46632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc4-0005cp-Ko for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:06 -0400 Received: by mail-wm1-x329.google.com with SMTP id m25-20020a7bcb99000000b002e751bcb5dbso1563926wmi.5 for ; Wed, 01 Sep 2021 03:37:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hrL7wY7FeSozFPbmJ1hgaWugx0ZzntiXknL52DAZLEI=; b=UGQHxkBimLl+WaYrpOfJ+i3UkzChwU6rCuaAsO63sINIMh9DrIn/PiVxh/OyBr28uY f1Uvy4hWT4C57k3m7yh1CCtZ3TlilDtjGms/22xcPmkM0bsjkwD6rvkhOVQCqi1zv5dP wtyfPJp/4NFyOemtGWyuVWf8+wk6TCWlGT3SxZMYgPNmBYTRxnYZAB5IEdq3AkV2fV86 y+4yrubxlkx/NkegSizNyqwgerMGix0VA6C1M8eD4i7qY48ded/Jqm91kCC8jWMf8d5b M6P2HwG6LwVg3X9+qb+AU/li6x9yBCGBpwUz3pn5Xdx3IlBEmfvlD04/wX6Z+OINISFw 2pcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hrL7wY7FeSozFPbmJ1hgaWugx0ZzntiXknL52DAZLEI=; b=a0Q624rekHJUOtfvQxYjzjL1V1dfM/5b0Fuyn8uVMLjwH/lx2a4ECC/AJPdqXHOsHK i5VIR9SVJZI3q6ixqM9ojhucZSwy9y5idDzw9F2/DibPvhMRu/6h6RzilHCJoaW727pM TDM4ROar/1ix0Xayi+0g4sRSpBWyt+1wJUi+iy5W82Ub82+/VFG7U/P9HxnGc4WNVmWB hi4PC14WT/XSeqxaWyUatnfMyeiLyEvMJ8NI4CIK2Xz5kgvGg742VbHxZwPO4UdC846o WUlw1yMYIylN6vN5YiPzf16kuWiG2OCDLMM5hcJTsm96AcSV3EFA6BAxmMX5ayvejvW9 5Bxg== X-Gm-Message-State: AOAM531ziwzZKH0WgdPOUchoLEAPhLhntcn6eDfgdsrCb6BELZcO1scl h2o2QeXal+s+qgsIspgZbymAz4x4yyFIdA== X-Google-Smtp-Source: ABdhPJz9WppEH/auTLlrGUz6j6/7CCs/sgdFw/02jpa6XkEHfwlLxoghNNlamyu03uZePoA9WE7EVA== X-Received: by 2002:a1c:4e11:: with SMTP id g17mr9116196wmh.2.1630492619070; Wed, 01 Sep 2021 03:36:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/51] hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans Date: Wed, 1 Sep 2021 11:36:06 +0100 Message-Id: <20210901103653.13435-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493107777100001 From: Philippe Mathieu-Daud=C3=A9 Quoting Peter Maydell: These MEMTX_* aren't from the memory transaction API functions; they're just being used by gicd_readl() and friends as a way to indicate a success/failure so that the actual MemoryRegionOps read/write fns like gicv3_dist_read() can log a guest error. Arguably this is a bit of a misuse of the MEMTX_* constants and perhaps we should have gicd_readl etc return a bool instead. Follow his suggestion and replace the MEMTX_* constants by boolean values, simplifying a bit the gicv3_dist_read() / gicv3_dist_write() handlers. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210826180704.2131949-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_dist.c | 201 +++++++++++++++++++++------------------ 1 file changed, 106 insertions(+), 95 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 7e9b393d9ab..5beb7c4235a 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -262,8 +262,21 @@ static void gicd_write_irouter(GICv3State *s, MemTxAtt= rs attrs, int irq, gicv3_update(s, irq, 1); } =20 -static MemTxResult gicd_readb(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +/** + * gicd_readb + * gicd_readw + * gicd_readl + * gicd_readq + * gicd_writeb + * gicd_writew + * gicd_writel + * gicd_writeq + * + * Return %true if the operation succeeded, %false otherwise. + */ + +static bool gicd_readb(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Most GICv3 distributor registers do not support byte accesses. */ switch (offset) { @@ -273,17 +286,17 @@ static MemTxResult gicd_readb(GICv3State *s, hwaddr o= ffset, /* This GIC implementation always has affinity routing enabled, * so these registers are all RAZ/WI. */ - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: *data =3D gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writeb(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writeb(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Most GICv3 distributor registers do not support byte accesses. */ switch (offset) { @@ -293,25 +306,25 @@ static MemTxResult gicd_writeb(GICv3State *s, hwaddr = offset, /* This GIC implementation always has affinity routing enabled, * so these registers are all RAZ/WI. */ - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int irq =3D offset - GICD_IPRIORITYR; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } gicd_write_ipriorityr(s, attrs, irq, value); gicv3_update(s, irq, 1); - return MEMTX_OK; + return true; } default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_readw(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readw(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETS= PI_NSR * support 16 bit accesses, and those registers are all part of the @@ -319,11 +332,11 @@ static MemTxResult gicd_readw(GICv3State *s, hwaddr o= ffset, * implement (ie for us GICD_TYPER.MBIS =3D=3D 0), so for us they are * reserved. */ - return MEMTX_ERROR; + return false; } =20 -static MemTxResult gicd_writew(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writew(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETS= PI_NSR * support 16 bit accesses, and those registers are all part of the @@ -331,11 +344,11 @@ static MemTxResult gicd_writew(GICv3State *s, hwaddr = offset, * implement (ie for us GICD_TYPER.MBIS =3D=3D 0), so for us they are * reserved. */ - return MEMTX_ERROR; + return false; } =20 -static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readl(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Almost all GICv3 distributor registers are 32-bit. * Note that WO registers must return an UNKNOWN value on reads, @@ -363,7 +376,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, } else { *data =3D s->gicd_ctlr; } - return MEMTX_OK; + return true; case GICD_TYPER: { /* For this implementation: @@ -387,61 +400,61 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, =20 *data =3D (1 << 25) | (1 << 24) | (sec_extn << 10) | (0xf << 19) | itlinesnumber; - return MEMTX_OK; + return true; } case GICD_IIDR: /* We claim to be an ARM r0p0 with a zero ProductID. * This is the same as an r0p0 GIC-500. */ *data =3D gicv3_iidr(); - return MEMTX_OK; + return true; case GICD_STATUSR: /* RAZ/WI for us (this is an optional register and our implementat= ion * does not track RO/WO/reserved violations to report them to the = guest) */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: { int irq; =20 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { *data =3D 0; - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGROUPR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } *data =3D *gic_bmp_ptr32(s->group, irq); - return MEMTX_OK; + return true; } case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ISENABLER); - return MEMTX_OK; + return true; case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ICENABLER); - return MEMTX_OK; + return true; case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge= 1, offset - GICD_ISPENDR); - return MEMTX_OK; + return true; case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge= 2, offset - GICD_ICPENDR); - return MEMTX_OK; + return true; case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, offset - GICD_ISACTIVER); - return MEMTX_OK; + return true; case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, offset - GICD_ICACTIVER); - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int i, irq =3D offset - GICD_IPRIORITYR; @@ -452,12 +465,12 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, value |=3D gicd_read_ipriorityr(s, attrs, i); } *data =3D value; - return MEMTX_OK; + return true; } case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: /* RAZ/WI since affinity routing is always enabled */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_ICFGR ... GICD_ICFGR + 0xff: { /* Here only the even bits are used; odd bits are RES0 */ @@ -466,7 +479,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } =20 /* Since our edge_trigger bitmap is one bit per irq, we only need @@ -478,7 +491,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, value =3D extract32(value, (irq & 0x1f) ? 16 : 0, 16); value =3D half_shuffle32(value) << 1; *data =3D value; - return MEMTX_OK; + return true; } case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: { @@ -489,16 +502,16 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, * security enabled and this is an NS access */ *data =3D 0; - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGRPMODR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } *data =3D *gic_bmp_ptr32(s->grpmod, irq); - return MEMTX_OK; + return true; } case GICD_NSACR ... GICD_NSACR + 0xff: { @@ -507,7 +520,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } =20 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { @@ -515,17 +528,17 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, * security enabled and this is an NS access */ *data =3D 0; - return MEMTX_OK; + return true; } =20 *data =3D s->gicd_nsacr[irq / 16]; - return MEMTX_OK; + return true; } case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: /* RAZ/WI since affinity routing is always enabled */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: { uint64_t r; @@ -537,26 +550,26 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, } else { *data =3D (uint32_t)r; } - return MEMTX_OK; + return true; } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ *data =3D gicv3_idreg(offset - GICD_IDREGS); - return MEMTX_OK; + return true; case GICD_SGIR: /* WO registers, return unknown value */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read from WO register at offset " TARGET_FMT_plx "\n", __func__, offset); *data =3D 0; - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writel(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Almost all GICv3 distributor registers are 32-bit. Note that * RO registers must ignore writes, not abort. @@ -600,68 +613,68 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, s->gicd_ctlr &=3D ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); } gicv3_full_update(s); - return MEMTX_OK; + return true; } case GICD_STATUSR: /* RAZ/WI for our implementation */ - return MEMTX_OK; + return true; case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: { int irq; =20 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGROUPR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } *gic_bmp_ptr32(s->group, irq) =3D value; gicv3_update(s, irq, 32); - return MEMTX_OK; + return true; } case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ISENABLER, value); - return MEMTX_OK; + return true; case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ICENABLER, value); - return MEMTX_OK; + return true; case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, offset - GICD_ISPENDR, value); - return MEMTX_OK; + return true; case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, offset - GICD_ICPENDR, value); - return MEMTX_OK; + return true; case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, offset - GICD_ISACTIVER, value); - return MEMTX_OK; + return true; case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, offset - GICD_ICACTIVER, value); - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int i, irq =3D offset - GICD_IPRIORITYR; =20 if (irq < GIC_INTERNAL || irq + 3 >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 for (i =3D irq; i < irq + 4; i++, value >>=3D 8) { gicd_write_ipriorityr(s, attrs, i, value); } gicv3_update(s, irq, 4); - return MEMTX_OK; + return true; } case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: /* RAZ/WI since affinity routing is always enabled */ - return MEMTX_OK; + return true; case GICD_ICFGR ... GICD_ICFGR + 0xff: { /* Here only the odd bits are used; even bits are RES0 */ @@ -669,7 +682,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, uint32_t mask, oldval; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 /* Since our edge_trigger bitmap is one bit per irq, our input @@ -687,7 +700,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, oldval =3D *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); value =3D (oldval & ~mask) | (value & mask); *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) =3D value; - return MEMTX_OK; + return true; } case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: { @@ -697,16 +710,16 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, /* RAZ/WI if security disabled, or if * security enabled and this is an NS access */ - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGRPMODR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } *gic_bmp_ptr32(s->grpmod, irq) =3D value; gicv3_update(s, irq, 32); - return MEMTX_OK; + return true; } case GICD_NSACR ... GICD_NSACR + 0xff: { @@ -714,41 +727,41 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, int irq =3D (offset - GICD_NSACR) * 4; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { /* RAZ/WI if security disabled, or if * security enabled and this is an NS access */ - return MEMTX_OK; + return true; } =20 s->gicd_nsacr[irq / 16] =3D value; /* No update required as this only affects access permission check= s */ - return MEMTX_OK; + return true; } case GICD_SGIR: /* RES0 if affinity routing is enabled */ - return MEMTX_OK; + return true; case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: /* RAZ/WI since affinity routing is always enabled */ - return MEMTX_OK; + return true; case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: { uint64_t r; int irq =3D (offset - GICD_IROUTER) / 8; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 /* Write half of the 64-bit register */ r =3D gicd_read_irouter(s, attrs, irq); r =3D deposit64(r, (offset & 7) ? 32 : 0, 32, value); gicd_write_irouter(s, attrs, irq, r); - return MEMTX_OK; + return true; } case GICD_IDREGS ... GICD_IDREGS + 0x2f: case GICD_TYPER: @@ -757,14 +770,14 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " TARGET_FMT_plx "\n", __func__, offset); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writeq(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -773,14 +786,14 @@ static MemTxResult gicd_writeq(GICv3State *s, hwaddr = offset, case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: irq =3D (offset - GICD_IROUTER) / 8; gicd_write_irouter(s, attrs, irq, value); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_readq(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readq(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -789,9 +802,9 @@ static MemTxResult gicd_readq(GICv3State *s, hwaddr off= set, case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: irq =3D (offset - GICD_IROUTER) / 8; *data =3D gicd_read_irouter(s, attrs, irq); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 @@ -799,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset= , uint64_t *data, unsigned size, MemTxAttrs attrs) { GICv3State *s =3D (GICv3State *)opaque; - MemTxResult r; + bool r; =20 switch (size) { case 1: @@ -815,11 +828,11 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offs= et, uint64_t *data, r =3D gicd_readq(s, offset, data, attrs); break; default: - r =3D MEMTX_ERROR; + r =3D false; break; } =20 - if (r =3D=3D MEMTX_ERROR) { + if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); @@ -829,19 +842,18 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offs= et, uint64_t *data, * trigger the guest-error logging but don't return it to * the caller, or we'll cause a spurious guest data abort. */ - r =3D MEMTX_OK; *data =3D 0; } else { trace_gicv3_dist_read(offset, *data, size, attrs.secure); } - return r; + return MEMTX_OK; } =20 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) { GICv3State *s =3D (GICv3State *)opaque; - MemTxResult r; + bool r; =20 switch (size) { case 1: @@ -857,11 +869,11 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr off= set, uint64_t data, r =3D gicd_writeq(s, offset, data, attrs); break; default: - r =3D MEMTX_ERROR; + r =3D false; break; } =20 - if (r =3D=3D MEMTX_ERROR) { + if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); @@ -871,11 +883,10 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr off= set, uint64_t data, * trigger the guest-error logging but don't return it to * the caller, or we'll cause a spurious guest data abort. */ - r =3D MEMTX_OK; } else { trace_gicv3_dist_write(offset, data, size, attrs.secure); } - return r; + return MEMTX_OK; } =20 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630492768; cv=none; d=zohomail.com; s=zohoarc; b=l6p5HX4QvLwzXMyK31Xpkv3JE0J9miLScpE1stHvx4JFWEs/CiiubjO5s29nEbMBkBFNChDW/HYqqe5MvzT4YcBj0VbA5Qwn254NyWoEd+BJHwR1GDhak0s5OGjm+LfCkZPF1Cv4gU9+7Pn1gs1Itx61hEsY8jR2xnd7FFMb1jM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630492768; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kw+tgxnJQFgyIKtC9H3QhpTCdzasNtrMOVm+PcV5arQ=; b=RusSTD3wtB6RE6OV0q8z7oGKr5Jsbzu0kbu6fdbg3B/xm1xwIfNiTYPUG5Os5g7xRyCtKo0ylq/IAnYwG+29l1UiUcpiC+Y57H1kAOTBO8KRjS1JPTKFiX/PDL9wXbHRCBqdPv7CE74eSnIwbms0twNEdH1gq8WVMKJML6inSV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163049276843423.823329659990236; Wed, 1 Sep 2021 03:39:28 -0700 (PDT) Received: from localhost ([::1]:48226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNeR-0001RM-Eb for importer@patchew.org; Wed, 01 Sep 2021 06:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNc8-0006jq-4i for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:04 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc5-0005dB-2K for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:03 -0400 Received: by mail-wr1-x429.google.com with SMTP id u16so3749816wrn.5 for ; Wed, 01 Sep 2021 03:37:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Kw+tgxnJQFgyIKtC9H3QhpTCdzasNtrMOVm+PcV5arQ=; b=ioXyUWKLhk3NPSbBlb40NKHCGzSdo+rJCPCRlg0chYz+H2xXpBjKj4MhMau19aMJCl dEvWM5N8czO/x3dhhytEwNmR/Rghza+WJ2Tv8mWDyXRhY0DK+PsMR6uo9wsVkDPTBpNn QeasL0sLg0rUUPJVLQWaIilzjgtrSjvODV9tfTP+GjsK0pWBkm6HLdGYzXCQMZZA1hRp 7S6/lbMIiATIieivA7YrLkZBy/iTM4YfD0nEOvbPQ5592gFXATwWQi59fzwR1QS2iKuY nPf0+hEOBdZ549+vcOwl3VWIIO+S8GGP+Tx1RIQNFyyG/jcd2dmpp9d+kwt78YwBQL+P JPHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kw+tgxnJQFgyIKtC9H3QhpTCdzasNtrMOVm+PcV5arQ=; b=WwMHg0zFPJKvFviOz8XenIKAYJsia6L84aqMkTMq3LcAHl+oZMhfAzKiKZbHd238po UDNzloJZ/cp5wJxyPMciXy4cV4Ul0tPeG9ICcH3GCs43TzPKiLiH3qHf/at6d02p4dNO OTmlkIQsinsO7Of2JOoDllU9599ld1lNhOAAGRg/EoYGr9XjzIUnuumBqWrE4bWfKkaj bfm5iQmjDgORXB+XoSSqt4LkEYmRI7crU2Ky9aOrMBvZnRzOnDg1KHKqYS4b/xYi9GAn IzgE4Wg3yfyYsddOzMjAuMLaPH5omNom517fI5AIY4Ml537Ur031iXKit4VR7J2TpayG cKdg== X-Gm-Message-State: AOAM53181WI7LMG5bWCKFZTE3Opq1mBetPif1QUKpYsTUoHImnNNDjUp 8dT3XtvzmRnPdN9Mpew9V4tZO6l4IzKq/Q== X-Google-Smtp-Source: ABdhPJyT4uDWUhKGFBPc41aAljyjs3WYkwLgTp112y8f1nBje/wXyABlmKMu0KR+Ut0jH2Rlfh4P0g== X-Received: by 2002:adf:b7c1:: with SMTP id t1mr37468326wre.387.1630492619745; Wed, 01 Sep 2021 03:36:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/51] hw: Add compat machines for 6.2 Date: Wed, 1 Sep 2021 11:36:07 +0100 Message-Id: <20210901103653.13435-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492770670100001 Content-Type: text/plain; charset="utf-8" From: Yanan Wang Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang Acked-by: David Gibson Reviewed-by: Andrew Jones Reviewed-by: Cornelia Huck Reviewed-by: Pankaj Gupta Signed-off-by: Peter Maydell --- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ hw/arm/virt.c | 11 +++++++++-- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 14 +++++++++++++- hw/i386/pc_q35.c | 13 ++++++++++++- hw/ppc/spapr.c | 17 ++++++++++++++--- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++++- 9 files changed, 73 insertions(+), 8 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index accd6eff35a..463a5514f97 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -353,6 +353,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 +extern GlobalProperty hw_compat_6_1[]; +extern const size_t hw_compat_6_1_len; + extern GlobalProperty hw_compat_6_0[]; extern const size_t hw_compat_6_0_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 88dffe75172..97b4ab79b53 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -196,6 +196,9 @@ void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, siz= e_t flash_size); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); =20 +extern GlobalProperty pc_compat_6_1[]; +extern const size_t pc_compat_6_1_len; + extern GlobalProperty pc_compat_6_0[]; extern const size_t pc_compat_6_0_len; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 86c8a4ca3d7..dbb77b59974 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2783,10 +2783,17 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 -static void virt_machine_6_1_options(MachineClass *mc) +static void virt_machine_6_2_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(6, 1) +DEFINE_VIRT_MACHINE_AS_LATEST(6, 2) + +static void virt_machine_6_1_options(MachineClass *mc) +{ + virt_machine_6_2_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); +} +DEFINE_VIRT_MACHINE(6, 1) =20 static void virt_machine_6_0_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 54e040587dd..067f42b528f 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -37,6 +37,9 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" =20 +GlobalProperty hw_compat_6_1[] =3D {}; +const size_t hw_compat_6_1_len =3D G_N_ELEMENTS(hw_compat_6_1); + GlobalProperty hw_compat_6_0[] =3D { { "gpex-pcihost", "allow-unmapped-accesses", "false" }, { "i8042", "extended-state", "false"}, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 102b2239468..1276bfeee45 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -93,6 +93,9 @@ #include "trace.h" #include CONFIG_DEVICES =20 +GlobalProperty pc_compat_6_1[] =3D {}; +const size_t pc_compat_6_1_len =3D G_N_ELEMENTS(pc_compat_6_1); + GlobalProperty pc_compat_6_0[] =3D { { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 1bc30167acc..c5da7739cef 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -412,7 +412,7 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); } =20 -static void pc_i440fx_6_1_machine_options(MachineClass *m) +static void pc_i440fx_6_2_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); @@ -421,6 +421,18 @@ static void pc_i440fx_6_1_machine_options(MachineClass= *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_I440FX_MACHINE(v6_2, "pc-i440fx-6.2", NULL, + pc_i440fx_6_2_machine_options); + +static void pc_i440fx_6_1_machine_options(MachineClass *m) +{ + pc_i440fx_6_2_machine_options(m); + m->alias =3D NULL; + m->is_default =3D false; + compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); + compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); +} + DEFINE_I440FX_MACHINE(v6_1, "pc-i440fx-6.1", NULL, pc_i440fx_6_1_machine_options); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index eeb0b185b11..565fadce540 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -354,7 +354,7 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_6_1_machine_options(MachineClass *m) +static void pc_q35_6_2_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_machine_options(m); @@ -362,6 +362,17 @@ static void pc_q35_6_1_machine_options(MachineClass *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, + pc_q35_6_2_machine_options); + +static void pc_q35_6_1_machine_options(MachineClass *m) +{ + pc_q35_6_2_machine_options(m); + m->alias =3D NULL; + compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); + compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); +} + DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, pc_q35_6_1_machine_options); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 81699d4f8be..d39fd4e6449 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4686,14 +4686,25 @@ static void spapr_machine_latest_class_options(Mach= ineClass *mc) type_init(spapr_machine_register_##suffix) =20 /* - * pseries-6.1 + * pseries-6.2 */ -static void spapr_machine_6_1_class_options(MachineClass *mc) +static void spapr_machine_6_2_class_options(MachineClass *mc) { /* Defaults for the latest behaviour inherited from the base class */ } =20 -DEFINE_SPAPR_MACHINE(6_1, "6.1", true); +DEFINE_SPAPR_MACHINE(6_2, "6.2", true); + +/* + * pseries-6.1 + */ +static void spapr_machine_6_1_class_options(MachineClass *mc) +{ + spapr_machine_6_2_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); +} + +DEFINE_SPAPR_MACHINE(6_1, "6.1", false); =20 /* * pseries-6.0 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index e4b18aef496..4d25278cf20 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -791,14 +791,26 @@ bool css_migration_enabled(void) } = \ type_init(ccw_machine_register_##suffix) =20 +static void ccw_machine_6_2_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_6_2_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(6_2, "6.2", true); + static void ccw_machine_6_1_instance_options(MachineState *machine) { + ccw_machine_6_2_instance_options(machine); } =20 static void ccw_machine_6_1_class_options(MachineClass *mc) { + ccw_machine_6_2_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); } -DEFINE_CCW_MACHINE(6_1, "6.1", true); +DEFINE_CCW_MACHINE(6_1, "6.1", false); =20 static void ccw_machine_6_0_instance_options(MachineState *machine) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630492916; cv=none; d=zohomail.com; s=zohoarc; b=LQ+h6uoba88axxY/c8A0B4U+HqWOGqCI4Wbg1ThqHMW81bvAsIMMEROiwpK5gaaXioEz2+IgRXDdxPZ7AauTNp8HsXqwFr3Kmmj6r1Ff6W9eFnD6GO4qpaibQk2gIRhv7yN8Xr7Om84zsYSvzRBX2dNmGNiDD2gkCI3R8m7QNWk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630492916; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.36.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mWFsqLJx/ZREG9fsj3Ycq1zQrSJgiL5MT7G2IKi2KCc=; b=vR5OJvH84Lqs2vbAIWyVvUS9iyluzShJ4f5LlEO/tYqL0yRkJh8UJfVOkgEMoWOGz9 LVW3G8T5ypkgg9XTz7CAKHcH1HLQ2o1JVTzNxSYqCoN0YQL2Df+Ka5SH8+dm6CmWBDSR nrYKmHok/RX3RCNdPrXxlX9lj+scnHyF1+Uz3lLpOGeOn3QP5xgiDle2o18jpUF08Njo 7Z5htVGiFOy2hEkgBdNgmVbIsY/sTNYiggh4nfzBJon25+LNyVCBuoFjQulrKqX8ukYp rxR037A/QcDbZikLXRpUV1Nha0u6oBwuSQkyiCBsx4ap/LJ2Z4+EJLwwv8sLf5sbhqT+ fz3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mWFsqLJx/ZREG9fsj3Ycq1zQrSJgiL5MT7G2IKi2KCc=; b=IITbr10oDXajxK4aFfFQcMj/D+zMFtzmpk2ApZyGUMcaN5V1QNvfUmkZo9PKqjnJIg KSRdVB7U9EK+vDt94iAOBJuKB5U2clK/yUWiZS4iya/VmcrNDRNxFLfz0Gc520TW6Qwb zTiiDSg45OosYasQ9SmsRDVfeLeGHwtxny6BfeCty/nPXq6yQb7Xd/dWgk3qePyVaLS9 QAK3nZj36U5FpGcEVZ1JGJ/RbuplSAw7453JPOx/LVnxwILV0CfDcM9i3R9Lt/VmF7Df zvKcZRbEELJxh5vJpe80RrNlHVpAGcYP+urN+oaJ4GvP8npxcmKqKBcct2T5fG9XLCY7 kqhQ== X-Gm-Message-State: AOAM530Fk2FtgDgk4ZKQyb549UJTjWBXyXoFEhCjeuM/KqwJx6ReXHWX buhXJkbyz8HS1EgfEGSo2A0Z0f2nV8ONyg== X-Google-Smtp-Source: ABdhPJzOlJ4foWY/6uOA3gNFGDhysGI5YIa+rVxTKp+1FgnFqNDwNbM7XRbuyEqIp/LHYdh8CeCo5A== X-Received: by 2002:a1c:20d7:: with SMTP id g206mr9229605wmg.153.1630492620383; Wed, 01 Sep 2021 03:37:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/51] target/arm: Implement MVE VADD (floating-point) Date: Wed, 1 Sep 2021 11:36:08 +0100 Message-Id: <20210901103653.13435-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492918521100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 3 +++ target/arm/translate.h | 6 ++++++ target/arm/mve.decode | 10 ++++++++++ target/arm/mve_helper.c | 40 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 17 ++++++++++++++++ target/arm/translate-neon.c | 6 ------ 6 files changed, 76 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 3db9b15f121..32fd2e1f9be 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -410,6 +410,9 @@ DEF_HELPER_FLAGS_4(mve_vhcadd270b, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vhcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) =20 +DEF_HELPER_FLAGS_4(mve_vfaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfadds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 241596c5bda..8636c20c3b4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -181,6 +181,12 @@ static inline int rsub_8(DisasContext *s, int x) return 8 - x; } =20 +static inline int neon_3same_fp_size(DisasContext *s, int x) +{ + /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ + return MO_32 - x; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 87446816293..e211cb016c6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -26,6 +26,10 @@ # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit %size_28 28:1 !function=3Dplus_1 =20 +# 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit, +# like Neon FP insns. +%2op_fp_size 20:1 !function=3Dneon_3same_fp_size + # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 =20 @@ -118,6 +122,9 @@ =20 @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 +@2op_fp .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -615,3 +622,6 @@ VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1= 0 0 .... @vcmp_scalar VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar + +# 2-operand FP +VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c2826eb5f9f..abca7c0b2ab 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" +#include "fpu/softfloat.h" =20 static uint16_t mve_eci_mask(CPUARMState *env) { @@ -2798,3 +2799,42 @@ DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) + +/* + * 2-operand floating point. Note that if an element is partially + * predicated we must do the FP operation to update the non-predicated + * bytes, but we must be careful to avoid updating the FP exception + * state unless byte 0 of the element was unpredicated. + */ +#define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_2OP_FP_ALL(OP, FN) \ + DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ + DO_2OP_FP(OP##s, 4, float32, float32_##FN) + +DO_2OP_FP_ALL(vfadd, add) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 78229c44c68..d2c40ede564 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -831,6 +831,23 @@ static bool trans_VSBCI(DisasContext *s, arg_2op *a) return do_2op(s, a, gen_helper_mve_vsbci); } =20 +#define DO_2OP_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ + { \ + static MVEGenTwoOpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2op(s, a, fns[a->size]); \ + } + +DO_2OP_FP(VADD_fp, vfadd) + static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) { diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index c53ab20fa48..dd43de558e4 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -28,12 +28,6 @@ #include "translate.h" #include "translate-a32.h" =20 -static inline int neon_3same_fp_size(DisasContext *s, int x) -{ - /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ - return MO_32 - x; -} - /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493109; cv=none; d=zohomail.com; s=zohoarc; b=GzSeDakrEifcD8YP3Y0kqazYJhj7bm/b8cMPC5sy5x49MyGiDk4eiu6XaS9bAHPB9lXwkE7xcRXPUKyw1RNFCsTAhzkFLdTHapuRXCPCDa26b+FK42t/GNoouhBhC5dgxxZwTSMftZy6I5ztq0pOVxoYLISkUjqjXeN9fV68rGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493109; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7mTQUcJGT6UFVXbJpvXZ1T20jSlBRZTOds7w3SMrgYQ=; b=RnA0Y0t60NnlnBJkx/Rgmtau0EcAzexrWXlV7PFHpXZb6bGHfZ/w9DBXZExHD+MBp90TAu1ySbM65QxsUrdyZKfHpvsrIaANEpjnkXZZ20ZW2/DJcVJECwq7UJ7nPUC9K/+JNmFphfJBq3pEt6LY5wOv9eeQ47byUlAc0IB5n2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493109466763.1774862559654; Wed, 1 Sep 2021 03:45:09 -0700 (PDT) Received: from localhost ([::1]:37138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNjw-0004NY-AX for importer@patchew.org; Wed, 01 Sep 2021 06:45:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNc9-0006lc-55 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:05 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:45961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc6-0005e9-Am for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:04 -0400 Received: by mail-wm1-x332.google.com with SMTP id j17-20020a05600c1c1100b002e754875260so1569980wms.4 for ; Wed, 01 Sep 2021 03:37:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7mTQUcJGT6UFVXbJpvXZ1T20jSlBRZTOds7w3SMrgYQ=; b=pENUcH9Krk15VERU8CJ0cufUf9enjtt5+m3/chVjE3VyfCpSQuYagB0pN9N2OGVHW5 KYPXEDbJGnn6x2npRlm2IoU0uPwZThyQOyoksdBLRHF5GnmQ+tLE6jMCvg2AQ/HkTIha ZLNTUvOv7qcnBGJA+DV8i4ZX9oUk1LfjtlT461CnV2RewY/DOIMt3b3BIrAN/Sb+CV1E taiU2zYPk8CT/LLnHOBarYnzo/V3i3lQTNCt2nxWJvrcTuc3/5DhZpax5KktZo/KrMay t3MdOomFhuQ3c5YwM3ruytcINo4AcOK9gpkZ6dS62RtOxMrc0nR4ZWhXtCL6s19ENbLF OrIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7mTQUcJGT6UFVXbJpvXZ1T20jSlBRZTOds7w3SMrgYQ=; b=EG1E25bUsIzyh8lTZIFV751wN86vi1qwsnoLF8O9GGSmbGS/8ecu+kb7TUDHSukDao PMLtamurAdZ+X1NmKy3sbPzbYQu8Z6yNp4MkSrcyafIbmNsYVlx4mDv2PsKmzO8Am432 pujkBcz1Njy0sCPl4tpZTJDA0ZpWbBAsj51FwZCEQ5WWx+dbOpq1KP89Uoyj1VCZBwQC BbO0EvmixIaoLtBOccH6bH5dA5PrBDkbzKrqimgLo2mDUM0KqSXHi8NBbjCHKsW3Jtx9 DtJRb9YyhLHPDISAoKmR3NckVotGE733DpeKgM4lvsz0KY+EjPh1/3r6qkdyqFX1IHVa nuWA== X-Gm-Message-State: AOAM532tYfwRqZWtpD43Tez7yHRavfYEiBmtaZVlJAvFK4SxFpF7OcDs dzgn2/cCDDYIbvgjj4L7GXjzSTvVCTHVIA== X-Google-Smtp-Source: ABdhPJxLjOTN7g40jGmMyfa6A35QMfkMdDRFD5xF00WUwupF8J8JAgVFlCdfFSEdcLZyI/aRjCOJrw== X-Received: by 2002:a1c:a5c2:: with SMTP id o185mr9066465wme.34.1630492620928; Wed, 01 Sep 2021 03:37:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/51] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM Date: Wed, 1 Sep 2021 11:36:09 +0100 Message-Id: <20210901103653.13435-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493110134100001 Content-Type: text/plain; charset="utf-8" Implement more simple 2-operand floating point MVE insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 15 +++++++++++++++ target/arm/mve.decode | 6 ++++++ target/arm/mve_helper.c | 16 ++++++++++++++++ target/arm/translate-mve.c | 5 +++++ 4 files changed, 42 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 32fd2e1f9be..370876d7934 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -413,6 +413,21 @@ DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, voi= d, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfadds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vfsubh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfsubs, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmuls, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfabdh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfabds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmaxnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index e211cb016c6..cdbfaa4245b 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -625,3 +625,9 @@ VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1= 1 0 .... @vcmp_scalar =20 # 2-operand FP VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp +VSUB_fp 1110 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp +VMUL_fp 1111 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 1 ... 0 @2op_fp +VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp + +VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp +VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index abca7c0b2ab..d6bc686c985 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2838,3 +2838,19 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) DO_2OP_FP(OP##s, 4, float32, float32_##FN) =20 DO_2OP_FP_ALL(vfadd, add) +DO_2OP_FP_ALL(vfsub, sub) +DO_2OP_FP_ALL(vfmul, mul) + +static inline float16 float16_abd(float16 a, float16 b, float_status *s) +{ + return float16_abs(float16_sub(a, b, s)); +} + +static inline float32 float32_abd(float32 a, float32 b, float_status *s) +{ + return float32_abs(float32_sub(a, b, s)); +} + +DO_2OP_FP_ALL(vfabd, abd) +DO_2OP_FP_ALL(vmaxnm, maxnum) +DO_2OP_FP_ALL(vminnm, minnum) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d2c40ede564..98282335820 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -847,6 +847,11 @@ static bool trans_VSBCI(DisasContext *s, arg_2op *a) } =20 DO_2OP_FP(VADD_fp, vfadd) +DO_2OP_FP(VSUB_fp, vfsub) +DO_2OP_FP(VMUL_fp, vfmul) +DO_2OP_FP(VABD_fp, vfabd) +DO_2OP_FP(VMAXNM, vmaxnm) +DO_2OP_FP(VMINNM, vminnm) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CDghGKNxB38lPfiyQ/7haMC6qZxl8ZbSdUy9LBKKEMk=; b=z1ZezLE75PtzMtp7lCgSBWG88uCu0bhR4gK+QybqT1OXKvER7qvsC9Q8Jq1Zd2t3ha mswLM0Q94MdM1tlaRbYlkxUBoMpK6FWngu1OLf7w4/tXpA/5JhQTGdyafhHSYuQhEBJh /uj2MJHg3z6NmmBUSHovj7n/9xUoI+Dl/GasBWYnq7/Z47jq7RtrQJ0AMyKyW9h60Zqo mXSe1V5ud/ukK/NkoK/u5SXeAYTDcl4f0V8BctfQ2Mai56TYo4jCcS+BFkxitjjdtrld U7hylHh/L5ONBVwZJsGTfx9fMyrjBxLDB4zXYbt4NVGxUV6gbRh/He3n8ngMeiQIXMu1 kVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CDghGKNxB38lPfiyQ/7haMC6qZxl8ZbSdUy9LBKKEMk=; b=F6hHgWkSzqgFOVlpqOGK93VoDWENyBeDdZ7OPwwuQ7pIUq3xuRVOTMm5ix07yKBR2x PJaziQZG45U2mzuBP+frhyVFFjVfu4lZVHqW+i4da5ZeN6mjx4KARVqIvU3ktDUcIOhR jLcmAxz1f7SpixBmtYM1W5lDwq+GGV6+NQKKcbIDGeIVcK6VIBmt8EVexxccOCak3+C9 FBarHUYYInvzHZhaSh5xUW0ng04PABZRuJeHDjRuz1nox2GywLQ96Jg1fpVocmSOjhnN VAjOz4Coq0aI5no6LaPZtQf5UPtaXwB1PtY2AWkhNeu+h0r1mwoUiMiMPCf7BD2MqemA 8iWw== X-Gm-Message-State: AOAM533RYrWDJKfyfzsGTIzTKnjoWFGL+aGO8MojX3CmnmFQqQ+P4Z9R OR40JlKk7HafXe9dU4o9GTDfoqjsGsVJIQ== X-Google-Smtp-Source: ABdhPJwpHIEIQfFsOHDx0tjVxWrp8cr4JSh8GHKEWOd7lSivVIYIn2jtc6r1yDsHD7ey+BAkUqqlTw== X-Received: by 2002:adf:b745:: with SMTP id n5mr37850991wre.338.1630492621571; Wed, 01 Sep 2021 03:37:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/51] target/arm: Implement MVE VCADD Date: Wed, 1 Sep 2021 11:36:10 +0100 Message-Id: <20210901103653.13435-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492770830100003 Content-Type: text/plain; charset="utf-8" Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz =3D=3D 1 && Qd =3D=3D Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 8 ++++++++ target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 +++- 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 370876d7934..42eba8ea96d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -428,6 +428,12 @@ DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vfcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vfcadd270s, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index cdbfaa4245b..c728c7089ac 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -29,6 +29,8 @@ # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit, # like Neon FP insns. %2op_fp_size 20:1 !function=3Dneon_3same_fp_size +# VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit +%2op_fp_size_rev 20:1 !function=3Dplus_1 =20 # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 @@ -125,6 +127,9 @@ @2op_fp .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size =20 +@2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size_rev + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -631,3 +636,6 @@ VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . = 1 . 0 ... 0 @2op_fp =20 VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp + +VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d6bc686c985..2cc8b3e11b7 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2854,3 +2854,43 @@ static inline float32 float32_abd(float32 a, float32= b, float_status *s) DO_2OP_FP_ALL(vfabd, abd) DO_2OP_FP_ALL(vmaxnm, maxnum) DO_2OP_FP_ALL(vminnm, minnum) + +#define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r[16 / ESIZE]; \ + uint16_t tm, mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + /* Calculate all results first to avoid overwriting inputs */ \ + for (e =3D 0, tm =3D mask; e < 16 / ESIZE; e++, tm >>=3D ESIZE) { = \ + if ((tm & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + r[e] =3D 0; \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(tm & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + if (!(e & 1)) { \ + r[e] =3D FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ + } else { \ + r[e] =3D FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ + } \ + } \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + mergemask(&d[H##ESIZE(e)], r[e], mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) +DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) +DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) +DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 98282335820..6203e3ff916 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -852,6 +852,8 @@ DO_2OP_FP(VMUL_fp, vfmul) DO_2OP_FP(VABD_fp, vfabd) DO_2OP_FP(VMAXNM, vmaxnm) DO_2OP_FP(VMINNM, vminnm) +DO_2OP_FP(VCADD90_fp, vfcadd90) +DO_2OP_FP(VCADD270_fp, vfcadd270) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) @@ -883,7 +885,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar = *a, return true; } =20 -#define DO_2OP_SCALAR(INSN, FN) \ +#define DO_2OP_SCALAR(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ { \ static MVEGenTwoOpScalarFn * const fns[] =3D { \ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493342; cv=none; d=zohomail.com; s=zohoarc; b=h4q/Ca4ac+67rzJPH74u+oPAbau8WZm4rstsPt773qWET3hXIQTT8jJ6bp4hu0oMBWg8AY3uB0Kkfia6DDUqMSSxK0KPq2enAbl6VqKOlsKlSfHgqCA2xfWcGVZMmocwiin1KAUeeqaVYC88kXuHIXQJxQPUkRYr13EoH5flUjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493342; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DtXlyh+x5hTL1mWaYC4Ui4ld7VP7J6g7isQSBi8KZMQ=; b=QoB8RAkzpR+/HkKa+4N/AGXq8ZflPU9EohvBXfpV6ffNBtntzBASP6VU7sR3VQ0nuL0ovibhUIaz9/bLsDyutDpWcqnM4YJ0Sk7Lp7TJMg+vlzOX0msOeNhTX46YAMQeKk3HO1ZhOiWabYA6s9rze3jQWs5tADH1N9d2OhYtF90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493342379108.06949877404998; Wed, 1 Sep 2021 03:49:02 -0700 (PDT) Received: from localhost ([::1]:45592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNnh-0001d0-Bi for importer@patchew.org; Wed, 01 Sep 2021 06:49:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcB-0006pl-NN for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:07 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:51920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc7-0005fX-Jv for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:06 -0400 Received: by mail-wm1-x32b.google.com with SMTP id u15so1523738wmj.1 for ; Wed, 01 Sep 2021 03:37:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DtXlyh+x5hTL1mWaYC4Ui4ld7VP7J6g7isQSBi8KZMQ=; b=COozZcOx+a/awhnpLbGOG4GHJoc7b35w3FgRVLqtSoEpC/ERnTBKc9wz0oOBmbxFl2 rL8/Xp6p3iG5rWrSwkpxpoJDqgHaQcjMQW/AqAXEg2Wdrej8egHynJWuleNO7vYhjLAN YsbPzkcM0wn6EBIaEs62nCUtMLektKiLwG+CIj6RV3K/E4ycZtl+pmFvubMhbvUCOgPX pnzvKemsA2C4UkA/5EOISRH6lCsJ3EM5701dKnhvgx+841Lx+1Yo3MGdVfwrIFc0wxM+ NPCpTOKTFEYlwQvxIngp5ggDP/4uoFAcfLBa4ysdv4cieh8rnH9iln61Gqn1eeXkjiM1 ntKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DtXlyh+x5hTL1mWaYC4Ui4ld7VP7J6g7isQSBi8KZMQ=; b=fAHvRE0xKnAaMxf/4OujJJIKjHyAtrR6LDOrCgI4VaMfqx14fy97pZby/dGPdWcn9W vb59tEXzV182CZ6Ecdl18vyGYO4znl+xckVkHoOlfh4ZPqxcdNfxj2QZFBgm+T4ApXCp xvmxnmGltkkSanUdUs11lRWRrSZuFHQdtqKs0O2a7R+JfN5M2Q7gUHhAMIrBu3YQ782K Qj2K2qoAWQEMme+SG2KPcdATdYwgznYZBJTGydxVfRYaVfoyq7ZBbVr81DL1SwXKXNSm W9mA6jW7SUjPCstOkg3LcdUnAYupI8CU15VAVA5G6JedOQqEqkJF21KJgNYM6pRoveVM BzTw== X-Gm-Message-State: AOAM531hvT/Tu2P5jNvzxVo7GV4Ik+CyNMriFDYYtMvXLS0ESM6N4r+M 9WK67zeBysuAqf+fD049fONrdSvhCvpuFw== X-Google-Smtp-Source: ABdhPJxdtY4rk1asOHnJvM/MI5crvsAKbrxs4CuSgmX2jt379lTNUUhPWziudrD0kK6lpYpqqgvw6g== X-Received: by 2002:a7b:c190:: with SMTP id y16mr8764138wmi.158.1630492622209; Wed, 01 Sep 2021 03:37:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/51] target/arm: Implement MVE VFMA and VFMS Date: Wed, 1 Sep 2021 11:36:11 +0100 Message-Id: <20210901103653.13435-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493343557100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VFMA and VFMS insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 48 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 42eba8ea96d..c230610d25c 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -434,6 +434,12 @@ DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) DEF_HELPER_FLAGS_4(mve_vfcadd270s, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) =20 +DEF_HELPER_FLAGS_4(mve_vfmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfmsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmss, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c728c7089ac..3a2056f6b34 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -639,3 +639,6 @@ VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . = 1 . 1 ... 0 @2op_fp =20 VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev + +VFMA 1110 1111 0 . 0 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp +VFMS 1110 1111 0 . 1 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2cc8b3e11b7..d7f250a4455 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2894,3 +2894,40 @@ DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, floa= t16_add) DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) + +#define DO_VFMA(OP, ESIZE, TYPE, CHS) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D n[H##ESIZE(e)]; \ + if (CHS) { \ + r =3D TYPE##_chs(r); \ + } \ + r =3D TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ + 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VFMA(vfmah, 2, float16, false) +DO_VFMA(vfmas, 4, float32, false) +DO_VFMA(vfmsh, 2, float16, true) +DO_VFMA(vfmss, 4, float32, true) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6203e3ff916..d61abc6d46f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -854,6 +854,8 @@ DO_2OP_FP(VMAXNM, vmaxnm) DO_2OP_FP(VMINNM, vminnm) DO_2OP_FP(VCADD90_fp, vfcadd90) DO_2OP_FP(VCADD270_fp, vfcadd270) +DO_2OP_FP(VFMA, vfma) +DO_2OP_FP(VFMS, vfms) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493393; cv=none; d=zohomail.com; s=zohoarc; b=oHl324NDiOh3Iekf4iys+oWRm7ZbXp8Necn8MlJjktfHUY+O5hlgSH7eQNFZegOn7Xqmr+QaYcJo670wTIrXxEXs2NRN6Um9ai/fW3vSeaOKELMVzQw+eGQj3vdEpdX9PzDZQgFQD6vT9nlryVZwEj0Mm2rjxdRm6M1kda7a70M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493393; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h5i+dvsMZeu+jpAZcIFJXNcZxOlG/Is/9TBheeSFdjU=; b=EP0Ni1tNb867w9TfMQUs3B16/tmgHrsrWDxB6hsJA5Wq3W4d0EkTeQBMe/WSDEyPkCwFVDrJVvM1lUXRPgq70MVDHqtfRw0n5MIbGCX4AX3EWyJA0qNsYLc2QwC2lUGjg6cEMmmfzxkL628NXpxxSaptxcseJioKu3HN82vc17k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163049339383936.113861649878345; Wed, 1 Sep 2021 03:49:53 -0700 (PDT) Received: from localhost ([::1]:48644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNoW-0003fM-PB for importer@patchew.org; Wed, 01 Sep 2021 06:49:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcB-0006s7-Gq for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:07 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:33788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNc8-0005gK-EQ for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:07 -0400 Received: by mail-wm1-x335.google.com with SMTP id j14-20020a1c230e000000b002e748b9a48bso3536055wmj.0 for ; Wed, 01 Sep 2021 03:37:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h5i+dvsMZeu+jpAZcIFJXNcZxOlG/Is/9TBheeSFdjU=; b=vSD1gxsVmLMElTqGvwGoBIi+xd5K2FIA/PPCtYh5S+R6z6gnyzOLeH7MAiBhxEEWbR GWPhe2k5v1jU+hfePoUKITahO1KIUl7H7RG4qid+KffiWkXR/IKSIhvtiTFekCM2nKlR kH34QyTCKPp4vtEXQDyjDEFi4h4g8v3pFWThilQKmhmMitCDUw68b/KNL2aQvagaWwXB MdZX0kdHEWBzcTANhXLKPW8StgPQdA2U2jeZH/7VHIYS857BXeNAfHThvjB3ZSgd2H9d pTH9Qq3ex8qqt4OVZ+UzuZHIeIiCXFQEU3G6Sl20UwgeVqOgBTyKmWGiw1mOapAoZAP2 qqRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h5i+dvsMZeu+jpAZcIFJXNcZxOlG/Is/9TBheeSFdjU=; b=dj0BHrSDgpnXlXHXGOE9iq6fw39XYsVS8EZ0c6FqPdMmj3yCr14pmw5lnT8zexVxpb dzrn2G2m4225EGyz44jCTW5XGVvaeXp/UNjQRwN6k7KCvzbudyWt3cFJz01m8zIqUqEk MJ4OxC/Gl5HyYEMckaOtNSwLaM/qBx//DFNu2KvA5KbZm83WtWw+Zrj7q2ugdG18Aw+M oFD7IGrTFtC9Slr3MDUFjEzZsuZRnrMvczGW2LNKsUsb0CRuk+dA9o46aBZV3E6ahRUb WlL7g8pUqoTg/bSL9oRWmT9Xc3GLoK7JphUINsS0hrLFh6nGMMwS4cil/bmaG7Kv2/+k Cilw== X-Gm-Message-State: AOAM532DFT5t9wAoxCPmvJS5iQebHTforWz3vvZdchvByD2bGF51yMPL s8CbfgP6FFpquxoLOtamKSQ3/W+0kHJLbA== X-Google-Smtp-Source: ABdhPJwe7+zplUVrX789St6VfdGDhyPQEoa3977rjZ0xQ68nmuGm1K1AhdGuEF2ZzjgrX3joihO7RQ== X-Received: by 2002:a1c:9d50:: with SMTP id g77mr8723812wme.67.1630492622878; Wed, 01 Sep 2021 03:37:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA Date: Wed, 1 Sep 2021 11:36:12 +0100 Message-Id: <20210901103653.13435-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493395958100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCMUL and VCMLA insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 18 ++++++++ target/arm/mve.decode | 35 ++++++++++++---- target/arm/mve_helper.c | 86 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 8 ++++ 4 files changed, 139 insertions(+), 8 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index c230610d25c..73950403bc3 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -440,6 +440,24 @@ DEF_HELPER_FLAGS_4(mve_vfmas, TCG_CALL_NO_WG, void, en= v, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfmsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfmss, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vcmul0h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul0s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul180h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul180s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul270s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vcmla0h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla0s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla180h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla180s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla270s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 3a2056f6b34..403381eef61 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -286,15 +286,29 @@ VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 .= 1 . 1 ... 0 @2op_rev VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev =20 -VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op -VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op -VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op -VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +{ + VCMUL0 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 0 @2op_sz28 + VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op + VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op +} =20 -VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op -VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op -VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op -VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +{ + VCMUL180 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 0 @2op_sz28 + VQDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op + VQDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op +} + +{ + VCMUL90 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 1 @2op_sz28 + VQRDMLADH 111 0 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op + VQRDMLSDH 111 1 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op +} + +{ + VCMUL270 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 1 @2op_sz28 + VQRDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op + VQRDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +} =20 VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 @@ -642,3 +656,8 @@ VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . = 1 . 0 ... 0 @2op_fp_size_ =20 VFMA 1110 1111 0 . 0 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp VFMS 1110 1111 0 . 1 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp + +VCMLA0 1111 110 00 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA90 1111 110 01 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA180 1111 110 10 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA270 1111 110 11 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d7f250a4455..e478408fddd 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2931,3 +2931,89 @@ DO_VFMA(vfmah, 2, float16, false) DO_VFMA(vfmas, 4, float32, false) DO_VFMA(vfmsh, 2, float16, true) DO_VFMA(vfmss, 4, float32, true) + +#define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r0, r1, e1, e2, e3, e4; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst0, *fpst1; \ + float_status scratch_fpst; \ + /* We loop through pairs of elements at a time */ \ + for (e =3D 0; e < 16 / ESIZE; e +=3D 2, mask >>=3D ESIZE * 2) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) =3D=3D 0) { = \ + continue; \ + } \ + fpst0 =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 = : \ + &env->vfp.standard_fp_status; \ + fpst1 =3D fpst0; \ + if (!(mask & 1)) { \ + scratch_fpst =3D *fpst0; \ + fpst0 =3D &scratch_fpst; \ + } \ + if (!(mask & (1 << ESIZE))) { \ + scratch_fpst =3D *fpst1; \ + fpst1 =3D &scratch_fpst; \ + } \ + switch (ROT) { \ + case 0: \ + e1 =3D m[H##ESIZE(e)]; \ + e2 =3D n[H##ESIZE(e)]; \ + e3 =3D m[H##ESIZE(e + 1)]; \ + e4 =3D n[H##ESIZE(e)]; \ + break; \ + case 1: \ + e1 =3D TYPE##_chs(m[H##ESIZE(e + 1)]); \ + e2 =3D n[H##ESIZE(e + 1)]; \ + e3 =3D m[H##ESIZE(e)]; \ + e4 =3D n[H##ESIZE(e + 1)]; \ + break; \ + case 2: \ + e1 =3D TYPE##_chs(m[H##ESIZE(e)]); \ + e2 =3D n[H##ESIZE(e)]; \ + e3 =3D TYPE##_chs(m[H##ESIZE(e + 1)]); \ + e4 =3D n[H##ESIZE(e)]; \ + break; \ + case 3: \ + e1 =3D m[H##ESIZE(e + 1)]; \ + e2 =3D n[H##ESIZE(e + 1)]; \ + e3 =3D TYPE##_chs(m[H##ESIZE(e)]); \ + e4 =3D n[H##ESIZE(e + 1)]; \ + break; \ + default: \ + g_assert_not_reached(); \ + } \ + r0 =3D FN(e2, e1, d[H##ESIZE(e)], fpst0); \ + r1 =3D FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ + mergemask(&d[H##ESIZE(e)], r0, mask); \ + mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) +#define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) + +#define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) +#define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) + +DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) +DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) +DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) +DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) +DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) +DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) +DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) +DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) + +DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) +DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) +DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) +DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) +DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) +DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) +DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) +DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d61abc6d46f..d62ed1fc295 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -856,6 +856,14 @@ DO_2OP_FP(VCADD90_fp, vfcadd90) DO_2OP_FP(VCADD270_fp, vfcadd270) DO_2OP_FP(VFMA, vfma) DO_2OP_FP(VFMS, vfms) +DO_2OP_FP(VCMUL0, vcmul0) +DO_2OP_FP(VCMUL90, vcmul90) +DO_2OP_FP(VCMUL180, vcmul180) +DO_2OP_FP(VCMUL270, vcmul270) +DO_2OP_FP(VCMLA0, vcmla0) +DO_2OP_FP(VCMLA90, vcmla90) +DO_2OP_FP(VCMLA180, vcmla180) +DO_2OP_FP(VCMLA270, vcmla270) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493502; cv=none; d=zohomail.com; s=zohoarc; b=XLVKsqOzA6wfYyR+rsR2SDl6yywL9oWqfKyLgpJQAOW+uzoVC47CaovOReN55S04y/dXKDTqFV98NoUbUawUiSMw+kSc8t6/LMi/eyInIKxrEiVshxBCpccjUpkTmPzojWCp7O+zHmCBnJi7AaIreXnTIKgC04sDu62TCJ7+zEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493502; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uIL/JKNlltw4EN6kRtqTAh5RgOnu1Wq5yQDPOpSyymg=; b=sKENnf0IlKPZI/ecKr1NkdWiW8UbKS8RCSJCJY/mVEeM5BVPzEMe7/E1j/iuXrjcys FwQbXsbpcYMDlUfNzVM99NP5ULMy4Q/PynygtZxim3RjtwsxnxkHKQPLuo9xsfRGlqVM 5VWbY1aabZeUeK1S+/b6KLgTnIYRKZQsbe5roQgV6Ln0JO+ciT4+Q7x5U94lbfEedyVm wmyRQ68fIN7lWH9N+7N16kvIO7jBvZxSrJ6Stk/GXisQ275y+CTom7FiChIz7+6h7Q5f AReUTuu9Qq/puVombpFYMfPVzBPpSg8+BrrYwuNl2tM1OSwflaZ5QHwLSiRgvovLcapt adqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uIL/JKNlltw4EN6kRtqTAh5RgOnu1Wq5yQDPOpSyymg=; b=TJq/qzlSjHlNAWuBNfVoVk2uV9w7xO0G7yRtgnpy9pApBWeeWQYfhhI0I84PZ7PQs+ ZVR+0MxF8vHW1I8LuWkBQXU/388/355L5BggToTphANszYkQ6cFsiutjMU3c3zrIMtBR LTxGQhT0souzzy3jCaELG7YCSfi7j2p4wa2KIprGQH5xO3prOxjbj5YeXqwdDLopwOPI FjQxNyAVs1Rhx13Gy9IuC/b26z23NPXuHpWuzupJPxZaxl7WzxH1VwNs2gvQF8XDVInT bcSACRFneTQMLPA9uRtVp+fRC3tlPXcnifwbrVss94J1xXeBr1+PowSVofQaC9JWjexb yKIw== X-Gm-Message-State: AOAM532g6kWI/iHywJ++jhCfIt5Vn7P3aBDb15yRKHHl6MZAG4sCTj5d QuEHmysHpYaOQk+jBJXqVZeqKMG9aVgegw== X-Google-Smtp-Source: ABdhPJwB48oca6kfd7Ru9SoiWqyEoh6USRic82gZODp0yUUbP/eApZ/TIGfEIop0ooL5BXKHVNCWeg== X-Received: by 2002:a1c:a9d2:: with SMTP id s201mr8717082wme.81.1630492623508; Wed, 01 Sep 2021 03:37:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/51] target/arm: Implement MVE VMAXNMA and VMINNMA Date: Wed, 1 Sep 2021 11:36:13 +0100 Message-Id: <20210901103653.13435-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493503627100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but the destination register must be the same as one of the source registers. We defer the decode of the size in bit 28 to the individual insn patterns rather than doing it in the format, because otherwise we would have a single insn pattern that overlapped with two groups (eg VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn patterns per insn seems clearer than a complex multilevel nesting of overlapping and non-overlapping groups. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 11 +++++++++++ target/arm/mve_helper.c | 23 +++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 42 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 73950403bc3..57ab3f7b59f 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -428,6 +428,12 @@ DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vmaxnmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxnmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vminnmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminnmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vfcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 403381eef61..b0622e1f62c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -130,6 +130,11 @@ @2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size_rev =20 +# 2-operand, but Qd and Qn share a field. Size is in bit 28, but we +# don't decode it in this format +@vmaxnma .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qd qm=3D%qm + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -199,6 +204,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op # The VSHLL T2 encoding is not a @2op pattern, but is here because it # overlaps what would be size=3D0b11 VMULH/VRMULH { + VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma = size=3D2 + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -211,6 +218,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -221,6 +230,7 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D2 VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -233,6 +243,7 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index e478408fddd..a6ad894414a 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2855,6 +2855,29 @@ DO_2OP_FP_ALL(vfabd, abd) DO_2OP_FP_ALL(vmaxnm, maxnum) DO_2OP_FP_ALL(vminnm, minnum) =20 +static inline float16 float16_maxnuma(float16 a, float16 b, float_status *= s) +{ + return float16_maxnum(float16_abs(a), float16_abs(b), s); +} + +static inline float32 float32_maxnuma(float32 a, float32 b, float_status *= s) +{ + return float32_maxnum(float32_abs(a), float32_abs(b), s); +} + +static inline float16 float16_minnuma(float16 a, float16 b, float_status *= s) +{ + return float16_minnum(float16_abs(a), float16_abs(b), s); +} + +static inline float32 float32_minnuma(float32 a, float32 b, float_status *= s) +{ + return float32_minnum(float32_abs(a), float32_abs(b), s); +} + +DO_2OP_FP_ALL(vmaxnma, maxnuma) +DO_2OP_FP_ALL(vminnma, minnuma) + #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ void HELPER(glue(mve_, OP))(CPUARMState *env, \ void *vd, void *vn, void *vm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d62ed1fc295..4d702da808d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -864,6 +864,8 @@ DO_2OP_FP(VCMLA0, vcmla0) DO_2OP_FP(VCMLA90, vcmla90) DO_2OP_FP(VCMLA180, vcmla180) DO_2OP_FP(VCMLA270, vcmla270) +DO_2OP_FP(VMAXNMA, vmaxnma) +DO_2OP_FP(VMINNMA, vminnma) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XWsZ0dwwlBs0O41NutAlFgZAHDfWz5UxtIKmvjeuAtQ=; b=Es67gE50caPeNr6pRilcZkHar8VNd+DioxcnXFGVZ79XJ7uFWV2FilD4d0t1nbXiuZ EKakJ5nhoQnMW6Q8XnqlrtpLcyTt1a0L0pZXwWjgT4Nvn+BFSweCqufYsk7WH4sanPg3 Mcgr63UXh05fYNeboWPE2xjiTxPGlim8/OOYLgjN3jZ1seSuu01N8KUF1o5bhsT1Zd8f 0vY3MxvDYso+DATwWwW4KrLcJ0+/YrT5mXkIGMzWLckQ3tJ2JsC/9CJJXCFm0HoEqR1z bMOdtvE6o1GVuTOGchz0oE100y5bSUkKZ+4aECnaxWjxpecxOzFEAxrVnfhMDlxdNkVq C3Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XWsZ0dwwlBs0O41NutAlFgZAHDfWz5UxtIKmvjeuAtQ=; b=l4Sv0yTgtzRaA4v+yLO5cKZCRgzfA/auck8nmuamvf8SaWvz/hbTfYLHX0YBo+gVwi O1/arufLLyCDygmWmm/3jH1RvjosrRizjlSTbJuOxW+tR1oH2s407uiLumBZ5QbV1ZA1 d/hyy2zFIbXQiq3+qSc9l7SFXv9ErjDfi/Cnmipu1Gnff1qKJQrCVjjAfgRI1yfQRrb+ QBX5WDnqYT169NfZWSAPrhhaZyT72jGqPhComJLdy3opZVeDGcXfIku57mwWZiaLNqg0 WdjkMV1LEXMLzOtYPnMa4ZQ8XkMba8NpoJykFaPys3sOjUvi/Fd9MCusceQfZRK1jwWi 3+Eg== X-Gm-Message-State: AOAM531SzR5YTNQy+CaM8XVXGdzB/z/++/HPIQqOcDV7bPvrNKkB/UFW zYsKt7+uWWwMyYQRNrEYwQiG6+Vq4GitXA== X-Google-Smtp-Source: ABdhPJwDXPHJZ4agxrvP1ToFRuGJWFm1xjnbNikzq7fa3+nUpDsjKZ3YWlhdAoCgB7pHCsRt5ygqhA== X-Received: by 2002:adf:d191:: with SMTP id v17mr24157291wrc.345.1630492624449; Wed, 01 Sep 2021 03:37:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/51] target/arm: Implement MVE scalar fp insns Date: Wed, 1 Sep 2021 11:36:14 +0100 Message-Id: <20210901103653.13435-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493103428100001 Content-Type: text/plain; charset="utf-8" Implement the MVE scalar floating point insns VADD, VSUB and VMUL. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 9 +++++++++ target/arm/mve.decode | 27 +++++++++++++++++++++------ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 20 ++++++++++++++++++++ 4 files changed, 85 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 57ab3f7b59f..091ec4b4270 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -800,3 +800,12 @@ DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarw, TCG_CALL_NO_WG,= void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfsub_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfmul_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index b0622e1f62c..5ba8b6deeaa 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -31,6 +31,8 @@ %2op_fp_size 20:1 !function=3Dneon_3same_fp_size # VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit %2op_fp_size_rev 20:1 !function=3Dplus_1 +# FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit +%2op_fp_scalar_size 28:1 !function=3Dneon_3same_fp_size =20 # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 @@ -135,6 +137,9 @@ @vmaxnma .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qd qm=3D%qm =20 +@2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \ + qd=3D%qd qn=3D%qn size=3D%2op_fp_scalar_size + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -471,10 +476,17 @@ VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . = 100 .... @2scalar VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar } =20 -VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar -VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar -VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar -VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +{ + VADD_fp_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 100 .... @2op_fp_sc= alar + VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar + VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar +} + +{ + VSUB_fp_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 100 .... @2op_fp_sc= alar + VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar + VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +} =20 { VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar @@ -490,8 +502,11 @@ VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 1= 00 .... @2scalar size=3D%size_28 } =20 -VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar -VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar +{ + VMUL_fp_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 110 .... @2op_fp_sc= alar + VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar + VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar +} =20 # The U bit (28) is don't-care because it does not affect the result VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a6ad894414a..b49975fdc01 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3040,3 +3040,38 @@ DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) + +#define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE r, m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_2OP_FP_SCALAR_ALL(OP, FN) \ + DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ + DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) + +DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) +DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) +DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4d702da808d..bc4b3f840a0 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -960,6 +960,26 @@ static bool trans_VQDMULLT_scalar(DisasContext *s, arg= _2scalar *a) return do_2op_scalar(s, a, fns[a->size]); } =20 + +#define DO_2OP_FP_SCALAR(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ + { \ + static MVEGenTwoOpScalarFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2op_scalar(s, a, fns[a->size]); \ + } + +DO_2OP_FP_SCALAR(VADD_fp_scalar, vfadd_scalar) +DO_2OP_FP_SCALAR(VSUB_fp_scalar, vfsub_scalar) +DO_2OP_FP_SCALAR(VMUL_fp_scalar, vfmul_scalar) + static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenLongDualAccOpFn *fn) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493557; cv=none; d=zohomail.com; s=zohoarc; b=G0UpFHV4ftw/OimVUQpqNpaX5jkZ7fWC7XiRuoG5H31ETnwbH6cANRduWhtRIy/BtZQFr8L3/hTXoZg3okaaFRylzyBdmRUmaFMH7jH1r4aMsEh6bEK9P8g9hft8GJe1wOH4+OHsY5u9EElgiU6iiTJmHJ/BHGpAGfoNoASEasE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493557; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pxVLqK6kXQ+5nBuyyoif5i95RPPyNrsG2guWRQSwNtQ=; b=NpBCJ+Dy7OwJpC0vCLl3hQS8mHaBfgzP2Yqylc1uaCzF8lxbgBAJlLNpJXSVpJH0jObIHGyISTRdsYRdMYxzPp53AzTHYXVWSmffR7tan6vk7jHssJXBM3aBChnfpEQlrDsmx1Xv4Of4VIIdVAa+U3XKOnNid4KX8Q1JXLzPLqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493557592594.1201727037376; Wed, 1 Sep 2021 03:52:37 -0700 (PDT) Received: from localhost ([::1]:57282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNrA-000116-Ft for importer@patchew.org; Wed, 01 Sep 2021 06:52:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcC-0006uh-GU for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:08 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcA-0005hV-9S for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:08 -0400 Received: by mail-wr1-x42f.google.com with SMTP id m9so3795078wrb.1 for ; Wed, 01 Sep 2021 03:37:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pxVLqK6kXQ+5nBuyyoif5i95RPPyNrsG2guWRQSwNtQ=; b=QmnTQZM7PhUo/zzQpqMERxtCB2womoDELdjtP2wgtwuJ9ZdFoxABvNslLd+PTjDn3Z mnNDaGoYjvFcxNKttQUA7bjLv/3EKEd7b0XJ/QRo30ZwYlTztsbfJKwPl16JJs8QapSM Mk+dh/ganwcW+X1rpxFgvODN3AiECQQiY9gbLf4Rn9jEbNo6mUCi1BpLmLbnch/F4iwI G02cF1sHCoS7Hrv+cmg0aH6MLAxIzc3u5bTmIC1db7Vb8CfYMnbb00q2CfU9Nwz6AAvP V4FjyvmnGU/AAPKL4wdyIWI/wmIjiF+CeLHeqogJzl4isCieGjXF9mOJu+8MOwgM7trl xy1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pxVLqK6kXQ+5nBuyyoif5i95RPPyNrsG2guWRQSwNtQ=; b=KLMUIlf4DKQQcSzYebMlit1PTVa91itW/b700z9wLB4dWUYDbVz/lx0KIz6Wk9dg4+ VGCKcUjDna0tTM4S7TvKiTH6zqylYvGLiNlNekFr62o5o2myUGj0QQRkQW5Eg84KLWMN 4f7wenKg+y3LyJWDCp2tMtqqEFj3pBS9PX3a7fkb033FGb53LddTuzNgMd5LDCYm5e17 x2mh/DKMiAvHm70Vys/J6Q+2RCMB3X2KX8VhRnETSiAIP4/LVfYLBKdlPpxxf7I+jzn7 RDRwUNMm6CHNhmnvB4aIYDJtDE2ZFl2TN1xX7xPafoBQqJM/OO5tA7GYjOlL0jPk1eVC 1Hug== X-Gm-Message-State: AOAM530yG3DxSPo43MXICGd8WFQFEgW8Q7UdIxEqtebAoi0e9FimIBF5 4+LVlhQa2Lro5wf4tv0EgI9QHsB1Z3499w== X-Google-Smtp-Source: ABdhPJy3QBzm3AFXJZXbDP9zkMVktRIFfquUQXYSawngJMur/1w4k0aTgpIwhiHp60Hk2OT2xs35iA== X-Received: by 2002:a5d:4647:: with SMTP id j7mr37298274wrs.149.1630492625002; Wed, 01 Sep 2021 03:37:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/51] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS Date: Wed, 1 Sep 2021 11:36:15 +0100 Message-Id: <20210901103653.13435-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493558824100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp-with-scalar VFMA and VFMAS insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 14 +++++++++++--- target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 091ec4b4270..cb7b6423239 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -809,3 +809,9 @@ DEF_HELPER_FLAGS_4(mve_vfsub_scalars, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vfmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfmul_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfma_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vfma_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) + +DEF_HELPER_FLAGS_4(mve_vfmas_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfmas_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 5ba8b6deeaa..d2bd6815bc3 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -508,9 +508,17 @@ VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 1= 00 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar } =20 -# The U bit (28) is don't-care because it does not affect the result -VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar -VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar +{ + VFMA_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 100 .... @2op_fp_sc= alar + # The U bit (28) is don't-care because it does not affect the result + VMLA 111 - 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar +} + +{ + VFMAS_scalar 111 . 1110 0 . 11 ... 1 ... 1 1110 . 100 .... @2op_fp_sc= alar + # The U bit (28) is don't-care because it does not affect the result + VMLAS 111 - 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar +} =20 VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b49975fdc01..36f0910b856 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3075,3 +3075,40 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) + +#define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE r, m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +/* VFMAS is vector * vector + scalar, so swap op2 and op3 */ +#define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) +#define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) + +/* VFMA is vector * scalar + vector */ +DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) +DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) +DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) +DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index bc4b3f840a0..3627ba227f2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -979,6 +979,8 @@ static bool trans_VQDMULLT_scalar(DisasContext *s, arg_= 2scalar *a) DO_2OP_FP_SCALAR(VADD_fp_scalar, vfadd_scalar) DO_2OP_FP_SCALAR(VSUB_fp_scalar, vfsub_scalar) DO_2OP_FP_SCALAR(VMUL_fp_scalar, vfmul_scalar) +DO_2OP_FP_SCALAR(VFMA_scalar, vfma_scalar) +DO_2OP_FP_SCALAR(VFMAS_scalar, vfmas_scalar) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenLongDualAccOpFn *fn) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493331; cv=none; d=zohomail.com; s=zohoarc; b=S5EqUWi6jLwG+Nhf6hxDSCsDKyPgijZfllagfMzp///bvBK6Lcvc4GOd9ChUXK6jaugkFW6rqK9LG5MlhWxuxXOV2Fps1U3P7txQ4HYgnWo8H0dgjv8x5sSPm2si+WVZJ4B/qM90pQjIb+JG2r6f+9Sybj2HB5ArGwbSzh26Bo8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493331; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=R7ZUJ9JEib+4oRPUW25BZ9uRGVU+5zucDssNPCnJUaVolMUZYKlJiL00q7vc7TLW/DvlcVzNBXeeUoa/MElwKe8iq8XWQK4k6PmFPk0pTNWdlbh8pulp6jcDcQFOy5vaaHKGpZ8vhra+dgpe9475OgKAlg2WCjCIBCUTyUaX978= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493331929848.0875074623879; Wed, 1 Sep 2021 03:48:51 -0700 (PDT) Received: from localhost ([::1]:45254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNnW-0001P6-Hn for importer@patchew.org; Wed, 01 Sep 2021 06:48:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcF-00071F-Lp for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:13 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcA-0005iC-Vz for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:11 -0400 Received: by mail-wr1-x431.google.com with SMTP id q14so3762879wrp.3 for ; Wed, 01 Sep 2021 03:37:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=wKr2lax2EPFSWl/D4FRw94e5QxwF4TQLedfhHdYlEVkmJ8xmP2lCNpfgHDtT2l7fX6 UtpZby4CmRkSn84InKZcTV/YBc/DR5RB8pqlkVqPQxAQ7CgpQmFYLcAYDERBMqhpnwwK RYW3GZ7vk9q1GrxBVn+Ucc61bCtQDWM9cG2NKiXhLojW+LW51Drlpy0FKWMmdppef49S wLjRzSqDm9NTYjHRQpcpGrUvJUxJBpaPfEd4wdxGUXgf2nt1LD960uSyQ7pIUy7IQwai so46L7k89CEIWo6LdKDGuu1qYKgSdgoHPeqEJZ+64MBnwXBy70Dz6r8DWcXEU5rW8800 2LWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=oECz8zNcDoHMFeWa+aH03Jo7+kBHKcWGqaV7mUTnBKOSV586wVJGGhD5XxYHc7R0yg I6MUtUobGL7S/Qs0gFvS4TAyHqUsGidxAAztCCqpDqLN5gY5NEboAU7cR8Rf7MiZVczZ jLivopQ8JAPS4DXZMQLzs1eptdspxVomKIIioIHzMgR6hLFtZivuLQoorQXFNAd44um5 gKHFu8qzGKFeAGUljlizHkHXuHL3voCbjrKi9eFZ6aB1Gt40nDmnNP4Whu6wXzXregtJ 9BslhQMElxWArHVS/u3L+AQO56z1VA3ecWD/MevdXAgXc2J1lWIa90GQMxNrDZdjjf7M DdUQ== X-Gm-Message-State: AOAM531sKGQ3/V6Xem57vE323oF4J/KIB0MhGAxkUefrcJb+VeyBp1M/ Hv3exiQ1GdqYVhZ+qWhZ2J9Yrulcew6zzw== X-Google-Smtp-Source: ABdhPJyZV0KhTg0n8jZgc2Po4fLbG/edqYTNCKxuCJKFRdXn/P4paFV/4UfwxHtCLKXs4w5llXDbfg== X-Received: by 2002:adf:82a8:: with SMTP id 37mr37514525wrc.123.1630492625578; Wed, 01 Sep 2021 03:37:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode Date: Wed, 1 Sep 2021 11:36:16 +0100 Message-Id: <20210901103653.13435-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493332540100001 Content-Type: text/plain; charset="utf-8" In commit a777d6033447a we added an assertion to parts_silence_nan() that prohibits calling float*_silence_nan() when in default-NaN mode. This ties together a property of the output ("do we generate a default NaN when the result is a NaN?") with an operation on an input ("silence this input NaN"). It's true that most of the time when in default-NaN mode you won't need to silence an input NaN, because you can just produce the default NaN as the result instead. But some functions like float*_maxnum() are defined to be able to work with quiet NaNs, so silencing an input SNaN is still reasonable. In particular, the upcoming implementation of MVE VMAXNMV would fall over this assertion if we didn't delete it. Delete the assertion. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 12467bb9bba..f2ad0f335e6 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -198,7 +198,6 @@ static void parts128_default_nan(FloatParts128 *p, floa= t_status *status) static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) { g_assert(!no_signaling_nans(status)); - g_assert(!status->default_nan_mode); =20 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493783; cv=none; d=zohomail.com; s=zohoarc; b=O4/9k/0i6a7RiUtOiG0g4ZcphlHRP2T4jY7qF1c4erCk2JjlctN+1dXWsYJ53YjHNhphXUS8kow5DGnpoAgOjv/STzzasbWqePbLYWcLjWmTEGA4Pu3oEvohFwdZd0cFCb2BYdP36L7iLiATnYlWgehaXNlj84R3AONnTp2DE5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493783; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L4PKaHtv8gBbsF0q/KRkX5988ST0a4oNQuaOXRtk64c=; b=d7Ad5zWMaXPIa7mZOgVSJSilQt2+iURr0bWNzWdnUEFUHdVeMlknv2l7vP+AsIMgVCTo9wekBV+1NR/VYGkDsRc/NA+2mw0dw/mbwjC+auGDeinB0cSJBoaohdlXkZeEkDoDSV0khgGydbiLMvN0NXHLo1zaqrFWFgDCHfPbdDc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493783038151.92481985651955; Wed, 1 Sep 2021 03:56:23 -0700 (PDT) Received: from localhost ([::1]:37416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNun-0006aK-VX for importer@patchew.org; Wed, 01 Sep 2021 06:56:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcE-0006yF-FD for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:10 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:46641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcB-0005jH-J3 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:10 -0400 Received: by mail-wm1-x332.google.com with SMTP id m25-20020a7bcb99000000b002e751bcb5dbso1564125wmi.5 for ; Wed, 01 Sep 2021 03:37:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=L4PKaHtv8gBbsF0q/KRkX5988ST0a4oNQuaOXRtk64c=; b=m2YEMVlLUBrDynVj4yho5kd2zIwBDqHg08aen8OB52JI2YqzGP/V+yT8nJh746ooW9 1FUGnYt0LQQU0vH9G6FAQ60HnKKcPuKusBCMoTIhf/QkLOXuvM4xFLSHTUcnF9dpvLvo FnJOMA5W4X2mw2S02QVXrZ9unIo5ZhuNj6wxOjUkooaxX+dttttEmLaLK/i5khpwEqox +j0mPuLt9/e3vlBeSVddoaLuy3efd6LD9WN6vcyYJHBsNNt3TyHVJ/cdwosLtRDIbt6h +gO0QOmhzuPM/E2aW4VJLKCz5CZfhTVnD8PYq0cEWV9e4+yVJ63hah8cCux7DYuECpVA fyhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L4PKaHtv8gBbsF0q/KRkX5988ST0a4oNQuaOXRtk64c=; b=qtN3Gwe46tqLnH+HBU898cND15ymxt/V88qJ5Ao6yBlE1jBZvAsZglMu2JCRcV1bk5 Go98GOrPip6v97ANwUvWhU/gXbwOhVprXNkCqocCX/MRSpEDtMlyfYmmgLlD1XO3wKbJ CYvF3p+XOis0LMKuN+kyReansR3+NFuCYSgSB+uwHlVrWEGVJK3MKeZx06nkX1fE0uPt l7/zUJAezUYJS/nHKno0M0f8FzFWah4KZ3rH/+vvqAUhH9cQZTb1NSkfbllyEQeJURcS Fm149fFGz4N0igHAvuosc8LAXSSesH5navw+BrjrXsf6U0IJqGERWsmXI1843vUCnlOx 8HkA== X-Gm-Message-State: AOAM532Bvg5bKFDxjHSfKgLm195iAULZrH6t4P6BtfjT9XJzzPW1QXWr aQqkpBlqq2x0a9/oEmaOLeHa7RmMtIBKDA== X-Google-Smtp-Source: ABdhPJy45e2CPB7NnHlCR706YM+P9TQbOGRXLjYG5dKKVGOHgQl0H6DSt0vWyqxTWcITwOnIP5L/UQ== X-Received: by 2002:a1c:3b56:: with SMTP id i83mr8412186wma.115.1630492626172; Wed, 01 Sep 2021 03:37:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/51] target/arm: Implement MVE FP max/min across vector Date: Wed, 1 Sep 2021 11:36:17 +0100 Message-Id: <20210901103653.13435-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493783508100003 Content-Type: text/plain; charset="utf-8" Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These calculate the maximum or minimum of floating point elements across a vector, starting with a value in a general purpose register and returning the result there. The pseudocode silences a possible SNaN in the accumulating result on every iteration (by calling FPConvertNaN), but we do it only on the input ra, because if none of the inputs to float*_maxnum or float*_minnum are SNaNs then the result can't be an SNaN. Note that we can't use the float*_maxnuma() etc functions we defined earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute value of the starting general-purpose register value, which could be negative. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 12 +++++++++++ target/arm/mve.decode | 32 +++++++++++++++++++++------ target/arm/mve_helper.c | 44 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 20 +++++++++++++++++ 4 files changed, 102 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index cb7b6423239..47fd18dddbf 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -614,6 +614,18 @@ DEF_HELPER_FLAGS_3(mve_vminavb, TCG_CALL_NO_WG, i32, e= nv, ptr, i32) DEF_HELPER_FLAGS_3(mve_vminavh, TCG_CALL_NO_WG, i32, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vminavw, TCG_CALL_NO_WG, i32, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vmaxnmvh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxnmvs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vminnmvh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminnmvs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vmaxnmavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxnmavs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vminnmavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminnmavs, TCG_CALL_NO_WG, i32, env, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d2bd6815bc3..a46372f8c77 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -137,6 +137,10 @@ @vmaxnma .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qd qm=3D%qm =20 +# Here also we don't decode the bit 28 size in the format to avoid +# awkward nested overlap groups +@vmaxnmv .... .... .... .... rda:4 .... .... .... &vmaxv qm=3D%qm + @2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \ qd=3D%qd qn=3D%qn size=3D%2op_fp_scalar_size =20 @@ -440,17 +444,33 @@ VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0= . 0 ... 1 @vmladav_nosz VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_n= osz =20 { - VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv - VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv - VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv - VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv + [ + VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + ] + [ + VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv + ] VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_n= osz VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz } =20 { - VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv - VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + [ + VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + ] + [ + VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + ] VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_n= osz VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz } diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 36f0910b856..52e5a8f2a8b 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3112,3 +3112,47 @@ DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float= 16_muladd) DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) + +/* Floating point max/min across vector. */ +#define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ + uint32_t ra_in) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *m =3D vm; \ + TYPE ra =3D (TYPE)ra_in; \ + float_status *fpst =3D (ESIZE =3D=3D 2) ? \ + &env->vfp.standard_fp_status_f16 : \ + &env->vfp.standard_fp_status; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + if (mask & 1) { \ + TYPE v =3D m[H##ESIZE(e)]; \ + if (TYPE##_is_signaling_nan(ra, fpst)) { \ + ra =3D TYPE##_silence_nan(ra, fpst); \ + float_raise(float_flag_invalid, fpst); \ + } \ + if (TYPE##_is_signaling_nan(v, fpst)) { \ + v =3D TYPE##_silence_nan(v, fpst); \ + float_raise(float_flag_invalid, fpst); \ + } \ + if (ABS) { \ + v =3D TYPE##_abs(v); \ + } \ + ra =3D FN(ra, v, fpst); \ + } \ + } \ + mve_advance_vpt(env); \ + return ra; \ + } \ + +#define NOP(X) (X) + +DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) +DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) +DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) +DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) +DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) +DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) +DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) +DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 3627ba227f2..4e2aa2cae2d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1806,6 +1806,26 @@ DO_VMAXV(VMINV_S, vminvs) DO_VMAXV(VMINV_U, vminvu) DO_VMAXV(VMINAV, vminav) =20 +#define DO_VMAXV_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ + { \ + static MVEGenVADDVFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vmaxv(s, a, fns[a->size]); \ + } + +DO_VMAXV_FP(VMAXNMV, vmaxnmv) +DO_VMAXV_FP(VMINNMV, vminnmv) +DO_VMAXV_FP(VMAXNMAV, vmaxnmav) +DO_VMAXV_FP(VMINNMAV, vminnmav) + static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) { /* Absolute difference accumulated across vector */ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494207; cv=none; d=zohomail.com; s=zohoarc; b=ixrfg287hPwAU73jY3wDMKgsY7IlFYxA6vCXxNoWtM/XM4n1mSrrwZcdFeCPs4HPhXVAQMiAUyQX7Bt/bQ+Jl1wiif+29kIwu09AhXJSMlaR9UgoZI4mkfYOLxQE3wP5uke46xuqclZKayIj1pkZpjZhDEVpxTcrX2HSaxFIxTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494207; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qAXO2dMo/ihCKB/mnPoBc/r50/KVn+K0yjv9p814RMk=; b=iUls2CawnteY0uGXhiV2vyCFHyC/PAsvsveKNtSk5BAqmg1CIe7qaKd1guB2wlOg9anFDarWgpWoBNZ3gznRBM1pNcoq9EfrSBT0SFbHY+fKr3mjzITT8tXK9SltwYpEYiqTg+vw09jGdK4V0uHqEBdq6ifNiKVly59inMyF3Kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494207419816.9118243444495; Wed, 1 Sep 2021 04:03:27 -0700 (PDT) Received: from localhost ([::1]:56358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO1e-0002eq-8p for importer@patchew.org; Wed, 01 Sep 2021 07:03:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcK-00076O-4E for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:17 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:38582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcC-0005kA-I3 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:15 -0400 Received: by mail-wr1-x434.google.com with SMTP id u16so3750253wrn.5 for ; Wed, 01 Sep 2021 03:37:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qAXO2dMo/ihCKB/mnPoBc/r50/KVn+K0yjv9p814RMk=; b=PgO9byjIlzXHBcIRUEMdEx0HGx1pmqU0cZdahAgQslE0GJI1qUtpclgPe5FIihxXJz nTACNUNPS49nIhN5DacThaNwwoH0KHVQNKDq7uukJshFNce4Xo2OtumZToPXViQJO/dl wwwfr1y8YpktR9he8l3Wl+URPXBE4fj7DXiejK2KHj6/vGDEaBsPOFEuhWwzK5YouYu5 0KJsjgnbylKSiLMa1bQeQ3WFsO1tGHXsvLSg2jlYJzsak0U5o3/uFnBuKS2ShJmU7q59 OlKzNTzybS2rlVYDHjFVLzWLuORMDEiw0dzDP8xYYsq/4k1VyRugDpWc6isTErXg7xf0 AC5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qAXO2dMo/ihCKB/mnPoBc/r50/KVn+K0yjv9p814RMk=; b=ezGHno/8q27e1kYKk3eq5+0BvKZwf2iTlE/ae3ZSWpj5A3wyKbjGhzk7brtSqgLanl GVPwekhQeyFYIuOaLCmxKEVNgMgLx3lZ9kAs50m9AVHZbTwiDF9hCz32+3G3sM+fvEL1 BqX40CgpJF7bfHusK+vrM1wwDRwf1bgd5O83JK6JLNCg5EmtPdw/EX2aIp+OHtt0PGLF avH+a03QOZ1uAvQnHJ7PWdwoL0qMB8O21rZqS6P7DY4Qt3RSj9w6xXKxRu1prpu2b9ul AAn54B8dC6CViWQGQQNmHOWzXrFf5ZuwbOJKT5QPlrB0XV5qUXj1fbiMATSNhHoaPox6 dGAw== X-Gm-Message-State: AOAM533LUT2QGxXP4y/u+rmi6ab6Ee2lg+qTiKy+RhZmu8/Xk0BaoiAe ukGhpfzzwso5c+JG7YsDHZ7DJgaWYIq1/w== X-Google-Smtp-Source: ABdhPJzjBWDoi2L4uD+ZRW1DiMnVfzvUmQyLLfb25zWkfreb15yMEza8W814kNKWc38wZRIq69i8Ag== X-Received: by 2002:a5d:4591:: with SMTP id p17mr36924769wrq.57.1630492627048; Wed, 01 Sep 2021 03:37:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/51] target/arm: Implement MVE fp vector comparisons Date: Wed, 1 Sep 2021 11:36:18 +0100 Message-Id: <20210901103653.13435-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494209654100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp vector comparisons VCMP and VPT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 18 +++++++++++ target/arm/mve.decode | 39 +++++++++++++++++++---- target/arm/mve_helper.c | 64 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 22 +++++++++++++ 4 files changed, 137 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 47fd18dddbf..0c15c531641 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -813,6 +813,24 @@ DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG,= void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vfcmpeqh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpeqs, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpneh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpnes, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpgeh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpges, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmplth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmplts, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpgth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index a46372f8c77..49b7ef35937 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -124,6 +124,9 @@ @vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \ mask=3D%mask_22_13 =20 +@vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ + qm=3D%qm size=3D%2op_fp_scalar_size mask=3D%mask_22_13 + @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 @2op_fp .... .... .... .... .... .... .... .... &2op \ @@ -671,17 +674,41 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1= 100 rdm:4 qd=3D%qd # Comparisons. We expand out the conditions which are split across # encodings T1, T2, T3 and the fc bits. These include VPT, which is # effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero. -VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp -VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp +{ + VCMPEQ_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp_fp + VCMPEQ 111 1 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp +} + +{ + VCMPNE_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp_fp + VCMPNE 111 1 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp +} + +{ + VCMPGE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp_fp + VCMPGE 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp +} + +{ + VCMPLT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp_fp + VCMPLT 111 1 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp +} + +{ + VCMPGT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp_fp + VCMPGT 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp +} + +{ + VCMPLE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp= _fp + VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp +} + { VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp } -VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp -VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp -VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp -VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp =20 { VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 52e5a8f2a8b..07a1ab88814 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3156,3 +3156,67 @@ DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_= maxnum) DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) + +/* FP compares; note that all comparisons signal InvalidOp for QNaNs */ +#define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ + { \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + bool r; \ + for (e =3D 0; e < 16 / ESIZE; e++, emask <<=3D ESIZE) { = \ + if ((mask & emask) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & (1 << (e * ESIZE)))) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +/* + * Some care is needed here to get the correct result for the unordered ca= se. + * Architecturally EQ, GE and GT are defined to be false for unordered, but + * the NE, LT and LE comparisons are defined as simple logical inverses of + * EQ, GE and GT and so they must return true for unordered. The softfloat + * comparison functions float*_{eq,le,lt} all return false for unordered. + */ +#define DO_GE16(X, Y, S) float16_le(Y, X, S) +#define DO_GE32(X, Y, S) float32_le(Y, X, S) +#define DO_GT16(X, Y, S) float16_lt(Y, X, S) +#define DO_GT32(X, Y, S) float32_lt(Y, X, S) + +DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq) +DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq) + +DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq) +DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq) + +DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16) +DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32) + +DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16) +DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32) + +DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16) +DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32) + +DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16) +DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4e2aa2cae2d..da14a6f790e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1758,6 +1758,28 @@ DO_VCMP(VCMPLT, vcmplt) DO_VCMP(VCMPGT, vcmpgt) DO_VCMP(VCMPLE, vcmple) =20 +#define DO_VCMP_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ + { \ + static MVEGenCmpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vcmp(s, a, fns[a->size]); \ + } + +DO_VCMP_FP(VCMPEQ_fp, vfcmpeq) +DO_VCMP_FP(VCMPNE_fp, vfcmpne) +DO_VCMP_FP(VCMPGE_fp, vfcmpge) +DO_VCMP_FP(VCMPLT_fp, vfcmplt) +DO_VCMP_FP(VCMPGT_fp, vfcmpgt) +DO_VCMP_FP(VCMPLE_fp, vfcmple) + static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) { /* --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630492911; cv=none; d=zohomail.com; s=zohoarc; b=nQ+h7Xdm+4skT8W/X04PbF/6Lg4GcXPInjKxZzTQrJkvJomA6200reGXTeRAC0HLhuqYC5NsF9il6Tubjkk4/pVyUhGRFoKx8/kMhfaPj4niDmFwS4piySfnNiru9qpYhg6iE6WFkiwr+VDh+YWZU0vWJfwvzDIaj8UUMuewzo4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630492911; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v5pPz7UFQ9KY/Khb5OGJwbmVXcY4XGfYcfxtdVJ4joA=; b=NJ3AKAtcwqn5esPmKBWkxWdCFky3yfI7Fq2nGMK4fg0zA3CBVRyMAm2uKVZBw03rJfuZj97+64nhPBrWRn1pGl1c4gax9QrT+EHTgkS60F5lb+sgINjTBogS9iWULTIaLN9Cb81la1CCXBh1c9zeoIkchCwzZ7FpggQqUAu5Rco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630492911475396.45928351637315; Wed, 1 Sep 2021 03:41:51 -0700 (PDT) Received: from localhost ([::1]:56158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNgk-0006iv-Ca for importer@patchew.org; Wed, 01 Sep 2021 06:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcF-000704-FX for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:11 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33548) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcD-0005kc-By for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:11 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d26so3849560wrc.0 for ; Wed, 01 Sep 2021 03:37:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v5pPz7UFQ9KY/Khb5OGJwbmVXcY4XGfYcfxtdVJ4joA=; b=G2FfmPAp38pdx4wiK2aMWBzx3AuW+CJjPAU76FgsJthEXjiQARyurch7HC0u0aUmzU +9cFWTlTMIdCmSS6+zWQm/j1hEPSt1WFW9C5KtcOKddGLLYJv7IruhdpS16OEn2sJcDC qfKjg2in9FPnmsnikaxuJ4BYrQaEuABplGXIAtVXE7eF3saq+qe7qW9YFKrzVsutixOF 1kBFn/FHYbO3u41+bz+I36CDSBQkY+60bloWn8sDDCbkcWiN4ojFjb88GR3xGzLrKvzl eWjdbJV0eD4z2g+CXgbKOX/qBHNNsPGiiUUXwx5qupd5Cgf0BDrgZ/J6Y5vT7VFRxXqt g03g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v5pPz7UFQ9KY/Khb5OGJwbmVXcY4XGfYcfxtdVJ4joA=; b=KtaeAauAz63c1O8RHQyyGuKAN6W/2tKgIIQY9XQ0r/AiRmwbMF/LHkcSuZfrGG/I5A 4pPgnr2Euyv7kpnqcfJeZwhbjHPavdkuu7Dyv1hC9FvhbGnVL57fiXXWaOxBV72heiLF OudbK17A5SWz1UEYVK1XxkXTJmzvJltf6BHRcUxGhISBUY97E+zuy3Y3U46Nl2HuCuAI 0Gdex3jfCD5WdVx+DTudLRSf3Y0HROMmt+YSt7HElLa1hIqp7cQIW2DtPM1WULsoYE5c cMXBveIdgbi7/dBA9aQNYy0UJkHl+Sm7X1qtDZ62lMfAYXVhNo2VG6xhzHczGCUpI7ax VD0Q== X-Gm-Message-State: AOAM5311GWGKv7o4Cjs3bdN0QSXjC3uyBnTugdLCYsauTvx3L5ASjEDW bG4+GDvBpEfMzUtHLIab1uW+rH8CLmyo9w== X-Google-Smtp-Source: ABdhPJyiqBrqeVa7C6cDgK18FaGMJuw7h5pHIjqTfQrNhGBUSoRJhu4F1kdHXhmKv+TM3FbXk6g4dg== X-Received: by 2002:adf:e809:: with SMTP id o9mr36900062wrm.425.1630492627748; Wed, 01 Sep 2021 03:37:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/51] target/arm: Implement MVE fp scalar comparisons Date: Wed, 1 Sep 2021 11:36:19 +0100 Message-Id: <20210901103653.13435-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630492912246100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp scalar comparisons VCMP and VPT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 18 +++++++++++ target/arm/mve.decode | 61 +++++++++++++++++++++++++++++-------- target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++-------- target/arm/translate-mve.c | 14 +++++++++ 4 files changed, 131 insertions(+), 24 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 0c15c531641..9ee841cdf01 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -831,6 +831,24 @@ DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void,= env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmple_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 49b7ef35937..f1b8afb4778 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -127,6 +127,11 @@ @vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ qm=3D%qm size=3D%2op_fp_scalar_size mask=3D%mask_22_13 =20 +# Bit 28 is a 2op_fp_scalar_size bit, but we do not decode it in this +# format to avoid complicated overlapping-instruction-groups +@vcmp_fp_scalar .... .... .... qn:3 . .... .... .... rm:4 &vcmp_scalar \ + mask=3D%mask_22_13 + @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 @2op_fp .... .... .... .... .... .... .... .... &2op \ @@ -400,8 +405,10 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 = 0 1 0000 @vdup size=3D2 VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup } { - VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup - VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup + VCMPGT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_s= calar size=3D2 + VCMPLE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_s= calar size=3D2 + VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup + VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup } =20 # multiply-add long dual accumulate @@ -480,8 +487,17 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 = . 0 ... 1 @vmladav_nosz =20 # Scalar operations =20 -VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar -VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +{ + VCMPEQ_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VCMPNE_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar +} + +{ + VCMPLT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VCMPGE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +} =20 { VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar @@ -711,17 +727,38 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1= 100 rdm:4 qd=3D%qd } =20 { - VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 - VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask= _22_13 - VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_sca= lar + VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 + VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mas= k_22_13 + VCMPEQ_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0100 .... @vcmp_scalar } -VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_sca= lar + +{ + VCMPNE_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1100 .... @vcmp_scalar +} + +{ + VCMPGT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_sc= alar size=3D1 + VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0110 .... @vcmp_scalar +} + +{ + VCMPLE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_sc= alar size=3D1 + VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1110 .... @vcmp_scalar +} + +{ + VCMPGE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0100 .... @vcmp_scalar +} +{ + VCMPLT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1100 .... @vcmp_scalar +} + VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_sca= lar VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_sca= lar -VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_sca= lar -VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar -VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar -VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar =20 # 2-operand FP VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 07a1ab88814..891926c124d 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3191,6 +3191,44 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_= minnum) mve_advance_vpt(env); \ } =20 +#define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + uint32_t rm) \ + { \ + TYPE *n =3D vn; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + bool r; \ + for (e =3D 0; e < 16 / ESIZE; e++, emask <<=3D ESIZE) { = \ + if ((mask & emask) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & (1 << (e * ESIZE)))) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +#define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) + /* * Some care is needed here to get the correct result for the unordered ca= se. * Architecturally EQ, GE and GT are defined to be false for unordered, but @@ -3203,20 +3241,20 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32= _minnum) #define DO_GT16(X, Y, S) float16_lt(Y, X, S) #define DO_GT32(X, Y, S) float32_lt(Y, X, S) =20 -DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq) -DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq) +DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) +DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) =20 -DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq) -DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq) +DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) +DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) =20 -DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16) -DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32) +DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) +DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) =20 -DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16) -DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32) +DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) +DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) =20 -DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16) -DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32) +DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) +DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) =20 -DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16) -DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32) +DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) +DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index da14a6f790e..e8a3dec6683 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1771,6 +1771,20 @@ DO_VCMP(VCMPLE, vcmple) return false; \ } \ return do_vcmp(s, a, fns[a->size]); \ + } \ + static bool trans_##INSN##_scalar(DisasContext *s, \ + arg_vcmp_scalar *a) \ + { \ + static MVEGenScalarCmpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##_scalarh, \ + gen_helper_mve_##FN##_scalars, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vcmp_scalar(s, a, fns[a->size]); \ } =20 DO_VCMP_FP(VCMPEQ_fp, vfcmpeq) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oPfkL3Cu9SyMP90dfWKppbYc+M39u0zDP8KCQ6gbCQY=; b=mhlCZKiVnADvhHvbJ/4F4+R7Ho+wcsdaZWys/OLwUephcsuPl0wf1CD0nWJE0c8o2a vjoZcsmzFU+cIXbK3xpwkIsSZhWn2vyIOjvlC7BM7XkWYL2NMyiieJYhA8MODMOCgbYj eCACoA/cS/he5fFycRiJEsGWJi/+MQX5WxLSDjSssTmV5hv7dal+8ll58w9WcsNxFjLd qSYbVoP9+fwUjTGMOEjtnPnTwGyglUGL9xMjoWUTDuM/QSRDyTWOPs17lLbTB2rskHMW E4qnEswRzt0R9GFixGVz4H2e5RzpCcKCGtdJv/0w+9PaVH4vowqPZ2LiYJc9rKkPooY7 nqBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oPfkL3Cu9SyMP90dfWKppbYc+M39u0zDP8KCQ6gbCQY=; b=QI1TowNziX3hiHHwi3LU0rKF5BL78T33fWravkWeFuU66xak1AKeJv6CBiGB6JNpuI 8WuxNbAaO2ZxUeFqirAGxgdxASJYbhmvAeF6B4ZKQX3n8Y60L8r351C77nzded32PfS3 WhiNbP1jsZ2W97XzaLkB96FYQQ2FIrYRKm8ccWeN+AJG03IfNcvfg1KwvGLJZ/gaUBJU gx7GB34q7XQpqyR4vMdjU/bfBnS2p+rRZhSqBkUrcTiHlW64B5yNSbPH5qn5AL6LL+hS RHh+aBSklZPQbP4jNgM48oyiq6W/XoK2aVIQgMAxykBXUOzVXLtCEB/0EcsYbxG3jmDe 0Htw== X-Gm-Message-State: AOAM532vB/PAeb3Iv+HzvovtVB6txU+ulheQF+pwwCM3p37oOMtP52cE 87D4MifbhiS5Hi39FDT36/zm+dXAQ8Bq0w== X-Google-Smtp-Source: ABdhPJy1XsGeqpJ6aO63iP16Kqf4/EjQHNPn6cpALTse6h2EMANuK/qY+oAQ55mxKbZsbKwhU2zgQg== X-Received: by 2002:adf:fb91:: with SMTP id a17mr34860772wrr.376.1630492628376; Wed, 01 Sep 2021 03:37:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/51] target/arm: Implement MVE VCVT between floating and fixed point Date: Wed, 1 Sep 2021 11:36:20 +0100 Message-Id: <20210901103653.13435-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493929777100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT insns which convert between floating and fixed point. As with the Neon equivalents, these use essentially the same constant encoding as right-shift-by-immediate. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 9 +++++++++ target/arm/mve.decode | 19 +++++++++++++++++++ target/arm/mve_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 18 ++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 9ee841cdf01..f3c2b43bf43 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -863,3 +863,12 @@ DEF_HELPER_FLAGS_4(mve_vfma_scalars, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vfmas_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfmas_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vcvt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_hs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_hu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_sf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_uf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_fs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_fu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index f1b8afb4778..d93083065d6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -779,3 +779,22 @@ VCMLA0 1111 110 00 . 1 . ... 0 ... 0 1000 .= 1 . 0 ... 0 @2op_fp_size_ VCMLA90 1111 110 01 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCMLA180 1111 110 10 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCMLA270 1111 110 11 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev + +# floating-point <-> fixed-point conversions. Naming convention: +# VCVT_, S =3D signed int, U =3D unsigned int, H =3D halfprec, F= =3D singleprec +@vcvt .... .... .. 1 ..... .... .. 1 . .... .... &2shift \ + qd=3D%qd qm=3D%qm shift=3D%rshift_i5 size=3D2 +@vcvt_f16 .... .... .. 11 .... .... .. 0 . .... .... &2shift \ + qd=3D%qd qm=3D%qm shift=3D%rshift_i4 size=3D1 + +VCVT_SH_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 +VCVT_UH_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 + +VCVT_HS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 +VCVT_HU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 + +VCVT_SF_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt +VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt + +VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt +VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 891926c124d..d829ffe12d6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3258,3 +3258,39 @@ DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float3= 2, DO_GT32) =20 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) + +#define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ + uint32_t shift) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], shift, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) +DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) +DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) +DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) +DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) +DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) +DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) +DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e8a3dec6683..9269dbc3324 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1439,6 +1439,24 @@ DO_2SHIFT(VRSHRI_U, vrshli_u, true) DO_2SHIFT(VSRI, vsri, false) DO_2SHIFT(VSLI, vsli, false) =20 +#define DO_2SHIFT_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2shift(s, a, gen_helper_mve_##FN, false); \ + } + +DO_2SHIFT_FP(VCVT_SH_fixed, vcvt_sh) +DO_2SHIFT_FP(VCVT_UH_fixed, vcvt_uh) +DO_2SHIFT_FP(VCVT_HS_fixed, vcvt_hs) +DO_2SHIFT_FP(VCVT_HU_fixed, vcvt_hu) +DO_2SHIFT_FP(VCVT_SF_fixed, vcvt_sf) +DO_2SHIFT_FP(VCVT_UF_fixed, vcvt_uf) +DO_2SHIFT_FP(VCVT_FS_fixed, vcvt_fs) +DO_2SHIFT_FP(VCVT_FU_fixed, vcvt_fu) + static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, MVEGenTwoOpShiftFn *fn) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493890; cv=none; d=zohomail.com; s=zohoarc; b=NTz9Uhho2CmSpteA3D38j0GBPQqgmV4eWXDG2mcCjsDQVA2t477Le95cCZUdMjHsuVm/2KEQfpBL/HPt40I30sjEqBVO/f8MN0zHAxOM2CMQv/pGpfS5OwbBchgbJDMvK+gEjKfe97f8on32KVmoMXnXI46GKbBI71J/TRRVAyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493890; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wxV8ETbRwpnY1TML7JdJIQOdN91j+ccB0uTrt2mBY2U=; b=Dgwb9Qxt/XzkKP1UuEg8ZwqMLAKYQamGgCW2dgwcmyyiFuAAYphhadhrmcHniwx4+TJoKgW4lFlp2TAKqlFX5QvAlHL5fJepvtwgyUbq1AMsnZVVdLt99OJ3UUa5nEunPI3Fxy62JQ4JZ77BTmOqS1k8c3tfGr+kdAO4ZVZG0UY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493890544242.9771571816848; Wed, 1 Sep 2021 03:58:10 -0700 (PDT) Received: from localhost ([::1]:43108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNwX-0001zH-EO for importer@patchew.org; Wed, 01 Sep 2021 06:58:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcK-00076Q-KD for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:17 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcE-0005l7-9S for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:16 -0400 Received: by mail-wr1-x429.google.com with SMTP id v10so3743108wrd.4 for ; Wed, 01 Sep 2021 03:37:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wxV8ETbRwpnY1TML7JdJIQOdN91j+ccB0uTrt2mBY2U=; b=dBPdDr/VH7wiSEgnhzjU1nuWEGbndjqHS5QAyGumc2e7KplPVAR5l7PA5ffwHGMlMu SVDx6euOMjLqQiIcZAXydpL+b6j4vvQFkGIG/cuQYj4OA6jHPF+S0s07NlsHe/8B0ilf vrDRLVqMPIs6j0oZCn5ZkOJU+DfQooLVoDsFrA71rtLBE7Fh2x+r7qh+oDT3qkcfu7wp eiit3ZjArpyL815arlKSj77mfh6FR/f8eXuImI1tK2Fgjo+RVUoTHiPbz6ld8BPVSFbD +T63ajViLMayU/UrRuG+6365pWmTtL5N7VATxd8X+xlXVgig9lsU7ksoSBpS3zo9/mn0 WAqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wxV8ETbRwpnY1TML7JdJIQOdN91j+ccB0uTrt2mBY2U=; b=FssYrg3s/IFkN9N7lABwO72xPQ/FwcB0PzSgZsXyKCaiQaICBat0CwfCufxfZivxp3 f3U3XI3K1pmnXAB9DhYHJPRZ14wJcLJDT96DnJaoZOxIxpfO/kI+pNLVBAFlxvSTWi4K l1ReGhP3Wmz2SxmjtK+jo1M9QfjPBkcSn7FLSAcn97DowjgkLAGej5Hvqxg0UpNog4pW ndekv/UVCW/7QFbE68kDzyhwM3BA9zmC01Js3yMuI0GTZp05rvKruor81wsxW6VX0rHG rk9E4+evtvg2d4PP5CmMb7Q4uQxLcU9lZf4cRnF2fl4Kje9TvlCmAcTWJdFgtAHe3uae /Nqg== X-Gm-Message-State: AOAM532XaKSguWab8Ic0NuSr0s6CfM7fOvQy8tolwhcwWPVrdy1KE3ym aIkNMI77K97CwjhqEQSbi/1mGJ2L402Btg== X-Google-Smtp-Source: ABdhPJwmVqR4vCrWLfORyVrkDf44YApfDay3IshDwyPmxeb+TC7bozJTnFwBpU4awOSL2Pg2TQJ66Q== X-Received: by 2002:adf:914a:: with SMTP id j68mr34529868wrj.73.1630492628902; Wed, 01 Sep 2021 03:37:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/51] target/arm: Implement MVE VCVT between fp and integer Date: Wed, 1 Sep 2021 11:36:21 +0100 Message-Id: <20210901103653.13435-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493892504100001 Content-Type: text/plain; charset="utf-8" Implement the MVE "VCVT (between floating-point and integer)" insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 7 +++++++ target/arm/translate-mve.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d93083065d6..89b8c6fc8e6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -798,3 +798,10 @@ VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01= . 1 ... 0 @vcvt =20 VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt + +# VCVT between floating point and integer (halfprec and single); +# VCVT_, S =3D signed int, U =3D unsigned int, F =3D float +VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op +VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op +VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op +VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 9269dbc3324..351033af1ec 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -543,6 +543,38 @@ DO_1OP(VQNEG, vqneg) DO_1OP(VMAXA, vmaxa) DO_1OP(VMINA, vmina) =20 +/* + * For simple float/int conversions we use the fixed-point + * conversion helpers with a zero shift count + */ +#define DO_VCVT(INSN, HFN, SFN) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##HFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##SFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] =3D { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VCVT(VCVT_SF, vcvt_sh, vcvt_sf) +DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf) +DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) +DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493498; cv=none; d=zohomail.com; s=zohoarc; b=N/LC4e/f/0vfeivNhkVUZ7jwfnvDEpULoMQhZTfOlpXrl79Dp7Fjkjx5GztqbI3mGRjouV+dU/K/QeMBlydBIcJtFIkxQie3sRjKyCxgPJm89+n4x+W5guXtEGYMlh/b6eOUpEWuYXevLGpEGAoXVkzHrjduu/5a3SZJJY5yeJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493498; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0wI7j8ZzlRJ/lDfh+vnYQ5kxrT4haUCPSHWV+blV5z8=; b=kn6w+U0M+WRsfFRCUXafI2yQq6CjBkJ0i+U+oVKFjQOdk+3xK4lL2gQKg+6BxAU6w6Fx8mb8eIp/b96bKbRt4c+nZ4QZhvOlNLb9eRIbpSdKljRpMyAcxfUvcoM+5XFXwGtQeu5PD5nOC0/8I2eAAf6ScQoQ2PMASDkmW7BAnaU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493498876333.4075221736066; Wed, 1 Sep 2021 03:51:38 -0700 (PDT) Received: from localhost ([::1]:53710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNqD-00075e-Kw for importer@patchew.org; Wed, 01 Sep 2021 06:51:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcH-00073M-S9 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:14 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40662) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcG-0005mK-0N for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:13 -0400 Received: by mail-wr1-x435.google.com with SMTP id t15so3732996wrg.7 for ; Wed, 01 Sep 2021 03:37:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0wI7j8ZzlRJ/lDfh+vnYQ5kxrT4haUCPSHWV+blV5z8=; b=OCBJ2pZv5lRXdrR0JasWdGpix9nUdVjWamJABqk4EMeWhMucJiG6NaSWx0trrPpvW7 Y1+XWKDbzY06PdFd0kaMlJWevBzmJyXdMQXmM5x24Vw/qDQr2EzbEe5GzoWttMolZdzM E495hLwUo2PQuJ1BMcFWg7QGCqNxs4/YWSAnnPMIilTD70cNgUa061QKOH+7/LdFS++L 9Q2Z8LP/vyDs1o/bP9KaJFgyVjlo+yL+8xGNBSAAQLFzL7PRIqtVvSTfBzSyVz9bjP/l XycxGc5URXFQn7UAe7jh28NKhGvTCNFSjrcO1HONTy9NbqgI82tcRUd0cN7rs3pQ5NxU N9tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0wI7j8ZzlRJ/lDfh+vnYQ5kxrT4haUCPSHWV+blV5z8=; b=rpGbamuKnRnF56DkGaWu6LSmGXWIsAxLAn7i0KFnJ24AXUXOHDmsipwoe4LeQi3gkI JCF1v1eChEwhaleGNfg8cv3PfdpOumyiFjOYC5/2tcISDaBg6MwzGyeU7lnIhnP3Q0KR +54xsYQCZROe5iNwItwS11+r5N9M63wEH2Bf3T9mMCBImQYQP6oe4R7ZfaHJmhyZgKkU qppZ4/xLvEQiuG/qvriV08aRZny0W71exV9lEjq9Rv2YNqbxe7IyBAQbY6lly4vFpTpR J6jCv2IFlXGBbz1RI2Hnl1b2rgiG2cBuRZvzpgW8dA9ZCEzp2mDUwwjKhCVdeTrVbaHv sfUw== X-Gm-Message-State: AOAM53091aEOYzSti051+pAl1QQPtcQ5r9HyitvpjdOHMZhEqTE/tzWI vid4eLOkFFkhMNEOBaIMUlR6rX+0pj5qjg== X-Google-Smtp-Source: ABdhPJzwzfnc5YFiqeTlGpnq0x2mbPVsducKXbY7QsyppBK5uJt+2CwPaict+g5moDosb5ow64eC2Q== X-Received: by 2002:a5d:51ca:: with SMTP id n10mr36341987wrv.119.1630492629553; Wed, 01 Sep 2021 03:37:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/51] target/arm: Implement MVE VCVT with specified rounding mode Date: Wed, 1 Sep 2021 11:36:22 +0100 Message-Id: <20210901103653.13435-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493501360100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT which converts from floating-point to integer using a rounding mode specified by the instruction. We implement this similarly to the Neon equivalents, by passing the required rounding mode as an extra integer parameter to the helper functions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 ++++ target/arm/mve.decode | 10 ++++++++ target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++ target/arm/translate-mve.c | 52 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f3c2b43bf43..6d4052a5269 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -177,6 +177,11 @@ DEF_HELPER_FLAGS_3(mve_vminab, TCG_CALL_NO_WG, void, e= nv, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vminah, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vminaw, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vcvt_rm_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_ss, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_us, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 89b8c6fc8e6..55e8ce304e5 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -805,3 +805,13 @@ VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 = 1 . 0 ... 0 @1op VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op + +# VCVT from floating point to integer with specified rounding mode +VCVTAS 1111 1111 1 . 11 .. 11 ... 000 00 0 1 . 0 ... 0 @1op +VCVTAU 1111 1111 1 . 11 .. 11 ... 000 00 1 1 . 0 ... 0 @1op +VCVTNS 1111 1111 1 . 11 .. 11 ... 000 01 0 1 . 0 ... 0 @1op +VCVTNU 1111 1111 1 . 11 .. 11 ... 000 01 1 1 . 0 ... 0 @1op +VCVTPS 1111 1111 1 . 11 .. 11 ... 000 10 0 1 . 0 ... 0 @1op +VCVTPU 1111 1111 1 . 11 .. 11 ... 000 10 1 1 . 0 ... 0 @1op +VCVTMS 1111 1111 1 . 11 .. 11 ... 000 11 0 1 . 0 ... 0 @1op +VCVTMU 1111 1111 1 . 11 .. 11 ... 000 11 1 1 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d829ffe12d6..a793199fbee 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3294,3 +3294,41 @@ DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) + +/* VCVT with specified rmode */ +#define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vm, uint32_t rmode) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + float_status *base_fpst =3D (ESIZE =3D=3D 2) ? = \ + &env->vfp.standard_fp_status_f16 : \ + &env->vfp.standard_fp_status; \ + uint32_t prev_rmode =3D get_float_rounding_mode(base_fpst); \ + set_float_rounding_mode(rmode, base_fpst); \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D base_fpst; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + set_float_rounding_mode(prev_rmode, base_fpst); \ + mve_advance_vpt(env); \ + } + +DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) +DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) +DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) +DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 351033af1ec..e80a55eb62e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -49,6 +49,7 @@ typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i3= 2); typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i32); +typedef void MVEGenVCVTRmodeFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -575,6 +576,57 @@ DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf) DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) =20 +static bool do_vcvt_rmode(DisasContext *s, arg_1op *a, + enum arm_fprounding rmode, bool u) +{ + /* + * Handle VCVT fp to int with specified rounding mode. + * This is a 1op fn but we must pass the rounding mode as + * an immediate to the helper. + */ + TCGv_ptr qd, qm; + static MVEGenVCVTRmodeFn * const fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_mve_vcvt_rm_sh, gen_helper_mve_vcvt_rm_uh }, + { gen_helper_mve_vcvt_rm_ss, gen_helper_mve_vcvt_rm_us }, + { NULL, NULL }, + }; + MVEGenVCVTRmodeFn *fn =3D fns[a->size][u]; + + if (!dc_isar_feature(aa32_mve_fp, s) || + !mve_check_qreg_bank(s, a->qd | a->qm) || + !fn) { + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +#define DO_VCVT_RMODE(INSN, RMODE, U) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + return do_vcvt_rmode(s, a, RMODE, U); \ + } \ + +DO_VCVT_RMODE(VCVTAS, FPROUNDING_TIEAWAY, false) +DO_VCVT_RMODE(VCVTAU, FPROUNDING_TIEAWAY, true) +DO_VCVT_RMODE(VCVTNS, FPROUNDING_TIEEVEN, false) +DO_VCVT_RMODE(VCVTNU, FPROUNDING_TIEEVEN, true) +DO_VCVT_RMODE(VCVTPS, FPROUNDING_POSINF, false) +DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) +DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) +DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=w3KXVNoxhsJO5H+sS6XekepmNFJDc+Q5EgHCZoxBLOM=; b=h6qUvFacLfpYCoQ5Vp37a4L+qUwFEFhq1Dg4nZoiN1JAg3zcwXZsIFluzIWQgJUNoq kyikKDcoJpUiewVl1DlPFOk+di6B1O/OTPEn+64+ZONL9H/qCyGIUfhS7wvj0m3sKvp4 vy6yHchARSSEKzJapawmCQLagLapnngWX0RvgmfBdAnl/EUsPCI1wcl/g78IdkyzZ97C wIR063Z/M8H0zbCNqQ5aOX5uOnR1II1Dc1AHA9DerOlTFrqTVxmk/mwuzG/Ppn2t5vNX fj0Vs5614RorKKM3qkzhwIyiiK/b/OCu6lkOi5PsdBPL9sq6Z0T7iHpHoCWastRW+aNR mwNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w3KXVNoxhsJO5H+sS6XekepmNFJDc+Q5EgHCZoxBLOM=; b=g23oxjcEOgGNrXlR/q7gZF3wC2S94KZwSLJU0fGJY6qlixlTmbMO1Q0cVkr+DQpqHD iNh22MNtpnaVtpwl9VdeTHny9BTrvyAhEPSjH0zmprmydBW1W0KdgFYQV+vGqBIN7iJ8 Y/Cj8uwWVF09QTVmUz2hlG0jiulY6nRUPld6YaYZfLDqILYUmZXD0SDmc+gnEb8f6/PF XTBXqiJm/DpxrRNhv91juZ45UUMu8ptX3ZMhNNvXCPJo62VIFxI23znpSZNEgSv9kEUy YVOTzNY+cDYAV1lYxOXF4fAe4cYoxpOENfeDsU7Bxu8M4SK/6/yxP6y4PdpVwvVdSZtq atEg== X-Gm-Message-State: AOAM533jDqfT8ZPf/sxdLK9EC5KEU4spF2IvvdhRLEGkVm3VCP9IG4Ab WtEOYINQyukILSSqXLCBIdYJYYogcvxcQQ== X-Google-Smtp-Source: ABdhPJyke38c4zY9a+3oau/CBH4NvGzjxhknth21PIQGKRRUsddRnQB81txhTj4BQBv8jZ5hQUB/9g== X-Received: by 2002:a1c:e904:: with SMTP id q4mr9122821wmc.26.1630492630300; Wed, 01 Sep 2021 03:37:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/51] target/arm: Implement MVE VCVT between single and half precision Date: Wed, 1 Sep 2021 11:36:23 +0100 Message-Id: <20210901103653.13435-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493659113100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT instruction which converts between single and half precision floating point. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++ target/arm/mve.decode | 8 ++++ target/arm/mve_helper.c | 81 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 14 +++++++ 4 files changed, 108 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6d4052a5269..f6345c7abbe 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -182,6 +182,11 @@ DEF_HELPER_FLAGS_4(mve_vcvt_rm_uh, TCG_CALL_NO_WG, voi= d, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_rm_ss, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(mve_vcvt_rm_us, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) =20 +DEF_HELPER_FLAGS_3(mve_vcvtb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtb_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 55e8ce304e5..10f0f1de7b1 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -221,6 +221,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op # The VSHLL T2 encoding is not a @2op pattern, but is here because it # overlaps what would be size=3D0b11 VMULH/VRMULH { + VCVTB_SH 111 0 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_nosz + VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma = size=3D2 =20 VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -235,6 +237,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTB_HS 111 1 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_no= sz + VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 =20 VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -247,6 +251,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_SH 111 0 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D2 VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h @@ -260,6 +266,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_HS 111 1 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a793199fbee..1ed76ac5ed8 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3332,3 +3332,84 @@ DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_to= shh) DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) + +/* + * VCVT between halfprec and singleprec. As usual for halfprec + * conversions, FZ16 is ignored and AHP is observed. + */ +static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) +{ + uint16_t *d =3D vd; + uint32_t *m =3D vm; + uint16_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fz =3D get_flush_to_zero(base_fpst); + set_flush_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & 1)) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float32_to_float16(m[H4(e)], ieee, fpst); + mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); + } + set_flush_to_zero(old_fz, base_fpst); + mve_advance_vpt(env); +} + +static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) +{ + uint32_t *d =3D vd; + uint16_t *m =3D vm; + uint32_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fiz =3D get_flush_inputs_to_zero(base_fpst); + set_flush_inputs_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & (1 << (top * 2)))) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); + mergemask(&d[H4(e)], r, mask); + } + set_flush_inputs_to_zero(old_fiz, base_fpst); + mve_advance_vpt(env); +} + +void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 1); +} +void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 1); +} diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e80a55eb62e..194ef99cc74 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -627,6 +627,20 @@ DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) =20 +#define DO_VCVT_SH(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, gen_helper_mve_##FN); \ + } \ + +DO_VCVT_SH(VCVTB_SH, vcvtb_sh) +DO_VCVT_SH(VCVTT_SH, vcvtt_sh) +DO_VCVT_SH(VCVTB_HS, vcvtb_hs) +DO_VCVT_SH(VCVTT_HS, vcvtt_hs) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u9XrxnOjxPXtQ8fmSKp6DWMiWXBpdhUDNVvPv6HOSgI=; b=wCY7RzrR6WwavKaZSDCDGwQ4tjXVP6ze9qKc3bEfnpkgPWGeFdM7sLxCcwu1HZPKiR SSAaocFmCQaXMdx53RDRf+Ae0f1FsvMtZmUEE73sPE7ZB96inApj6sPeWrZeB1wAH9gE qLlY29HvuOcKZ49PE6MwypB99UKyAdw3C/ZEzhtjsQB+zVYwnxj+unYnNBWmVTUbBeQH wt12aX3liRcFxBc2yLbBx4JgZOq7WKAcDYYc97/joYYMqteNcaIzeyH8EleVpADc3xS0 g4U4JXHidjm7FZmqzkICX2pmAvO1stwIKC5athRX6i0f5grrI4S/k2wdlvKUHZ9pKka5 8TSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u9XrxnOjxPXtQ8fmSKp6DWMiWXBpdhUDNVvPv6HOSgI=; b=NqInQ2F1jJtk9W+41rylKm6nLhQk94fw/FPkvIf+hytJSKKbp0zUCrsPBmanBkm8nK H8FWelSOiD0HOxHvS+pOv6VYTpshZvqmzz57PIaJCZUPsVeKnTMLXrIWNMTh4qYRIRBI k4e1eXtkVE1zTCajI0ndtNdUEATHLSfSTZnoDzV9Y+ADCt2TWP+3AjS59yo5seYBKHG+ e0jpzoC8Yjonl35420ceeYq7WCGvDWUJjEKoOrtDiA5tYLd/rBnf4QRFQ4+FmLxDWNRa f/84r6fK0RBvDva9q6Cvgv1XPvoaq69G4+64OihHy45t5Qc/mtKOpTtYf8KE3j67Tau6 ojZw== X-Gm-Message-State: AOAM533f25xBrCuBDvaqQD39T9S/ukVS7lwIM43sPe1FqLwM1zvQ9tKh uZopZ1GL8LPs+ZtqYw7Q3lMZrPwJlM1qGw== X-Google-Smtp-Source: ABdhPJxXngk8tofJTLUu7jTyRpfh2W4j846lUp0CrrNsZyL+S5O98y1tPkqfsvF6UJDC0AIzV3mZEQ== X-Received: by 2002:adf:9ccc:: with SMTP id h12mr36468239wre.385.1630492630864; Wed, 01 Sep 2021 03:37:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/51] target/arm: Implement MVE VRINT insns Date: Wed, 1 Sep 2021 11:36:24 +0100 Message-Id: <20210901103653.13435-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493654771100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VRINT insns, which round floating point inputs to integer values, leaving them in floating point format. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 6 +++++ target/arm/mve.decode | 7 ++++++ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++ target/arm/translate-mve.c | 45 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f6345c7abbe..76bd25006d8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -882,3 +882,9 @@ DEF_HELPER_FLAGS_4(mve_vcvt_sf, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_uf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_fs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_fu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vrint_rm_h, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vrint_rm_s, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vrintx_h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrintx_s, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 10f0f1de7b1..14a4f398020 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -823,3 +823,10 @@ VCVTPS 1111 1111 1 . 11 .. 11 ... 000 10 0 = 1 . 0 ... 0 @1op VCVTPU 1111 1111 1 . 11 .. 11 ... 000 10 1 1 . 0 ... 0 @1op VCVTMS 1111 1111 1 . 11 .. 11 ... 000 11 0 1 . 0 ... 0 @1op VCVTMU 1111 1111 1 . 11 .. 11 ... 000 11 1 1 . 0 ... 0 @1op + +VRINTN 1111 1111 1 . 11 .. 10 ... 001 000 1 . 0 ... 0 @1op +VRINTX 1111 1111 1 . 11 .. 10 ... 001 001 1 . 0 ... 0 @1op +VRINTA 1111 1111 1 . 11 .. 10 ... 001 010 1 . 0 ... 0 @1op +VRINTZ 1111 1111 1 . 11 .. 10 ... 001 011 1 . 0 ... 0 @1op +VRINTM 1111 1111 1 . 11 .. 10 ... 001 101 1 . 0 ... 0 @1op +VRINTP 1111 1111 1 . 11 .. 10 ... 001 111 1 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1ed76ac5ed8..846962bf4c5 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3333,6 +3333,12 @@ DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_to= uhh) DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) =20 +#define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) +#define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) + +DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) +DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) + /* * VCVT between halfprec and singleprec. As usual for halfprec * conversions, FZ16 is ignored and AHP is observed. @@ -3413,3 +3419,32 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd= , void *vm) { do_vcvt_hs(env, vd, vm, 1); } + +#define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) +DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 194ef99cc74..2ed91577ec8 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -641,6 +641,51 @@ DO_VCVT_SH(VCVTT_SH, vcvtt_sh) DO_VCVT_SH(VCVTB_HS, vcvtb_hs) DO_VCVT_SH(VCVTT_HS, vcvtt_hs) =20 +#define DO_VRINT(INSN, RMODE) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_h(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))= ); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_s(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))= ); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] =3D { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) +DO_VRINT(VRINTZ, FPROUNDING_ZERO) +DO_VRINT(VRINTM, FPROUNDING_NEGINF) +DO_VRINT(VRINTP, FPROUNDING_POSINF) + +static bool trans_VRINTX(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vrintx_h, + gen_helper_mve_vrintx_s, + NULL, + }; + if (!dc_isar_feature(aa32_mve_fp, s)) { + return false; + } + return do_1op(s, a, fns[a->size]); +} + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dlNDMB/8L65w3rYQrh4g4+ZBy9+++yz/Uc57+3Riqgs=; b=epMPq3ghMGNjs2aUnH1azSrBXvvW4sD27Er7fl+nB8bcKpp20oQ/HlUaVDmRoa7tHw KxX0Aa5HtpIfOJjQmrRMiSa/9xoU+ERa4aopIPMBG8jGS2CAIsufSBSljdlBNa8eCniQ XlVYoM7ZjFe/ciXHiAwNyEsXPRcE8r8WaiOwnrVWKpukMb8tIFDI7wzXDy6DYQcCbcFp 3kaJDi0rRrUoWJ/tJbXv9CZrD/UE7EPgExudYUjUgj6aTdjoHP6RAKrDH+yAHqGHme8Q F2RtNRXUt1AeK04d8Y95dD+yeOPiOhqq6vwoAUw3jiPSJC+WTcqqHwqOfxrjHHXvIfiK AkfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dlNDMB/8L65w3rYQrh4g4+ZBy9+++yz/Uc57+3Riqgs=; b=Vf+b4Bm0gwTpd6DSDvhe/Y/tujC+txc/RsWEwQcOzQgX+PK7QOcMvrhYcYirGssfiT ECPIynWHsi7JKrE/eYNwITb10dkhCiO2KvzYkJBdSXzdfXvTQ7uV+lQj/IO2AryQ+GC8 JhCGVJU9G84+lT/Hu7ckeFt+pd1qV0iULl3O0wYCF/uTRxJ3J95emXp0qcYOiTJ1jN7C MrA+JdcAKxPp0rFs1Jzf0mhTCN1edJxX0mlfpcobX7dqO4CcQIdU0NQZThrvhTR4C/2j SXJWudP5FWoOlx1/q+dBnF53P187kiJ403wPDSdxkozExjhyqK+kksQnN9zyljrZ79YF yPRw== X-Gm-Message-State: AOAM530VDMher2qGFB2s6oKmjTQ4TFoB8XgEeKYMVezs0IUSFO6E2jrC BOHFtJmgdgSgEAbNlFLp49r+xMS8LlVbLA== X-Google-Smtp-Source: ABdhPJy8HEDwjK+AOnZCZ7542ATXZD6XXLre9ZXAzUfoFujyFXhywYDa18zJLrwvF7LMg+RSK8HUNQ== X-Received: by 2002:a1c:4e11:: with SMTP id g17mr9117159wmh.2.1630492631418; Wed, 01 Sep 2021 03:37:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/51] target/arm: Enable MVE in Cortex-M55 Date: Wed, 1 Sep 2021 11:36:25 +0100 Message-Id: <20210901103653.13435-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493881458100001 Content-Type: text/plain; charset="utf-8" We now have a complete MVE emulation, so we can enable it in our Cortex-M55 model by setting the ID registers to match those of a Cortex-M55 with full MVE support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ed444bf436a..33cc75af57d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -654,12 +654,9 @@ static void cortex_m55_initfn(Object *obj) cpu->revidr =3D 0; cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; - /* - * These are the MVFR* values for the FPU, no MVE configuration; - * we will update them later when we implement MVE - */ + /* These are the MVFR* values for the FPU + full MVE configuration */ cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12100011; + cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; cpu->isar.id_pfr0 =3D 0x20000030; cpu->isar.id_pfr1 =3D 0x00000230; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493997; cv=none; d=zohomail.com; s=zohoarc; b=isK6das5M1aZe66Rj3H1DtQUNgt4uRDHVcS1sJZSxL0vbqeKQDpnX3/N3wuvGuEZo/LTOvSZN9mjgRsap8HW+6pyrFBZ4K6Dhsn7UkOulJinuP3moRXRD2EQjuT2XtKTbMCij9n8E4x0YKfdZ5or4tG3u11pGKadt94JPbMM/8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493997; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1L/RlCqBiqLml/hFd0+F4uicJlE4I9SpOhrbXo7Iy/w=; b=kWQDr/o9NhFEpUKrnXtoz7/f66uFd4gsVXPZ8QQAQDB9ks6ErLNOhBVZEggtjt+R6mk7NC4BafQm3PTG4UUy2bG0NW+5ToEERCVa2olkBmDvkR+RMUwVvX/5k9IRwxDxQH1gn5m/I6w6XFU33+3IXSwT+jA73kHvi+T5S/mOJrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493997817324.4036955820343; Wed, 1 Sep 2021 03:59:57 -0700 (PDT) Received: from localhost ([::1]:50028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNyF-0006Yk-LG for importer@patchew.org; Wed, 01 Sep 2021 06:59:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcJ-00075j-6t for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:15 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:51166) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcH-0005oB-AS for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:14 -0400 Received: by mail-wm1-x330.google.com with SMTP id m2so1549062wmm.0 for ; Wed, 01 Sep 2021 03:37:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1L/RlCqBiqLml/hFd0+F4uicJlE4I9SpOhrbXo7Iy/w=; b=KAc3cgnz8qMRNwjpuYTS5etFj6yWICTU1+XC+WYBJEJimZtuJjKoMSqqz6swPpgQdH jVPu1XNfEx5JSzBkB9LYbQ8qplvuBMSHFVFR/2wQQPbnzVu76mGj9CnX+AdJ5URxj6YL P3+BOdUvAmmF22ebu3TeUuOXEm/iK3HtPsyRatE5jdEpQWCbK24yUgJsTl+Ks0pzihez k4TkVRkeDeQOppwftrlm0y647m4I9SSBBSyAK349CwilMfCHF03+EdoFUiD6brElBz+Z vWJEIwbKPGN/2hBU0pLzjjJrlRFZQ24KEpQvO8BnueJmhhQHHWf7LyiNjNjIN8cLJErW pqHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1L/RlCqBiqLml/hFd0+F4uicJlE4I9SpOhrbXo7Iy/w=; b=P2Sncb4A3N9I3xaAyCXdQWT0gMEJFZFHN5BQvFpCxAirCwz9N8aJBOW0zjFdijN5WP nHaWJeFC3TSH1tu2phj2jE/9WTFOniKut1pVyAK2gxJlNgdrB8M0k6JhMbldDNEaPFL5 6Ael1Ahn2+BUnSjecPV99MBwsa0UlBtHlLwr7rxyR273nkS9JPAn5f3+XWU9YIXJmD+I YhoWlix9PgSSaT9ThMNxNlEHQYX0UqLfJuYZCm+DClGsL62er/lv4TlAasepnYbUdJt3 ll9DgPJfhKqAHpRdGFtv/Ip3CefBmXlw1EGE2Z/lWURNtbRmSwjbyY5NKHcSmZc6Bi9b Nuog== X-Gm-Message-State: AOAM530gcbQhz6pQvmhdOJHmjY4c2nn15slUQCpHxeGCW4NtFqNvL8gI QrVl7pVL7ROK+6wDYlUk3k35ENk1e2e9cg== X-Google-Smtp-Source: ABdhPJy1zTrkf+njzXNB9pxJ1Y3kokGU76OrS3r9wPaj1Dat2jGcQ/PRe/hGPanFBgRu7mwyj7HwqQ== X-Received: by 2002:a1c:20d7:: with SMTP id g206mr9230512wmg.153.1630492632002; Wed, 01 Sep 2021 03:37:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/51] target-arm: Add support for Fujitsu A64FX Date: Wed, 1 Sep 2021 11:36:26 +0100 Message-Id: <20210901103653.13435-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493999167100001 Content-Type: text/plain; charset="utf-8" From: Shuuichirou Ishii Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths. The Identification register values are defined based on the FX700, and have been tested and confirmed. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2f0cbddab56..15245a60a8c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -841,10 +841,58 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL); } =20 +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + aarch64_add_sve_properties(obj); + bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); + set_bit(0, cpu->sve_vq_supported); /* 128bit */ + set_bit(1, cpu->sve_vq_supported); /* 256bit */ + set_bit(3, cpu->sve_vq_supported); /* 512bit */ + + /* TODO: Add A64FX specific HPC extension registers */ +} + static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, }; =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494000; cv=none; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+kXhFUWLQCA6qo5Trwr0Tjft3elFXFhPwM9yjPGmMdQ=; b=guE/YLgfckOMifOMAbujoeU4g74ijB+/37fn72gGMxFHo0AjiXQTew6rBRjB8PLF+r L6lvJLIn3n7dAePHJOAkx53WrUcgLXXZ28rph71lvqtBsMDxHQTttCrCZxDMp4npH0up fq7zWBncAqVy35RGWw+9tSMMHrETBH/e5aPZQllXVEAc/YvhSNIKbzPe3jyoAafOVgSj oGr4V402+JzFjVWu9hELbBCPI9iG7qqpzUbncMmPGoiCXJRf8XTpY8vQuNTaYxQ0iIbY At1YZP4sNWuy9FnmMe0FfuiKkXpF46f3MZnc5HlTV0dmN7bRtn72+ncjL9t0AC9upxl7 Zk3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kXhFUWLQCA6qo5Trwr0Tjft3elFXFhPwM9yjPGmMdQ=; b=pFOl0zrjkGsyM8f0K/7rCXxD51YVx6dInuyvBm8v4o4aYDKcHLkYi1Ezup8xFka5rB gSIEFBIB4kHj3q9jXLDw3VOZw/mvMtbJPdw+2n91wIMI1EMYBJIU3xBGjlUPiRAkalfn lF/BSzUwrGeYshugcwRN08On0QKs07QjrTjJcrjVfWX0icpDp/j5bZwHLNICNzRUYgRX 7EezDjFma3AVXyAyqgCKx74pWJbcukWPb+reaJAACni+IyuE4iXZU/G04OIjXkqKYCmo lU89ds5lbGyK7mC/nrUW2wjfG8HIyv5tWSeXwJl38I0PaCALAnDpu+soRGwRpKjx7MSF e9fQ== X-Gm-Message-State: AOAM5316GUp7/V7ONFJgW/oV5oZG6sIv2wZTDGagJ9r0uVpBx5AaJkiP VEa2jctEbvBjjjJBs0YzEpp61KSPbPwh6A== X-Google-Smtp-Source: ABdhPJw/FXD1lIQYCZs91Kmu7yQJaTFGb0M87WZFgj0R6GmDG5GRTgeGdgAIhEqxxD5mwbN6KNL/kg== X-Received: by 2002:a1c:1dcc:: with SMTP id d195mr9204958wmd.85.1630492632618; Wed, 01 Sep 2021 03:37:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/51] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Date: Wed, 1 Sep 2021 11:36:27 +0100 Message-Id: <20210901103653.13435-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494001722100001 Content-Type: text/plain; charset="utf-8" From: Shuuichirou Ishii Add -cpu a64fx to use A64FX processor when -machine virt option is specified. In addition, add a64fx to the Supported guest CPU types in the virt.rst document. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 59acf0eeafa..850787495be 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index dbb77b59974..73e9c6bb7cb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -200,6 +200,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494081; cv=none; d=zohomail.com; s=zohoarc; b=Pn7IBVrBgAIgIw/8TOPvLBADeqv64NbfhsU1ClUMTmZqV/0vJmlgV8Qfztx8SOkRB7drUrjZ0JR/rNuWsZNSQPpsNjSMtxQ45fCNe412XYtP7q1gdCJhHTqGAlCgK1xP8OT7dmCWlLgoDMBSrwroIYSyEBDdju88l71zFBt37Sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494081; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qj0i5KL2ZuTJWlh9USuRwTygN60Vm69qctNqMX3MHmg=; b=YXw53v55eyweFcUw45RjAzKMIoZhh4TYg1rq6nyA0/ahtEGLG1qvEUUlieKNA5LqV8Cs0cKKIP/BxwdGG9UGfmep/uO2ivbMxYRmpPJnYY8mryMjDJE+FUTHtnACp18951EfDBt7lMd0rpAhXL6OBtDpK5rYLg/2vlXHyvUChNk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494081411457.46844809050685; Wed, 1 Sep 2021 04:01:21 -0700 (PDT) Received: from localhost ([::1]:52554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNzY-0008IJ-9d for importer@patchew.org; Wed, 01 Sep 2021 07:01:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcL-00076q-KX for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:17 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:35548) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcI-0005q0-Kp for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:17 -0400 Received: by mail-wr1-x42b.google.com with SMTP id i6so3792399wrv.2 for ; Wed, 01 Sep 2021 03:37:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qj0i5KL2ZuTJWlh9USuRwTygN60Vm69qctNqMX3MHmg=; b=o1Qn5q0JKVnKcB3L8o5kHATiO8zOGZn4K8q3VUoUdotBmANRFwllfWbsu73UcRD7Q/ fafFz/vSBk83CEYw7zc3jdKkKaQTepNjQnl6SxGCT/TBi4nBSfFVA9NaEfXF82gnO4Pq KeQsH9ypjpeBwwveOBEuKe/N0gjFC1/LmKIQMaNlHNpbznAODkrUO8nhXB1Pg48kJ69l 6ZgKaPI1xapkDMKj1KGJMQZgSV5K1VK0fir7tyHCKjjh/R2aNnx++iUPV9akIguDxOwE K6OuPp26jnWNdBXejQ+WDTFZkpALPogcLwk0jD//KpIsYUVrKyS3cXvO6ENWRhyLDfys 6FGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qj0i5KL2ZuTJWlh9USuRwTygN60Vm69qctNqMX3MHmg=; b=dkQXW+L1CKkjs0q8QylAlUsUyFehaoyGrWzRrTAaN5RJqC38LbzYQpUAyW+1EGWrw2 tWJuYF1xN3Sy2/3MRpy+FP5sC8ug/Ivl+78+ctPp2gwnzZl7YIM4jthczkp7sPZwlNAQ l5ofUj5qplauOh3xVB804Wp+Y7Nj0BjFHOGTTZMrxe6vHHYGA1k8WeacogU/Pu/Iu8y3 /FKs/ANLd1xxbfuTEwMzTyuYzBhR0Ejpkf8YQhQyu7g83ZhpPUXmo77xmr3LwOuR2pHc uJ4+Nt6bf0kmkqmOWcw0+YS3aHNSEvYMVHIA8ErlF6geyIw0TacpiYtTAvej5lX2SfAM NFVw== X-Gm-Message-State: AOAM533RLsZtgOBM28uFEDfEuu3TtTM4Uo86lWC30ETqBuGQcUdqa4my b8JukgMxRAA37ydeiyofaslAOVmRDM5ixA== X-Google-Smtp-Source: ABdhPJw+a4jbvuS0/dXsmImmpNdoOl6wydCdSh39poYOWuAb1REwheN02MZ3G5Dc/2LQHf0X62PZug== X-Received: by 2002:a5d:560e:: with SMTP id l14mr23410932wrv.205.1630492633258; Wed, 01 Sep 2021 03:37:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/51] tests/arm-cpu-features: Add A64FX processor related tests Date: Wed, 1 Sep 2021 11:36:28 +0100 Message-Id: <20210901103653.13435-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494085225100001 Content-Type: text/plain; charset="utf-8" From: Shuuichirou Ishii Add tests that the A64FX CPU model exposes the expected features. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones [PMM: added commit message body] Signed-off-by: Peter Maydell --- tests/qtest/arm-cpu-features.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb85..90a87f0ea9f 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -473,6 +473,19 @@ static void test_query_cpu_model_expansion(const void = *data) assert_has_feature_enabled(qts, "cortex-a57", "pmu"); assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); =20 + assert_has_feature_enabled(qts, "a64fx", "pmu"); + assert_has_feature_enabled(qts, "a64fx", "aarch64"); + /* + * A64FX does not support any other vector lengths besides those + * that are enabled by default(128bit, 256bits, 512bit). + */ + assert_has_feature_enabled(qts, "a64fx", "sve"); + assert_sve_vls(qts, "a64fx", 0xb, NULL); + assert_error(qts, "a64fx", "cannot enable sve384", + "{ 'sve384': true }"); + assert_error(qts, "a64fx", "cannot enable sve640", + "{ 'sve640': true }"); + sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494270; cv=none; d=zohomail.com; s=zohoarc; b=USh6PfmXKBvHAZXuSuo9OYyzehRtZ4TP3hgPURXmCCtHcOl4sgdyVxhsi25WeGACAmkL87YizSqs5evqO0UEW4feTG/Pvc1K2LovKTEQcKOVXkw3qfUZN1Vs9FNTLQrXyr1t98xLqFxnKEyvSXRrSTdUA5Q+hSx4azjnMFBegMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494270; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wzZ0UeKNIh1arAaHhjnBPH9e/IIKM2NpmXHjt0CDyCU=; b=GrOPM3LcyhpapZqLGHyD2di5xKZZYveT0N5D/6imCf4FVDofV+x9CAc2oBA3ma9Xur3+imm2B7DXLf/+pf/Gp5ThT62SahJvcJb4i2xtRV8//P2CuMFUPO9Idcq3ecKEd+FMu+0SftMkUc1TWETI6MK8ezYQZwNV89XGyMLFCyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163049427065114.036510425038387; Wed, 1 Sep 2021 04:04:30 -0700 (PDT) Received: from localhost ([::1]:58796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO2f-0004Lc-BT for importer@patchew.org; Wed, 01 Sep 2021 07:04:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcQ-00079n-5t for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:22 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcJ-0005qG-E7 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:21 -0400 Received: by mail-wm1-x32d.google.com with SMTP id u26-20020a05600c441a00b002f66b2d8603so984951wmn.4 for ; Wed, 01 Sep 2021 03:37:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wzZ0UeKNIh1arAaHhjnBPH9e/IIKM2NpmXHjt0CDyCU=; b=JgYcbhfra9052Nnfa1H5AE4udV1e8orWijo+oq31aEI3bin85ZSv2s3eEuaSwTdY4G 2gaICU0nNM62ggLAA+o2V3Mep6RgrPTQTst4L6KP3Qzj9LIq8WuH9NCTte2TkmlR99m5 6miW56Bo7J6yyZzBQC1GFFCeD6/L6KyShiC7F93Xrv7h3f8M6Tu0QweBXHAcVvnTz5DV 2SAX3sImQTQTg5sbuA1C7Zz/a7T/iWmYVvLB3+qAAeuMd5kRwdt/0t93INjZE7iwnTOV wxPI0lFMNU7WMcPVyRa2A9MOvDfe9fZ0QiTTTTceIwmXkthktWnsFkijdgBJpOG5GYpb WULQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wzZ0UeKNIh1arAaHhjnBPH9e/IIKM2NpmXHjt0CDyCU=; b=RSD8cIDja7pSX59SamuP6Ha53z/U0sjQfHl/PDZD/W1yns93iidSkpeOP9v8Kzi2Rs BBcRgWc9hBkfeKVFDKvNsOJWUFBMh3Ou4J8crYF/UIQLTqQt+G5j7fEXpV3yAp6yxXPQ +ZAMAO83n33gTQz8gZIu52kcjyVPdzHdY69hwrGqLD6eEAOMba4MIuyHaCAQU68Lk7p+ hcHtCKkEc15UjGKEvYclzCiG6Nn0lc9+fwGRF/+pUQQeP9AL+UN9MAjx+m0qTMc0Q3gY qXI9I2p/jBTTkoLlbjtiwF4vGuSaPRbjPr/SDRDf/MqVV1VPafn7eDlp2wS3oOruJUr9 FbIg== X-Gm-Message-State: AOAM530Lqj6qQs+XOidzKAXPsnSmAKNks6MJRNvrmNFfVM7SuoWnCiTv 7rWJsuBLh7zLMZHOgDf0kqraDgpacYtqUQ== X-Google-Smtp-Source: ABdhPJxzuHt8Et2/op/0IDoWc3c4g1cSPC/pb1qWSHHeREe5VwPPlUKO7nI/ChzjGjcuj6NMG+1xwQ== X-Received: by 2002:a7b:c190:: with SMTP id y16mr8765042wmi.158.1630492634052; Wed, 01 Sep 2021 03:37:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/51] arm: Move M-profile RAS register block into its own device Date: Wed, 1 Sep 2021 11:36:29 +0100 Message-Id: <20210901103653.13435-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494272646100001 Content-Type: text/plain; charset="utf-8" Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-2-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 2 + include/hw/intc/armv7m_nvic.h | 1 - include/hw/misc/armv7m_ras.h | 37 ++++++++++++++ hw/arm/armv7m.c | 12 +++++ hw/intc/armv7m_nvic.c | 56 --------------------- hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/misc/meson.build | 2 + 8 files changed, 148 insertions(+), 57 deletions(-) create mode 100644 include/hw/misc/armv7m_ras.h create mode 100644 hw/misc/armv7m_ras.c diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index bc6733c5184..4cae0d7eeaa 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -12,6 +12,7 @@ =20 #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" +#include "hw/misc/armv7m_ras.h" #include "target/arm/idau.h" #include "qom/object.h" =20 @@ -58,6 +59,7 @@ struct ARMv7MState { NVICState nvic; BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; + ARMv7MRAS ras; =20 /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 39c71e15936..33b6d8810c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,7 +83,6 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; - MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; =20 diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h new file mode 100644 index 00000000000..ba6daccf3fc --- /dev/null +++ b/include/hw/misc/armv7m_ras.h @@ -0,0 +1,37 @@ +/* + * Arm M-profile RAS (Reliability, Availability and Serviceability) block + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the RAS register block of an M-profile CPU + * (the registers starting at 0xE0005000 with ERRFRn). + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + * The QEMU implementation currently provides "minimal RAS" only. + */ + +#ifndef HW_MISC_ARMV7M_RAS_H +#define HW_MISC_ARMV7M_RAS_H + +#include "hw/sysbus.h" + +#define TYPE_ARMV7M_RAS "armv7m-ras" +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS) + +struct ARMv7MRAS { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; +}; + +#endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 9ce5c30cd5c..8964730d153 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 + /* If the CPU has RAS support, create the RAS register block */ + if (cpu_isar_feature(aa32_ras, s->cpu)) { + object_initialize_child(OBJECT(dev), "armv7m-ras", + &s->ras, TYPE_ARMV7M_RAS); + sbd =3D SYS_BUS_DEVICE(&s->ras); + if (!sysbus_realize(sbd, errp)) { + return; + } + memory_region_add_subregion_overlap(&s->container, 0xe0005000, + sysbus_mmio_get_region(sbd, 0)= , 1); + } + for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { if (s->enable_bitband) { Object *obj =3D OBJECT(&s->bitband[i]); diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1e7ddcb94cb..a5975592dfa 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 - -static MemTxResult ras_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - if (attrs.user) { - return MEMTX_ERROR; - } - - switch (addr) { - case 0xe10: /* ERRIIDR */ - /* architect field =3D Arm; product/variant/revision 0 */ - *data =3D 0x43b; - break; - case 0xfc8: /* ERRDEVID */ - /* Minimal RAS: we implement 0 error record indexes */ - *data =3D 0; - break; - default: - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", - (uint32_t)addr); - *data =3D 0; - break; - } - return MEMTX_OK; -} - -static MemTxResult ras_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - if (attrs.user) { - return MEMTX_ERROR; - } - - switch (addr) { - default: - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", - (uint32_t)addr); - break; - } - return MEMTX_OK; -} - -static const MemoryRegionOps ras_ops =3D { - .read_with_attrs =3D ras_read, - .write_with_attrs =3D ras_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) &s->systick_ns_mem, 1); } =20 - if (cpu_isar_feature(aa32_ras, s->cpu)) { - memory_region_init_io(&s->ras_mem, OBJECT(s), - &ras_ops, s, "nvic_ras", 0x1000); - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem); - } - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c new file mode 100644 index 00000000000..de24922c944 --- /dev/null +++ b/hw/misc/armv7m_ras.c @@ -0,0 +1,93 @@ +/* + * Arm M-profile RAS (Reliability, Availability and Serviceability) block + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "hw/misc/armv7m_ras.h" +#include "qemu/log.h" + +static MemTxResult ras_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + case 0xe10: /* ERRIIDR */ + /* architect field =3D Arm; product/variant/revision 0 */ + *data =3D 0x43b; + break; + case 0xfc8: /* ERRDEVID */ + /* Minimal RAS: we implement 0 error record indexes */ + *data =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", + (uint32_t)addr); + *data =3D 0; + break; + } + return MEMTX_OK; +} + +static MemTxResult ras_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + default: + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", + (uint32_t)addr); + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ras_ops =3D { + .read_with_attrs =3D ras_read, + .write_with_attrs =3D ras_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + + +static void armv7m_ras_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + ARMv7MRAS *s =3D ARMV7M_RAS(obj); + + memory_region_init_io(&s->iomem, obj, &ras_ops, + s, "armv7m-ras", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void armv7m_ras_class_init(ObjectClass *klass, void *data) +{ + /* This device has no state: no need for vmstate or reset */ +} + +static const TypeInfo armv7m_ras_info =3D { + .name =3D TYPE_ARMV7M_RAS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ARMv7MRAS), + .instance_init =3D armv7m_ras_init, + .class_init =3D armv7m_ras_class_init, +}; + +static void armv7m_ras_register_types(void) +{ + type_register_static(&armv7m_ras_info); +} + +type_init(armv7m_ras_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index dffcb651f46..f9d843ce0ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c F: hw/misc/arm_l2x0.c +F: hw/misc/armv7m_ras.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h F: include/hw/timer/a9gtimer.h F: include/hw/timer/arm_mptimer.h F: include/hw/timer/armv7m_systick.h +F: include/hw/misc/armv7m_ras.h F: tests/qtest/test-arm-mptimer.c =20 Exynos diff --git a/hw/misc/meson.build b/hw/misc/meson.build index a53b849a5a0..3f41a3a5b27 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: = files('arm_integrator_d softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) =20 +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) + # Mac devices softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eBt5P+WEQI8XZSApXglAcqpV6GH9r8ahPX4b9vNojmU=; b=r7s/IKp8oryYsJSC49QLz6Ty/y/NycDNw71zn2B/4kWu0ykg3UeKx//Q6YWR8g8H4m FPbxjAaPij9qetHQcMACq8N8c//04qkhQuO/xiLHfFAehJBA2WFA6hCp2jMwUdvzTkSV 4qjtrAzg9aBaNfmoZkBAHuOlQ9jmZcjjuOVQaAJdQbhloVwcuWibFBoxe4+symjBfcCM 85EMYri35w4nS6OYzX33+AMHSTZGVku2eHm0mCbIhMfO0IKfozW/bids08WvQ2+7gJtp FMTLx4YFLoStQV82yiUPrFAvAXS59CuGLylKKCWpCaysBInBn3x441zrjBpuo1BIxmfi xBXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eBt5P+WEQI8XZSApXglAcqpV6GH9r8ahPX4b9vNojmU=; b=B4DDZBm/ViIq1aPwrQUrWXx37jwXVAnRli/UcUAe9kHHb3AT6TtAyv0sPKjxHgTExp 2H1vxabFxaF0tte/VLEfat1e3fmzkHOsRBBEJMM5a52dyhhfvvmONXi9R361OHELCHpH x7TJGKnhQJOClPdjEubnSRMfhIpxYZ78YxkoXFf+8Ym8gWush0zH5F2hS/iCzfyB9Tp3 PbVSjRHttto6XlDdy/4JizFKbvo7z9dTuxlWePS+/CwxzgjisJz49P/sji9Rpw0qXRj3 Lps90QF8z+zIjePBotawAYnCXQzwsm6wqxDA10QnBLeOUlayYCliEA4OyI9YcTrPz5ev U9pw== X-Gm-Message-State: AOAM530JYaDEf5R93ALMXcZPhagcoduivys7rKXLQ2XZ09OYZAKhb1zZ f1wNaxWAV9SRJlIcK9p9F2shWeAQ4DMeXg== X-Google-Smtp-Source: ABdhPJwKluFuNJz5QK8rc1naZ7t+sjtIaewLCKn64BkBqwwk4GbSIDMCzgx1Ia0V90piGV+LPYPP5w== X-Received: by 2002:adf:ded1:: with SMTP id i17mr36161096wrn.303.1630492634867; Wed, 01 Sep 2021 03:37:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/51] arm: Move systick device creation from NVIC to ARMv7M object Date: Wed, 1 Sep 2021 11:36:30 +0100 Message-Id: <20210901103653.13435-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494473834100001 Content-Type: text/plain; charset="utf-8" There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place. This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-3-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 12 ++++ include/hw/intc/armv7m_nvic.h | 4 -- hw/arm/armv7m.c | 125 ++++++++++++++++++++++++++++++++++ hw/intc/armv7m_nvic.c | 73 -------------------- 4 files changed, 137 insertions(+), 77 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 4cae0d7eeaa..360c35c5fb2 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -60,11 +60,23 @@ struct ARMv7MState { BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; ARMv7MRAS ras; + SysTickState systick[M_REG_NUM_BANKS]; =20 /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. */ MemoryRegion container; + /* + * MemoryRegion which passes the transaction to either the S or the + * NS systick device depending on the transaction attributes + */ + MemoryRegion systickmem; + /* + * MemoryRegion which enforces the S/NS handling of the systick + * device NS alias region and passes the transaction to the + * NS systick device if appropriate. + */ + MemoryRegion systick_ns_mem; =20 /* Properties */ char *cpu_type; diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 33b6d8810c7..6a6a99090c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -81,16 +81,12 @@ struct NVICState { =20 MemoryRegion sysregmem; MemoryRegion sysreg_ns_mem; - MemoryRegion systickmem; - MemoryRegion systick_ns_mem; MemoryRegion container; MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; qemu_irq sysresetreq; - - SysTickState systick[M_REG_NUM_BANKS]; }; =20 #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8964730d153..364ac069702 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -124,6 +124,85 @@ static const hwaddr bitband_output_addr[ARMV7M_NUM_BIT= BANDS] =3D { 0x22000000, 0x42000000 }; =20 +static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + MemoryRegion *mr =3D opaque; + + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attr= s); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; + } +} + +static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + MemoryRegion *mr =3D opaque; + + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_TE, attrs= ); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; + } +} + +static const MemoryRegionOps v7m_sysreg_ns_ops =3D { + .read_with_attrs =3D v7m_sysreg_ns_read, + .write_with_attrs =3D v7m_sysreg_ns_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + ARMv7MState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attrs); +} + +static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + ARMv7MState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, + attrs); +} + +static const MemoryRegionOps v7m_systick_ops =3D { + .read_with_attrs =3D v7m_systick_read, + .write_with_attrs =3D v7m_systick_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static void armv7m_instance_init(Object *obj) { ARMv7MState *s =3D ARMV7M(obj); @@ -137,6 +216,13 @@ static void armv7m_instance_init(Object *obj) object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq"); =20 + object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS], + TYPE_SYSTICK); + /* + * We can't initialize the secure systick here, as we don't know + * yet if we need it. + */ + for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { object_initialize_child(obj, "bitband[*]", &s->bitband[i], TYPE_BITBAND); @@ -231,6 +317,45 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 + /* Create and map the systick devices */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, + qdev_get_gpio_in_named(DEVICE(&s->nvic), + "systick-trigger", M_REG_NS)= ); + + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + /* + * We couldn't init the secure systick device in instance_init + * as we didn't know then if the CPU had the security extensions; + * so we have to do it here. + */ + object_initialize_child(OBJECT(dev), "systick-reg-s", + &s->systick[M_REG_S], TYPE_SYSTICK); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, + qdev_get_gpio_in_named(DEVICE(&s->nvic), + "systick-trigger", M_REG= _S)); + } + + memory_region_init_io(&s->systickmem, OBJECT(s), + &v7m_systick_ops, s, + "v7m_systick", 0xe0); + + memory_region_add_subregion_overlap(&s->container, 0xe000e010, + &s->systickmem, 1); + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + memory_region_init_io(&s->systick_ns_mem, OBJECT(s), + &v7m_sysreg_ns_ops, &s->systickmem, + "v7m_systick_ns", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0xe002e010, + &s->systick_ns_mem, 1); + } + /* If the CPU has RAS support, create the RAS register block */ if (cpu_isar_feature(aa32_ras, s->cpu)) { object_initialize_child(OBJECT(dev), "armv7m-ras", diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a5975592dfa..2b3e79a3da9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2517,38 +2517,6 @@ static const MemoryRegionOps nvic_sysreg_ns_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - NVICState *s =3D opaque; - MemoryRegion *mr; - - /* Direct the access to the correct systick */ - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attrs); -} - -static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - NVICState *s =3D opaque; - MemoryRegion *mr; - - /* Direct the access to the correct systick */ - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, - attrs); -} - -static const MemoryRegionOps nvic_systick_ops =3D { - .read_with_attrs =3D nvic_systick_read, - .write_with_attrs =3D nvic_systick_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2801,29 +2769,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) =20 s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; =20 - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, - qdev_get_gpio_in_named(dev, "systick-trigger", - M_REG_NS)); - - if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { - /* We couldn't init the secure systick device in instance_init - * as we didn't know then if the CPU had the security extensions; - * so we have to do it here. - */ - object_initialize_child(OBJECT(dev), "systick-reg-s", - &s->systick[M_REG_S], TYPE_SYSTICK); - - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, - qdev_get_gpio_in_named(dev, "systick-trigger", - M_REG_S)); - } - /* * This device provides a single sysbus memory region which * represents the whole of the "System PPB" space. This is the @@ -2877,23 +2822,11 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) "nvic_sysregs", 0x1000); memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); =20 - memory_region_init_io(&s->systickmem, OBJECT(s), - &nvic_systick_ops, s, - "nvic_systick", 0xe0); - - memory_region_add_subregion_overlap(&s->container, 0xe010, - &s->systickmem, 1); - if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); - memory_region_init_io(&s->systick_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, &s->systickmem, - "nvic_systick_ns", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x2e010, - &s->systick_ns_mem, 1); } =20 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); @@ -2905,12 +2838,6 @@ static void armv7m_nvic_instance_init(Object *obj) NVICState *nvic =3D NVIC(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS= ], - TYPE_SYSTICK); - /* We can't initialize the secure systick here, as we don't know - * yet if we need it. - */ - sysbus_init_irq(sbd, &nvic->excpout); qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493389; cv=none; d=zohomail.com; s=zohoarc; b=BK4GPNHWe+DOM5W0t5gJj6j9dZdQvwdqSOaCYsIEnFby8qpB9wBE2dG5dNrrVU5F2a3z+LRL17EnTYzKclT8vOqee3CyP//UUPLmS0Q/XrxALOqmiDN0vzD9Pb3d5RSzIbINp7TqoyLmdPKTwa9nfbv4SjaiMk4oGUjk440gmsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493389; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=41L8u27j8vHYUKkU+btlgtEvGEpOUd/O3/eo2ddhcf0=; b=k5bU9XLWZxjsM6hKUCWZQ7VejF0qHpWeOPDI9AHUtZ6qA4xVN4K+FqPqMj8GcgisR5YA2ri5i/fHOH/yn6jfp+b1H9wkZuoenZ4X2JsPhoOoHsmU9ObwQbymit4ahtY267UIOMiwOaYDhSAL00BlySBBVLbR0qsFz0JYzPbmcQM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163049338998752.79764515707143; Wed, 1 Sep 2021 03:49:49 -0700 (PDT) Received: from localhost ([::1]:48436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNoS-0003Wu-Rz for importer@patchew.org; Wed, 01 Sep 2021 06:49:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcS-0007Aj-1P for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:25 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcK-0005rS-Uk for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:23 -0400 Received: by mail-wm1-x32e.google.com with SMTP id d22-20020a1c1d16000000b002e7777970f0so4387251wmd.3 for ; Wed, 01 Sep 2021 03:37:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=41L8u27j8vHYUKkU+btlgtEvGEpOUd/O3/eo2ddhcf0=; b=bVWF8VPotSFvgCCuY9rlgws0tYhRF2NNqxzTQsiGzcEGgInHm/UTo9Cd8f8ZfG5Jhx AEN850U6VFHRLXTF/tb9hqd4eH8Umxlw2/rTkVj4CWnlbogmhiVp2X8uWIGYDrZv7sI0 WexsigxWU/kcnDltLlmDi+WAGWPKGZma//9g/y53TqytINGyYeVEsK7nCmkdgStS7kv6 VSbdbrvVQ6XO1KRje2kky3AWvoSvXODnPMmh2t/qYV85R8QMz2PPgRqAVcxQRmllwwsG SkJAgCsw1zxgnzXkimCPzs0fJPFnPTpA05nCwZQLP7L4jIBYA+96pn7GID/Od7H+tRql 2q2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=41L8u27j8vHYUKkU+btlgtEvGEpOUd/O3/eo2ddhcf0=; b=uTWnFt8i9sOxYfTUzcIVe9jvTMSzpbitzUL+5JTRDcSCAupfbk3i5g0yIc3C4keEu2 NLgOETpJY80lxhRhANTP7ZU1CrmNU9NtdZ6qulWIupyMgwRg7a96vdG+Cw/Ktq83UIQU JcVwCRUEmp7aS2jrWT5B6UJNgqnSTriN/NYz99La70TQDEfQZXCtxClrT8FeIAakVO59 o/tBbj37YgvnjmMfqmVgxFoav7czIWUnUGxmxBUtfMNix0DDI+rGvhgYsWEeUI/HPHRg i2yvIHvZzcoUrv8hYFSbtju18DrkOrCk3W3snBwmMJsIXVdfDCVvOUUkkrDmnecVFy2e ydEw== X-Gm-Message-State: AOAM530RBkX9Ta77aJMvJXTE/jBD0C37VayUT0PmWqVP79ctNb+7s1Rp vFFfWo8j8BAKGcYnTc+eEUXFECNpEN78jQ== X-Google-Smtp-Source: ABdhPJyKPjSejC//wJsRfKISWGLmNpLY1jWFrV92ixTTfvdjDU9z57CcJ8AEmYtsBmdWWpvcYqN6YQ== X-Received: by 2002:a1c:a9d2:: with SMTP id s201mr8718043wme.81.1630492635584; Wed, 01 Sep 2021 03:37:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/51] arm: Move system PPB container handling to armv7m Date: Wed, 1 Sep 2021 11:36:31 +0100 Message-Id: <20210901103653.13435-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493391183100001 Content-Type: text/plain; charset="utf-8" Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Luc Michel Message-id: 20210812093356.1946-4-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 4 + include/hw/intc/armv7m_nvic.h | 3 - hw/arm/armv7m.c | 100 ++++++++++++++++++++++- hw/intc/armv7m_nvic.c | 145 +--------------------------------- 4 files changed, 107 insertions(+), 145 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 360c35c5fb2..fe8b248a6c6 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -77,6 +77,10 @@ struct ARMv7MState { * NS systick device if appropriate. */ MemoryRegion systick_ns_mem; + /* Ditto, for the sysregs region provided by the NVIC */ + MemoryRegion sysreg_ns_mem; + /* MR providing default PPB behaviour */ + MemoryRegion defaultmem; =20 /* Properties */ char *cpu_type; diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 6a6a99090c7..0180c7b0ca1 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -80,9 +80,6 @@ struct NVICState { int vectpending_prio; /* group prio of the exeception in vectpending */ =20 MemoryRegion sysregmem; - MemoryRegion sysreg_ns_mem; - MemoryRegion container; - MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 364ac069702..899159f70b1 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -18,6 +18,7 @@ #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "qemu/log.h" #include "target/arm/idau.h" =20 /* Bitbanded IO. Each word corresponds to a single bit. */ @@ -203,6 +204,43 @@ static const MemoryRegionOps v7m_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +/* + * Unassigned portions of the PPB space are RAZ/WI for privileged + * accesses, and fault for non-privileged accesses. + */ +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; +} + +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ppb_default_ops =3D { + .read_with_attrs =3D ppb_default_read, + .write_with_attrs =3D ppb_default_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, +}; + static void armv7m_instance_init(Object *obj) { ARMv7MState *s =3D ARMV7M(obj); @@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **= errp) qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); =20 + /* + * We map various devices into the container MR at their architected + * addresses. In particular, we map everything corresponding to the + * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff + * and includes the NVIC, the System Control Space (system registers), + * the systick timer, and for CPUs with the Security extension an NS + * banked version of all of these. + * + * The default behaviour for unimplemented registers/ranges + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) + * is to RAZ/WI for privileged access and BusFault for non-privileged + * access. + * + * The NVIC and System Control Space (SCS) starts at 0xe000e000 + * and looks like this: + * 0x004 - ICTR + * 0x010 - 0xff - systick + * 0x100..0x7ec - NVIC + * 0x7f0..0xcff - Reserved + * 0xd00..0xd3c - SCS registers + * 0xd40..0xeff - Reserved or Not implemented + * 0xf00 - STIR + * + * Some registers within this space are banked between security states. + * In v8M there is a second range 0xe002e000..0xe002efff which is the + * NonSecure alias SCS; secure accesses to this behave like NS accesses + * to the main SCS range, and non-secure accesses (including when + * the security extension is not implemented) are RAZ/WI. + * Note that both the main SCS range and the alias range are defined + * to be exempt from memory attribution (R_BLJT) and so the memory + * transaction attribute always matches the current CPU security + * state (attrs.secure =3D=3D env->v7m.secure). In the v7m_sysreg_ns_o= ps + * wrappers we change attrs.secure to indicate the NS access; so + * generally code determining which banked register to use should + * use attrs.secure; code determining actual behaviour of the system + * should use env->v7m.secure. + * + * Within the PPB space, some MRs overlap, and the priority + * of overlapping regions is: + * - default region (for RAZ/WI and BusFault) : -1 + * - system register regions (provided by the NVIC) : 0 + * - systick : 1 + * This is because the systick device is a small block of registers + * in the middle of the other system control registers. + */ + + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, + "nvic-default", 0x100000); + memory_region_add_subregion_overlap(&s->container, 0xe0000000, + &s->defaultmem, -1); + /* Wire the NVIC up to the CPU */ sbd =3D SYS_BUS_DEVICE(&s->nvic); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); =20 - memory_region_add_subregion(&s->container, 0xe0000000, + memory_region_add_subregion(&s->container, 0xe000e000, sysbus_mmio_get_region(sbd, 0)); + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + /* Create the NS alias region for the NVIC sysregs */ + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), + &v7m_sysreg_ns_ops, + sysbus_mmio_get_region(sbd, 0), + "nvic_sysregs_ns", 0x1000); + memory_region_add_subregion(&s->container, 0xe002e000, + &s->sysreg_ns_mem); + } =20 /* Create and map the systick devices */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b3e79a3da9..13df002ce4d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2470,90 +2470,6 @@ static const MemoryRegionOps nvic_sysreg_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - MemoryRegion *mr =3D opaque; - - if (attrs.secure) { - /* S accesses to the alias act like NS accesses to the real region= */ - attrs.secure =3D 0; - return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attr= s); - } else { - /* NS attrs are RAZ/WI for privileged, and BusFault for user */ - if (attrs.user) { - return MEMTX_ERROR; - } - return MEMTX_OK; - } -} - -static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - MemoryRegion *mr =3D opaque; - - if (attrs.secure) { - /* S accesses to the alias act like NS accesses to the real region= */ - attrs.secure =3D 0; - return memory_region_dispatch_read(mr, addr, data, - size_memop(size) | MO_TE, attrs= ); - } else { - /* NS attrs are RAZ/WI for privileged, and BusFault for user */ - if (attrs.user) { - return MEMTX_ERROR; - } - *data =3D 0; - return MEMTX_OK; - } -} - -static const MemoryRegionOps nvic_sysreg_ns_ops =3D { - .read_with_attrs =3D nvic_sysreg_ns_read, - .write_with_attrs =3D nvic_sysreg_ns_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -/* - * Unassigned portions of the PPB space are RAZ/WI for privileged - * accesses, and fault for non-privileged accesses. - */ -static MemTxResult ppb_default_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", - (uint32_t)addr); - if (attrs.user) { - return MEMTX_ERROR; - } - *data =3D 0; - return MEMTX_OK; -} - -static MemTxResult ppb_default_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", - (uint32_t)addr); - if (attrs.user) { - return MEMTX_ERROR; - } - return MEMTX_OK; -} - -static const MemoryRegionOps ppb_default_ops =3D { - .read_with_attrs =3D ppb_default_read, - .write_with_attrs =3D ppb_default_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 8, -}; - static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -2770,66 +2686,13 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; =20 /* - * This device provides a single sysbus memory region which - * represents the whole of the "System PPB" space. This is the - * range from 0xe0000000 to 0xe00fffff and includes the NVIC, - * the System Control Space (system registers), the systick timer, - * and for CPUs with the Security extension an NS banked version - * of all of these. - * - * The default behaviour for unimplemented registers/ranges - * (for instance the Data Watchpoint and Trace unit at 0xe0001000) - * is to RAZ/WI for privileged access and BusFault for non-privileged - * access. - * - * The NVIC and System Control Space (SCS) starts at 0xe000e000 - * and looks like this: - * 0x004 - ICTR - * 0x010 - 0xff - systick - * 0x100..0x7ec - NVIC - * 0x7f0..0xcff - Reserved - * 0xd00..0xd3c - SCS registers - * 0xd40..0xeff - Reserved or Not implemented - * 0xf00 - STIR - * - * Some registers within this space are banked between security states. - * In v8M there is a second range 0xe002e000..0xe002efff which is the - * NonSecure alias SCS; secure accesses to this behave like NS accesses - * to the main SCS range, and non-secure accesses (including when - * the security extension is not implemented) are RAZ/WI. - * Note that both the main SCS range and the alias range are defined - * to be exempt from memory attribution (R_BLJT) and so the memory - * transaction attribute always matches the current CPU security - * state (attrs.secure =3D=3D env->v7m.secure). In the nvic_sysreg_ns_= ops - * wrappers we change attrs.secure to indicate the NS access; so - * generally code determining which banked register to use should - * use attrs.secure; code determining actual behaviour of the system - * should use env->v7m.secure. - * - * The container covers the whole PPB space. Within it the priority - * of overlapping regions is: - * - default region (for RAZ/WI and BusFault) : -1 - * - system register regions : 0 - * - systick : 1 - * This is because the systick device is a small block of registers - * in the middle of the other system control registers. + * This device provides a single memory region which covers the + * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the + * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF. */ - memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); - memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, - "nvic-default", 0x100000); - memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, = -1); memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); - memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); - - if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { - memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, &s->sysregmem, - "nvic_sysregs_ns", 0x1000); - memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); - } - - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem); } =20 static void armv7m_nvic_instance_init(Object *obj) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493189; cv=none; d=zohomail.com; s=zohoarc; b=Zu+2DUuDEQAITFavE6h800Z1t+P/ftyfRdMTtm60aoTrcb+gAqFkY/QW03sYYdbV6QUhRzTxWEz75ZNHWKm3UPR4YieKVTQaZUhI4AXwmQqFplYDVJjEHOAOMvfaemALt1iM/c9WoPE2eZF7wN2Dx7La//hT1G6M2dpo0LApLCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493189; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qx8wsOMhtL2NtE+ycWwK1nQUW28qH1evLQrUvakhzE0=; b=du9Gc+81I2i2GX1Wo07V7NWmv1/oJYajSrggkjyUkVDGJJOUWrC9SGlwWL/Ps7HkaAaHj5Cr/CWyQMJAbj+6tfYQ/hm4PJDGfB3xWfh79RKa7/9ENHUwUTJQrCMw+iqtiSr6WxjdqbxWB5Jy8f8tzVPMWPFLGN+xuczMN9xAVa4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493189214389.55793930576647; Wed, 1 Sep 2021 03:46:29 -0700 (PDT) Received: from localhost ([::1]:39816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNlD-00069P-Ih for importer@patchew.org; Wed, 01 Sep 2021 06:46:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcO-00078n-Ux for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:20 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:40675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcL-0005sN-FD for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:20 -0400 Received: by mail-wm1-x32c.google.com with SMTP id x2-20020a1c7c02000000b002e6f1f69a1eso4372877wmc.5 for ; Wed, 01 Sep 2021 03:37:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qx8wsOMhtL2NtE+ycWwK1nQUW28qH1evLQrUvakhzE0=; b=mObLd0wL3pG6jt4vXlwYBCTsV2ygYUvQFsL4+13vixOCjsOGhmhxO37M3xfl01pGug 43xuEHDGUvTLYB/8W3TqAsApXtevQa0ET62mH0QYtPZb4NO/9JMvpkhhmjMy6UFYsT4A +fXxmKNhVNTzx4SomUSWpg4hLL5H1mlb4JKWNnpobng9w5gvadPQ9Qk0bnht/epoq6qM 3MknmutnUEb7dwvh0CU2aoMY7IQ3aUW2LlOd0roc4GYttynWGTPCthBfJjJpMkCS/UJ+ lhiLZjQJ7Aqxz3bt7QGG9EgwkVDVvFjjiBk0zSnWA32ocxo61/ZiyU5up34SQg1lBhsw ZtXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qx8wsOMhtL2NtE+ycWwK1nQUW28qH1evLQrUvakhzE0=; b=Com3ClDYuJhjFqYf5GpxT6VtXk4bnMeb5cRxdiVcLIIJM93oP+TD0p45J2smluhzNy uQkuuFUPU5FPLvBS51EkNZZO0MiCU5ii9NxNpPxxduLjieGtfYK0BvAJF5OsBxE1mSPt cg/yYJJ0y6Uueci2RcH6CBUTetJD6JkHDeA5Q/ZwbVAtZUriSDvUxDSlS/mlEcAX0dXn MHsLhvrHmT8kQE5rwkkAfVuxNDvi1WwmHO1Dv4ZnGUD/Um462159TlBE6VUir1PpUtb+ LiRW4VlHPbLQ2LrCOJ2TpmooHIVSDXOSLQo6tmwoGGv3BLNeu675rIFZVFsf637khzPa W6kg== X-Gm-Message-State: AOAM533Zye0uLhHV9RPrV11fIagdny2u0Lu5AIkrR9GDzx7uoG/awIhv +pUQFqFs4nRhz6H7gODbfX+efi2NQY/Hmw== X-Google-Smtp-Source: ABdhPJyI6lfN2uG2lDm3OVpqtXU8lKQ6ed06CB7MYK0JDTKh2X6kIJiiXvCNQ6BsGhIR0mKGCG8Keg== X-Received: by 2002:a1c:f30b:: with SMTP id q11mr8915602wmq.91.1630492636148; Wed, 01 Sep 2021 03:37:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/51] hw/timer/armv7m_systick: Add usual QEMU interface comment Date: Wed, 1 Sep 2021 11:36:32 +0100 Message-Id: <20210901103653.13435-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493190891100001 Content-Type: text/plain; charset="utf-8" Add the usual-style QEMU interface comment documenting what properties, etc, this device exposes. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-5-peter.maydell@linaro.org --- include/hw/timer/armv7m_systick.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 84496faaf96..685fc5bc0d7 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -20,6 +20,13 @@ =20 OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK) =20 +/* + * QEMU interface: + * + sysbus MMIO region 0 is the register interface (covering + * the registers which are mapped at address 0xE000E010) + * + sysbus IRQ 0 is the interrupt line to the NVIC + */ + struct SysTickState { /*< private >*/ SysBusDevice parent_obj; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494209; cv=none; d=zohomail.com; s=zohoarc; b=UVC1HSuMs6F0sq4o/LKp2K88NJ6cqw+QJO0Qz0GQP+DjFQv+CyUnTSQfSoxzAhIFXo5Deu3g2BYrFHdwhaMEqKvGnMHikGqOOJJzvwE0VoDKo7Q65+1lsQCNfL+5J7OlQJn1/F3mVALVTQcA9f+nycD5FtbgQkNrnPyQyOUSgMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494209; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7K40W+n2BmNQl8Ueq80FHzUsouD+Q77Hv2+ZcA1BX38=; b=Ns29Xzq/K1rSkV0rEQxzdGZJSN0qhAoLDKnyeV9iIGxQSWOqwvsafK8kqerdNs99uR5UxrhiZt2yTzZJl5v19uRFlgZsTXKQe64XHqABiVOLYnEyPKWIQ4+otqjrKPJ7AjuUyMPRoSwlcbYUHv83KGnwNx4juFe8MXKbRbyOJuk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494209353485.34771224602196; Wed, 1 Sep 2021 04:03:29 -0700 (PDT) Received: from localhost ([::1]:56548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO1g-0002ms-50 for importer@patchew.org; Wed, 01 Sep 2021 07:03:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcR-0007Ai-UK for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:25 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:40679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcM-0005sn-O6 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:22 -0400 Received: by mail-wm1-x330.google.com with SMTP id x2-20020a1c7c02000000b002e6f1f69a1eso4372898wmc.5 for ; Wed, 01 Sep 2021 03:37:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7K40W+n2BmNQl8Ueq80FHzUsouD+Q77Hv2+ZcA1BX38=; b=ID0oCYKIma52uVgmslopmEhKlJi7MG8z1KkEzzjRMef8BMMwceqmGL7CZ2KUWdWm4G bH7GJq2Xo8z9yUMeNqvZcHWKukp68M9gXrkKUs9HJVzxtLEvlc3vlOxABcHcDxwXKozU 2BgQdSf6zFbCZBFhP6I4Msjq87lbGn4tnJECMKdB61JsfPldvfCTQiNJDmhcfprLidGB NJT9c8WxXnSmqNypAhbPcoORXyB4yHREVJMXEOnBzwV0vH9pjtFyS/ryrmZFhkOCAtzw iEPmRpj9OxpbX2fo8jYBVFqh+Pn2GQ2wYPCfBG3S2lj2NG14qDFs8mckc6gugWSzH4bE +xiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7K40W+n2BmNQl8Ueq80FHzUsouD+Q77Hv2+ZcA1BX38=; b=pPQVhuufB4B5bOlzAqTdJej8E7QwW+FNoXSKeE96YpAbFmC5g2UCdOv5Fn3usbDlIx uGqj3FVle52iLwIDBw5tiQTSjA94uTpr3vxL3zmNp9yS1SGqW4VnmEh8a/NhW2c17Bb/ mj1S8riZVCLv5uBZDvnXkK5ZJZ/M/4Ug5BOD0hxdxzIRcPkpTcUj0ynA+jYUzxFh2YQJ GVFY4/hXY8yu8pX3nGKXtub1qLj6Ck4RO7PVxOMrzLcz0pHm+bFKCRjnw0p4+e9+RWkx 1ql8/9oPIXkGppGgZxlqM3HAV+2e5/uNEgiUY9khk2sszdkoAe6WSEH7pZXadVIfi8Nf T/cg== X-Gm-Message-State: AOAM530nboBe+HD7DBK1X3fUc3lOl4aYI3BV5fQjUlEJTpmZuWOZe0S3 KAlw3B7V/6OJAN/m5TbgA8ePAOY0aayPPg== X-Google-Smtp-Source: ABdhPJwIxt3Z6L9csgX5hm8wIeqMgQw0+HW2A5aLrhDUPA0t2EdPtHS6Hmzka0mSosBZHTKiINbm5A== X-Received: by 2002:a1c:3b05:: with SMTP id i5mr8963348wma.136.1630492636774; Wed, 01 Sep 2021 03:37:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/51] hw/timer/armv7m_systick: Add input clocks Date: Wed, 1 Sep 2021 11:36:33 +0100 Message-Id: <20210901103653.13435-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494210089100003 Content-Type: text/plain; charset="utf-8" The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE =3D=3D 0) * the main CPU clock (when SYST_CSR.CLKSOURCE =3D=3D 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-6-peter.maydell@linaro.org --- include/hw/timer/armv7m_systick.h | 7 +++++++ hw/timer/armv7m_systick.c | 10 ++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 685fc5bc0d7..38adf8d274e 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "qom/object.h" #include "hw/ptimer.h" +#include "hw/clock.h" =20 #define TYPE_SYSTICK "armv7m_systick" =20 @@ -25,6 +26,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK) * + sysbus MMIO region 0 is the register interface (covering * the registers which are mapped at address 0xE000E010) * + sysbus IRQ 0 is the interrupt line to the NVIC + * + Clock input "refclk" is the external reference clock + * (used when SYST_CSR.CLKSOURCE =3D=3D 0) + * + Clock input "cpuclk" is the main CPU clock + * (used when SYST_CSR.CLKSOURCE =3D=3D 1) */ =20 struct SysTickState { @@ -38,6 +43,8 @@ struct SysTickState { ptimer_state *ptimer; MemoryRegion iomem; qemu_irq irq; + Clock *refclk; + Clock *cpuclk; }; =20 /* diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index 2f192011eb0..e43f74114e8 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" @@ -201,6 +202,9 @@ static void systick_instance_init(Object *obj) memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0= ); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); } =20 static void systick_realize(DeviceState *dev, Error **errp) @@ -215,9 +219,11 @@ static void systick_realize(DeviceState *dev, Error **= errp) =20 static const VMStateDescription vmstate_systick =3D { .name =3D "armv7m_systick", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(refclk, SysTickState), + VMSTATE_CLOCK(cpuclk, SysTickState), VMSTATE_UINT32(control, SysTickState), VMSTATE_INT64(tick, SysTickState), VMSTATE_PTIMER(ptimer, SysTickState), --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494403; cv=none; d=zohomail.com; s=zohoarc; b=ThBH621f+KcHb16RvipKiT/gE+I9kTe+tbmm1x35scrTVMSebqBZho8u0Gt+AUmDYM9YKHiGJl9IZQyiu6PJfjb1ovzV+Q7RzTpTZZJBiMj9s/Wt0CKV7XTm3dHH0ksT0+wi4cRJjtorDKoHtPfoZchzF6s3Go/juxtOJgiGu/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494403; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LskhgeDFxMSe9BFJVw4Kt1/jQ0fSUufDcVp7/+pC9/A=; b=DrUanzyIhS1l+Ype21X6EJdrVJZOq7XEFth/HO/meMhszy9FhII/wCv9ggCp5YhU+9oK25h0oMRM9QITbgMWHN1gDCOEDrRnAGp0R6L188oYvc1l7IhQx9NEu9o9BKwWXRDc5iWsOXMkDXBvGvGfDdCxWZkbi8DZGwxG25DNGjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494403754655.156303606022; Wed, 1 Sep 2021 04:06:43 -0700 (PDT) Received: from localhost ([::1]:34466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO4o-0007Dd-Mg for importer@patchew.org; Wed, 01 Sep 2021 07:06:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcS-0007Am-O7 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:25 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcN-0005tY-I7 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:24 -0400 Received: by mail-wr1-x430.google.com with SMTP id q14so3763640wrp.3 for ; Wed, 01 Sep 2021 03:37:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LskhgeDFxMSe9BFJVw4Kt1/jQ0fSUufDcVp7/+pC9/A=; b=lR0gZfpCyRpistYNqp66Nfu54FhSoq8ra5CyxWQBNRrKb2b6tvqIYVL43JZrOc962n jektqxfJoNHYsu0Xg8vTT+1pmxu8RvXXlHNJp4+VqOMaWs/+E2TGE8IIq5dAzqzmh9qV vFKrvcX44hFp5QfLpPdzokST4lGO147ERB+1yD4SKHHOmDwpWfZPkpY7MMaZdHLcJn2p 43808ElyX/GFomOOuJO0R6eqdM51k267OPIe25XRXqiQG/wQJghhqh5QtUkgSlEVwxTg tS9ed6hWKQQdMyTSo1d8jBOwTcw8mVn7Ryp7jWvUTDaTG38/mPB/meN28A+4iaX6aDoe AIIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LskhgeDFxMSe9BFJVw4Kt1/jQ0fSUufDcVp7/+pC9/A=; b=fGLJnnyfeIISFGidzRpyXsxcSE2BGcB6zJAgBBaymVSylUwsS0lPGXgBKLyH+vi8Wg EBcGpN6tQ/RhboZxvKIoLEKvE2RLh0EDuA3oPKouL/8Nn4sC9XgjMGScZ8LKLfp5DQQ8 S0VPoGn6OBD91bTBx2HsxtQ788GIjaofsBr/JkacAZ1W/H4XSmR+++bbGiNPOnVMQe9O gnzb3zRACUtKF829IaRg0IRlYJv4Ml2hVqfUkfbEIfTpv9qPEa7vbgksFe9+hQOrNpTd P2FooNbbLpH2zE5EcZW2vhQanH0ZDophUiIPdO4bO5qm7J+2tTeU2xXvP2nT88n/5RCu 87cw== X-Gm-Message-State: AOAM531EWK0BC7S84sbPwPez+tJ2iVDjLJfHjmsCfH0/Vzhu1F/KCanw eoFKSBS87A+BcRq/qDsUBkZ5mWxF68q99Q== X-Google-Smtp-Source: ABdhPJwiqOmTXJmryOtBGr/alf/cj56/nyaHFJXrggNd6NTpBoDk5tZs2zMXCguhERsRzZ00/rP8qw== X-Received: by 2002:a5d:6149:: with SMTP id y9mr37430096wrt.162.1630492637401; Wed, 01 Sep 2021 03:37:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/51] hw/arm/armv7m: Create input clocks Date: Wed, 1 Sep 2021 11:36:34 +0100 Message-Id: <20210901103653.13435-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494405550100003 Content-Type: text/plain; charset="utf-8" Create input clocks on the armv7m container object which pass through to the systick timers, so that users of the armv7m object can specify the clocks being used. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-7-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 6 ++++++ hw/arm/armv7m.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index fe8b248a6c6..b7ba0ff409c 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -15,6 +15,7 @@ #include "hw/misc/armv7m_ras.h" #include "target/arm/idau.h" #include "qom/object.h" +#include "hw/clock.h" =20 #define TYPE_BITBAND "ARM-bitband-memory" OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND) @@ -51,6 +52,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO + * + Clock input "refclk" is the external reference clock for the systick = timers + * + Clock input "cpuclk" is the main CPU clock */ struct ARMv7MState { /*< private >*/ @@ -82,6 +85,9 @@ struct ARMv7MState { /* MR providing default PPB behaviour */ MemoryRegion defaultmem; =20 + Clock *refclk; + Clock *cpuclk; + /* Properties */ char *cpu_type; /* MemoryRegion the board provides to us (with its devices, RAM, etc) = */ diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 899159f70b1..8d08db80be8 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -14,12 +14,14 @@ #include "hw/arm/boot.h" #include "hw/loader.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "elf.h" #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/log.h" #include "target/arm/idau.h" +#include "migration/vmstate.h" =20 /* Bitbanded IO. Each word corresponds to a single bit. */ =20 @@ -265,6 +267,9 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "bitband[*]", &s->bitband[i], TYPE_BITBAND); } + + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); } =20 static void armv7m_realize(DeviceState *dev, Error **errp) @@ -416,6 +421,8 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) } =20 /* Create and map the systick devices */ + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refc= lk); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuc= lk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { return; } @@ -431,6 +438,10 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) */ object_initialize_child(OBJECT(dev), "systick-reg-s", &s->systick[M_REG_S], TYPE_SYSTICK); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", + s->refclk); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk", + s->cpuclk); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { return; @@ -504,11 +515,23 @@ static Property armv7m_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static const VMStateDescription vmstate_armv7m =3D { + .name =3D "armv7m", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(refclk, SysTickState), + VMSTATE_CLOCK(cpuclk, SysTickState), + VMSTATE_END_OF_LIST() + } +}; + static void armv7m_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D armv7m_realize; + dc->vmsd =3D &vmstate_armv7m; device_class_set_props(dc, armv7m_properties); } =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494645; cv=none; d=zohomail.com; s=zohoarc; b=njGmfQLAuG1E2AOM/N8LV3KRc/IcauYOZImWEFRHMZIBupl/gOwGhk28ByXaf91rMSxZ+5+8slJXWiFRuY4IQDuOUO4/yKLIOGLjHS1ga19LmsePwc4hSxgKSJIKk+klNmv+Kq3Gbb/gbEpEJTGc5oFQPysC6/Z7RdKpZa/UpHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494645; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X6DKKwrxjW32EfCvSWfAmj3EcMaeoYEpjbuklyKkPSQ=; b=LCyRKRcFmLy7KyXA/BnJTn2sn/bAvH2+LOV+HeSV98rN+73aZGbxuAIjhL8cS1uOfUutYnEZqsxTtb+tUFW6p9fzc4+umI48Axca2aYuukCRQm4CsCvnyrAfuTY6WG4OlWGV7rsz7zhr+OiPkv7gim0pmhmVj9e73Ape6N9q4F4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494645834281.292773264008; Wed, 1 Sep 2021 04:10:45 -0700 (PDT) Received: from localhost ([::1]:41102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO8i-00046U-SV for importer@patchew.org; Wed, 01 Sep 2021 07:10:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcS-0007Al-Kj for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:26 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:51162) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcN-0005tb-IK for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:24 -0400 Received: by mail-wm1-x32b.google.com with SMTP id m2so1549242wmm.0 for ; Wed, 01 Sep 2021 03:37:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X6DKKwrxjW32EfCvSWfAmj3EcMaeoYEpjbuklyKkPSQ=; b=EFMhro5mF3RMnoJ48ODZ81uaFRHes4WXMYfRUAsAIkhSWZreDmqk83r0ExmFEe9SF2 snSTRKEz7JfuxCpSg+fhhwrVnqgqHzOVTwUJhq5L+K3KyFWCIV+LvvJMmJOt+oJsZ3bO sObLVmgi3Tp0Z/k50AE+DOklJGWWQ/XsuVmwulUBESZXvi9bZSMKhy4UgicWxm0Bp8Jb v3W4dpdx/dhhRL0aA+hOV9WVwCD0vWh1eGcp33UyO6Jdz0Cirmyw69mDtQZfUWonj48F Km2XR02IPx04TzaBg2HNvCXo/buecvDklLqJIumC24Z/zDZGqNMD/EDQM0LPHQ09UX7u xx1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X6DKKwrxjW32EfCvSWfAmj3EcMaeoYEpjbuklyKkPSQ=; b=b5l8RmKz7fXCB6wKfaYtR6fFG+1F4LnOqqTKUJqTrem5tA6RLSUmJo9stqAy6l5LKi F9pxm2P2cj91HdvmIUI5uBmKxGp1EWSMQ/Ge6slpHXyr31canbt9WCTwS4/E3YDj2+F8 AR+YFZVuAcyzyxRmBrBvSRly0mTtxCdic6K3W4PVKkFlmfT/vVqIfartyRr8V0AQlN7S QXV9tTUeuC5qw45Jg6wVjHbwDr82FEFw5BJLzKM6NWP/Gy5qN9147F4rZqJfZ57pWMSY oNxMmg5dF+mi13/FRChrW1cAOE//4OYpYB4rWlYfIpIou8cAKskXmTQ1uuVHYEUaS8Ja NHQw== X-Gm-Message-State: AOAM5302yYT9X6XXfFkmIbK5pPe7jE8/YBtHM1azlJ8xVZ/xwwekaFP/ YHdvfsdE0YbTtNeuGm0P7iWD8+czT4VM/w== X-Google-Smtp-Source: ABdhPJxwUi1Knzdn0GxDwLY8Sjl2s2MGhWix7EV5C6mmV697XXIfBFEl7pgUI9vBN0cKhiosMBrvUQ== X-Received: by 2002:a7b:c30f:: with SMTP id k15mr9043445wmj.128.1630492637994; Wed, 01 Sep 2021 03:37:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/51] armsse: Wire up systick cpuclk clock Date: Wed, 1 Sep 2021 11:36:35 +0100 Message-Id: <20210901103653.13435-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494647902100001 Content-Type: text/plain; charset="utf-8" Wire up the cpuclk for the systick devices to the SSE object's existing mainclk clock. We do not wire up the refclk because the SSE subsystems do not provide a refclk. (This is documented in the IoTKit and SSE-200 TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the same approach.) When we update the systick device later to honour "no refclk connected" this will fix a minor emulation inaccuracy for the SSE-based boards. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-8-peter.maydell@linaro.org --- hw/arm/armsse.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index a1456cb0f42..70b52c3d4b9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) int j; char *gpioname; =20 + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk); + /* The SSE subsystems do not wire up a systick refclk */ + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IR= QS); /* * In real hardware the initial Secure VTOR is set from the INITSV= TOR* --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494639; cv=none; d=zohomail.com; s=zohoarc; b=Gfe/Q6F4Iu1XJEJriDwB0Ml6cuhW4o6EPpjPwfSUweF3WemvaynQNj9is1ToI4Cp1U4wJEApqvJ8EZUsV2rM3CYebeXfJ1CL/4RiS5KzJTrRs25kbKQEuB2cvkO7VMCVhJmSOGZYEWVndEdnotqrkU6RPPASPeXEK5C+vV1lJtg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494639; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wWVJBXgzRhaVQ69jIiCGvMtiBVCp4jd/hsLtG4YGx/E=; b=aDoFh9Gk++xOlPljnxK2e90Rn6sQdjN7/qtUJpAmChvzClEHp6gxmIPjGKqVkrlLjs8WMWYf1y9LphirUp1nethDH9Qd79vR+CgD7SI6mjs+sA6a/IFjwBlB7INYTjyNm5oqOMfRtVkyz7kMu/8iJobk1qjTuNMslzdIisWjsmk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494639275449.3240723604474; Wed, 1 Sep 2021 04:10:39 -0700 (PDT) Received: from localhost ([::1]:40998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO8b-00042Q-SH for importer@patchew.org; Wed, 01 Sep 2021 07:10:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcW-0007Ci-G8 for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:31 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:46643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcO-0005ur-9r for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:27 -0400 Received: by mail-wm1-x333.google.com with SMTP id m25-20020a7bcb99000000b002e751bcb5dbso1564472wmi.5 for ; Wed, 01 Sep 2021 03:37:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wWVJBXgzRhaVQ69jIiCGvMtiBVCp4jd/hsLtG4YGx/E=; b=rMYUJ461OP7Y+AcLpJcQ07ECw4eJf7zKEsycfmRC0e1WS8xgwlKSTP2qKvqFltPUtp Q9F3P/f4AtTsU9echBMCQlYLA81XjZFrFW2hVtHr7fxKjHuBt61AhWGaRtGiSittHXMz 90nGzCfXKqZLUOMlHCZ2Fzdn3ZDjw1BFJQ0p/p8E5pAKp9pLC9VKlDIHcJNdTTccUVGL ZC4Z1WowDCckwlFe0cDGKvahnlwEPjebLpiTuw2aysQynmZDHJ/GSqQOZQ8F+z4//tdh 71IajVE0mF9Jt3oQSV0pDvphydmUzLDSKwSm9Sd0ykD42f/LAThkdS8TGhV2RmJN6VJ9 RRNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wWVJBXgzRhaVQ69jIiCGvMtiBVCp4jd/hsLtG4YGx/E=; b=FvjrWNzkJE4P7NQDlb6gVkScZa/mPfwI4e65QeHr79Ub+GqJM2RsyVhloxfruGD/8X vXXPPwqGYTUomRHFuZbEID6G4t/siWFxPMrkiq0/3dFo8PX+hxohODNBL9ZxozBDEsH4 INt9XtPMXwSPfWPUcAa4KwozChU00sv2rw9H7NQ431P1FI9FNXeYn/rX3h8Rdg9mOxyD WuhNbA1lWDNhqe0FakNCqthmOAJ03Yqcnjhs7DwrW+/PsqvIJFtZEGfFXi29lGBsA97X OBGaPySQkrffBt1E0xolumwdJU0JF8fh77wY8FnItNd9ehAE6k1Gx6f9l+IDMOkmZ1o5 g/mg== X-Gm-Message-State: AOAM5309Kf5JYvKO1l6xnAgWB9PWjLKO3oX3EuADNAgrEUirjfngeLSZ ASvi9oYzn63hw0I+eqiLXX4GX2X7LNkBBw== X-Google-Smtp-Source: ABdhPJxdP7v2SCW37/ygPU+bMfYKXbX/D3vmk7A13BLcm7NZ9W42NcQRHApRq9Dx8Ac67gI3vTm0vw== X-Received: by 2002:a1c:a181:: with SMTP id k123mr8822616wme.90.1630492638571; Wed, 01 Sep 2021 03:37:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/51] hw/arm/mps2.c: Connect up armv7m clocks Date: Wed, 1 Sep 2021 11:36:36 +0100 Message-Id: <20210901103653.13435-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494641259100001 Content-Type: text/plain; charset="utf-8" Connect up the armv7m clocks on the mps2-an385/386/500/511. Connect up the armv7m object's clocks on the MPS boards defined in mps2.c. The documentation for these FPGA images doesn't specify what systick reference clock is used (if any), so for the moment we provide a 1MHz refclock, which will result in no behavioural change from the current hardwired 1MHz clock implemented in armv7m_systick.c:systick_scale(). Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210812093356.1946-9-peter.maydell@linaro.org --- hw/arm/mps2.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 81413b7133e..3671f49ad7b 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -86,6 +86,7 @@ struct MPS2MachineState { CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; Clock *sysclk; + Clock *refclk; }; =20 #define TYPE_MPS2_MACHINE "mps2" @@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass,= MPS2_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 25000000 =20 +/* + * The Application Notes don't say anything about how the + * systick reference clock is configured. (Quite possibly + * they don't have one at all.) This 1MHz clock matches the + * pre-existing behaviour that used to be hardcoded in the + * armv7m_systick implementation. + */ +#define REFCLK_FRQ (1 * 1000 * 1000) + /* Initialize the auxiliary RAM region @mr and map it into * the memory map at @base. */ @@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine) mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); =20 + mms->refclk =3D clock_new(OBJECT(machine), "REFCLK"); + clock_set_hz(mms->refclk, REFCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine) default: g_assert_not_reached(); } + qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); + qdev_connect_clock_in(armv7m, "refclk", mms->refclk); qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&mms->armv7m), "memory", --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494402; cv=none; d=zohomail.com; s=zohoarc; b=NWOF3ufap6ji7rg5MZxyHSPR1dIzRwbykdK53Ll7WoaKllL1dQW7l2HJg5Hs9g1uQVsitzHjZty/7Ef0Fpjk8EOfMxKcvwW4fcUb9FGng3/BFyiyyxLPAHPtCwQGtvg8VR4fN9DvvoLPqd8ZFJdPqBIsNs9evSxF2DJX+/puO18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494402; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dfANVgMVQgJeK7ytzWbU9YLsmaHGDdVsw9CUvopHHgE=; b=WxW3ZmDr8zhLlxu/yK7VDPIVc1IdFuZgDGesNWYyj33aaefTyt9cLZ2i2crrKstFhPR8QRaZ8IFuZiU6OZK+OttYlHOosD+inLEe9lM872MWg2swmt5fOV92JzRDVQe/ke5JqcW7At44ulJKlKpyyaP0zBu+q4rvOoN7xI6Ptc0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494402702630.8818596707796; Wed, 1 Sep 2021 04:06:42 -0700 (PDT) Received: from localhost ([::1]:34346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLO4n-00078b-FK for importer@patchew.org; Wed, 01 Sep 2021 07:06:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcV-0007BF-LD for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:27 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:42976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcO-0005w3-Qu for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:27 -0400 Received: by mail-wm1-x32d.google.com with SMTP id k20-20020a05600c0b5400b002e87ad6956eso1598551wmr.1 for ; Wed, 01 Sep 2021 03:37:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dfANVgMVQgJeK7ytzWbU9YLsmaHGDdVsw9CUvopHHgE=; b=yQ7c0ECf1lPHmgzWy3PfQqJ+EuxQ1Xz0DoZM+Nx6Vejjq1Isy1aPgO4JTHwd8oCVfV eqU5nOVpL2Z4aDF1AxnGoI4ecgUjHj8Ncleub/9vYRFX75qFelbjjT/xf2pT1g5j6QO6 PAANkf6X8iEGSCcNXZd9PUVuKnwv3MCCgFAob9VM1OwbjiqT761u4WiTHXou0bq5ukXP wkGM0x5Rq9CD9di26vfqvDO9vAJT7N+AW0xIiU4hCq5IGJoIPv1SZl1CIOv35U/zWroW dm+Jyq9klROuUGuG6lOALR6M9MLfDMTVIz1kDBl8MXt8VqUP+52WjT923mCArKt2F8C0 dsWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dfANVgMVQgJeK7ytzWbU9YLsmaHGDdVsw9CUvopHHgE=; b=eDXIhVuH5IXjDkcll/J3KNg4uZhlTwgZrrfkAlOkjW0slpPbhaXnjlO4x1+2HYL73r MGUo8S4moR4exabrkBFyWcMmYYB0o1VcmAcANY8qRJCizHw6mjNpnbrYMenYy1AID9Ri Dkg5ChWkzE6kM2tDv0+Nr1ldBnE5Bvd6jre0FcqN4kZ4F5XXFCEqiGof+Jpr74zlsG9o aakKp5+98q5wV2ln+n743xr4LaWGWpzK7/k9WczNkd52VGCXRmlqNEf7HSMNWfwXcaqQ 5IRbYPK6RELt2etuwQk8ZjM0ieAPw1BZ6Sxw5sMBr41L/jaO+GsQhqDFCGEyo/iGANSX rdVw== X-Gm-Message-State: AOAM530JUDzIVc3pN2kpZlUU9XrPne0Ce9EK9HyPGtGi/fvb+sd6rg9H VCO1my+ZsG006ko+vm8DORBHMXyJgoSluw== X-Google-Smtp-Source: ABdhPJykdh305koofHlMd0mNEhdTF5Ju1u0zReq6IbwJl82pMUQ1vzIsz5MBmcaQ/I/FY0rmEV+n2A== X-Received: by 2002:a1c:e904:: with SMTP id q4mr9123514wmc.26.1630492639261; Wed, 01 Sep 2021 03:37:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/51] clock: Provide builtin multiplier/divider Date: Wed, 1 Sep 2021 11:36:37 +0100 Message-Id: <20210901103653.13435-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494403614100001 It is quite common for a clock tree to involve possibly programmable clock multipliers or dividers, where the frequency of a clock is for instance divided by 8 to produce a slower clock to feed to a particular device. Currently we provide no convenient mechanism for modelling this. You can implement it by having an input Clock and an output Clock, and manually setting the period of the output clock in the period-changed callback of the input clock, but that's quite clunky. This patch adds support in the Clock objects themselves for setting a multiplier or divider. The effect of setting this on a clock is that when the clock's period is changed, all the children of the clock are set to period * multiplier / divider, rather than being set to the same period as the parent clock. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-10-peter.maydell@linaro.org --- docs/devel/clocks.rst | 23 +++++++++++++++++++++++ include/hw/clock.h | 29 +++++++++++++++++++++++++++++ hw/core/clock-vmstate.c | 40 +++++++++++++++++++++++++++++++++++++++- hw/core/clock.c | 31 +++++++++++++++++++++++++++---- hw/core/trace-events | 1 + 5 files changed, 119 insertions(+), 5 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 956bd147ea0..675fbeb6abe 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clo= ck 3* and *Clock 4*. It is not possible to disconnect a clock or to change the clock connection after it is connected. =20 +Clock multiplier and divider settings +------------------------------------- + +By default, when clocks are connected together, the child +clocks run with the same period as their source (parent) clock. +The Clock API supports a built-in period multiplier/divider +mechanism so you can configure a clock to make its children +run at a different period from its own. If you call the +``clock_set_mul_div()`` function you can specify the clock's +multiplier and divider values. The children of that clock +will all run with a period of ``parent_period * multiplier / divider``. +For instance, if the clock has a frequency of 8MHz and you set its +multiplier to 2 and its divider to 3, the child clocks will run +at 12MHz. + +You can change the multiplier and divider of a clock at runtime, +so you can use this to model clock controller devices which +have guest-programmable frequency multipliers or dividers. + +Note that ``clock_set_mul_div()`` does not automatically call +``clock_propagate()``. If you make a runtime change to the +multiplier or divider you must call clock_propagate() yourself. + Unconnected input clocks ------------------------ =20 diff --git a/include/hw/clock.h b/include/hw/clock.h index a7187eab95e..11f67fb9701 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -81,6 +81,10 @@ struct Clock { void *callback_opaque; unsigned int callback_events; =20 + /* Ratio of the parent clock to run the child clocks at */ + uint32_t multiplier; + uint32_t divider; + /* Clocks are organized in a clock tree */ Clock *source; QLIST_HEAD(, Clock) children; @@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk) */ char *clock_display_freq(Clock *clk); =20 +/** + * clock_set_mul_div: set multiplier/divider for child clocks + * @clk: clock + * @multiplier: multiplier value + * @divider: divider value + * + * By default, a Clock's children will all run with the same period + * as their parent. This function allows you to adjust the multiplier + * and divider used to derive the child clock frequency. + * For example, setting a multiplier of 2 and a divider of 3 + * will run child clocks with a period 2/3 of the parent clock, + * so if the parent clock is an 8MHz clock the children will + * be 12MHz. + * + * Setting the multiplier to 0 will stop the child clocks. + * Setting the divider to 0 is a programming error (diagnosed with + * an assertion failure). + * Setting a multiplier value that results in the child period + * overflowing is not diagnosed. + * + * Note that this function does not call clock_propagate(); the + * caller should do that if necessary. + */ +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider); + #endif /* QEMU_HW_CLOCK_H */ diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c index 260b13fc2c8..9d9174ffbd7 100644 --- a/hw/core/clock-vmstate.c +++ b/hw/core/clock-vmstate.c @@ -14,12 +14,50 @@ #include "migration/vmstate.h" #include "hw/clock.h" =20 +static bool muldiv_needed(void *opaque) +{ + Clock *clk =3D opaque; + + return clk->multiplier !=3D 1 || clk->divider !=3D 1; +} + +static int clock_pre_load(void *opaque) +{ + Clock *clk =3D opaque; + /* + * The initial out-of-reset settings of the Clock might have been + * configured by the device to be different from what we set + * in clock_initfn(), so we must here set the default values to + * be used if they are not in the inbound migration state. + */ + clk->multiplier =3D 1; + clk->divider =3D 1; + + return 0; +} + +const VMStateDescription vmstate_muldiv =3D { + .name =3D "clock/muldiv", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D muldiv_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(multiplier, Clock), + VMSTATE_UINT32(divider, Clock), + }, +}; + const VMStateDescription vmstate_clock =3D { .name =3D "clock", .version_id =3D 0, .minimum_version_id =3D 0, + .pre_load =3D clock_pre_load, .fields =3D (VMStateField[]) { VMSTATE_UINT64(period, Clock), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_muldiv, + NULL + }, }; diff --git a/hw/core/clock.c b/hw/core/clock.c index fc5a99683f8..916875e07a2 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period) return true; } =20 +static uint64_t clock_get_child_period(Clock *clk) +{ + /* + * Return the period to be used for child clocks, which is the parent + * clock period adjusted for for multiplier and divider effects. + */ + return muldiv64(clk->period, clk->multiplier, clk->divider); +} + static void clock_call_callback(Clock *clk, ClockEvent event) { /* @@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent = event) static void clock_propagate_period(Clock *clk, bool call_callbacks) { Clock *child; + uint64_t child_period =3D clock_get_child_period(clk); =20 QLIST_FOREACH(child, &clk->children, sibling) { - if (child->period !=3D clk->period) { + if (child->period !=3D child_period) { if (call_callbacks) { clock_call_callback(child, ClockPreUpdate); } - child->period =3D clk->period; + child->period =3D child_period; trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), - CLOCK_PERIOD_TO_HZ(clk->period), + CLOCK_PERIOD_TO_HZ(child->period), call_callbacks); if (call_callbacks) { clock_call_callback(child, ClockUpdate); @@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src) =20 trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src)); =20 - clk->period =3D src->period; + clk->period =3D clock_get_child_period(src); QLIST_INSERT_HEAD(&src->children, clk, sibling); clk->source =3D src; clock_propagate_period(clk, false); @@ -133,10 +143,23 @@ char *clock_display_freq(Clock *clk) return freq_to_str(clock_get_hz(clk)); } =20 +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider) +{ + assert(divider !=3D 0); + + trace_clock_set_mul_div(CLOCK_PATH(clk), clk->multiplier, multiplier, + clk->divider, divider); + clk->multiplier =3D multiplier; + clk->divider =3D divider; +} + static void clock_initfn(Object *obj) { Clock *clk =3D CLOCK(obj); =20 + clk->multiplier =3D 1; + clk->divider =3D 1; + QLIST_INIT(&clk->children); } =20 diff --git a/hw/core/trace-events b/hw/core/trace-events index 360ddeb2c87..9b3ecce3b2f 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -34,3 +34,4 @@ clock_disconnect(const char *clk) "'%s'" clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz-= >%"PRIu64"Hz" clock_propagate(const char *clk) "'%s'" clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s',= src=3D'%s', val=3D%"PRIu64"Hz cb=3D%d" +clock_set_mul_div(const char *clk, uint32_t oldmul, uint32_t mul, uint32_t= olddiv, uint32_t div) "'%s', mul: %u -> %u, div: %u -> %u" --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZW7hOgDfBwQm6WjLSXPRTnwUiqdqnjJPibh0v1ucACM=; b=D83mRXsUWoshHo0ePBj4u3+g55akx9iDmTjELC4g2P/E5H+KVKlRFF2EZPsJbChC57 amASoAWV5xj6Y7GMfw1bjCwRhKtouZPxrqtOs+VBWqszD+VesFcpPbJdNLQdZHUiCEKN b2iUqLGJXHTaQF1JZS4Fj05q5N6YkwFvlp6pOfpVeChg47YcdXdKPBhc0TeGzIEnS3RP z5wcnq+a8EmuEfr2yewJCQELOmiBp0Y50Vt3qpB9GS9KNe9XqgX7n3boF2eHQ5KsDmpg 6BJDE+6ow9C+DYKXAML1dRnEXgfIokmZfjRpk/AKlg3NaWEFFsLvFYLYUWHgZDrEgiOE I+jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZW7hOgDfBwQm6WjLSXPRTnwUiqdqnjJPibh0v1ucACM=; b=gZC3vM0djSz3dEOoZxeUaA3u/OsWr+N9FIlEaxHzOxfSD751KS7BkSgg1pGyIljCa0 AkKG0D+cWwIQ0+3IaEDg0wTGO6iKQWtd8NSBYeHg6CwnX1fEnMVRSBb1KTaOnDVeQsTz AacOQ/fnZvYYps/dtTvkKMs3+L5UPp0eSoJla/S4mrZY9953H/ERDWhsogCnbkgjbibQ gXjz4fR+l29u+gZK/n6TFLzR4UukV4hiYfTs6a+VQxlA5Vc4Y2yeq9HYDTkJRSaolIhM sdT7LR0qO3bwC0ern99/MBFi9yPiFgQMt2IRlX2DcutgoyumsTfU6dElhw6oN3LIqe2e eIgQ== X-Gm-Message-State: AOAM5313WHEMhNxrGbFId4kjY1QzSfnHCfR4Cr4KI43V2dH5goBru3WU oBzlFxadMjQNvFroMAr+6cswW5F+alueug== X-Google-Smtp-Source: ABdhPJysvT5lLv/J5ZzJN3ejjFL1ERH8+1x3Dln/8O+66q4wMJ3RoSkpxxAKbKagcXtF2XKcJroEtA== X-Received: by 2002:adf:82a8:: with SMTP id 37mr37515831wrc.123.1630492639903; Wed, 01 Sep 2021 03:37:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/51] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Date: Wed, 1 Sep 2021 11:36:38 +0100 Message-Id: <20210901103653.13435-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494971994100001 Content-Type: text/plain; charset="utf-8" In the realize methods of the stm32f100 and stm32f205 SoC objects, we call g_new() to create new MemoryRegion objects for the sram, flash, and flash_alias. This is unnecessary (and leaves open the possibility of leaking the allocations if we exit from realize with an error). Make these MemoryRegions member fields of the device state struct instead, as stm32f405 already does. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-11-peter.maydell@linaro.org --- include/hw/arm/stm32f100_soc.h | 4 ++++ include/hw/arm/stm32f205_soc.h | 4 ++++ hw/arm/stm32f100_soc.c | 17 +++++++---------- hw/arm/stm32f205_soc.c | 17 +++++++---------- 4 files changed, 22 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 71bffcf4fd5..b7d71c6c634 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -52,6 +52,10 @@ struct STM32F100State { =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; }; =20 #endif diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 985ff63aa9e..75251494917 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -63,6 +63,10 @@ struct STM32F205State { STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 qemu_or_irq *adc_irqs; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; }; =20 #endif diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 0c4a5c66451..0be92b2c475 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); - MemoryRegion *flash =3D g_new(MemoryRegion, 1); - MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); =20 /* * Init flash region * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 */ - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash", + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash", FLASH_SIZE, &error_fatal); - memory_region_init_alias(flash_alias, OBJECT(dev_soc), - "STM32F100.flash.alias", flash, 0, FLASH_SIZE= ); - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); - memory_region_add_subregion(system_memory, 0, flash_alias); + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "STM32F100.flash.alias", &s->flash, 0, FLASH_= SIZE); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); =20 /* Init SRAM region */ - memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE, + memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 9cd41bf56da..0bd215aebd7 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); - MemoryRegion *flash =3D g_new(MemoryRegion, 1); - MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); =20 - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash", + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", FLASH_SIZE, &error_fatal); - memory_region_init_alias(flash_alias, OBJECT(dev_soc), - "STM32F205.flash.alias", flash, 0, FLASH_SIZE= ); + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "STM32F205.flash.alias", &s->flash, 0, FLASH_= SIZE); =20 - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); - memory_region_add_subregion(system_memory, 0, flash_alias); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); =20 - memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, + memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494869; cv=none; d=zohomail.com; s=zohoarc; b=mUV6H3GYClQAivEMiHMRkq/+jGzh7vV4gNGECyyi5XWIzplbq9Xc5j2B2jDiW4NQ5RW67K9b5uRcjVdduKNqP1Yko3yt410ceF3PQRon7KL/o0xnLsco6rKDwqWJ3lDfasBNljXmMvQdtWIU1NpBwv5tAp/Gsm0oW+DWSOWbMZo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494869; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZH+7uLQj2dLMKVJSJdfJETvzXmbYV5Lk1vf1xsCoB0Y=; b=NbikmXaKk1OWulDOh2pSCrzQEApRQ5JtFeuIOBImKgpnAhiIU+2Vrt/rtRjaCI2KOf pTuSctLJ6yc25/qBVG0sMoupEA9S8N3pmisVhgVWrAmqNrYx33tGetEAzYscYSDer1zK x4m2187C/ShJ2xcIIcDBv6kxar8qaqaKrsMgQfMI2dyh+BLx0xej2EvSlcxtkCSQu76Q xscm22JwPN6ZCncoDlyhLIyhToSCLUtjIZ1Og64VrQbuiN3DrssM/N4yJWLSNk80zwPk jRrvDSS42HIUIc5pYFGOcvmmCgsZlp+AjJrhd3jAdTGf+JMKgH4/yrLuPQHN1z2ffTp+ FUaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZH+7uLQj2dLMKVJSJdfJETvzXmbYV5Lk1vf1xsCoB0Y=; b=Yc9VN48fw6PJWQDX6Fwm7A/yfiZCOUiSlMnQU2ZGwP37flLi2maEKQdPoaERJiWxwq nUBNCIbizVdDNGJhlnt9XTfNKCPsGX6MYbXD/s7TdX27Q6gBPsf9l4HLTocmqeXcA1Ae z7mXmqGVyzeaVCcyiRM/ZA6Y5HuNIk8+vXzJDyzBeVsIVTC71M4ptzN1Eu+3lRIhoKvf Ohx0IOWTtbXb85HtmMkREE8MlISoeY4OWyqy/RzJQaX3Uxu+IMwKpBxmMDUYAdm3f5x5 KMdECdmUgKJQ79RnhEBWn/xfKPdHpzLNb22Euiq+ce5oPT1fvZGbsSHZt79tjRCwhkOe Xt2g== X-Gm-Message-State: AOAM530S3jAlbciRAePZLssPn3fuEiZ43r6IPL9qpuXyTJ5LQdYD/NEv LlMm85dvyk9XyGY9HgTMP/FpiXV3jmroNg== X-Google-Smtp-Source: ABdhPJxGhhKfWWAR4JFRy3LDc5ZkexAMYltWhA4zEXcL/1GuetqNHD3EMhUlA9C3wEYgiUYZkcjNPQ== X-Received: by 2002:adf:cf0b:: with SMTP id o11mr37435847wrj.72.1630492640680; Wed, 01 Sep 2021 03:37:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk Date: Wed, 1 Sep 2021 11:36:39 +0100 Message-Id: <20210901103653.13435-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494870123100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Alexandre Iooss Reviewed-by: Luc Michel Message-id: 20210812093356.1946-12-peter.maydell@linaro.org --- include/hw/arm/stm32f100_soc.h | 4 ++++ hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++ hw/arm/stm32vldiscovery.c | 12 +++++++----- 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index b7d71c6c634..40cd415b284 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -29,6 +29,7 @@ #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" #include "qom/object.h" +#include "hw/clock.h" =20 #define TYPE_STM32F100_SOC "stm32f100-soc" OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) @@ -56,6 +57,9 @@ struct STM32F100State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 0be92b2c475..f7b344ba9fb 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -30,6 +30,7 @@ #include "exec/address-spaces.h" #include "hw/arm/stm32f100_soc.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" =20 @@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj) for (i =3D 0; i < STM_NUM_SPIS; i++) { object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) @@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, = Error **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + /* * Init flash region * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 @@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, = Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 61); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 7e8191ebf5f..07e401a818d 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" @@ -39,16 +40,17 @@ static void stm32vldiscovery_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F100_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=grFRI+D7JkW2E8rV8tw+47QyhO8xc+d2mM/hwxYtrCo=; b=p08btrUlFFUsNsjc7O9O/IrtvFxq1sKK3d07ZMeXlTyGitJNcOCEIziWLxNSbmgzyX eXZKC+W+sgv0oBeSBR7sZKchLjsGrPazlfJhpJdKQU/GFwo1Wojz6TQ9sA94BEJITJh+ 6pH6LaRALfLGEoXhSEOKFxXujXzqcQZs94z0bwX0SzuffyY+6NyreGQkg9qB4oyNIcQA LBznKDm7jMOzsV4NFyiIyyuaWqcDSmrzGyIKVe2LOvfPgJFHX1O0LJVA5EwUwaIG8XI9 0AJU5Mp5wsaPrDdmETjvhPpnqOsXsbUv8hSRv6iIuTYogMNSujE0ciX7bd8r9b0E8e67 wrTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=grFRI+D7JkW2E8rV8tw+47QyhO8xc+d2mM/hwxYtrCo=; b=ox/g5z7tPKFKHvXU5se4Iy/D3rel8XL/ev6VTUyXFBmsWYsXqzHrj0Mefy9dyaZR9J EZApu59iMY54yEyo89uPt+y+DYOplJubfnEjnCwzBQAgV71bjx61JN4G9mx7chq/mTgn 9UPm0r7r+AJ+nN3Jy4aNOwiDpN38PzqlQSFnifYMWBcWcKewkNk3a4qtfGym4tmHQTve Wv8X0tBZoEZUiNz5NKUTweHNX/L8d+Opf/Ve4QJsD3VGQdJ+fMbTcunbYIJ60F6qDRK0 3fPVklf+8nS3ZbRPKgLEBI/BDESlGV7cqasRR8Qo0QlaTnvPkxL1TTkA+1nQoiU1NJsl yi4Q== X-Gm-Message-State: AOAM530lWV8E2joLSl3VLd/py9b0u3nfAYV/vm6u/gxQrYCoLWVZO7U6 RuvU+wSiLxyAn+hOKgaQyMBfii/LfyaP2Q== X-Google-Smtp-Source: ABdhPJwqS4oHEHjuLCJIN025QAYWcLP23qbUkecy4bNCKDxAxejiBZHInkct6c4Hj6ybwaIcsqqckQ== X-Received: by 2002:a1c:a5c2:: with SMTP id o185mr9068005wme.34.1630492641327; Wed, 01 Sep 2021 03:37:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/51] hw/arm/stm32f205: Wire up sysclk and refclk Date: Wed, 1 Sep 2021 11:36:40 +0100 Message-Id: <20210901103653.13435-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495456096100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Alexandre Iooss Reviewed-by: Luc Michel Message-id: 20210812093356.1946-13-peter.maydell@linaro.org --- include/hw/arm/stm32f205_soc.h | 4 ++++ hw/arm/netduino2.c | 12 +++++++----- hw/arm/stm32f205_soc.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 75251494917..849d3ed8891 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -32,6 +32,7 @@ #include "hw/or-irq.h" #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_STM32F205_SOC "stm32f205-soc" @@ -67,6 +68,9 @@ struct STM32F205State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 1733b71507c..b5c0ba23ee5 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" @@ -36,16 +37,17 @@ static void netduino2_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F205_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 0bd215aebd7..c6b75a381d9 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -29,6 +29,7 @@ #include "exec/address-spaces.h" #include "hw/arm/stm32f205_soc.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "sysemu/sysemu.h" =20 /* At the moment only Timer 2 to 5 are modelled */ @@ -74,6 +75,9 @@ static void stm32f205_soc_initfn(Object *obj) for (i =3D 0; i < STM_NUM_SPIS; i++) { object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -85,6 +89,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, = Error **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", FLASH_SIZE, &error_fatal); memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), @@ -101,6 +129,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xim/VTGiMpFpK7yoj6VQGZClgrcpeiHaCqqogETdERo=; b=HKPdV4Y1CE4S5AdZxPf0rSu5tWkCBkYmpBq3+yFVOgTVwcpWfz+YJZwRClkyyOEMJw 4Vyje26kj5ezLkWKQ874gOtpCBwgtf4/fXA91YGVktpWuQSTTgRNv2WhaOmUGeAhzkZi 2CJGf9lodOkyaPT8p34+Grul9KKqJxl6B0hO3ek9AsGQ3A/geUdtqk9vVH8VHmHJP5m1 wqfKRyIGfJx5xWDwkN8+KV/BpuwHftF3WmVe6iwpeVPWd+FJoDdmA/nYIW1+crg5nL+Q flAL9K42/c6O8tbcl3gLUlKFTiqiCDdiNgdEjUug+8/UsXnaa0J9cFr67FomIfmFIEK5 5GbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xim/VTGiMpFpK7yoj6VQGZClgrcpeiHaCqqogETdERo=; b=hzfdaGZm/9/2/tpwYJttYhYa2OJposGv+UpBEXhSh4MiTIw9vqf9E2mUBz+HzuPJ8y cELZNjURB3lfdCdYXUweHq+vi7AZGmYshqqiHsukNHC591nJvBvP1Q17zXWMoWGCREXQ kP8PVzWvVo4OowLPwWsxsvS98K4DxV8rJl//z7Qp3irSpc2Pa4MOBHyoDbe1no8rK9O4 xK+RwMO9pMcUv1oeurDwnYKp4T15MTorr7naDjLNlUvG53P/pceQ1ljS6qqrrWemuD50 uAfsvD3jOF/rDWZNh6FXr7bYCczoV5RqruGUlDs+uwl2s05IA1Jyj1W2I2uwo/tdQ1jV +/Lg== X-Gm-Message-State: AOAM531WnCI9AAL+P0Q+iZqF0Bo7ZkYWuYbpkhjoSACv0+Xmr46hXwX6 nZuJfBe1xQtWG1BDspB5DYVxw9yDxt76Uw== X-Google-Smtp-Source: ABdhPJzIUyusag5kKRWjAW9yM613x1jfVH759UJ3JBTF9xUGE09LVsu8uLaBrS/UW53JCNmMVFQTzw== X-Received: by 2002:a5d:5452:: with SMTP id w18mr36533629wrv.221.1630492641911; Wed, 01 Sep 2021 03:37:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/51] hw/arm/stm32f405: Wire up sysclk and refclk Date: Wed, 1 Sep 2021 11:36:41 +0100 Message-Id: <20210901103653.13435-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493556694100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Alexandre Iooss Reviewed-by: Luc Michel Message-id: 20210812093356.1946-14-peter.maydell@linaro.org --- include/hw/arm/stm32f405_soc.h | 3 +++ hw/arm/netduinoplus2.c | 12 +++++++----- hw/arm/stm32f405_soc.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 347105e709b..5bb0c8d5697 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -68,6 +68,9 @@ struct STM32F405State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index d3ad7a2b675..a5a8999cc8c 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" @@ -36,16 +37,17 @@ static void netduinoplus2_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F405_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cb04c111987..0019b7f4785 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/arm/stm32f405_soc.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 #define SYSCFG_ADD 0x40013800 @@ -80,6 +81,9 @@ static void stm32f405_soc_initfn(Object *obj) } =20 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) @@ -91,6 +95,30 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, = Error **errp) Error *err =3D NULL; int i; =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", FLASH_SIZE, &err); if (err !=3D NULL) { @@ -116,6 +144,8 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,= Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(system_memory), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q5pqQLnCswODdqUl/t5tCfNALYIC/vCIVqmbDLDjpMY=; b=p9rUr7x7EZTUy51D0lHJrH2nJfz7zadRGrGs3kTVGco3aeCIp6HLiflY7ZZzvMJajN ZQ4zKhW70KXZUFv1/ALnj3qTG/SIh4JG0fiO//qK5DjoQ2tjM4rH69cUR0UQvKQEm5UN 39OliiJHZBTPa/nSO/+cLejyQc80uN8ggoR/JPp5xV5hEQSlANP8ascZ8PNNEl4dn9bo thvfYt+RzweIlpUH04kCDn7temCnzmnlUA79SocGmF5sg4MqWK2TNANS/PXvo1d8ygWY Hdzckq+MBVnuCTkJjKa9qC8IWyDcT9ZTmZCEd65ZADJHPWhqXpgulXEzv9q2Xp1IDCYe sM/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q5pqQLnCswODdqUl/t5tCfNALYIC/vCIVqmbDLDjpMY=; b=fYA8T6GjL1f0GO20RGJ3qpC36PctPbr7N0wqWJkAqVpdoJr7KSze+6Us3cydcwfKxg Jp3e9U3m+OKoKuDpgiHrafkKXt6yBdUpnfVwJMxgL2xzf/2nX3nnS8SVHa6V/uQz4Udr tZPvHsyvWShapkwHxXFeEEEng7B1m4fO+4EiHrLZT1+XU5gsJseXW+CHJTV35HOvLtq8 2uvMpGYT5MHXj4blVFn2xUmXQFW6g5N5Pu3XP9j41dEMOcZhFXQRdk6wRRdKK5rlwnbB 2TuKlZExazRDAsVRTP1u01aL+n4/Q7VGnGE/q4anIUWDmj3wj7lMfkK7R4HJ0f7C3ojp uU8A== X-Gm-Message-State: AOAM5338dAKepTedoY4hfutfAoziN0oQ+wf0G8/v2xyV5hljpVp3/KLn +VSr7YPhYEQ+tEVGfib6RYIhGcVptDawdw== X-Google-Smtp-Source: ABdhPJzNWU/XfsHd08nrd1nX1HyaywrS4pB4KwUzG26uEB5LKBWIetuRTze7uUE6cXvrCFk2Nsr+Eg== X-Received: by 2002:adf:e809:: with SMTP id o9mr36901324wrm.425.1630492642585; Wed, 01 Sep 2021 03:37:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/51] hw/arm/stm32vldiscovery: Delete trailing blank line Date: Wed, 1 Sep 2021 11:36:42 +0100 Message-Id: <20210901103653.13435-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494726284100001 Content-Type: text/plain; charset="utf-8" Delete the trailing blank line at the end of the source file. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20210812093356.1946-15-peter.maydell@linaro.org --- hw/arm/stm32vldiscovery.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 07e401a818d..9b79004703b 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *m= c) } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) - --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630494851; cv=none; d=zohomail.com; s=zohoarc; b=CxEsv/yojVg0azZ/GPoPjcoXfjViOtjFPpOmR4wzMRelCnji2bytDLVDv30PJhHzKB6c/y8B32z49UvoQ922H3VqJgEb2lgLzLgl+LwB0ok6KsjdFMzox/ECQbXS9raiY1f5ZVonH6SlctWRu3oXmxk5yb8ZQ66MsWVo36WwjEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630494851; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jf3SvTXtr+76cdXYcw41T1oM3y829AbGpi+8zN1P7Tg=; b=alm+xkdZtfRUdPddwJJNf9e8gFIeIP16APydhq5I6SwFnkzTpicDoCwnuzXc9kTxsj6WAKyEuZ3fb4x76NWAW66Ha+GH2fKMz0Y/2x4+AC49k4cnvAXz9i/h9uCm2GeCnkkmZDq6ktiyX1ZGEUZYoFbklNlOe5NPd2A9PifafP8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630494851098310.75853482772357; Wed, 1 Sep 2021 04:14:11 -0700 (PDT) Received: from localhost ([::1]:49138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOC1-0001On-QA for importer@patchew.org; Wed, 01 Sep 2021 07:14:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNca-0007DA-3M for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:35 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:42872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcS-0005yd-Jn for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:30 -0400 Received: by mail-wr1-x42a.google.com with SMTP id q11so3716082wrr.9 for ; Wed, 01 Sep 2021 03:37:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jf3SvTXtr+76cdXYcw41T1oM3y829AbGpi+8zN1P7Tg=; b=tjvHHT307ckqVNFSb8p8SBTBJy3mdAy62oL03DppLHQ2mEYjAY1GdQwV/afx+oCPdh /i+EUNs8B8tStHtbLOGaVxz8wPcd1GRiXtufWfGa8fFKFCM/l+G4CTSEGcF84Imi5eJK CrArnNnnPHTh5l8IpvqVQqUj6V8VatqAuzWv+6YPHB5gbzGgbQd+f13vHds6PFyGKAPD so1QJUaJ9ADU+Dd+F6vcSav9t5dRcbKe/Fg2Rn6KcHDCvPT42xdXFnsQ+sgxMCMahTvt fRnyr8X4Xd9Fhu7bMMRx4Sj0Hq85u4uqPhJ6MEvWqc94VZVAQu3Zehq2tuPVoR1u5Wt0 55Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jf3SvTXtr+76cdXYcw41T1oM3y829AbGpi+8zN1P7Tg=; b=tQAtGdLpux6wpfwdFsc+eFaIJdYRNxMRic5eJeJnloQj9kan1ABDHXWDYxYNKWpybT Mmjqnjj4E479GLYyBtlP0PMeDT9A4Mi4IRzLUkMXwU3zNiQJq+27adL7N0/lctAWMUmT gbkPoceif/84N4fGmAzn4JlQYIR0Cn5ua67L6XEZG76RbuAnC9EOpvolIjBlC6liZHQI oK52bUfqLdALhVYwOkm5PIYsmVYvnxTyLhe06djy3OayZ/ygCtBI5k0iGsr3dnjCBQib UReBnR1Pwgi/ePSFjudGvzMVOqg1NR4kPxpxOEZkR1qWyYksQfcri7KNETPKJ9xrTs/G 9f2A== X-Gm-Message-State: AOAM531iFfUUGw2Di2fVIUHETjIjdNicrHcroDytVWpcgxfF3/nwuzgH XYP8C62n/8YG4YGy3ehsfWPQshA9hbII0g== X-Google-Smtp-Source: ABdhPJxEtlNqcSqhGd51WyD/BLZdOtthRPUpPO/mH7ViSLbhu9r3dlfzgfpz1CdcSCimds8VHduoqQ== X-Received: by 2002:adf:816f:: with SMTP id 102mr36520723wrm.368.1630492643184; Wed, 01 Sep 2021 03:37:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/51] hw/arm/nrf51: Wire up sysclk Date: Wed, 1 Sep 2021 11:36:43 +0100 Message-Id: <20210901103653.13435-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630494851740100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-16-peter.maydell@linaro.org --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index f8a6725b775..e52a56e75e0 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -17,6 +17,7 @@ #include "hw/gpio/nrf51_gpio.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" @@ -50,6 +51,7 @@ struct NRF51State { =20 MemoryRegion container; =20 + Clock *sysclk; }; =20 #endif diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 9407c2f268b..e3e849a32b1 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/arm/boot.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "qemu/log.h" =20 @@ -66,6 +67,23 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) return; } =20 + /* + * HCLK on this SoC is fixed, so we set up sysclk ourselves and + * the board shouldn't connect it. + */ + if (clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must not be wired up by the board c= ode"); + return; + } + /* This clock doesn't need migration because it is fixed-frequency */ + clock_set_hz(s->sysclk, HCLK_FRQ); + qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); + /* + * This SoC has no systick device, so don't connect refclk. + * TODO: model the lack of systick (currently the armv7m object + * will always provide one). + */ + system_clock_scale =3D NANOSECONDS_PER_SECOND / HCLK_FRQ; =20 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->contain= er), @@ -191,6 +209,8 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_TIMER); =20 } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 static Property nrf51_soc_properties[] =3D { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495088; cv=none; d=zohomail.com; s=zohoarc; b=PSqUKbkxIx1BJAKBTGU31yRQRUJL+5n+ZmMdxmEsfQnzg0EUd55FVD4Aa3qf7FpWkliRXTndGX7jYD8Ps0fQT7SxBnuZn586iHnldSVDLVfpwFSJvYT2/bYTLyxUQ4RA0QtHTxlu/xArImbunnDhFQVJqXw5R+Nv3ysaPadd9XE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495088; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j83XUPV97J381oMF7qSvoBGESd0UTWy6ZMCHvkTRW4Y=; b=WqKQ1+ywKgUoQH3YG8kkk+yx0karDw6KVnURIwwxQjIY3k3HRn2nwuIQNeUpb5dMDf5T0sj1NJgp6wrFTSYm/j0Xo/utcGHQgyLJ9Xd1/xrv+dte1urlbfbQTCUd4Q4ooOT/C4DJBlX953vlnxhKEszRwc4GjRxW6oCISlY0sEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16304950881931002.9541949727554; Wed, 1 Sep 2021 04:18:08 -0700 (PDT) Received: from localhost ([::1]:55452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOFq-0005rs-V5 for importer@patchew.org; Wed, 01 Sep 2021 07:18:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcd-0007EC-LS for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:36 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:37852) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcU-0005zf-7E for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:34 -0400 Received: by mail-wr1-x430.google.com with SMTP id v10so3744065wrd.4 for ; Wed, 01 Sep 2021 03:37:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=j83XUPV97J381oMF7qSvoBGESd0UTWy6ZMCHvkTRW4Y=; b=qtNIt07tA70+/bC4lF7JqB03lYM/9futLrbWLQ7IJ/8pX1iEqkHruzXy+bW7QKDHaU PNudWrJ3FFHegi3G6RdxYeSAhd3OsPwne5e4EokZhhCXshBNmSCS30odAiFzhkAiGppy XgxMvyFd6jSJyBd4w249WhM4dAfgsyDkG2+e1YciJh5CcJzs2Z3bsnX/OkxwUE+LKlpA 6fbYUVUHw2DwqVrJJwqpke+9jXpTnrpIbIUhpOjeS94MwTLZ5246MvpoXif1pQRS7A3a Rez+O6veLfpUkaUOD5IzQFMzb9VpjtcGp1ULqIVrn6akGIgL4bLb5uxRKwbSivpE/MBJ 38Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j83XUPV97J381oMF7qSvoBGESd0UTWy6ZMCHvkTRW4Y=; b=o0Tv2Pms7kl1OORSDWMKvgBbgn8k2jSRLFXL1C4paEPbMbyi3lEwVPePVf2WtxEzQl uzf2O8d0JYBlfKMtPi5nwphg1PfETgTT/HVRde1c3qCe7hMZY/MUDKHm97rPvAZfaU6W uzlDiuB1h5uIyDlVEoF/jV/IHsw8cLQjhA5wvQdaGN6g3fKqAiB2UZtPcsIESFV0A+aR u8+Tk5C4zqq7qgBSdwKtBgvM9Doc7CspH7N/8nRYwaQk4X+EbdDqCabzyw7ej83YobbE HD5dG71yONmcWO56CPPpRc/Gm/i3HISz5iH5XODnJLlHkgNzmWbbqsmpLjF0iSZMqmys N5/Q== X-Gm-Message-State: AOAM530OOTlwc21csa+cQzgMuTxq+obcTp9FZXlgoSLzv8VNb6RHo2cU LLomDUgrMADmF1+YURlvf9x3hhg4EpIFfA== X-Google-Smtp-Source: ABdhPJybbfxVVP2uIoVKeWMIgi4YfSZWhZcYSTf35xc9cj3ym9z6Yew26voETnyoBTuHeKIEjPGVVg== X-Received: by 2002:adf:c148:: with SMTP id w8mr29040415wre.317.1630492643919; Wed, 01 Sep 2021 03:37:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/51] hw/arm/stellaris: split stellaris_sys_init() Date: Wed, 1 Sep 2021 11:36:44 +0100 Message-Id: <20210901103653.13435-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495088800100001 Content-Type: text/plain; charset="utf-8" Currently the stellaris_sys_init() function creates the TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its MMIO region and connects its IRQ. In order to support wiring the sysclk up to the armv7m object, we need to split this function apart, because to connect the clock output of the STELLARIS_SYS object to the armv7m object we need to create the STELLARIS_SYS object before the armv7m object, but we can't wire up the IRQ until after we've created the armv7m object. Remove the stellaris_sys_init() function, and instead put the create/configure/realize parts before we create the armv7m object and the mmio/irq connection parts afterwards. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-17-peter.maydell@linaro.org --- hw/arm/stellaris.c | 56 +++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ad48cf26058..bf24abd44fd 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -755,33 +755,6 @@ static void stellaris_sys_instance_init(Object *obj) s->sysclk =3D qdev_init_clock_out(DEVICE(s), "SYSCLK"); } =20 -static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, - stellaris_board_info *board, - uint8_t *macaddr) -{ - DeviceState *dev =3D qdev_new(TYPE_STELLARIS_SYS); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - - /* Most devices come preprogrammed with a MAC address in the user data= . */ - qdev_prop_set_uint32(dev, "user0", - macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 1= 6)); - qdev_prop_set_uint32(dev, "user1", - macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 1= 6)); - qdev_prop_set_uint32(dev, "did0", board->did0); - qdev_prop_set_uint32(dev, "did1", board->did1); - qdev_prop_set_uint32(dev, "dc0", board->dc0); - qdev_prop_set_uint32(dev, "dc1", board->dc1); - qdev_prop_set_uint32(dev, "dc2", board->dc2); - qdev_prop_set_uint32(dev, "dc3", board->dc3); - qdev_prop_set_uint32(dev, "dc4", board->dc4); - - sysbus_realize_and_unref(sbd, &error_fatal); - sysbus_mmio_map(sbd, 0, base); - sysbus_connect_irq(sbd, 0, irq); - - return dev; -} - /* I2C controller. */ =20 #define TYPE_STELLARIS_I2C "stellaris-i2c" @@ -1349,6 +1322,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) DeviceState *ssys_dev; int i; int j; + uint8_t *macaddr; =20 MemoryRegion *sram =3D g_new(MemoryRegion, 1); MemoryRegion *flash =3D g_new(MemoryRegion, 1); @@ -1366,6 +1340,26 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) &error_fatal); memory_region_add_subregion(system_memory, 0x20000000, sram); =20 + /* + * Create the system-registers object early, because we will + * need its sysclk output. + */ + ssys_dev =3D qdev_new(TYPE_STELLARIS_SYS); + /* Most devices come preprogrammed with a MAC address in the user data= . */ + macaddr =3D nd_table[0].macaddr.a; + qdev_prop_set_uint32(ssys_dev, "user0", + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 1= 6)); + qdev_prop_set_uint32(ssys_dev, "user1", + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 1= 6)); + qdev_prop_set_uint32(ssys_dev, "did0", board->did0); + qdev_prop_set_uint32(ssys_dev, "did1", board->did1); + qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); + qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); + qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); + qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); + qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); + nvic =3D qdev_new(TYPE_ARMV7M); qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); @@ -1375,6 +1369,10 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) /* This will exit with an error if the user passed us a bad cpu_type */ sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); =20 + /* Now we can wire up the IRQ and MMIO of the system registers */ + sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); + sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic,= 28)); + if (board->dc1 & (1 << 16)) { dev =3D sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), @@ -1397,10 +1395,6 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) } } =20 - ssys_dev =3D stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), - board, nd_table[0].macaddr.a); - - if (board->dc1 & (1 << 3)) { /* watchdog present */ dev =3D qdev_new(TYPE_LUMINARY_WATCHDOG); =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NiuR82k4Z/QjftRCChwntyHfqleW/Hw4RZMhUwxUflY=; b=xa9vyP1JVJ4TEgbnufk9mPKhIKrw98RYG+Y4LJ2VSMISGNiYY0NVXXhehuos36e13A uhXFYua7enGxO6o5v8wniksbPfKu3hXRrxPa+CbRK9Xd1MXXrPMhOs44P2+OySGaaYfF Rfe2Ag/LtWYrnI9YGjtEoqICr9NFjhnjqFq+gNWbMkaXv2cbBAjaEHhLn3yw/Iu8aGX8 c+XQyS7Le2pC8m47ImFPShfbk4L2VEEH9ipGJleK2RnpiJ4rRQoWF2zxnIwn9v3JyPyz EPUPZ78v+FVeZboEB2K44PK7tCKXh4CJ+0J6eFPO3a0I27a18kruJqaFYE8TNdUVuzy+ G42w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NiuR82k4Z/QjftRCChwntyHfqleW/Hw4RZMhUwxUflY=; b=dL8tyydrFQ2UG+x1mnOQTqmcd1VWmvfCOd5cKR/aNGFvpjjsKtVOfd/akVQLmK5lCy IGDshdjESmPXcAblxUyTa+GmLGuSbIkeb/7dHN3rzDLltrAyo1RMFpnEAwk/mhdlnDzz QFGsrMAaYCtYJVb/+1OKJEnIDEngU6f+TZPYPA/+q1mPSU9kMd3V9ZFtnL2OeVKjO8mx 97gNt4s+JdWHKDu4Yo30Ius9hAmdIsI536KajaTcCemHfgSb+k317dN7yUk1+ljdHW1d i+ynaNB4BGjm9Lb2ztPKLC0qqDPZnYx4omVGrqe/bVg+1Om/NF2kNBiHBsLvQvmuaddB 6Mcg== X-Gm-Message-State: AOAM532ID82+xydeGrNY8QdzychwcCAm2Ku3xY7k+PGZIPxRpRGVR5LS 2t+Hm7bhijkQbeub5IkTz2bs4vAULdgaIA== X-Google-Smtp-Source: ABdhPJy1VZee5qV1EJg4x3GXXaoancIXeCXq7dvUoXm4yLPsyBkmwqExaHh9qxrmaTjUrBupyZtWvw== X-Received: by 2002:adf:b7c1:: with SMTP id t1mr37470496wre.387.1630492644655; Wed, 01 Sep 2021 03:37:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/51] hw/arm/stellaris: Wire sysclk up to armv7m Date: Wed, 1 Sep 2021 11:36:45 +0100 Message-Id: <20210901103653.13435-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495090845100003 Content-Type: text/plain; charset="utf-8" Connect the sysclk to the armv7m object. This board's SoC does not connect up the systick reference clock, so we don't need to connect a refclk. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-18-peter.maydell@linaro.org --- hw/arm/stellaris.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index bf24abd44fd..8c8bd39e2fe 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1322,7 +1322,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) DeviceState *ssys_dev; int i; int j; - uint8_t *macaddr; + const uint8_t *macaddr; =20 MemoryRegion *sram =3D g_new(MemoryRegion, 1); MemoryRegion *flash =3D g_new(MemoryRegion, 1); @@ -1364,6 +1364,9 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); + qdev_connect_clock_in(nvic, "cpuclk", + qdev_get_clock_out(ssys_dev, "SYSCLK")); + /* This SoC does not connect the systick reference clock */ object_property_set_link(OBJECT(nvic), "memory", OBJECT(get_system_memory()), &error_abort); /* This will exit with an error if the user passed us a bad cpu_type */ --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495635; cv=none; d=zohomail.com; s=zohoarc; b=fUtpI3iI8ECogUosq5S/ItXnZKEsjFAwoUzFkTmmCTmVNi3CRntWknXz4QgWHiG9WirVaaOHrr6Bb9Yvy6OOeBCkeOYs/FLfDT/s6Q9qhwnrChkLZ7qCTwVNqpUSuLHdeMXJBFXlMad81vtsFywDMWezZMqKM7ZpPkGATYI2RRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495635; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FHlQJkP738avfN2ghaMhCgKtY64B2XdP/tvv/GsErWE=; b=TJ2ZLks78ErTfkESFu+Em1i6PacbD8braqfuS3iEC/n72U8vjKINrPu2nLX2lqIYUEtHej2ulKSpRsdRRR1aV6HHmFFsSDzTlvZiQzwNIPv5dIHTP9Y0x5pBVxrGuJz9b4+nP650OfuLLab/derRM1UEyea+Vjyj9InMwdS/y4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630495635555461.87819463665244; Wed, 1 Sep 2021 04:27:15 -0700 (PDT) Received: from localhost ([::1]:46506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOOg-00026a-Gl for importer@patchew.org; Wed, 01 Sep 2021 07:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcc-0007E7-AL for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:35 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:51927) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcV-00060e-AH for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:34 -0400 Received: by mail-wm1-x330.google.com with SMTP id u15so1524471wmj.1 for ; Wed, 01 Sep 2021 03:37:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FHlQJkP738avfN2ghaMhCgKtY64B2XdP/tvv/GsErWE=; b=Y8KBl81eIiKV6xNIVgYJarRDQcivRMsrPE6unb3qfEBkMtEsSugTMZRpwFc72WGcGm s52Yg6BUYuZID9OvuENrHACI0dNHlFQKSRd0eZ3cCc2H1yl5KeEWSE+zYKR9h0vBEbKu 61WmLg8l0EHxprOhDuqeBmkj+HIx5sqp5EW9em84rrWhsQlBA38t37PyAuFTwmfSXQme WE7KoaWLeGpMMNlSSDAN2WcJgg5gEvpOIaca1IV6eIMtHkskYWrFgYTT/su6X4tfgDEE Tt27u8FcTirwy/foVZHPc61R1hLoTt49VOkuMVk+YPdR+8FYjhv3IrXowtp5xUALEZZI PUTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FHlQJkP738avfN2ghaMhCgKtY64B2XdP/tvv/GsErWE=; b=rqvXzlwBW7wQV9nPjXyhubqe1cFMkjPShg3ZcKWP3CKxUJB61Z+PNgNrfaP8dj2tlM gVW24mee3MYuFAnFQo3obRIWk+EVREBEDIcEtpFhnr8VGZHfRVNrBLlq041736wyv2We egk9bqwi8adM7FBhyNo/s+qMfYwwUr2ef1J20MLA5v9Rl1PZi5lu9qwpFkPYibr1ahVs FTNH3y325HJsDbIm33mBE8b/Cl0sho9j6PUulKeD795HwxXYZUQupB+7Xq81lCjPgGHP U8fF9YIZU/BJQIcn9F7pOdHa8aemx3UIj5lYmoTIoUz17E/K4xbw0/OvMFYDoHHtoBqY bTbg== X-Gm-Message-State: AOAM530DNECq2/il9V7xPHHhlPfrTlZiWInCo1gnNWOqYceXaRrRPd8w avuij0GR5/ixInhnLf3f5tkOOuzhwyJLNg== X-Google-Smtp-Source: ABdhPJzhqjNPNzN/XoM7A3x1+4BI5g4agO3t3Mj5KImg8uvff9SbvMoWhYaKUMlxjWT2J+lq3MfHaA== X-Received: by 2002:a1c:9d50:: with SMTP id g77mr8725488wme.67.1630492645454; Wed, 01 Sep 2021 03:37:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/51] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Date: Wed, 1 Sep 2021 11:36:46 +0100 Message-Id: <20210901103653.13435-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495636170100001 Content-Type: text/plain; charset="utf-8" In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-19-peter.maydell@linaro.org --- include/hw/arm/msf2-soc.h | 4 ++++ hw/arm/msf2-soc.c | 17 +++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index d4061846855..38e10ce20aa 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -65,6 +65,10 @@ struct MSF2State { MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; MSF2EmacState emac; + + MemoryRegion nvm; + MemoryRegion nvm_alias; + MemoryRegion sram; }; =20 #endif diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 5cfe7caf834..f36788054b3 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -83,11 +83,8 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *nvm =3D g_new(MemoryRegion, 1); - MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); =20 - memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size, + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* * On power-on, the eNVM region 0x60000000 is automatically @@ -95,15 +92,15 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) * start address (0x0). We do not support remapping other eNVM, * eSRAM and DDR regions by guest(via Sysreg) currently. */ - memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm,= 0, - s->envm_size); + memory_region_init_alias(&s->nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", + &s->nvm, 0, s->envm_size); =20 - memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); - memory_region_add_subregion(system_memory, 0, nvm_alias); + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, &s->nvm); + memory_region_add_subregion(system_memory, 0, &s->nvm_alias); =20 - memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, + memory_region_init_ram(&s->sram, NULL, "MSF2.eSRAM", s->esram_size, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630493781; cv=none; d=zohomail.com; s=zohoarc; b=g3H4CzvwGyt++fN+hUkYgWSp6jZz0GhbS+v68uBqcT69QIugw2/jAKnE1ixTgYDkDjULkzA2zAtmNcGoSBJTTQKhXTMgDddhRA0TMAIMnRTEURbMYEER7B2Q14sdKqO1ns8LcMCK2F4s00ENrYhirfNSoH9wkMgUkrhYTqsC7xA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630493781; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LS8ZO8ZtENjVWsYJtincFRMevTLsUGHR1SCOeJNrNN8=; b=XzdvPpyLwIvpp95dhUxtZ7XFN76QmBL0tcQE3khGfBLXIMeQWPYk+lJvzFxD9kMVHkva4RAno1cH/tK5CqnA0lxkpFswrlxaocgBkgJBljPl5/DsKhP0rEyVCYt8r7B0CuO+9N3ltG8jk6I8eoUSBHxg/DPbeeTZrrxc2H/URho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630493781493598.8516876214552; Wed, 1 Sep 2021 03:56:21 -0700 (PDT) Received: from localhost ([::1]:37338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLNum-0006X5-GX for importer@patchew.org; Wed, 01 Sep 2021 06:56:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcc-0007E4-7x for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:40676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcW-00061I-8p for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:32 -0400 Received: by mail-wm1-x32b.google.com with SMTP id x2-20020a1c7c02000000b002e6f1f69a1eso4373248wmc.5 for ; Wed, 01 Sep 2021 03:37:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LS8ZO8ZtENjVWsYJtincFRMevTLsUGHR1SCOeJNrNN8=; b=LnYekATdds91qVz0w6yzWiskRVAI8ZV5s4lZ3kZR6l0B1SuQL1gCjfjpIXG1BcKt0P NY78Mz9YS5aq70xZ5SJUiRfUR4jhWPtEwsxG7PjTyt3Ac8LKRyPi7d/ab/bmBhrd0ylJ Up4gFBlH7LYeSYQIL8CwkiP7Jf19ZUsQLFuj5tpVPFmYSGY/YR7KH+LBEIHYkztkgxDo ziX7Qfgvub2UOG5KPAUj6WVlwuNkmZJdLLkk5H/m8S1odsrS5dYu5T9fI74pcifwDdYl 4uGjvnpel2S2Bk/6Dqfmvx6/LJz5Ektff44YnaEHIRHvGDkkGQSSxiPKcCYWhGYrTkU1 gThw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LS8ZO8ZtENjVWsYJtincFRMevTLsUGHR1SCOeJNrNN8=; b=FD0Rd+6wBo54vka/OZvWvrz2fa72tUW/hhfOg8WOeYxs1PpJGiJ8r7zZ9ItJFQXj3u KZQlrPCW/yvXIHNJHUPG4WRxcZ+efJneqjssYQ2aRKYt9U6UGRPK7Zi184ZqkC55SD8n uv9eVawlBbpHH2xbzGPTSDpxldUd1919JJ+3BQXiZDMv7OlOTGvX8SFwlahJUZh+wqqp ndc4aw63vfIIo1mvbnRJLg8dfUP2eoc/cJgojcAnerjigXaA4NaotAUto7JLRUq7/f6O +lFbkVeW77+Qc0buhBG8YPdrp86ACAhjjXgHqJGIvLhIOUKvYB0kO246ZWSU1pKLSzss kHuA== X-Gm-Message-State: AOAM533MLiyOWWSkKh89LHb7K2DPnfDCz1ZuSkdkGxXQa8cdAzLOpXmh bQLBFgMp/u4FCvCAVjn9muX5ErYz6O9qLA== X-Google-Smtp-Source: ABdhPJzQrKlyI8DEmM9k3wLMxI64j6+Pfp5Wbvun2AHSzfgzaJl1T2yzRZ9vnrDDuVMEUNPQLdutxA== X-Received: by 2002:a1c:80c3:: with SMTP id b186mr8638841wmd.105.1630492646323; Wed, 01 Sep 2021 03:37:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/51] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Date: Wed, 1 Sep 2021 11:36:47 +0100 Message-Id: <20210901103653.13435-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630493783392100001 Content-Type: text/plain; charset="utf-8" Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-20-peter.maydell@linaro.org --- include/hw/arm/msf2-soc.h | 3 ++- hw/arm/msf2-soc.c | 28 +++++++++++++++++----------- hw/arm/msf2-som.c | 7 ++++++- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 38e10ce20aa..01f904cec47 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -30,6 +30,7 @@ #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" #include "hw/net/msf2-emac.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_MSF2_SOC "msf2-soc" @@ -57,7 +58,7 @@ struct MSF2State { uint64_t envm_size; uint64_t esram_size; =20 - uint32_t m3clk; + Clock *m3clk; uint8_t apb0div; uint8_t apb1div; =20 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index f36788054b3..0a1e594aee6 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -29,6 +29,7 @@ #include "hw/char/serial.h" #include "hw/arm/msf2-soc.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "sysemu/sysemu.h" =20 #define MSF2_TIMER_BASE 0x40004000 @@ -73,6 +74,8 @@ static void m2sxxx_soc_initfn(Object *obj) } =20 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); + + s->m3clk =3D qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -84,6 +87,11 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + if (!clock_has_source(s->m3clk)) { + error_setg(errp, "m3clk must be wired up by the board code"); + return; + } + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* @@ -106,19 +114,14 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, = Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 81); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { return; } =20 - if (!s->m3clk) { - error_setg(errp, "Invalid m3clk value"); - error_append_hint(errp, "m3clk can not be zero\n"); - return; - } - - system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk; + system_clock_scale =3D clock_ticks_to_ns(s->m3clk, 1); =20 for (i =3D 0; i < MSF2_NUM_UARTS; i++) { if (serial_hd(i)) { @@ -129,8 +132,13 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, E= rror **errp) } =20 dev =3D DEVICE(&s->timer); - /* APB0 clock is the timer input clock */ - qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); + /* + * APB0 clock is the timer input clock. + * TODO: ideally the MSF2 timer device should use a Clock rather than a + * clock-frequency integer property. + */ + qdev_prop_set_uint32(dev, "clock-frequency", + clock_get_hz(s->m3clk) / s->apb0div); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { return; } @@ -207,8 +215,6 @@ static Property m2sxxx_soc_properties[] =3D { DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SI= ZE), DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_MAX_SIZE), - /* Libero GUI shows 100Mhz as default for clocks */ - DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), /* default divisors in Libero GUI */ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 343ec977c07..396e8b99138 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/qdev-clock.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" =20 @@ -49,6 +50,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) BusState *spi_bus; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *ddr =3D g_new(MemoryRegion, 1); + Clock *m3clk; =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { error_report("This board can only be used with CPU %s", @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machin= e) * in Libero. CPU clock is divided by APB0 and APB1 divisors for * peripherals. Emcraft's SoM kit comes with these settings by default. */ - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); + /* This clock doesn't need migration because it is fixed-frequency */ + m3clk =3D clock_new(OBJECT(machine), "m3clk"); + clock_set_hz(m3clk, 142 * 1000000); + qdev_connect_clock_in(dev, "m3clk", m3clk); qdev_prop_set_uint32(dev, "apb0div", 2); qdev_prop_set_uint32(dev, "apb1div", 2); =20 --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495216; cv=none; d=zohomail.com; s=zohoarc; b=fBfKbNDRDY3A2GzeAQJDQ4Gl/J0LqJWkuA0RUcNNYDxviOYjaJ4eTiRFVeK+mOfG2ptq+d/my3npcb9quL59GZyYhg4GxL730Bb2Hr/Ugb2AGZi6c9SP65D7PBpFXIa3qE456HkS/mIUbOSmxAfB9jq3A2UzbfO1USLD7KWsBss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495216; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YfmS8KcbL5xTQ2x/y0zCDcF/pwktqOgewwCvAoUA9UE=; b=gT0eNTqCR3QS+pxejqrkVwZIXPT881Nld9LbpnH3wWvRep0eDvnxFoIzwVKxTsH9hxxH62GSb7KGsEuyA6sJp23A/ZIpVannbGHelztriD3dYcXVU7Q5wKF/rIU88Bsm/mhYfNAs03LSxCvtQnP1S/53FoX+G6sUwzZw/4xr/28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163049521633559.618203418314806; Wed, 1 Sep 2021 04:20:16 -0700 (PDT) Received: from localhost ([::1]:58430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOHv-00081V-7x for importer@patchew.org; Wed, 01 Sep 2021 07:20:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcd-0007ED-LY for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:36 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:35428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcW-00061e-RO for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:34 -0400 Received: by mail-wm1-x331.google.com with SMTP id z9-20020a7bc149000000b002e8861aff59so4426863wmi.0 for ; Wed, 01 Sep 2021 03:37:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YfmS8KcbL5xTQ2x/y0zCDcF/pwktqOgewwCvAoUA9UE=; b=OMPkUxOBBK2ka76XaXJ1OSeXCIxuE8z1qVLZYjal3zkyDIdsNXKj0SjwbKnFJR5h2+ ApUsvJP70Z1i4W35tekGVCDAgJf7gGxVz884MWgEgZPQsWiZZ49+E33m3PIOfPMbhdUy F3hy9uD6KGQol80GDyqKTuwPN9bhcFePNC0odMadZLR+hLe4alBTAa7l7eZcMfnDOWJM z7HSDmyq+El14pO8xLq62STGjCt34Jneaf+ted+z6v6EO1rX5hwHEB/ZGkuXJ2UOoWr+ DnlOOR968I9L4aRTU+o0xaHq6uWXmZM0fpBUVDtRAbpc0z834C+WXpDGfH4wDiM2YUkp 2HbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YfmS8KcbL5xTQ2x/y0zCDcF/pwktqOgewwCvAoUA9UE=; b=BcxbrArtxTydQctcSngSsmBbHBlrMVaGrzL9CAux/7aiBUDpZYWo+vxMdexUWCnk3O pPNGwltfR6qfjr4lxCT5a9XbXrsVgBiT3DneQ2njrInzgtZDcYoHzwpotWYHucxAX7V2 1tefNk12uZFvFoo3fa48ia7NfVu8nCTURyokMf8FnLhv1/ErkqKYeCRbvL4CxUYq9t+v o5qILvTTF8bkk+tLL7zsWSymO4JUTsDauN/+gyQSkRtbpwQCz+249AJTIdDr2OST4GW8 PxewLhiySB4/Mv2i0nq7VjucUxgrHc6hSiNofDf7z17YX2M959NTSkqToW9JY6LRT6Y/ ydag== X-Gm-Message-State: AOAM530YD+rRRIkRyhS0qJ8VN9aNKoRAcWc10aAvNgn4S+pv38ch9cFh wMLX5e0MdLtr+DljVw3MKWN+Wmvkyho0lQ== X-Google-Smtp-Source: ABdhPJxGy0aBDavDq18kQHZEQpzZAxh7CqzTKFGbsro29QrIeKfNP+bKI4e9sDSXBr+bOqL/p2FTQA== X-Received: by 2002:a1c:1b49:: with SMTP id b70mr9022646wmb.17.1630492647020; Wed, 01 Sep 2021 03:37:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/51] hw/arm/msf2-soc: Wire up refclk Date: Wed, 1 Sep 2021 11:36:48 +0100 Message-Id: <20210901103653.13435-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495218391100001 Content-Type: text/plain; charset="utf-8" Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-21-peter.maydell@linaro.org --- include/hw/arm/msf2-soc.h | 1 + hw/arm/msf2-soc.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 01f904cec47..ce417a6266a 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -59,6 +59,7 @@ struct MSF2State { uint64_t esram_size; =20 Clock *m3clk; + Clock *refclk; uint8_t apb0div; uint8_t apb1div; =20 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 0a1e594aee6..dbc6d936a76 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -76,6 +76,7 @@ static void m2sxxx_soc_initfn(Object *obj) object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); =20 s->m3clk =3D qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -92,6 +93,27 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk must not be wired up by the board code"); + return; + } + + /* + * TODO: ideally we should model the SoC SYSTICK_CR register at 0xe004= 2038, + * which allows the guest to program the divisor between the m3clk and + * the systick refclk to either /4, /8, /16 or /32, as well as setting + * the value the guest can read in the STCALIB register. Currently we + * implement the divisor as a fixed /32, which matches the reset value + * of SYSTICK_CR. + */ + clock_set_mul_div(s->refclk, 32, 1); + clock_set_source(s->refclk, s->m3clk); + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* @@ -115,6 +137,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495297; cv=none; d=zohomail.com; s=zohoarc; b=I5pRhwjKU90V4mCin9c3U4j0AImmidKqEBuvqhOzwCG/xxMRc7+fvHGhL0g37Q4myNCX4G6SabHR2TQmBNoSKOI6rOwCagOP9fgoQSFgySK+JLWkcoo2uo8JRmCJZNDONTz8H2gBx+M3YhxMcqxaMRjVLiCMgTjca7hRHIuJAXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495297; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x6V7x8vd8mmDx6jlbA/cnFhWbNTtQAMda9Ty8V7a0BY=; b=lR1ANST1O4PAP8SsgChqXOr4U45Sl0GScxgB1lcgcTz0GEv2p/NTaEjiri4SkCchgu4NC0ydzIbAcnQ4+9KqPbsakh1RphS5od7lmpCkZnsoMPq/udQUiEWwV5L66pKbEFDxTWhxlPFflUHJDPr5gngcB6VN434sFu2VhWej7Ck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630495297379710.5816785842587; Wed, 1 Sep 2021 04:21:37 -0700 (PDT) Received: from localhost ([::1]:33756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOJE-00020w-5f for importer@patchew.org; Wed, 01 Sep 2021 07:21:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcd-0007EE-Tq for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:36 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:38726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcX-00061q-JO for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:35 -0400 Received: by mail-wm1-x333.google.com with SMTP id d22-20020a1c1d16000000b002e7777970f0so4387714wmd.3 for ; Wed, 01 Sep 2021 03:37:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=x6V7x8vd8mmDx6jlbA/cnFhWbNTtQAMda9Ty8V7a0BY=; b=gPrSATXXCMc1Z0VGT5U2kIpDgDtYWhjL4j6xTdpOrJ5ym0QsdIya0UGRcv0lgQ9DAk uJbkru8MgdwZFmiK8Hgr9kj4F0VDUZ76SvTehgxG8bm5wuifUEmMqviaRhnyLA4mqeLM Rfktc4km7sEZQfPE5Ffhs8rPG5h+EE0YUJm3OmXYsTybNjFSnPAZeavL93Gphpfxgy2J LWNvxpmYkfWTiTj3hsqBD92MQD3w/+Wapz5kDoZb5swMax0D7t3rwvQpLBPy4VqLaOf9 f81HcQ3cwsHxsyAshNZzOWUFEPm06OjrEhwX5bWNig0nZOH124mHRwzPcy+jpjOg1BH5 0kag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x6V7x8vd8mmDx6jlbA/cnFhWbNTtQAMda9Ty8V7a0BY=; b=aapn0hJQ2Z0nCUsC4xkdwVtpCpYNgro6qb/o6nSQ7m9bSXqmTuH89QiEhvM7jLu+u6 07TVWffK9VRbx3GpJDDF1kRBh2MF3vvZJqoM36FkZO2K4IR3EvsDkV9TCuTyBPPV1Z8u nH7I4HtCbzmXJw2W/ft8FSW1D9wFva4IvuMs6rWgcKB+tLVRQNXfHjsQUti4/EEbTJC8 HYkNlxRTHs4rX0vTpLBTiogV+y1cy3FsFsdAUusDArxQ9dvyajeFgylLu3bnVkBEPnU9 CKKltgIZM9678n+o6M3ZMYOxWs6zPxWUpb/tli4J0QoL96xeLwJko6+DgRvlfivAYCZj F0bA== X-Gm-Message-State: AOAM532XjqgxXQGyUSkJQZaS1jhC951G+xt29XQ0C+rtpfnk9Cx9qIz8 mZSFEBz2E+cJcV3/VsY8bnw8quUdM2dxlQ== X-Google-Smtp-Source: ABdhPJxsyV1tgajtaup0B3GlWB3/smSwkZsCgr+/v1JwZH65K96gkRVwaXga4jvHfF8Di2mXGflMXQ== X-Received: by 2002:a1c:3b56:: with SMTP id i83mr8413900wma.115.1630492647729; Wed, 01 Sep 2021 03:37:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/51] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Date: Wed, 1 Sep 2021 11:36:49 +0100 Message-Id: <20210901103653.13435-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495298070100001 Content-Type: text/plain; charset="utf-8" Now that all users of the systick devices wire up the clock inputs, use those instead of the system_clock_scale and the hardwired 1MHz value for the reference clock. This will fix various board models where we were incorrectly providing a 1MHz reference clock instead of some other value or instead of providing no reference clock at all. Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-22-peter.maydell@linaro.org --- hw/timer/armv7m_systick.c | 112 ++++++++++++++++++++++++++++---------- 1 file changed, 84 insertions(+), 28 deletions(-) diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index e43f74114e8..21f6d0fd24f 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -18,25 +18,30 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qapi/error.h" #include "trace.h" =20 -/* qemu timers run at 1GHz. We want something closer to 1MHz. */ -#define SYSTICK_SCALE 1000ULL - #define SYSTICK_ENABLE (1 << 0) #define SYSTICK_TICKINT (1 << 1) #define SYSTICK_CLKSOURCE (1 << 2) #define SYSTICK_COUNTFLAG (1 << 16) =20 +#define SYSCALIB_NOREF (1U << 31) +#define SYSCALIB_SKEW (1U << 30) +#define SYSCALIB_TENMS ((1U << 24) - 1) + int system_clock_scale; =20 -/* Conversion factor from qemu timer to SysTick frequencies. */ -static inline int64_t systick_scale(SysTickState *s) +static void systick_set_period_from_clock(SysTickState *s) { + /* + * Set the ptimer period from whichever clock is selected. + * Must be called from within a ptimer transaction block. + */ if (s->control & SYSTICK_CLKSOURCE) { - return system_clock_scale; + ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); } else { - return 1000; + ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); } } =20 @@ -83,7 +88,28 @@ static MemTxResult systick_read(void *opaque, hwaddr add= r, uint64_t *data, val =3D ptimer_get_count(s->ptimer); break; case 0xc: /* SysTick Calibration Value. */ - val =3D 10000; + /* + * In real hardware it is possible to make this register report + * a different value from what the reference clock is actually + * running at. We don't model that (which usually happens due + * to integration errors in the real hardware) and instead always + * report the theoretical correct value as described in the + * knowledgebase article at + * https://developer.arm.com/documentation/ka001325/latest + * If necessary, we could implement an extra QOM property on this + * device to force the STCALIB value to something different from + * the "correct" value. + */ + if (!clock_has_source(s->refclk)) { + val =3D SYSCALIB_NOREF; + break; + } + val =3D clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1; + val &=3D SYSCALIB_TENMS; + if (clock_ticks_to_ns(s->refclk, val + 1) !=3D 10 * SCALE_MS) { + /* report that tick count does not yield exactly 10ms */ + val |=3D SYSCALIB_SKEW; + } break; default: val =3D 0; @@ -115,6 +141,11 @@ static MemTxResult systick_write(void *opaque, hwaddr = addr, { uint32_t oldval; =20 + if (!clock_has_source(s->refclk)) { + /* This bit is always 1 if there is no external refclk */ + value |=3D SYSTICK_CLKSOURCE; + } + ptimer_transaction_begin(s->ptimer); oldval =3D s->control; s->control &=3D 0xfffffff8; @@ -122,19 +153,14 @@ static MemTxResult systick_write(void *opaque, hwaddr= addr, =20 if ((oldval ^ value) & SYSTICK_ENABLE) { if (value & SYSTICK_ENABLE) { - /* - * Always reload the period in case board code has - * changed system_clock_scale. If we ever replace that - * global with a more sensible API then we might be able - * to set the period only when it actually changes. - */ - ptimer_set_period(s->ptimer, systick_scale(s)); ptimer_run(s->ptimer, 0); } else { ptimer_stop(s->ptimer); } - } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) { - ptimer_set_period(s->ptimer, systick_scale(s)); + } + + if ((oldval ^ value) & SYSTICK_CLKSOURCE) { + systick_set_period_from_clock(s); } ptimer_transaction_commit(s->ptimer); break; @@ -177,20 +203,42 @@ static void systick_reset(DeviceState *dev) { SysTickState *s =3D SYSTICK(dev); =20 - /* - * Forgetting to set system_clock_scale is always a board code - * bug. We can't check this earlier because for some boards - * (like stellaris) it is not yet configured at the point where - * the systick device is realized. - */ - assert(system_clock_scale !=3D 0); - ptimer_transaction_begin(s->ptimer); s->control =3D 0; + if (!clock_has_source(s->refclk)) { + /* This bit is always 1 if there is no external refclk */ + s->control |=3D SYSTICK_CLKSOURCE; + } ptimer_stop(s->ptimer); ptimer_set_count(s->ptimer, 0); ptimer_set_limit(s->ptimer, 0, 0); - ptimer_set_period(s->ptimer, systick_scale(s)); + systick_set_period_from_clock(s); + ptimer_transaction_commit(s->ptimer); +} + +static void systick_cpuclk_update(void *opaque, ClockEvent event) +{ + SysTickState *s =3D SYSTICK(opaque); + + if (!(s->control & SYSTICK_CLKSOURCE)) { + /* currently using refclk, we can ignore cpuclk changes */ + } + + ptimer_transaction_begin(s->ptimer); + ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); + ptimer_transaction_commit(s->ptimer); +} + +static void systick_refclk_update(void *opaque, ClockEvent event) +{ + SysTickState *s =3D SYSTICK(opaque); + + if (s->control & SYSTICK_CLKSOURCE) { + /* currently using cpuclk, we can ignore refclk changes */ + } + + ptimer_transaction_begin(s->ptimer); + ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); ptimer_transaction_commit(s->ptimer); } =20 @@ -203,8 +251,10 @@ static void systick_instance_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); =20 - s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); - s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", + systick_refclk_update, s, ClockUpdate); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", + systick_cpuclk_update, s, ClockUpdate); } =20 static void systick_realize(DeviceState *dev, Error **errp) @@ -215,6 +265,12 @@ static void systick_realize(DeviceState *dev, Error **= errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); + + if (!clock_has_source(s->cpuclk)) { + error_setg(errp, "systick: cpuclk must be connected"); + return; + } + /* It's OK not to connect the refclk */ } =20 static const VMStateDescription vmstate_systick =3D { --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495298; cv=none; d=zohomail.com; s=zohoarc; b=GIHgxPQYZ3lx+5G94GPgWzkagLVwk7sH0/d0dIWNb/SIO2qmn/QP4cDi/i3wVzb6G9wQ/sHV54WiaB9owqtTV87hxQw1Gjx1gWb9QYf62DvcJMv+bq7EWkXutaotur4NQ8eKExETMLQlyC1XHKaWQFFGAM0yJKTsIbouvac0jcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495298; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ckp80nlDU4/ey/A8MJ/XLY8rFcOiqC46e1I8EaAN4Kw=; b=j8kuqgJ/p0hPFQL/X73oUnA9WgMpl5Ksl0JI6zWdVWxMfVecPv8Wck/qi/r03FlG8WEg2tLot2a72onv2+ehKWUif7IRBw2ZwskGdT4h/iKvBA+YCSESXMime7MerynL70r+w41cpJ/ffGYvm26DHhPr0Hn/Ml9PC/w5g3xwmhA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630495298967884.6982878151952; Wed, 1 Sep 2021 04:21:38 -0700 (PDT) Received: from localhost ([::1]:33918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOJF-00027F-V7 for importer@patchew.org; Wed, 01 Sep 2021 07:21:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNce-0007EF-7U for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:36 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:40665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcX-00061z-Js for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:35 -0400 Received: by mail-wr1-x434.google.com with SMTP id t15so3734191wrg.7 for ; Wed, 01 Sep 2021 03:37:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ckp80nlDU4/ey/A8MJ/XLY8rFcOiqC46e1I8EaAN4Kw=; b=B5RkjGbrsmxikKlMRG2RmL+UfeDS6lh6J/oLs5V/yD3UDu8A9QpKRs2zcIStAgmY6B BLlGsft31OeG8mjjsl25rFmgkEYoBflOPZngdVMS8JVyjQ/mnOh/bj/A6wQdNmw+5qHZ Oq+kCfIOQpT5TzIOejvkPFbj6ruqxLKep+spikSRNTdDwBKHYlBuH9cGs8B5zGvKyJKt kz42mrYP1JaGjjCgTCqxCgGjWxQq5woU0uu5AYpgZ0m+twNpIuXLSZusdoyoZGAdV8f7 IImH0Djwi16HHSMfhLP5WRAO55zUsTWlSf9FYt7nCnA05AiLd9EBvz3dKMHaWvx2td38 f3eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ckp80nlDU4/ey/A8MJ/XLY8rFcOiqC46e1I8EaAN4Kw=; b=ooptzRgmPsErjjBMAId/7zYAx1iPjbJBvFhNyimGN+7sQGnWxzuYZZhyPjUGUima4i yOpN+nEbtRwHg3pfcyleVaG29bK9Zc/MHGhKk+6J21c0J4z50eKBURo/LFB+Cwjbsmg6 e2t/xb5pp1JCwh3XgF5EIPrQPUWpCnH5rczqv/L9ZfZbpvRSayGrEzN0Ss56Bm3MHkAt boTd4p/iV0BfAip9F5UHBOQyn/+rk/27MD/Hpj5K/R+xmx/krninNVfqNhmsAMhwlALk mPS5AIx1HBCtbm646Q9oMGZJ7iwhybGF/Ghu2ojaN2UpudWVAP+HcbWx6Q/s6iPEERyD MR4g== X-Gm-Message-State: AOAM531Mma6VJ96XDlDEEK3dhQRLuVlg2budo0uN7goH2uLfpgrMJC/9 X/pn9LWCcTI1zb8KoqEJymo07kBMiLZ8UQ== X-Google-Smtp-Source: ABdhPJzDLt5/kmzUQP/pv6i4PC/9deV4PuoMoKmPAePorFLS8BJAEiCQ7eWCesz+rshZrNRR5Jpy3Q== X-Received: by 2002:a5d:674b:: with SMTP id l11mr36701521wrw.357.1630492648260; Wed, 01 Sep 2021 03:37:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/51] hw/arm/stellaris: Fix code style issues in GPTM code Date: Wed, 1 Sep 2021 11:36:50 +0100 Message-Id: <20210901103653.13435-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495300460100001 Content-Type: text/plain; charset="utf-8" Fix the code style issues in the Stellaris general purpose timer module code, so that when we move it to a different file in a following patch checkpatch doesn't complain. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Message-id: 20210812093356.1946-23-peter.maydell@linaro.org --- hw/arm/stellaris.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8c8bd39e2fe..a32c567ce11 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -97,10 +97,11 @@ static void gptm_stop(gptm_state *s, int n) static void gptm_reload(gptm_state *s, int n, int reset) { int64_t tick; - if (reset) + if (reset) { tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - else + } else { tick =3D s->tick[n]; + } =20 if (s->config =3D=3D 0) { /* 32-bit CountDown. */ @@ -227,9 +228,11 @@ static void gptm_write(void *opaque, hwaddr offset, gptm_state *s =3D (gptm_state *)opaque; uint32_t oldval; =20 - /* The timers should be disabled before changing the configuration. - We take advantage of this and defer everything until the timer - is enabled. */ + /* + * The timers should be disabled before changing the configuration. + * We take advantage of this and defer everything until the timer + * is enabled. + */ switch (offset) { case 0x00: /* CFG */ s->config =3D value; --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495830; cv=none; d=zohomail.com; s=zohoarc; b=TyZq4B/sekNTcgdmDJZOGNavn9f6FKMW+twXaqLFnNh4jJffm2mWRrqp1FwnF0bRYR1dceamd16N5IBNXldE3lVPGKfdZcA59wRgY6hqqyIX+xxF8SuIUoMIMWzOx2Tksx+565iKLIoxPPriJtm8fvIVuHJ5wnEaRvlORw8ukLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495830; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jFeBKbkPj8LtYhyHr0NKxlDTxKuftg2eP5azWhTlQ4o=; b=NWtr0f/fQjUjjcU1OvVdvxKsmcfP61DoKE8gUPSjecrtsc6wY0DlDE+QJNz0e+LbEt7AucmbLnk9ddTU+/WTeKgvL0PQWfVNbviSyDKZJISotOgGWMCWedTlrTNsCuVhr5ZYVfyeyOY2XER6AivW5hE4NA/j4+hvErm6h2+qjeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630495830482711.5805400062046; Wed, 1 Sep 2021 04:30:30 -0700 (PDT) Received: from localhost ([::1]:52882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLORp-0006Vu-Do for importer@patchew.org; Wed, 01 Sep 2021 07:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcg-0007If-6t for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:38 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:37863) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcZ-00063f-Rx for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:37 -0400 Received: by mail-wm1-x32a.google.com with SMTP id c8-20020a7bc008000000b002e6e462e95fso4410316wmb.2 for ; Wed, 01 Sep 2021 03:37:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jFeBKbkPj8LtYhyHr0NKxlDTxKuftg2eP5azWhTlQ4o=; b=jmw4hWMUsYGKpJRB05nSVY2T7iJ2TIczTcBCuenkt8ttm47gVtfiv9xZNHdC5jPGJN +pboArlVnE0u9MSHhmlBRP8tn836j9KMs3YwuHkquUZYFkcCoAtvo3i29xhN+h2DuRyV FJXZwcQGqstQzyJAa3zcyxczspPYiPGKIpI7SigGSQj5bhBZNaBV1V7/BHiQf3KyMWnv X3Fjl8lA9i9ITAa8Tlky4LDwKZOhNVLC/3YFiTXJFhA5CG+u2gv+9nRRV+TQaz1vWXIm Uj9/sKIRKGdKv8PD33sfH/HqbFwEwl+Q24sJOVZHjdWgwhMh5Wg1D9RGmOqfrJuEfy5B dcHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jFeBKbkPj8LtYhyHr0NKxlDTxKuftg2eP5azWhTlQ4o=; b=Yrp+eqKzo84lQq3ytroEyD22TDMvTu5j0dfMbfPCWZ1AQYj47BobYKcik3enatOmGG 1SubjG0uvfWuoig3nB6Ihz+vdua0VNSvOYN9QTPm/T6/ZebtKGaCXdqaCbdyxArsPVd+ iRJxVuY9ZPaeee6zqk+BVg6P5qfCBarOp6nglPTanuGOdx32UD2WzP95TsQWhiSo2RXb zn27VazlA5s3slN21qL4j189tNO58m65Ak5E9KqhKNyfQxA7l0CsShbq1/6C1c5BBFb/ JwEnXzPWO/yT9WbcEnMJdrvD/W+9+Ta2yaPXuUK5aTV7N6sC3vdyxU69m3d9nQQtJm+K 3+OA== X-Gm-Message-State: AOAM532vJgDwCKV2F1KS4StYNEPWEFktn/npqUF5r8e7hlre1/0l8EUq hgIsXPFPUbg/R+t5mvQaVvbkWv6mJ+o2oA== X-Google-Smtp-Source: ABdhPJzKuE/rGYHWBRVqI+HS/xNmj8tOHgOrGr056Onhk3gFfiG03ZlWI9CRPFZ3IL3CYHjzJdwtPA== X-Received: by 2002:a7b:ce87:: with SMTP id q7mr9018944wmj.126.1630492649124; Wed, 01 Sep 2021 03:37:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/51] hw/arm/stellaris: Split stellaris-gptm into its own file Date: Wed, 1 Sep 2021 11:36:51 +0100 Message-Id: <20210901103653.13435-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495839129100001 Content-Type: text/plain; charset="utf-8" The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-24-peter.maydell@linaro.org --- include/hw/timer/stellaris-gptm.h | 48 +++++ hw/arm/stellaris.c | 321 +----------------------------- hw/timer/stellaris-gptm.c | 314 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/timer/Kconfig | 3 + hw/timer/meson.build | 1 + 6 files changed, 368 insertions(+), 320 deletions(-) create mode 100644 include/hw/timer/stellaris-gptm.h create mode 100644 hw/timer/stellaris-gptm.c diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris= -gptm.h new file mode 100644 index 00000000000..b8fa43c94bf --- /dev/null +++ b/include/hw/timer/stellaris-gptm.h @@ -0,0 +1,48 @@ +/* + * Luminary Micro Stellaris General Purpose Timer Module + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#ifndef HW_TIMER_STELLARIS_GPTM_H +#define HW_TIMER_STELLARIS_GPTM_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_STELLARIS_GPTM "stellaris-gptm" +OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) + +/* + * QEMU interface: + * + sysbus MMIO region 0: register bank + * + sysbus IRQ 0: timer interrupt + * + unnamed GPIO output 0: trigger output for the ADC + */ +struct gptm_state { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t config; + uint32_t mode[2]; + uint32_t control; + uint32_t state; + uint32_t mask; + uint32_t load[2]; + uint32_t match[2]; + uint32_t prescale[2]; + uint32_t match_prescale[2]; + uint32_t rtc; + int64_t tick[2]; + struct gptm_state *opaque[2]; + QEMUTimer *timer[2]; + /* The timers have an alternate output used to trigger the ADC. */ + qemu_irq trigger; + qemu_irq irq; +}; + +#endif diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index a32c567ce11..8c547f146a9 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -26,6 +26,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" #include "hw/misc/unimp.h" +#include "hw/timer/stellaris-gptm.h" #include "hw/qdev-clock.h" #include "qom/object.h" =20 @@ -55,309 +56,6 @@ typedef const struct { uint32_t peripherals; } stellaris_board_info; =20 -/* General purpose timer module. */ - -#define TYPE_STELLARIS_GPTM "stellaris-gptm" -OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) - -struct gptm_state { - SysBusDevice parent_obj; - - MemoryRegion iomem; - uint32_t config; - uint32_t mode[2]; - uint32_t control; - uint32_t state; - uint32_t mask; - uint32_t load[2]; - uint32_t match[2]; - uint32_t prescale[2]; - uint32_t match_prescale[2]; - uint32_t rtc; - int64_t tick[2]; - struct gptm_state *opaque[2]; - QEMUTimer *timer[2]; - /* The timers have an alternate output used to trigger the ADC. */ - qemu_irq trigger; - qemu_irq irq; -}; - -static void gptm_update_irq(gptm_state *s) -{ - int level; - level =3D (s->state & s->mask) !=3D 0; - qemu_set_irq(s->irq, level); -} - -static void gptm_stop(gptm_state *s, int n) -{ - timer_del(s->timer[n]); -} - -static void gptm_reload(gptm_state *s, int n, int reset) -{ - int64_t tick; - if (reset) { - tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } else { - tick =3D s->tick[n]; - } - - if (s->config =3D=3D 0) { - /* 32-bit CountDown. */ - uint32_t count; - count =3D s->load[0] | (s->load[1] << 16); - tick +=3D (int64_t)count * system_clock_scale; - } else if (s->config =3D=3D 1) { - /* 32-bit RTC. 1Hz tick. */ - tick +=3D NANOSECONDS_PER_SECOND; - } else if (s->mode[n] =3D=3D 0xa) { - /* PWM mode. Not implemented. */ - } else { - qemu_log_mask(LOG_UNIMP, - "GPTM: 16-bit timer mode unimplemented: 0x%x\n", - s->mode[n]); - return; - } - s->tick[n] =3D tick; - timer_mod(s->timer[n], tick); -} - -static void gptm_tick(void *opaque) -{ - gptm_state **p =3D (gptm_state **)opaque; - gptm_state *s; - int n; - - s =3D *p; - n =3D p - s->opaque; - if (s->config =3D=3D 0) { - s->state |=3D 1; - if ((s->control & 0x20)) { - /* Output trigger. */ - qemu_irq_pulse(s->trigger); - } - if (s->mode[0] & 1) { - /* One-shot. */ - s->control &=3D ~1; - } else { - /* Periodic. */ - gptm_reload(s, 0, 0); - } - } else if (s->config =3D=3D 1) { - /* RTC. */ - uint32_t match; - s->rtc++; - match =3D s->match[0] | (s->match[1] << 16); - if (s->rtc > match) - s->rtc =3D 0; - if (s->rtc =3D=3D 0) { - s->state |=3D 8; - } - gptm_reload(s, 0, 0); - } else if (s->mode[n] =3D=3D 0xa) { - /* PWM mode. Not implemented. */ - } else { - qemu_log_mask(LOG_UNIMP, - "GPTM: 16-bit timer mode unimplemented: 0x%x\n", - s->mode[n]); - } - gptm_update_irq(s); -} - -static uint64_t gptm_read(void *opaque, hwaddr offset, - unsigned size) -{ - gptm_state *s =3D (gptm_state *)opaque; - - switch (offset) { - case 0x00: /* CFG */ - return s->config; - case 0x04: /* TAMR */ - return s->mode[0]; - case 0x08: /* TBMR */ - return s->mode[1]; - case 0x0c: /* CTL */ - return s->control; - case 0x18: /* IMR */ - return s->mask; - case 0x1c: /* RIS */ - return s->state; - case 0x20: /* MIS */ - return s->state & s->mask; - case 0x24: /* CR */ - return 0; - case 0x28: /* TAILR */ - return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); - case 0x2c: /* TBILR */ - return s->load[1]; - case 0x30: /* TAMARCHR */ - return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); - case 0x34: /* TBMATCHR */ - return s->match[1]; - case 0x38: /* TAPR */ - return s->prescale[0]; - case 0x3c: /* TBPR */ - return s->prescale[1]; - case 0x40: /* TAPMR */ - return s->match_prescale[0]; - case 0x44: /* TBPMR */ - return s->match_prescale[1]; - case 0x48: /* TAR */ - if (s->config =3D=3D 1) { - return s->rtc; - } - qemu_log_mask(LOG_UNIMP, - "GPTM: read of TAR but timer read not supported\n"); - return 0; - case 0x4c: /* TBR */ - qemu_log_mask(LOG_UNIMP, - "GPTM: read of TBR but timer read not supported\n"); - return 0; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", - offset); - return 0; - } -} - -static void gptm_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - gptm_state *s =3D (gptm_state *)opaque; - uint32_t oldval; - - /* - * The timers should be disabled before changing the configuration. - * We take advantage of this and defer everything until the timer - * is enabled. - */ - switch (offset) { - case 0x00: /* CFG */ - s->config =3D value; - break; - case 0x04: /* TAMR */ - s->mode[0] =3D value; - break; - case 0x08: /* TBMR */ - s->mode[1] =3D value; - break; - case 0x0c: /* CTL */ - oldval =3D s->control; - s->control =3D value; - /* TODO: Implement pause. */ - if ((oldval ^ value) & 1) { - if (value & 1) { - gptm_reload(s, 0, 1); - } else { - gptm_stop(s, 0); - } - } - if (((oldval ^ value) & 0x100) && s->config >=3D 4) { - if (value & 0x100) { - gptm_reload(s, 1, 1); - } else { - gptm_stop(s, 1); - } - } - break; - case 0x18: /* IMR */ - s->mask =3D value & 0x77; - gptm_update_irq(s); - break; - case 0x24: /* CR */ - s->state &=3D ~value; - break; - case 0x28: /* TAILR */ - s->load[0] =3D value & 0xffff; - if (s->config < 4) { - s->load[1] =3D value >> 16; - } - break; - case 0x2c: /* TBILR */ - s->load[1] =3D value & 0xffff; - break; - case 0x30: /* TAMARCHR */ - s->match[0] =3D value & 0xffff; - if (s->config < 4) { - s->match[1] =3D value >> 16; - } - break; - case 0x34: /* TBMATCHR */ - s->match[1] =3D value >> 16; - break; - case 0x38: /* TAPR */ - s->prescale[0] =3D value; - break; - case 0x3c: /* TBPR */ - s->prescale[1] =3D value; - break; - case 0x40: /* TAPMR */ - s->match_prescale[0] =3D value; - break; - case 0x44: /* TBPMR */ - s->match_prescale[0] =3D value; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", - offset); - } - gptm_update_irq(s); -} - -static const MemoryRegionOps gptm_ops =3D { - .read =3D gptm_read, - .write =3D gptm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static const VMStateDescription vmstate_stellaris_gptm =3D { - .name =3D "stellaris_gptm", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { - VMSTATE_UINT32(config, gptm_state), - VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), - VMSTATE_UINT32(control, gptm_state), - VMSTATE_UINT32(state, gptm_state), - VMSTATE_UINT32(mask, gptm_state), - VMSTATE_UNUSED(8), - VMSTATE_UINT32_ARRAY(load, gptm_state, 2), - VMSTATE_UINT32_ARRAY(match, gptm_state, 2), - VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), - VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), - VMSTATE_UINT32(rtc, gptm_state), - VMSTATE_INT64_ARRAY(tick, gptm_state, 2), - VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), - VMSTATE_END_OF_LIST() - } -}; - -static void stellaris_gptm_init(Object *obj) -{ - DeviceState *dev =3D DEVICE(obj); - gptm_state *s =3D STELLARIS_GPTM(obj); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - - sysbus_init_irq(sbd, &s->irq); - qdev_init_gpio_out(dev, &s->trigger, 1); - - memory_region_init_io(&s->iomem, obj, &gptm_ops, s, - "gptm", 0x1000); - sysbus_init_mmio(sbd, &s->iomem); - - s->opaque[0] =3D s->opaque[1] =3D s; -} - -static void stellaris_gptm_realize(DeviceState *dev, Error **errp) -{ - gptm_state *s =3D STELLARIS_GPTM(dev); - s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); - s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); -} - /* System controller. */ =20 #define TYPE_STELLARIS_SYS "stellaris-sys" @@ -1642,22 +1340,6 @@ static const TypeInfo stellaris_i2c_info =3D { .class_init =3D stellaris_i2c_class_init, }; =20 -static void stellaris_gptm_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &vmstate_stellaris_gptm; - dc->realize =3D stellaris_gptm_realize; -} - -static const TypeInfo stellaris_gptm_info =3D { - .name =3D TYPE_STELLARIS_GPTM, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(gptm_state), - .instance_init =3D stellaris_gptm_init, - .class_init =3D stellaris_gptm_class_init, -}; - static void stellaris_adc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1696,7 +1378,6 @@ static const TypeInfo stellaris_sys_info =3D { static void stellaris_register_types(void) { type_register_static(&stellaris_i2c_info); - type_register_static(&stellaris_gptm_info); type_register_static(&stellaris_adc_info); type_register_static(&stellaris_sys_info); } diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c new file mode 100644 index 00000000000..7846fe5f84e --- /dev/null +++ b/hw/timer/stellaris-gptm.c @@ -0,0 +1,314 @@ +/* + * Luminary Micro Stellaris General Purpose Timer Module + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" +#include "hw/timer/stellaris-gptm.h" +#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale= */ + +static void gptm_update_irq(gptm_state *s) +{ + int level; + level =3D (s->state & s->mask) !=3D 0; + qemu_set_irq(s->irq, level); +} + +static void gptm_stop(gptm_state *s, int n) +{ + timer_del(s->timer[n]); +} + +static void gptm_reload(gptm_state *s, int n, int reset) +{ + int64_t tick; + if (reset) { + tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } else { + tick =3D s->tick[n]; + } + + if (s->config =3D=3D 0) { + /* 32-bit CountDown. */ + uint32_t count; + count =3D s->load[0] | (s->load[1] << 16); + tick +=3D (int64_t)count * system_clock_scale; + } else if (s->config =3D=3D 1) { + /* 32-bit RTC. 1Hz tick. */ + tick +=3D NANOSECONDS_PER_SECOND; + } else if (s->mode[n] =3D=3D 0xa) { + /* PWM mode. Not implemented. */ + } else { + qemu_log_mask(LOG_UNIMP, + "GPTM: 16-bit timer mode unimplemented: 0x%x\n", + s->mode[n]); + return; + } + s->tick[n] =3D tick; + timer_mod(s->timer[n], tick); +} + +static void gptm_tick(void *opaque) +{ + gptm_state **p =3D (gptm_state **)opaque; + gptm_state *s; + int n; + + s =3D *p; + n =3D p - s->opaque; + if (s->config =3D=3D 0) { + s->state |=3D 1; + if ((s->control & 0x20)) { + /* Output trigger. */ + qemu_irq_pulse(s->trigger); + } + if (s->mode[0] & 1) { + /* One-shot. */ + s->control &=3D ~1; + } else { + /* Periodic. */ + gptm_reload(s, 0, 0); + } + } else if (s->config =3D=3D 1) { + /* RTC. */ + uint32_t match; + s->rtc++; + match =3D s->match[0] | (s->match[1] << 16); + if (s->rtc > match) + s->rtc =3D 0; + if (s->rtc =3D=3D 0) { + s->state |=3D 8; + } + gptm_reload(s, 0, 0); + } else if (s->mode[n] =3D=3D 0xa) { + /* PWM mode. Not implemented. */ + } else { + qemu_log_mask(LOG_UNIMP, + "GPTM: 16-bit timer mode unimplemented: 0x%x\n", + s->mode[n]); + } + gptm_update_irq(s); +} + +static uint64_t gptm_read(void *opaque, hwaddr offset, + unsigned size) +{ + gptm_state *s =3D (gptm_state *)opaque; + + switch (offset) { + case 0x00: /* CFG */ + return s->config; + case 0x04: /* TAMR */ + return s->mode[0]; + case 0x08: /* TBMR */ + return s->mode[1]; + case 0x0c: /* CTL */ + return s->control; + case 0x18: /* IMR */ + return s->mask; + case 0x1c: /* RIS */ + return s->state; + case 0x20: /* MIS */ + return s->state & s->mask; + case 0x24: /* CR */ + return 0; + case 0x28: /* TAILR */ + return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); + case 0x2c: /* TBILR */ + return s->load[1]; + case 0x30: /* TAMARCHR */ + return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); + case 0x34: /* TBMATCHR */ + return s->match[1]; + case 0x38: /* TAPR */ + return s->prescale[0]; + case 0x3c: /* TBPR */ + return s->prescale[1]; + case 0x40: /* TAPMR */ + return s->match_prescale[0]; + case 0x44: /* TBPMR */ + return s->match_prescale[1]; + case 0x48: /* TAR */ + if (s->config =3D=3D 1) { + return s->rtc; + } + qemu_log_mask(LOG_UNIMP, + "GPTM: read of TAR but timer read not supported\n"); + return 0; + case 0x4c: /* TBR */ + qemu_log_mask(LOG_UNIMP, + "GPTM: read of TBR but timer read not supported\n"); + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", + offset); + return 0; + } +} + +static void gptm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + gptm_state *s =3D (gptm_state *)opaque; + uint32_t oldval; + + /* + * The timers should be disabled before changing the configuration. + * We take advantage of this and defer everything until the timer + * is enabled. + */ + switch (offset) { + case 0x00: /* CFG */ + s->config =3D value; + break; + case 0x04: /* TAMR */ + s->mode[0] =3D value; + break; + case 0x08: /* TBMR */ + s->mode[1] =3D value; + break; + case 0x0c: /* CTL */ + oldval =3D s->control; + s->control =3D value; + /* TODO: Implement pause. */ + if ((oldval ^ value) & 1) { + if (value & 1) { + gptm_reload(s, 0, 1); + } else { + gptm_stop(s, 0); + } + } + if (((oldval ^ value) & 0x100) && s->config >=3D 4) { + if (value & 0x100) { + gptm_reload(s, 1, 1); + } else { + gptm_stop(s, 1); + } + } + break; + case 0x18: /* IMR */ + s->mask =3D value & 0x77; + gptm_update_irq(s); + break; + case 0x24: /* CR */ + s->state &=3D ~value; + break; + case 0x28: /* TAILR */ + s->load[0] =3D value & 0xffff; + if (s->config < 4) { + s->load[1] =3D value >> 16; + } + break; + case 0x2c: /* TBILR */ + s->load[1] =3D value & 0xffff; + break; + case 0x30: /* TAMARCHR */ + s->match[0] =3D value & 0xffff; + if (s->config < 4) { + s->match[1] =3D value >> 16; + } + break; + case 0x34: /* TBMATCHR */ + s->match[1] =3D value >> 16; + break; + case 0x38: /* TAPR */ + s->prescale[0] =3D value; + break; + case 0x3c: /* TBPR */ + s->prescale[1] =3D value; + break; + case 0x40: /* TAPMR */ + s->match_prescale[0] =3D value; + break; + case 0x44: /* TBPMR */ + s->match_prescale[0] =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", + offset); + } + gptm_update_irq(s); +} + +static const MemoryRegionOps gptm_ops =3D { + .read =3D gptm_read, + .write =3D gptm_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription vmstate_stellaris_gptm =3D { + .name =3D "stellaris_gptm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(config, gptm_state), + VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), + VMSTATE_UINT32(control, gptm_state), + VMSTATE_UINT32(state, gptm_state), + VMSTATE_UINT32(mask, gptm_state), + VMSTATE_UNUSED(8), + VMSTATE_UINT32_ARRAY(load, gptm_state, 2), + VMSTATE_UINT32_ARRAY(match, gptm_state, 2), + VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), + VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), + VMSTATE_UINT32(rtc, gptm_state), + VMSTATE_INT64_ARRAY(tick, gptm_state, 2), + VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), + VMSTATE_END_OF_LIST() + } +}; + +static void stellaris_gptm_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + gptm_state *s =3D STELLARIS_GPTM(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + sysbus_init_irq(sbd, &s->irq); + qdev_init_gpio_out(dev, &s->trigger, 1); + + memory_region_init_io(&s->iomem, obj, &gptm_ops, s, + "gptm", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + + s->opaque[0] =3D s->opaque[1] =3D s; +} + +static void stellaris_gptm_realize(DeviceState *dev, Error **errp) +{ + gptm_state *s =3D STELLARIS_GPTM(dev); + s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); + s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); +} + +static void stellaris_gptm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_stellaris_gptm; + dc->realize =3D stellaris_gptm_realize; +} + +static const TypeInfo stellaris_gptm_info =3D { + .name =3D TYPE_STELLARIS_GPTM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(gptm_state), + .instance_init =3D stellaris_gptm_init, + .class_init =3D stellaris_gptm_class_init, +}; + +static void stellaris_gptm_register_types(void) +{ + type_register_static(&stellaris_gptm_info); +} + +type_init(stellaris_gptm_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index dc050b5c37f..78fdd1b9350 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -235,6 +235,7 @@ config STELLARIS select SSI_SD select STELLARIS_INPUT select STELLARIS_ENET # ethernet + select STELLARIS_GPTM # general purpose timer module select UNIMP =20 config STM32VLDISCOVERY diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index bac25117155..1e73da7e120 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -52,5 +52,8 @@ config SSE_COUNTER config SSE_TIMER bool =20 +config STELLARIS_GPTM + bool + config AVR_TIMER16 bool diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 1aa3cd22844..e67478a8f10 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -31,6 +31,7 @@ softmmu_ss.add(when: 'CONFIG_SH_TIMER', if_true: files('s= h_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) +softmmu_ss.add(when: 'CONFIG_STELLARIS_GPTM', if_true: files('stellaris-gp= tm.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_t= imer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c')) --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oXzYNU8QlO8kqMuNHYrgC4Z06DT/XfVcKLfiR2ZMvaM=; b=lNkLokfbEJi1ctgnwJNEK0QnZ8v/BPYj/4N2btHlsfyDPXKioKdGLJGJE2/+XMxxuX OMSH8cknBO88qH5Jd51+7v1+etc6t8jQmp0L9zExet8Y885IWOe4ZLhzblk0uGmdY+ea m50fhj9cvrsJNkK2m/GVHzpDS2Bpl2GgkFAWP4wJAENxSdOHtkWW4TbFSDLTT1g8GpLJ nJbVaiLu+9jkw+6u3dtYLxwxWFKmdptgoa4V6/E6xSly+aLPvtJT8roMvOxcpnJoUGBX XrDwB1AMeu1ZRzY+9GaCXAKrMTTxGyfDMTaYhEbd/A2BJI/fmetpV8Yb87F0lhg9cqoP D+ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oXzYNU8QlO8kqMuNHYrgC4Z06DT/XfVcKLfiR2ZMvaM=; b=cZhNPDixozab9fHOD10e8Nt4NWovH1rOKzEWcR72v3MWEYw2QmcYfHAi+WF6prJ2L9 AD/8vwB8qhykWKaUYuzp4+Fisxsb8VZIz/vLgWD7fKsHBy1zmlhZfk3zOA7jJu5u45Gw +OS+hRaROycgMonf3V0TwFQ6PUopcNEpLM/Fag2imJvJeWfcBW1xJDJHXJxPU12KdUIV P1N/wZ3pUxApCFiWC2f2xEqD5RHXEJdZNatTqD/JIp20Ub6d84IJrxpucBuoZfGRg5mH EbQ8cKiblbc/AknZGqtbL4EBS5FPSf8X9z/JjQ3og+zZGHz6NoaLDKrcxLG6Bytd1J9c MuWQ== X-Gm-Message-State: AOAM532jRl47nWzfBZOz3n8ahzr9hW+LS3h5jHTKaFF35CP1AN+Vmfk2 YTxwqzHZDXlVGj6o2qmTlIZ3yUCOE84Ivg== X-Google-Smtp-Source: ABdhPJwdF06gYC4X433q4RJXEUtQn8FdarFhC6elNyY1z0I2r1Yo0uFdoeFm5E0BOW++nZI5aFm5aQ== X-Received: by 2002:adf:fb8f:: with SMTP id a15mr37378163wrr.92.1630492649730; Wed, 01 Sep 2021 03:37:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/51] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Date: Wed, 1 Sep 2021 11:36:52 +0100 Message-Id: <20210901103653.13435-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495532434100001 Content-Type: text/plain; charset="utf-8" The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde Message-id: 20210812093356.1946-25-peter.maydell@linaro.org --- include/hw/timer/stellaris-gptm.h | 3 +++ hw/arm/stellaris.c | 12 +++++++++--- hw/timer/stellaris-gptm.c | 26 ++++++++++++++++++++++---- 3 files changed, 34 insertions(+), 7 deletions(-) diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris= -gptm.h index b8fa43c94bf..fde1fc6f0c7 100644 --- a/include/hw/timer/stellaris-gptm.h +++ b/include/hw/timer/stellaris-gptm.h @@ -13,6 +13,7 @@ #include "qom/object.h" #include "hw/sysbus.h" #include "hw/irq.h" +#include "hw/clock.h" =20 #define TYPE_STELLARIS_GPTM "stellaris-gptm" OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) @@ -22,6 +23,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) * + sysbus MMIO region 0: register bank * + sysbus IRQ 0: timer interrupt * + unnamed GPIO output 0: trigger output for the ADC + * + Clock input "clk": the 32-bit countdown timer runs at this speed */ struct gptm_state { SysBusDevice parent_obj; @@ -43,6 +45,7 @@ struct gptm_state { /* The timers have an alternate output used to trigger the ADC. */ qemu_irq trigger; qemu_irq irq; + Clock *clk; }; =20 #endif diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8c547f146a9..3e7d1dabad1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1090,9 +1090,15 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) } for (i =3D 0; i < 4; i++) { if (board->dc2 & (0x10000 << i)) { - dev =3D sysbus_create_simple(TYPE_STELLARIS_GPTM, - 0x40030000 + i * 0x1000, - qdev_get_gpio_in(nvic, timer_irq[i]= )); + SysBusDevice *sbd; + + dev =3D qdev_new(TYPE_STELLARIS_GPTM); + sbd =3D SYS_BUS_DEVICE(dev); + qdev_connect_clock_in(dev, "clk", + qdev_get_clock_out(ssys_dev, "SYSCLK")); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]= )); /* TODO: This is incorrect, but we get away with it because the ADC output is only ever pulsed. */ qdev_connect_gpio_out(dev, 0, adc); diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c index 7846fe5f84e..fd71c79be48 100644 --- a/hw/timer/stellaris-gptm.c +++ b/hw/timer/stellaris-gptm.c @@ -10,9 +10,10 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qapi/error.h" #include "migration/vmstate.h" +#include "hw/qdev-clock.h" #include "hw/timer/stellaris-gptm.h" -#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale= */ =20 static void gptm_update_irq(gptm_state *s) { @@ -39,7 +40,7 @@ static void gptm_reload(gptm_state *s, int n, int reset) /* 32-bit CountDown. */ uint32_t count; count =3D s->load[0] | (s->load[1] << 16); - tick +=3D (int64_t)count * system_clock_scale; + tick +=3D clock_ticks_to_ns(s->clk, count); } else if (s->config =3D=3D 1) { /* 32-bit RTC. 1Hz tick. */ tick +=3D NANOSECONDS_PER_SECOND; @@ -247,8 +248,8 @@ static const MemoryRegionOps gptm_ops =3D { =20 static const VMStateDescription vmstate_stellaris_gptm =3D { .name =3D "stellaris_gptm", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(config, gptm_state), VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), @@ -263,6 +264,7 @@ static const VMStateDescription vmstate_stellaris_gptm = =3D { VMSTATE_UINT32(rtc, gptm_state), VMSTATE_INT64_ARRAY(tick, gptm_state, 2), VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), + VMSTATE_CLOCK(clk, gptm_state), VMSTATE_END_OF_LIST() } }; @@ -281,11 +283,27 @@ static void stellaris_gptm_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); =20 s->opaque[0] =3D s->opaque[1] =3D s; + + /* + * TODO: in an ideal world we would model the effects of changing + * the input clock frequency while the countdown timer is active. + * The best way to do this would be to convert the device to use + * ptimer instead of hand-rolling its own timer. This would also + * make it easy to implement reading the current count from the + * TAR and TBR registers. + */ + s->clk =3D qdev_init_clock_in(dev, "clk", NULL, NULL, 0); } =20 static void stellaris_gptm_realize(DeviceState *dev, Error **errp) { gptm_state *s =3D STELLARIS_GPTM(dev); + + if (!clock_has_source(s->clk)) { + error_setg(errp, "stellaris-gptm: clk must be connected"); + return; + } + s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); } --=20 2.20.1 From nobody Sun May 5 11:24:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1630495354; cv=none; d=zohomail.com; s=zohoarc; b=Kw6NvOr4MkUviHfJ3+KVjjxMl1LTomCjG077BKY9Exo1sEl1ZqV46DbSXuhA5bprfKtXKwitiCIXHWGSi0tIXfsZ3aCWroJCaPKes92Z/uqfBXduCzTg5ggKXfEczR/fskqIhFNehtyClkUSPdpzbtVIc8BZg62ovzIHRLXmebc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630495354; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pjHIglZVcmFuWS0fXi1aYzb1TFNuneqcQaujO+wsYlY=; b=H05e8jS8dD3P40tyl9Gd9dszWaGl+HwIxH3sbcDuDBfz1jD80Jbra5fq3IXtxjDjOLAbNjdBaWllKkfCu3dYuBxVEQ8DFM4DjOD6omNHyouTUELihPGNK6kEmDT9POhIl1cg0T2dN/aGXQuaCP1CcF8iHgwt/qIxItj2oWrdhlM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630495354031826.8588090329741; Wed, 1 Sep 2021 04:22:34 -0700 (PDT) Received: from localhost ([::1]:36678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLOK8-0003ym-SP for importer@patchew.org; Wed, 01 Sep 2021 07:22:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLNcf-0007ER-1c for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:37 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:39810) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLNcc-00064e-0R for qemu-devel@nongnu.org; Wed, 01 Sep 2021 06:37:36 -0400 Received: by mail-wm1-x336.google.com with SMTP id u26-20020a05600c441a00b002f66b2d8603so985521wmn.4 for ; Wed, 01 Sep 2021 03:37:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j207sm5494771wmj.40.2021.09.01.03.37.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Sep 2021 03:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pjHIglZVcmFuWS0fXi1aYzb1TFNuneqcQaujO+wsYlY=; b=SpH/Q41t9WTOFP4vUmbC8z4EDDMC4sapxNfDmUA/VISG0+Qd9Ycb3Y9+I4QZRsVN+l T+XOlo5aHMTcUUrr1ePMg+fBWnuGZN0TqoDrnUxFHi7342i45RQJyNUZRyCSs0GKQpLK WJOzuxWK+7vhJKeQAzrWHYjY/wRQGw6ii0DYAIdwBsfVg/zGjVtGgWdlC8cMj5fWiSu6 XbQ+R7QoZpCDV/DapWTgOSfwtxC/cZLU7UBKC08GhU3arS32fvT9Q7XReBqpDOON4+sI xXRqo0h4bohBr4S4K8iC2fT46HZ+xM3nWJ1OmcUz01DHGBgysvZeEQmO3yyHab0vUEkD naUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pjHIglZVcmFuWS0fXi1aYzb1TFNuneqcQaujO+wsYlY=; b=teXChD5kvWrQa8CKummg/8T66R6xCqrghXFnSm/3y7yfCn8rAvPymjvAXY0r8NtVQF 6wr5moNXKEBa9GqbV6K3dOzFK8FLamUygejRvjtcjNdZ01MMfu3uiFLEk+8HsS2Dx4oZ 66zk4neKNw6KVYb+EcZRTdMdM2qZHbDPL8EXj2YaiwapZ4JkYFNrvRNfyCJO3zh8M3c5 yb6uejE1IYIfh7xnXf444XsrGmgH+5CuTFqwOPX0c7XWDpdbE9cowDRPUwvEZH65qxWM Ctup7GkpYSBm3JD/TrItwpF2zJ5a/qdKJtmg+3ZrQVJsvly/VjvNrlrzU2O2f93c/jWQ gsqg== X-Gm-Message-State: AOAM531hdl7MXhNFERmk+PqoC6eXCs48Dsju4WaztlAe3lH2j8i0FLhZ 2N3F8KnMxVw5JqvJVWFkiu0wGgoQTxo/aw== X-Google-Smtp-Source: ABdhPJxJBKvngXoK5bXsaBgGjEddOKsPBVbfuKYJyzGRnnN9SxpI6/NPjvUeCrqoiabmLXrg/jHvhA== X-Received: by 2002:a05:600c:a49:: with SMTP id c9mr8718928wmq.159.1630492650335; Wed, 01 Sep 2021 03:37:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/51] arm: Remove system_clock_scale global Date: Wed, 1 Sep 2021 11:36:53 +0100 Message-Id: <20210901103653.13435-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org> References: <20210901103653.13435-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1630495355701100001 Content-Type: text/plain; charset="utf-8" All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20210812093356.1946-26-peter.maydell@linaro.org --- include/hw/timer/armv7m_systick.h | 22 ---------------------- hw/arm/armsse.c | 17 +---------------- hw/arm/mps2.c | 2 -- hw/arm/msf2-soc.c | 2 -- hw/arm/netduino2.c | 2 -- hw/arm/netduinoplus2.c | 2 -- hw/arm/nrf51_soc.c | 2 -- hw/arm/stellaris.c | 7 ++++--- hw/arm/stm32vldiscovery.c | 2 -- hw/timer/armv7m_systick.c | 2 -- 10 files changed, 5 insertions(+), 55 deletions(-) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 38adf8d274e..ee09b138810 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -47,26 +47,4 @@ struct SysTickState { Clock *cpuclk; }; =20 -/* - * Multiplication factor to convert from system clock ticks to qemu timer - * ticks. This should be set (by board code, usually) to a value - * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency - * in Hz of the CPU. - * - * This value is used by the systick device when it is running in - * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE =3D=3D 1) to - * set how fast the timer should tick. - * - * TODO: we should refactor this so that rather than using a global - * we use a device property or something similar. This is complicated - * because (a) the property would need to be plumbed through from the - * board code down through various layers to the systick device - * and (b) the property needs to be modifiable after realize, because - * the stellaris board uses this to implement the behaviour where the - * guest can reprogram the PLL registers to downclock the CPU, and the - * systick device needs to react accordingly. Possibly this should - * be deferred until we have a good API for modelling clock trees. - */ -extern int system_clock_scale; - #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 70b52c3d4b9..aecdeb9815a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -689,17 +689,6 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } =20 -static void armsse_mainclk_update(void *opaque, ClockEvent event) -{ - ARMSSE *s =3D ARM_SSE(opaque); - - /* - * Set system_clock_scale from our Clock input; this is what - * controls the tick rate of the CPU SysTick timer. - */ - system_clock_scale =3D clock_ticks_to_ns(s->mainclk, 1); -} - static void armsse_init(Object *obj) { ARMSSE *s =3D ARM_SSE(obj); @@ -711,8 +700,7 @@ static void armsse_init(Object *obj) assert(info->sram_banks <=3D MAX_SRAM_BANKS); assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 - s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", - armsse_mainclk_update, s, ClockUpdate); + s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0); s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); =20 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); @@ -1654,9 +1642,6 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * devices in the ARMSSE. */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); - - /* Set initial system_clock_scale from MAINCLK */ - armsse_mainclk_update(s, ClockUpdate); } =20 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 3671f49ad7b..4634aa1a1ca 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -439,8 +439,6 @@ static void mps2_common_init(MachineState *machine) qdev_get_gpio_in(armv7m, mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); } diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index dbc6d936a76..b5fe9f364d5 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -144,8 +144,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) return; } =20 - system_clock_scale =3D clock_ticks_to_ns(s->m3clk, 1); - for (i =3D 0; i < MSF2_NUM_UARTS; i++) { if (serial_hd(i)) { serial_mm_init(get_system_memory(), uart_addr[i], 2, diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index b5c0ba23ee5..3365da11bf7 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -39,8 +39,6 @@ static void netduino2_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index a5a8999cc8c..76cea8e4891 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -39,8 +39,6 @@ static void netduinoplus2_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e3e849a32b1..34da0d62f00 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -84,8 +84,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) * will always provide one). */ =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / HCLK_FRQ; - object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->contain= er), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 3e7d1dabad1..78827ace6b8 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -263,17 +263,18 @@ static bool ssys_use_rcc2(ssys_state *s) */ static void ssys_calculate_system_clock(ssys_state *s, bool propagate_cloc= k) { + int period_ns; /* * SYSDIV field specifies divisor: 0 =3D=3D /1, 1 =3D=3D /2, etc. Inp= ut * clock is 200MHz, which is a period of 5 ns. Dividing the clock * frequency by X is the same as multiplying the period by X. */ if (ssys_use_rcc2(s)) { - system_clock_scale =3D 5 * (((s->rcc2 >> 23) & 0x3f) + 1); + period_ns =3D 5 * (((s->rcc2 >> 23) & 0x3f) + 1); } else { - system_clock_scale =3D 5 * (((s->rcc >> 23) & 0xf) + 1); + period_ns =3D 5 * (((s->rcc >> 23) & 0xf) + 1); } - clock_set_ns(s->sysclk, system_clock_scale); + clock_set_ns(s->sysclk, period_ns); if (propagate_clock) { clock_propagate(s->sysclk); } diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 9b79004703b..04036da3ee0 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -42,8 +42,6 @@ static void stm32vldiscovery_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index 21f6d0fd24f..3bd951dd044 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -30,8 +30,6 @@ #define SYSCALIB_SKEW (1U << 30) #define SYSCALIB_TENMS ((1U << 24) - 1) =20 -int system_clock_scale; - static void systick_set_period_from_clock(SysTickState *s) { /* --=20 2.20.1