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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462233; x=1633054234; bh=KoU7XkDouYiICT5qUB tMPqWtkXPozf9NzlFInuCAXa4=; b=fyTM4t4/hKkb/o3/rqAxq75gh8cjKVQVGB YyjMfiDcuf72Iu1uOIFzMImC2974ygmKIIIxKKaCgFJ0SfooTJ+VOZSlnX+QTitf XnUiLhUn57exuKT8ouDThN8pEGqXKYMx6C5ZENROSJQQ4Q2XuaDzzA0kpQRxe/gR XkvTLKZFPDa+10d8deT94Qk8Mu+Il0DgTTEdBk19MT67gdBdA+TV/sbAX1MrLf6T vPC4Ep1NB8ckc73pJnpiVm4RfinwZj51qW5qi0F/crEnGzprRSbBzl3rrjoGDedr k2HNty8aFFrOiCYlLY7A5b846TwRnl3RfiLQXPLeOvzSBN9AdnAA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, LIU Zhiwei , Bin Meng , Alistair Francis Subject: [PULL 04/33] target/riscv: Don't wrongly override isa version Date: Wed, 1 Sep 2021 12:09:29 +1000 Message-Id: <20210901020958.458454-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462421152100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei For some cpu, the isa version has already been set in cpu init function. Thus only override the isa version when isa version is not set, or users set different isa version explicitly by cpu parameters. Signed-off-by: LIU Zhiwei Reviewed-by: Bin Meng Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..1a2b03d579 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - int priv_version =3D PRIV_VERSION_1_11_0; - int bext_version =3D BEXT_VERSION_0_93_0; - int vext_version =3D VEXT_VERSION_0_07_1; + int priv_version =3D 0; target_ulong target_misa =3D env->misa; Error *local_err =3D NULL; =20 @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - set_priv_version(env, priv_version); - set_bext_version(env, bext_version); - set_vext_version(env, vext_version); + if (priv_version) { + set_priv_version(env, priv_version); + } else if (!env->priv_ver) { + set_priv_version(env, PRIV_VERSION_1_11_0); + } =20 if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) target_misa |=3D RVH; } if (cpu->cfg.ext_b) { + int bext_version =3D BEXT_VERSION_0_93_0; target_misa |=3D RVB; =20 if (cpu->cfg.bext_spec) { @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) set_bext_version(env, bext_version); } if (cpu->cfg.ext_v) { + int vext_version =3D VEXT_VERSION_0_07_1; target_misa |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, --=20 2.31.1