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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462216; x=1633054217; bh=ArkLKSlz3inR61qthi X7vTGJiuccH9vBHN3FXIRV9Bw=; b=BwSBpfC0+e5tYUIHmwcyZWDsngUGIGGGNz 5TVSFQC+91qznuanmsEMtRLLfv9G5/hTCOLxUydCpo2eShK26K8ruKqorhmtxQNL E3HFl9M7jwyiFEm065JWR9YxTqp45XsNeGBlQ6OQcTu2XJqNEBr0u2h8Bf0UaMw3 /kiuxUcXLOs5gDA5+kYHJ5cr231pORmw0L9wKE1rxTaCcVeoMkK1euGkPrdBXjQG PTiwlfNoh+iiiPG17QlDjDcNR4mAO0rPQwS9vxyYvhAloZ+PA38o+nMPUolM7Rar ewkyHvzpvBD7H6D6LXMH3UhzZms7BAnceRsJ1FPFpbbkbUX1zKfw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Vijai Kumar K , Alistair Francis Subject: [PULL 01/33] hw/char: Add config for shakti uart Date: Wed, 1 Sep 2021 12:09:26 +1000 Message-Id: <20210901020958.458454-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462412484100003 Content-Type: text/plain; charset="utf-8" From: Vijai Kumar K Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart. Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Message-id: 20210731190229.137483-1-vijai@behindbytes.com Signed-off-by: Alistair Francis --- hw/char/Kconfig | 3 +++ hw/char/meson.build | 2 +- hw/riscv/Kconfig | 5 +---- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 2e4f620b13..6b6cf2fc1d 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -68,3 +68,6 @@ config SIFIVE_UART =20 config GOLDFISH_TTY bool + +config SHAKTI_UART + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index 8361d0ab28..7b594f51b8 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -16,7 +16,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('ser= ial.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c')) softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci= -multi.c')) -softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c')) +softmmu_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files('shakti_uart.c')) softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-consol= e.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 0590f443fd..ff75add6f3 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -22,13 +22,10 @@ config OPENTITAN select IBEX select UNIMP =20 -config SHAKTI - bool - config SHAKTI_C bool select UNIMP - select SHAKTI + select SHAKTI_UART select SIFIVE_CLINT select SIFIVE_PLIC =20 --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462221; x=1633054222; bh=gre89S+ a81XQEJ08b8fsC/oOWYrA8yqgQv2vZI/fekM=; b=bBsAEo71IOCnbVj3vN1XP5s HpCl7z31X+6p7OlpbU3BKnGyYympi6lsYehoV52lw638CCrPg1Dz1EfWYMcWpD4h TYNj+iS8ysdexavUl2bl6qdZxPj1ZV/IfDLmlOop0kyztihdmS7dZnScF1r6v7GV snCTJsSt7GThrWFglL/5WSeJOROovqL7Gs2AufGrEcMZEJot1tstwLD08R1++JAu 8mtB6MgvkpIK68nISDdCwVZoT1JlvTs49e3uUUoVxXrZlSpUc8bi9qiUi0vqwA/i Y1XQns6HSt7vulADg9eV5cieCmNZkE0gZeRcsKKvk20ghfVW5+gHmPSICudCsHQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 02/33] hw/riscv: virt: Move flash node to root Date: Wed, 1 Sep 2021 12:09:27 +1000 Message-Id: <20210901020958.458454-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462631228100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng The flash is not inside the SoC, so it's inappropriate to put it under the /soc node. Move it to root instead. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0e55411045..aa279c1bb6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -454,7 +454,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); g_free(name); =20 - name =3D g_strdup_printf("/soc/flash@%" PRIx64, flashbase); + name =3D g_strdup_printf("/flash@%" PRIx64, flashbase); qemu_fdt_add_subnode(mc->fdt, name); qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462227; x=1633054228; bh=vaYxnEf/0537kt2nb0 UwvsHsl3ytoVfv7r9+AnO3qH8=; b=KoMfg3XWFQxFdZwq5srHY1VwNqV7EEdahE bhYw2cHkpfVjTzCduifvZILyQ8gSwxhtvdxEoSJlqk15Ki/5K63InKGYGcwNsCOL dM3o7RH7mGyoMFZNeM8/6VmZ8pBq8bONlNySjkyxADNlnwk0N4+/N3tTQXs2gdBL hJcjnv/rR+H+DyUEkC6ptjq559d/Ji9lsGnwi+3pNG0pKErk+whXY3LXu099iHmm cIvzcmneoxhXlocqyUmyAzqW30ouxDEMjcDeeSo4N298ZHasWfPKpa6yg3loYhsl A8j7dSvn0lm8xakYMUVqtPb34fez6nKKKtY7qNLvI0GHVWkDbx2g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw() Date: Wed, 1 Sep 2021 12:09:28 +1000 Message-Id: <20210901020958.458454-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462787871100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned, not -1 (RISCV_EXCP_NONE). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9a4ed18ac5..e747fbe0e9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1423,7 +1423,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); =20 - /* check privileges and return -1 if check fails */ + /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ #if !defined(CONFIG_USER_ONLY) int effective_priv =3D env->priv; int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462233; x=1633054234; bh=KoU7XkDouYiICT5qUB tMPqWtkXPozf9NzlFInuCAXa4=; b=fyTM4t4/hKkb/o3/rqAxq75gh8cjKVQVGB YyjMfiDcuf72Iu1uOIFzMImC2974ygmKIIIxKKaCgFJ0SfooTJ+VOZSlnX+QTitf XnUiLhUn57exuKT8ouDThN8pEGqXKYMx6C5ZENROSJQQ4Q2XuaDzzA0kpQRxe/gR XkvTLKZFPDa+10d8deT94Qk8Mu+Il0DgTTEdBk19MT67gdBdA+TV/sbAX1MrLf6T vPC4Ep1NB8ckc73pJnpiVm4RfinwZj51qW5qi0F/crEnGzprRSbBzl3rrjoGDedr k2HNty8aFFrOiCYlLY7A5b846TwRnl3RfiLQXPLeOvzSBN9AdnAA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, LIU Zhiwei , Bin Meng , Alistair Francis Subject: [PULL 04/33] target/riscv: Don't wrongly override isa version Date: Wed, 1 Sep 2021 12:09:29 +1000 Message-Id: <20210901020958.458454-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462421152100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei For some cpu, the isa version has already been set in cpu init function. Thus only override the isa version when isa version is not set, or users set different isa version explicitly by cpu parameters. Signed-off-by: LIU Zhiwei Reviewed-by: Bin Meng Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..1a2b03d579 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - int priv_version =3D PRIV_VERSION_1_11_0; - int bext_version =3D BEXT_VERSION_0_93_0; - int vext_version =3D VEXT_VERSION_0_07_1; + int priv_version =3D 0; target_ulong target_misa =3D env->misa; Error *local_err =3D NULL; =20 @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - set_priv_version(env, priv_version); - set_bext_version(env, bext_version); - set_vext_version(env, vext_version); + if (priv_version) { + set_priv_version(env, priv_version); + } else if (!env->priv_ver) { + set_priv_version(env, PRIV_VERSION_1_11_0); + } =20 if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) target_misa |=3D RVH; } if (cpu->cfg.ext_b) { + int bext_version =3D BEXT_VERSION_0_93_0; target_misa |=3D RVB; =20 if (cpu->cfg.bext_spec) { @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) set_bext_version(env, bext_version); } if (cpu->cfg.ext_v) { + int vext_version =3D VEXT_VERSION_0_07_1; target_misa |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630462631381624.8850404733665; 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s=dkim; t=1630462239; x=1633054240; bh=Z8p9lUP52lSAzxzyeq BKXHuP01PsJixnSqSFhdByyPc=; b=TXQX5wOod+LdpVoQMboikAEg3uu++M8nwz MPiOnBQMij/Ouo21RVyItvlszWSqWv1bGj9FskAvVXiVfa3bGtGmFhKhSSdRZbQ6 WYpx9p5qycjPrnGe+sL/9lgJ1y9jzFvBcBBDr09ipt+FJW0vAQsMAZEmK7sZO23O 4DZY+eqma24abgHXM6m/vjrRCgdoWWvvDdT2ZNSI8+R7q9jSuOF1AktY+b+7B7lN mUKxKf0JHddwwuy5WZ185JgOK1beZddN5z47+LvPnCcFXAjbENjLFA+ALIDT32PX JkOGLdjpfJj30q2Q4A9M1779SFUEixtL0i/mY+xOH8DPB8Ja7J+w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, LIU Zhiwei , Bin Meng , Alistair Francis Subject: [PULL 05/33] target/riscv: Add User CSRs read-only check Date: Wed, 1 Sep 2021 12:09:30 +1000 Message-Id: <20210901020958.458454-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462633564100001 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei For U-mode CSRs, read-only check is also needed. Signed-off-by: LIU Zhiwei Reviewed-by: Bin Meng Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e747fbe0e9..6d7f2c2a95 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int = csrno, RISCVException ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); + int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; =20 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ #if !defined(CONFIG_USER_ONLY) int effective_priv =3D env->priv; - int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int = csrno, effective_priv++; } =20 - if ((write_mask && read_only) || - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { return RISCV_EXCP_ILLEGAL_INST; } #endif + if (write_mask && read_only) { + return RISCV_EXCP_ILLEGAL_INST; + } =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630462425751104.77100886597623; Tue, 31 Aug 2021 19:13:45 -0700 (PDT) Received: from localhost ([::1]:52228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFl2-0008IV-IL for importer@patchew.org; Tue, 31 Aug 2021 22:13:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFiL-0005NI-Ho for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462244; x=1633054245; bh=YR30PYr F3PGlyIcK6BYY0SsyqtN0OiW/JPVt8EMrx+g=; b=W1daSPbj5SW8LiW37kazue8 kaNWMATycann1O4koLonnC3s6tPNHw+FXL57+b+1nagQgjt9UjM5SsMFUazyGI2D 0ZICuWK3A07LoydpMP+3EYd6S6soVfUDAeLAysMOJMTgSCHuZlANeCUWrcakQdgj kg+LOiAPBq8nWzj8qmrtoBmM4tS8DEflo8fH+zNTM8528DFGbg85j+oat4IiZn/A pSZ+Q+XdGSzLSzFr1itAZm0w9vSO7N8Ik1i4JIO1AkInox3AwjlOfiVJq36dhhKl RAE/75hLzPdGxZMuueVPFZisp181m91Cle80ICHA1SpR7bVDpCp9pkItuaIIvug= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv() Date: Wed, 1 Sep 2021 12:09:31 +1000 Message-Id: <20210901020958.458454-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462427179100001 Content-Type: text/plain; charset="utf-8" From: Peter Maydell In the riscv virt machine init function, We assemble a string plic_hart_config which is a comma-separated list of N copies of the VIRT_PLIC_HART_CONFIG string. The code that does this has a misunderstanding of the strncat() length argument. If the source string is too large strncat() will write a maximum of length+1 bytes (length bytes from the source string plus a trailing NUL), but the code here assumes that it will write only length bytes at most. This isn't an actual bug because the code has correctly precalculated the amount of memory it needs to allocate so that it will never be too small (i.e. we could have used plain old strcat()), but it does mean that the code looks like it has a guard against accidental overrun when it doesn't. Rewrite the string handling here to use the glib g_strjoinv() function, which means we don't need to do careful accountancy of string lengths, and makes it clearer that what we're doing is "create a comma-separated string". Fixes: Coverity 1460752 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20210812144647.10516-1-peter.maydell@linaro.org Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index aa279c1bb6..5624adda58 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -540,6 +540,24 @@ static FWCfgState *create_fw_cfg(const MachineState *m= c) return fw_cfg; } =20 +/* + * Return the per-socket PLIC hart topology configuration string + * (caller must free with g_free()) + */ +static char *plic_hart_config_string(int hart_count) +{ + g_autofree const char **vals =3D g_new(const char *, hart_count + 1); + int i; + + for (i =3D 0; i < hart_count; i++) { + vals[i] =3D VIRT_PLIC_HART_CONFIG; + } + vals[i] =3D NULL; + + /* g_strjoinv() obliges us to cast away const here */ + return g_strjoinv(",", (char **)vals); +} + static void virt_machine_init(MachineState *machine) { const MemMapEntry *memmap =3D virt_memmap; @@ -548,13 +566,12 @@ static void virt_machine_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config, *soc_name; - size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; uint32_t fdt_load_addr; uint64_t kernel_entry; DeviceState *mmio_plic, *virtio_plic, *pcie_plic; - int i, j, base_hartid, hart_count; + int i, base_hartid, hart_count; =20 /* Check socket count limit */ if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { @@ -603,17 +620,7 @@ static void virt_machine_init(MachineState *machine) SIFIVE_CLINT_TIMEBASE_FREQ, true); =20 /* Per-socket PLIC hart topology configuration string */ - plic_hart_config_len =3D - (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; - plic_hart_config =3D g_malloc0(plic_hart_config_len); - for (j =3D 0; j < hart_count; j++) { - if (j !=3D 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); - } - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, - plic_hart_config_len); - plic_hart_config_len -=3D (strlen(VIRT_PLIC_HART_CONFIG) + 1); - } + plic_hart_config =3D plic_hart_config_string(hart_count); =20 /* Per-socket PLIC */ s->plic[i] =3D sifive_plic_create( --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163046279080214.608373769273726; Tue, 31 Aug 2021 19:19:50 -0700 (PDT) Received: from localhost ([::1]:39944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFqv-00021h-G3 for importer@patchew.org; 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s=dkim; t=1630462250; x=1633054251; bh=5K1mozyt4W1XrW3BXg v4zyOZRDhUhC1zOhW09n30Jus=; b=H2TCfSCVKjipwkDjJV+qhYmdVWZMfc91Tp aH/BV09PRWsQGvoSqKUqWZ09O6sz8chiIxJP7n6SI+4W6PRchZUqr+TiMR+hx7Nj Lmisx4q0ljdfNcKNWurEtAvaAaIBeWzmRFSAZdxsSCOvH0IfVp2AVVyyuIzATdGy +Erwes7VdKU+QmPNmngWBZkdpvvPAi6YcKEy8ykBJVv6RVJd/ayePl0XlXvCZDsn Nfi0SJSjol6DSRW/4x+Q+5blbYPgWhr6H00p7klMMg+trWk4k/dLJVCOLM/3ap/+ axfrizk1yVhhmwKbvfuHeJP3j8+uu2i9LP2GAUpiSp66OJSb46VA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, David Hoppenbrouwers , Alistair Francis Subject: [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp() Date: Wed, 1 Sep 2021 12:09:32 +1000 Message-Id: <20210901020958.458454-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462792135100001 Content-Type: text/plain; charset="utf-8" From: David Hoppenbrouwers `muldiv64` would overflow in cases where the final 96-bit value does not fit in a `uint64_t`. This would result in small values that cause an interrupt to be triggered much sooner than intended. The overflow can be detected in most cases by checking if the new value is smaller than the previous value. If the final result is larger than `diff` it is either correct or it doesn't matter as it is effectively infinite anyways. `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This resulted in high values such as `UINT64_MAX` being converted to `-1`, which caused an immediate timer interrupt. By limiting `next` to `INT64_MAX` no overflow will happen while the timer will still be effectively set to "infinitely" far in the future. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493 Signed-off-by: David Hoppenbrouwers Reviewed-by: Alistair Francis Message-id: 20210827152324.5201-1-david@salt-inc.org Signed-off-by: Alistair Francis --- hw/intc/sifive_clint.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c index 0f41e5ea1c..99c870ced2 100644 --- a/hw/intc/sifive_clint.c +++ b/hw/intc/sifive_clint.c @@ -59,8 +59,29 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, ui= nt64_t value, riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ - next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); + uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); + + /* + * check if ns_diff overflowed and check if the addition would potenti= ally + * overflow + */ + if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || + ns_diff > INT64_MAX) { + next =3D INT64_MAX; + } else { + /* + * as it is very unlikely qemu_clock_get_ns will return a value + * greater than INT64_MAX, no additional check is needed for an + * unsigned integer overflow. + */ + next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; + /* + * if ns_diff is INT64_MAX next may still be outside the range + * of a signed integer. + */ + next =3D MIN(next, INT64_MAX); + } + timer_mod(cpu->env.timer, next); } =20 --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630462649746794.8992372856501; Tue, 31 Aug 2021 19:17:29 -0700 (PDT) Received: from localhost ([::1]:60370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFoc-0005Ek-Rd for importer@patchew.org; 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s=dkim; t=1630462255; x=1633054256; bh=XD3rTi8XFggeJ+/STx qfhLkctUz2QETrSerNx3ORSl8=; b=o6VN+RT/ULqkJD1X1om0rUZrLzpOG6LPqb OtnkLpEST4cgWvasA0EErfvzntwTvtTzWcU/PYm9RuPCVyEcXB2QFeeMgHvsNHVX x6XpgnqOMvuWuMS7WE3HNMpIh6pL2yvrZnt23NeH9l9Qab4yQLxWrh2a3H3JmDwB TUWVA/s00aj/NrBXfA/N/OnA4OvXVUU29kMGSN8/ScFRSp2RUKkjcz5IevbUr7kG UMHCzH9ec7m3Dyx6KxXtQwEzwaOpqrSsk22JYqUqcO9X1GPlQkB9C9mK0sxSpoUl ttRE1b3tmYwGzkm1feuuUUYso7qsArmvuPCUTYBPCXuEQu/3TeOA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Joe Komlodi , Alistair Francis Subject: [PULL 08/33] hw/core/register: Add more 64-bit utilities Date: Wed, 1 Sep 2021 12:09:33 +1000 Message-Id: <20210901020958.458454-9-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462650853100001 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi We already have some utilities to handle 64-bit wide registers, so this just adds some more for: - Initializing 64-bit registers - Extracting and depositing to an array of 64-bit registers Signed-off-by: Joe Komlodi Reviewed-by: Alistair Francis Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis --- include/hw/register.h | 8 ++++++++ include/hw/registerfields.h | 8 ++++++++ hw/core/register.c | 12 ++++++++++++ 3 files changed, 28 insertions(+) diff --git a/include/hw/register.h b/include/hw/register.h index b480e3882c..6a076cfcdf 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -204,6 +204,14 @@ RegisterInfoArray *register_init_block32(DeviceState *= owner, bool debug_enabled, uint64_t memory_size); =20 +RegisterInfoArray *register_init_block64(DeviceState *owner, + const RegisterAccessInfo *rae, + int num, RegisterInfo *ri, + uint64_t *data, + const MemoryRegionOps *ops, + bool debug_enabled, + uint64_t memory_size); + /** * This function should be called to cleanup the registers that were initi= alized * when calling register_init_block32(). This function should only be call= ed diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 93fa4a84c2..9a03ac55e4 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -30,6 +30,10 @@ enum { A_ ## reg =3D (addr) }; = \ enum { R_ ## reg =3D (addr) / 2 }; =20 +#define REG64(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) / 8 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ =20 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LE= NGTH @@ -58,6 +62,8 @@ /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ FIELD_EX32((regs)[R_ ## reg], reg, field) +#define ARRAY_FIELD_EX64(regs, reg, field) \ + FIELD_EX64((regs)[R_ ## reg], reg, field) =20 /* Deposit a register field. * Assigning values larger then the target field will result in @@ -99,5 +105,7 @@ /* Deposit a field to array of registers. */ #define ARRAY_FIELD_DP32(regs, reg, field, val) \ (regs)[R_ ## reg] =3D FIELD_DP32((regs)[R_ ## reg], reg, field, val); +#define ARRAY_FIELD_DP64(regs, reg, field, val) \ + (regs)[R_ ## reg] =3D FIELD_DP64((regs)[R_ ## reg], reg, field, val); =20 #endif diff --git a/hw/core/register.c b/hw/core/register.c index d6f8c20816..95b0150c0a 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -300,6 +300,18 @@ RegisterInfoArray *register_init_block32(DeviceState *= owner, data, ops, debug_enabled, memory_size, 32); } =20 +RegisterInfoArray *register_init_block64(DeviceState *owner, + const RegisterAccessInfo *rae, + int num, RegisterInfo *ri, + uint64_t *data, + const MemoryRegionOps *ops, + bool debug_enabled, + uint64_t memory_size) +{ + return register_init_block(owner, rae, num, ri, (void *) + data, ops, debug_enabled, memory_size, 64); +} + void register_finalize_block(RegisterInfoArray *r_array) { object_unparent(OBJECT(&r_array->mem)); --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462661469100003 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi If we have a field that's wider than 32-bits, we need a data type wide enou= gh to be able to create the bitfield used to deposit the value. Signed-off-by: Joe Komlodi Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis --- include/hw/registerfields.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 9a03ac55e4..f2a3c9c41f 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -95,7 +95,7 @@ _d; }) #define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ - unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ } _v =3D { .v =3D val }; = \ uint64_t _d; \ _d =3D deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462266; x=1633054267; bh=lz817Jv sSmm1aKtE4F4PmAni6XVzBF3QL4K2kU6o6zk=; b=f1kK0u/noPfTCatPbSO67vu vHDiy9tWFazQnSozVeRluBqWrXRJVdgpOowxl9pKhq7baBxoNST9UWkiCkWOevlE rDsL2BtbGgI5FeSRLK292nsSCtfgpaC20yl4UHLtOO0faFmvbkgic4pFNltovGQ3 bZIzDECrbfpZWCD79U/BjiopyHFWC9EFQyNZt2jAQNTxUKFLP8tjqLmoB8/jPxj7 Ng6w3zdYJXZXbcgSyALsFr3WzlcMqUMPjofCH4/fQOlw2w9xYDiePRQMPIlVfD9o GbdtjUpKg3/XC+fJX2hw/zBRUPQk3Uiiq8uxhIuGypSdMOP70qjfvzEO58vQmvA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 10/33] target/riscv: Use tcg_constant_* Date: Wed, 1 Sep 2021 12:09:35 +1000 Message-Id: <20210901020958.458454-11-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462974967100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 36 ++++---------- target/riscv/insn_trans/trans_rvf.c.inc | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 65 +++++++++---------------- 3 files changed, 34 insertions(+), 70 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6983be5723..20a55c92fb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -104,20 +104,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) */ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) { - TCGv_i64 t_max =3D tcg_const_i64(0xffffffff00000000ull); - TCGv_i64 t_nan =3D tcg_const_i64(0xffffffff7fc00000ull); + TCGv_i64 t_max =3D tcg_constant_i64(0xffffffff00000000ull); + TCGv_i64 t_nan =3D tcg_constant_i64(0xffffffff7fc00000ull); =20 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); - tcg_temp_free_i64(t_max); - tcg_temp_free_i64(t_nan); } =20 static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - TCGv_i32 helper_tmp =3D tcg_const_i32(excp); - gen_helper_raise_exception(cpu_env, helper_tmp); - tcg_temp_free_i32(helper_tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -125,17 +121,13 @@ static void generate_exception_mtval(DisasContext *ct= x, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); - TCGv_i32 helper_tmp =3D tcg_const_i32(excp); - gen_helper_raise_exception(cpu_env, helper_tmp); - tcg_temp_free_i32(helper_tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_debug(void) { - TCGv_i32 helper_tmp =3D tcg_const_i32(EXCP_DEBUG); - gen_helper_raise_exception(cpu_env, helper_tmp); - tcg_temp_free_i32(helper_tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); } =20 /* Wrapper around tcg_gen_exit_tb that handles single stepping */ @@ -229,7 +221,7 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source= 2) */ cond1 =3D tcg_temp_new(); cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); + zeroreg =3D tcg_constant_tl(0); resultopt1 =3D tcg_temp_new(); =20 tcg_gen_movi_tl(resultopt1, (target_ulong)-1); @@ -250,7 +242,6 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source= 2) =20 tcg_temp_free(cond1); tcg_temp_free(cond2); - tcg_temp_free(zeroreg); tcg_temp_free(resultopt1); } =20 @@ -259,7 +250,7 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv sourc= e2) TCGv cond1, zeroreg, resultopt1; cond1 =3D tcg_temp_new(); =20 - zeroreg =3D tcg_const_tl(0); + zeroreg =3D tcg_constant_tl(0); resultopt1 =3D tcg_temp_new(); =20 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); @@ -272,7 +263,6 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv sourc= e2) tcg_gen_divu_tl(ret, source1, source2); =20 tcg_temp_free(cond1); - tcg_temp_free(zeroreg); tcg_temp_free(resultopt1); } =20 @@ -282,7 +272,7 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source= 2) =20 cond1 =3D tcg_temp_new(); cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); + zeroreg =3D tcg_constant_tl(0); resultopt1 =3D tcg_temp_new(); =20 tcg_gen_movi_tl(resultopt1, 1L); @@ -302,7 +292,6 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source= 2) =20 tcg_temp_free(cond1); tcg_temp_free(cond2); - tcg_temp_free(zeroreg); tcg_temp_free(resultopt1); } =20 @@ -310,7 +299,7 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv sourc= e2) { TCGv cond1, zeroreg, resultopt1; cond1 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); + zeroreg =3D tcg_constant_tl(0); resultopt1 =3D tcg_temp_new(); =20 tcg_gen_movi_tl(resultopt1, (target_ulong)1); @@ -323,7 +312,6 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv sourc= e2) source1); =20 tcg_temp_free(cond1); - tcg_temp_free(zeroreg); tcg_temp_free(resultopt1); } =20 @@ -384,15 +372,11 @@ static inline void mark_fs_dirty(DisasContext *ctx) {= } =20 static void gen_set_rm(DisasContext *ctx, int rm) { - TCGv_i32 t0; - if (ctx->frm =3D=3D rm) { return; } ctx->frm =3D rm; - t0 =3D tcg_const_i32(rm); - gen_helper_set_rounding_mode(cpu_env, t0); - tcg_temp_free_i32(t0); + gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } =20 static int ex_plus_1(DisasContext *ctx, int nf) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index db1c0c9974..89f78701e7 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -200,12 +200,11 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsg= njn_s *a) * Replace bit 31 in rs1 with inverse in rs2. * This formulation retains the nanboxing of rs1. */ - mask =3D tcg_const_i64(~MAKE_64BIT_MASK(31, 1)); + mask =3D tcg_constant_i64(~MAKE_64BIT_MASK(31, 1)); tcg_gen_nor_i64(rs2, rs2, mask); tcg_gen_and_i64(rs1, mask, rs1); tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); =20 - tcg_temp_free_i64(mask); tcg_temp_free_i64(rs2); } tcg_temp_free_i64(rs1); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 83d9a285ba..a8e7272487 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -33,7 +33,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ - s1 =3D tcg_const_tl(RV_VLEN_MAX); + s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { s1 =3D tcg_temp_new(); gen_get_gpr(s1, a->rs1); @@ -59,13 +59,13 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvl= i *a) return false; } =20 - s2 =3D tcg_const_tl(a->zimm); + s2 =3D tcg_constant_tl(a->zimm); dst =3D tcg_temp_new(); =20 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ - s1 =3D tcg_const_tl(RV_VLEN_MAX); + s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { s1 =3D tcg_temp_new(); gen_get_gpr(s1, a->rs1); @@ -76,7 +76,6 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli = *a) ctx->base.is_jmp =3D DISAS_NORETURN; =20 tcg_temp_free(s1); - tcg_temp_free(s2); tcg_temp_free(dst); return true; } @@ -183,7 +182,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. */ - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 gen_get_gpr(base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -194,7 +193,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free(base); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -334,7 +332,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, mask =3D tcg_temp_new_ptr(); base =3D tcg_temp_new(); stride =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 gen_get_gpr(base, rs1); gen_get_gpr(stride, rs2); @@ -347,7 +345,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, tcg_temp_free_ptr(mask); tcg_temp_free(base); tcg_temp_free(stride); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -462,7 +459,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); base =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 gen_get_gpr(base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -475,7 +472,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); tcg_temp_free(base); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -594,7 +590,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint3= 2_t data, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 gen_get_gpr(base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -605,7 +601,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint3= 2_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free(base); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -671,7 +666,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32= _t vs2, mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); base =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 gen_get_gpr(base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -684,7 +679,6 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32= _t vs2, tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); tcg_temp_free(base); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -874,7 +868,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -886,7 +880,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free(src1); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -1014,14 +1007,14 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, = uint32_t vs2, uint32_t vm, mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); if (zx) { - src1 =3D tcg_const_tl(imm); + src1 =3D tcg_constant_tl(imm); } else { - src1 =3D tcg_const_tl(sextract64(imm, 0, 5)); + src1 =3D tcg_constant_tl(sextract64(imm, 0, 5)); } data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1032,8 +1025,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); - tcg_temp_free(src1); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -1080,9 +1071,8 @@ GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp =3D tcg_const_i64(c); + TCGv_i64 tmp =3D tcg_constant_i64(c); tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); } =20 GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) @@ -1682,7 +1672,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), s1); } else { - TCGv_i32 desc ; + TCGv_i32 desc; TCGv_i64 s1_i64 =3D tcg_temp_new_i64(); TCGv_ptr dest =3D tcg_temp_new_ptr(); uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); @@ -1692,12 +1682,11 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_= v_x *a) }; =20 tcg_gen_ext_tl_i64(s1_i64, s1); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, dat= a)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1_i64, cpu_env, desc); =20 tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); tcg_temp_free_i64(s1_i64); } =20 @@ -1729,15 +1718,13 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_= v_i *a) TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - s1 =3D tcg_const_i64(simm); + s1 =3D tcg_constant_i64(simm); dest =3D tcg_temp_new_ptr(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, dat= a)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, cpu_env, desc); =20 tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); - tcg_temp_free_i64(s1); gen_set_label(over); } return true; @@ -1866,7 +1853,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1877,7 +1864,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); - tcg_temp_free_i32(desc); gen_set_label(over); return true; } @@ -2231,12 +2217,11 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfm= v_v_f *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 dest =3D tcg_temp_new_ptr(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, dat= a)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); =20 tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); gen_set_label(over); } return true; @@ -2428,7 +2413,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -2439,7 +2424,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free(dst); - tcg_temp_free_i32(desc); return true; } return false; @@ -2460,7 +2444,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D tcg_temp_new(); - desc =3D tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -2471,7 +2455,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free(dst); - tcg_temp_free_i32(desc); return true; } return false; @@ -2636,15 +2619,13 @@ static void vec_element_loadx(DisasContext *s, TCGv= _i64 dest, tcg_temp_free_i32(ofs); =20 /* Flush out-of-range indexing to zero. */ - t_vlmax =3D tcg_const_i64(vlmax); - t_zero =3D tcg_const_i64(0); + t_vlmax =3D tcg_constant_i64(vlmax); + t_zero =3D tcg_constant_i64(0); tcg_gen_extu_tl_i64(t_idx, idx); =20 tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx, t_vlmax, dest, t_zero); =20 - tcg_temp_free_i64(t_vlmax); - tcg_temp_free_i64(t_zero); tcg_temp_free_i64(t_idx); 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462272; x=1633054273; bh=ZeZw1rFHMyCdjwtcB+ dTpGsD9zIcn3Vwae2e5wZhJhU=; b=HU74ua6RSKMlaGjk3Kw7NSs06FcuntdY8V WnBGxnJlJjBNHDBJwgNJAZ5UatF6Lausd5Gm4jNm2ls3oOgKITJ8rlMLk5znnq8O brZafsmyzDosLIEp21ff3qID5+mYTWVzcQhFhbBQUyZ6920Spa++VubFd5K0AAfz FdX1P3PM8O3QsFQpNhL7KXpSpxirHIszqsNN9Kz8qvjgrhxS0xV8O/wMfQDm+qUf l2dmu+7qreN1NU7owwNBqdtMarcmYvTy6ouLktqbKOiFAb0qb3BfiZDr9xL6E1v8 RJ7JwxmnwFrvtZ6oRhjFc0xFeiFt65KsT70ooDoCBbWkFMjAXvwg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 11/33] tests/tcg/riscv64: Add test for division Date: Wed, 1 Sep 2021 12:09:36 +1000 Message-Id: <20210901020958.458454-12-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462802762100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Tested-by: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-3-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- tests/tcg/riscv64/test-div.c | 58 +++++++++++++++++++++++++++++++ tests/tcg/riscv64/Makefile.target | 5 +++ 2 files changed, 63 insertions(+) create mode 100644 tests/tcg/riscv64/test-div.c create mode 100644 tests/tcg/riscv64/Makefile.target diff --git a/tests/tcg/riscv64/test-div.c b/tests/tcg/riscv64/test-div.c new file mode 100644 index 0000000000..a90480be3f --- /dev/null +++ b/tests/tcg/riscv64/test-div.c @@ -0,0 +1,58 @@ +#include +#include + +struct TestS { + long x, y, q, r; +}; + +static struct TestS test_s[] =3D { + { 4, 2, 2, 0 }, /* normal cases */ + { 9, 7, 1, 2 }, + { 0, 0, -1, 0 }, /* div by zero cases */ + { 9, 0, -1, 9 }, + { LONG_MIN, -1, LONG_MIN, 0 }, /* overflow case */ +}; + +struct TestU { + unsigned long x, y, q, r; +}; + +static struct TestU test_u[] =3D { + { 4, 2, 2, 0 }, /* normal cases */ + { 9, 7, 1, 2 }, + { 0, 0, ULONG_MAX, 0 }, /* div by zero cases */ + { 9, 0, ULONG_MAX, 9 }, +}; + +#define ARRAY_SIZE(X) (sizeof(X) / sizeof(*(X))) + +int main (void) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(test_s); i++) { + long q, r; + + asm("div %0, %2, %3\n\t" + "rem %1, %2, %3" + : "=3D&r" (q), "=3Dr" (r) + : "r" (test_s[i].x), "r" (test_s[i].y)); + + assert(q =3D=3D test_s[i].q); + assert(r =3D=3D test_s[i].r); + } + + for (i =3D 0; i < ARRAY_SIZE(test_u); i++) { + unsigned long q, r; + + asm("divu %0, %2, %3\n\t" + "remu %1, %2, %3" + : "=3D&r" (q), "=3Dr" (r) + : "r" (test_u[i].x), "r" (test_u[i].y)); + + assert(q =3D=3D test_u[i].q); + assert(r =3D=3D test_u[i].r); + } + + return 0; +} diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile= .target new file mode 100644 index 0000000000..d41bf6d60d --- /dev/null +++ b/tests/tcg/riscv64/Makefile.target @@ -0,0 +1,5 @@ +# -*- Mode: makefile -*- +# RISC-V specific tweaks + +VPATH +=3D $(SRC_PATH)/tests/tcg/riscv64 +TESTS +=3D test-div --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630462833204362.516432274508; Tue, 31 Aug 2021 19:20:33 -0700 (PDT) Received: from localhost ([::1]:41106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFrc-0002nf-2T for importer@patchew.org; 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s=dkim; t=1630462277; x=1633054278; bh=w67LCT2lU+qHLX8ArE P0vmCI/g+0p14zU9IM8lbDyVU=; b=nsgSPcHOyqaWWCsQrh4hgaaZUTSQI07Kwu qFkHUt5ihb1xBa+3pR8KVipLXg6dJM2wsE405wzmtsxxWaVXvp5JZCGLj1t23rwq YNviddHpn08JAx3yBfjwXIDRh6/4dQLdUvTEiBnlxlpwbxnaQ/eSZ2d009nc1jaz dB8mMUnBHjEtN5RWugcFMoti3VyGuuqbblzImmZ4jf39BXspdlWoJIAYbHi2y/DG cAAgw4fYl3hJ0OkxdVTriRW2M49M7MPkPlIrFDKa3DPE2noJFWzEPhKrsQadsxLj GVN0MJ6mh90KaamLpsLF6h8BjzDzcQ3o+G0LSFwtHRLt5UH0P8BQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 12/33] target/riscv: Clean up division helpers Date: Wed, 1 Sep 2021 12:09:37 +1000 Message-Id: <20210901020958.458454-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630462834443100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Utilize the condition in the movcond more; this allows some of the setcond that were feeding into movcond to be removed. Do not write into source1 and source2. Re-name "condN" to "tempN" and use the temporaries for more than holding conditions. Tested-by: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 174 ++++++++++++++++++++------------------- 1 file changed, 91 insertions(+), 83 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 20a55c92fb..147b9c2f68 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -213,106 +213,114 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv ar= g2) =20 static void gen_div(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv temp1, temp2, zero, one, mone, min; + + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + mone =3D tcg_constant_tl(-1); + min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); + /* - * Handle by altering args to tcg_gen_div to produce req'd results: - * For overflow: want source1 in source1 and 1 in source2 - * For div by zero: want -1 in source1 and 1 in source2 -> -1 result + * If overflow, set temp2 to 1, else source2. + * This produces the required result of min. */ - cond1 =3D tcg_temp_new(); - cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_constant_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - ((target_ulong)1) << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 =3D overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 =3D div = 0 */ - /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); - /* if overflow or div by zero, set source2 to 1, else don't change */ - tcg_gen_or_tl(cond1, cond1, cond2); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(ret, source1, source2); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(resultopt1); + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); + tcg_gen_and_tl(temp1, temp1, temp2); + tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2); + + /* + * If div by zero, set temp1 to -1 and temp2 to 1 to + * produce the required result of -1. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1); + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2); + + tcg_gen_div_tl(ret, temp1, temp2); + + tcg_temp_free(temp1); + tcg_temp_free(temp2); } =20 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; - cond1 =3D tcg_temp_new(); + TCGv temp1, temp2, zero, one, max; =20 - zeroreg =3D tcg_constant_tl(0); - resultopt1 =3D tcg_temp_new(); + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + max =3D tcg_constant_tl(~0); =20 - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(ret, source1, source2); + /* + * If div by zero, set temp1 to max and temp2 to 1 to + * produce the required result of max. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1); + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); + tcg_gen_divu_tl(ret, temp1, temp2); =20 - tcg_temp_free(cond1); - tcg_temp_free(resultopt1); + tcg_temp_free(temp1); + tcg_temp_free(temp2); } =20 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; - - cond1 =3D tcg_temp_new(); - cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_constant_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, 1L); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - (target_ulong)1 << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 =3D overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 =3D div = 0 */ - /* if overflow or div by zero, set source2 to 1, else don't change */ - tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(resultopt1); + TCGv temp1, temp2, zero, one, mone, min; + + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + mone =3D tcg_constant_tl(-1); + min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); + + /* + * If overflow, set temp1 to 0, else source1. + * This avoids a possible host trap, and produces the required result = of 0. + */ + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); + tcg_gen_and_tl(temp1, temp1, temp2); + tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1); + + /* + * If div by zero, set temp2 to 1, else source2. + * This avoids a possible host trap, but produces an incorrect result. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); + + tcg_gen_rem_tl(temp1, temp1, temp2); + + /* If div by zero, the required result is the original dividend. */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1); + + tcg_temp_free(temp1); + tcg_temp_free(temp2); } =20 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; - cond1 =3D tcg_temp_new(); - zeroreg =3D tcg_constant_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(resultopt1); + TCGv temp, zero, one; + + temp =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + + /* + * If div by zero, set temp to 1, else source2. + * This avoids a possible host trap, but produces an incorrect result. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2); + + tcg_gen_remu_tl(temp, source1, temp); + + /* If div by zero, the required result is the original dividend. */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp); + + tcg_temp_free(temp); } =20 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462284; x=1633054285; bh=HyoCoEe pYSqF6cIrzeIp54ThvE0XsoZoAso1xfgsdEw=; b=avCW9w3cLKx1anAD+GdD9u6 WTbHLZI1CCudmKIsmT+KDsXxuUqcuhKxJv8FqDbllAGNNwHMfgvYN6ip/YucFzP0 Pwbd0zHhm7OaxJfjNntixvZjV4ytOEVwrl5F83zp3QLsbD/01ApuscFufY+01BGx XuOU4+32lKZmx09Wy5vaLoxO0sjyTr1+KLU30KsB9WD3AogDiKRPMPbQowEoad0a 3f/Z8w5L3I0w2Dk+x9y77sBZ6LXQq7lm1mNHfK3aAeBfT5Od/UarWIIlgKyBO6rr zSXenROrmUNfCa7czEteme+HeSCKwdN/59dX5GBSD+xn+Wxkn76kAx6d5pKYyeQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Date: Wed, 1 Sep 2021 12:09:38 +1000 Message-Id: <20210901020958.458454-14-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463195588100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will require the context to handle RV64 word operations. Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 58 ++++++++++++------------- target/riscv/insn_trans/trans_rva.c.inc | 18 ++++---- target/riscv/insn_trans/trans_rvb.c.inc | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 32 +++++++------- target/riscv/insn_trans/trans_rvf.c.inc | 32 +++++++------- target/riscv/insn_trans/trans_rvh.c.inc | 52 +++++++++++----------- target/riscv/insn_trans/trans_rvi.c.inc | 44 +++++++++---------- target/riscv/insn_trans/trans_rvm.c.inc | 12 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 36 +++++++-------- 9 files changed, 144 insertions(+), 144 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 147b9c2f68..ce4c56c179 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -175,7 +175,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) /* Wrapper for getting reg values - need to check of reg is zero since * cpu_gpr[0] is not actually allocated */ -static inline void gen_get_gpr(TCGv t, int reg_num) +static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) { if (reg_num =3D=3D 0) { tcg_gen_movi_tl(t, 0); @@ -189,7 +189,7 @@ static inline void gen_get_gpr(TCGv t, int reg_num) * since we usually avoid calling the OP_TYPE_gen function if we see a wri= te to * $zero */ -static inline void gen_set_gpr(int reg_num_dst, TCGv t) +static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t) { if (reg_num_dst !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); @@ -435,11 +435,11 @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i= *a, TCGv source1; source1 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); =20 (*func)(source1, source1, a->imm); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); return true; } @@ -451,12 +451,12 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i= *a, source1 =3D tcg_temp_new(); source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); tcg_gen_movi_tl(source2, a->imm); =20 (*func)(source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -487,15 +487,15 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r = *a, source1 =3D tcg_temp_new(); source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); tcg_gen_ext32s_tl(source1, source1); tcg_gen_ext32s_tl(source2, source2); =20 (*func)(source1, source1, source2); =20 tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -508,15 +508,15 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r= *a, source1 =3D tcg_temp_new(); source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); tcg_gen_ext32u_tl(source1, source1); tcg_gen_ext32u_tl(source2, source2); =20 (*func)(source1, source1, source2); =20 tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -606,7 +606,7 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a) TCGv source1 =3D tcg_temp_new(); TCGv source2; =20 - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); =20 if (a->shamt =3D=3D (TARGET_LONG_BITS - 8)) { /* rev8, byte swaps */ @@ -618,7 +618,7 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a) tcg_temp_free(source2); } =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); return true; } @@ -752,12 +752,12 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, source1 =3D tcg_temp_new(); source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 (*func)(source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -769,13 +769,13 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); (*func)(source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -800,12 +800,12 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *= a, TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); =20 tcg_gen_movi_tl(source2, a->shamt); (*func)(source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -817,14 +817,14 @@ static bool gen_shiftw(DisasContext *ctx, arg_r *a, TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_andi_tl(source2, source2, 31); (*func)(source1, source1, source2); tcg_gen_ext32s_tl(source1, source1); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -836,13 +836,13 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift = *a, TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); tcg_gen_movi_tl(source2, a->shamt); =20 (*func)(source1, source1, source2); tcg_gen_ext32s_tl(source1, source1); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -863,11 +863,11 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, { TCGv source =3D tcg_temp_new(); =20 - gen_get_gpr(source, a->rs1); + gen_get_gpr(ctx, source, a->rs1); =20 (*func)(source, source); =20 - gen_set_gpr(a->rd, source); + gen_set_gpr(ctx, a->rd, source); tcg_temp_free(source); return true; } diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index ab2ec4f0a5..3cc3c3b073 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -22,7 +22,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *= a, MemOp mop) { TCGv src1 =3D tcg_temp_new(); /* Put addr in load_res, data in load_val. */ - gen_get_gpr(src1, a->rs1); + gen_get_gpr(ctx, src1, a->rs1); if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -31,7 +31,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *= a, MemOp mop) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } tcg_gen_mov_tl(load_res, src1); - gen_set_gpr(a->rd, load_val); + gen_set_gpr(ctx, a->rd, load_val); =20 tcg_temp_free(src1); return true; @@ -45,10 +45,10 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - gen_get_gpr(src1, a->rs1); + gen_get_gpr(ctx, src1, a->rs1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 - gen_get_gpr(src2, a->rs2); + gen_get_gpr(ctx, src2, a->rs2); /* * Note that the TCG atomic primitives are SC, * so we can ignore AQ/RL along this path. @@ -56,7 +56,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, MemOp mop) tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, ctx->mem_idx, mop); tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); - gen_set_gpr(a->rd, dat); + gen_set_gpr(ctx, a->rd, dat); tcg_gen_br(l2); =20 gen_set_label(l1); @@ -66,7 +66,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, MemOp mop) */ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); tcg_gen_movi_tl(dat, 1); - gen_set_gpr(a->rd, dat); + gen_set_gpr(ctx, a->rd, dat); =20 gen_set_label(l2); /* @@ -88,12 +88,12 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1 =3D tcg_temp_new(); TCGv src2 =3D tcg_temp_new(); =20 - gen_get_gpr(src1, a->rs1); - gen_get_gpr(src2, a->rs2); + gen_get_gpr(ctx, src1, a->rs1); + gen_get_gpr(ctx, src2, a->rs2); =20 (*func)(src2, src1, src2, ctx->mem_idx, mop); =20 - gen_set_gpr(a->rd, src2); + gen_set_gpr(ctx, a->rd, src2); tcg_temp_free(src1); tcg_temp_free(src2); return true; diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 9e81f6e3de..260e15b47d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -424,7 +424,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_u= w *a) REQUIRE_EXT(ctx, RVB); =20 TCGv source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); + gen_get_gpr(ctx, source1, a->rs1); =20 if (a->shamt < 32) { tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); @@ -432,7 +432,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_u= w *a) tcg_gen_shli_tl(source1, source1, a->shamt); } =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); return true; } diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 7e45538ae0..11b9b3f90b 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -23,7 +23,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); =20 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -38,7 +38,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); =20 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); @@ -254,7 +254,7 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) =20 TCGv t0 =3D tcg_temp_new(); gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -267,7 +267,7 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) =20 TCGv t0 =3D tcg_temp_new(); gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -280,7 +280,7 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) =20 TCGv t0 =3D tcg_temp_new(); gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -293,7 +293,7 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclas= s_d *a) =20 TCGv t0 =3D tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -306,7 +306,7 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_= w_d *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -320,7 +320,7 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt= _wu_d *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -332,7 +332,7 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_= d_w *a) REQUIRE_EXT(ctx, RVD); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); @@ -348,7 +348,7 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt= _d_wu *a) REQUIRE_EXT(ctx, RVD); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); @@ -367,7 +367,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_= l_d *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -381,7 +381,7 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt= _lu_d *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -393,7 +393,7 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_= d *a) REQUIRE_EXT(ctx, RVD); =20 #ifdef TARGET_RISCV64 - gen_set_gpr(a->rd, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]); return true; #else qemu_build_not_reached(); @@ -407,7 +407,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_= d_l *a) REQUIRE_EXT(ctx, RVD); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); @@ -423,7 +423,7 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt= _d_lu *a) REQUIRE_EXT(ctx, RVD); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); @@ -440,7 +440,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_= x *a) =20 #ifdef TARGET_RISCV64 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_mov_tl(cpu_fpr[a->rd], t0); tcg_temp_free(t0); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 89f78701e7..fb9f7f9c00 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -28,7 +28,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); =20 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); @@ -44,7 +44,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_addi_tl(t0, t0, a->imm); =20 @@ -274,7 +274,7 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_= w_s *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -288,7 +288,7 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt= _wu_s *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -308,7 +308,7 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_= w *a) tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); #endif =20 - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -320,7 +320,7 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 =3D tcg_temp_new(); gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -331,7 +331,7 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 =3D tcg_temp_new(); gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -342,7 +342,7 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 =3D tcg_temp_new(); gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -356,7 +356,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclas= s_s *a) =20 gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); =20 - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); =20 return true; @@ -368,7 +368,7 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_= s_w *a) REQUIRE_EXT(ctx, RVF); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); @@ -385,7 +385,7 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt= _s_wu *a) REQUIRE_EXT(ctx, RVF); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); @@ -403,7 +403,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_= x *a) REQUIRE_EXT(ctx, RVF); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); @@ -423,7 +423,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_= l_s *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -437,7 +437,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt= _lu_s *a) TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); + gen_set_gpr(ctx, a->rd, t0); tcg_temp_free(t0); return true; } @@ -449,7 +449,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_= s_l *a) REQUIRE_EXT(ctx, RVF); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); @@ -466,7 +466,7 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt= _s_lu *a) REQUIRE_EXT(ctx, RVF); =20 TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 6b5edf82b7..585eb1d87e 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -37,10 +37,10 @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -59,10 +59,10 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -81,10 +81,10 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -103,10 +103,10 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_b= u *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -125,9 +125,9 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu = *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -146,8 +146,8 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); - gen_get_gpr(dat, a->rs2); + gen_get_gpr(ctx, t0, a->rs1); + gen_get_gpr(ctx, dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); =20 @@ -168,8 +168,8 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); - gen_get_gpr(dat, a->rs2); + gen_get_gpr(ctx, t0, a->rs1); + gen_get_gpr(ctx, dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); =20 @@ -190,8 +190,8 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); - gen_get_gpr(dat, a->rs2); + gen_get_gpr(ctx, t0, a->rs1); + gen_get_gpr(ctx, dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); =20 @@ -214,10 +214,10 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_w= u *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -238,10 +238,10 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d = *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -262,8 +262,8 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); - gen_get_gpr(dat, a->rs2); + gen_get_gpr(ctx, t0, a->rs1); + gen_get_gpr(ctx, dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); =20 @@ -284,10 +284,10 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx= _hu *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -306,10 +306,10 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx= _wu *a) =20 check_access(ctx); =20 - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); =20 gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 6e736c9d0d..f1a5d8de56 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -59,7 +59,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) TCGv t0 =3D tcg_temp_new(); =20 =20 - gen_get_gpr(cpu_pc, a->rs1); + gen_get_gpr(ctx, cpu_pc, a->rs1); tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 @@ -90,8 +90,8 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCo= nd cond) TCGv source1, source2; source1 =3D tcg_temp_new(); source2 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_brcond_tl(cond, source1, source2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); @@ -145,11 +145,11 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Me= mOp memop) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(a->rd, t1); + gen_set_gpr(ctx, a->rd, t1); tcg_temp_free(t0); tcg_temp_free(t1); return true; @@ -184,9 +184,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Mem= Op memop) { TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); - gen_get_gpr(dat, a->rs2); + gen_get_gpr(ctx, dat, a->rs2); =20 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); tcg_temp_free(t0); @@ -347,11 +347,11 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw = *a) { REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); - gen_get_gpr(t, a->rs1); + gen_get_gpr(ctx, t, a->rs1); tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); /* sign-extend for W instructions */ tcg_gen_ext32s_tl(t, t); - gen_set_gpr(a->rd, t); + gen_set_gpr(ctx, a->rd, t); tcg_temp_free(t); return true; } @@ -360,9 +360,9 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); TCGv t =3D tcg_temp_new(); - gen_get_gpr(t, a->rs1); + gen_get_gpr(ctx, t, a->rs1); tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); - gen_set_gpr(a->rd, t); + gen_set_gpr(ctx, a->rd, t); tcg_temp_free(t); return true; } @@ -385,14 +385,14 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a) TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_shl_tl(source1, source1, source2); =20 tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -404,8 +404,8 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 /* clear upper 32 */ tcg_gen_ext32u_tl(source1, source1); @@ -413,7 +413,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) tcg_gen_shr_tl(source1, source1, source2); =20 tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -425,8 +425,8 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); =20 - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 /* * first, trick to get it to act like working on 32 bits (get rid of @@ -436,7 +436,7 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_sar_tl(source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); =20 @@ -471,7 +471,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_= i *a) csr_store =3D tcg_temp_new(); \ dest =3D tcg_temp_new(); \ rs1_pass =3D tcg_temp_new(); \ - gen_get_gpr(source1, a->rs1); \ + gen_get_gpr(ctx, source1, a->rs1); \ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \ tcg_gen_movi_tl(rs1_pass, a->rs1); \ tcg_gen_movi_tl(csr_store, a->csr); \ @@ -479,7 +479,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_= i *a) } while (0) =20 #define RISCV_OP_CSR_POST do {\ - gen_set_gpr(a->rd, dest); \ + gen_set_gpr(ctx, a->rd, dest); \ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \ exit_tb(ctx); \ ctx->base.is_jmp =3D DISAS_NORETURN; \ diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 10ecc456fc..0a4318f18e 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -30,12 +30,12 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) REQUIRE_EXT(ctx, RVM); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_muls2_tl(source2, source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; @@ -52,12 +52,12 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) REQUIRE_EXT(ctx, RVM); TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); =20 tcg_gen_mulu2_tl(source2, source1, source1, source2); =20 - gen_set_gpr(a->rd, source1); + gen_set_gpr(ctx, a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index a8e7272487..de580c493c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -36,11 +36,11 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl = *a) s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { s1 =3D tcg_temp_new(); - gen_get_gpr(s1, a->rs1); + gen_get_gpr(ctx, s1, a->rs1); } - gen_get_gpr(s2, a->rs2); + gen_get_gpr(ctx, s2, a->rs2); gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); + gen_set_gpr(ctx, a->rd, dst); tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); lookup_and_goto_ptr(ctx); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -68,10 +68,10 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvl= i *a) s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { s1 =3D tcg_temp_new(); - gen_get_gpr(s1, a->rs1); + gen_get_gpr(ctx, s1, a->rs1); } gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); + gen_set_gpr(ctx, a->rd, dst); gen_goto_tb(ctx, 0, ctx->pc_succ_insn); ctx->base.is_jmp =3D DISAS_NORETURN; =20 @@ -184,7 +184,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, */ desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(base, rs1); + gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -334,8 +334,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, stride =3D tcg_temp_new(); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(base, rs1); - gen_get_gpr(stride, rs2); + gen_get_gpr(s, base, rs1); + gen_get_gpr(s, stride, rs2); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -461,7 +461,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, base =3D tcg_temp_new(); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(base, rs1); + gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -592,7 +592,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint3= 2_t data, base =3D tcg_temp_new(); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(base, rs1); + gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -668,7 +668,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32= _t vs2, base =3D tcg_temp_new(); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(base, rs1); + gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -863,7 +863,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); src1 =3D tcg_temp_new(); - gen_get_gpr(src1, rs1); + gen_get_gpr(s, src1, rs1); =20 data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -907,7 +907,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn= *gvec_fn, TCGv_i64 src1 =3D tcg_temp_new_i64(); TCGv tmp =3D tcg_temp_new(); =20 - gen_get_gpr(tmp, a->rs1); + gen_get_gpr(s, tmp, a->rs1); tcg_gen_ext_tl_i64(src1, tmp); gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); @@ -1400,7 +1400,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, TCGv_i32 src1 =3D tcg_temp_new_i32(); TCGv tmp =3D tcg_temp_new(); =20 - gen_get_gpr(tmp, a->rs1); + gen_get_gpr(s, tmp, a->rs1); tcg_gen_trunc_tl_i32(src1, tmp); tcg_gen_extract_i32(src1, src1, 0, s->sew + 3); gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), @@ -1666,7 +1666,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 s1 =3D tcg_temp_new(); - gen_get_gpr(s1, a->rs1); + gen_get_gpr(s, s1, a->rs1); =20 if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), @@ -2419,7 +2419,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); - gen_set_gpr(a->rd, dst); + gen_set_gpr(s, a->rd, dst); =20 tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); @@ -2450,7 +2450,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); - gen_set_gpr(a->rd, dst); + gen_set_gpr(s, a->rd, dst); =20 tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); @@ -2649,7 +2649,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a) vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); } tcg_gen_trunc_i64_tl(dest, tmp); - gen_set_gpr(a->rd, dest); + gen_set_gpr(s, a->rd, dest); =20 tcg_temp_free(dest); tcg_temp_free_i64(tmp); --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463166740210.98198932442926; Tue, 31 Aug 2021 19:26:06 -0700 (PDT) Received: from localhost ([::1]:57250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFwz-00059M-CK for importer@patchew.org; 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s=dkim; t=1630462289; x=1633054290; bh=I0syDRJtV2wn16n8wB MLqUksv37eMsmpSz/469s9+9A=; b=SmO1eJaijaBsGRjdjigK5Y0IlOVDG05/pn zL6cA6w1jKnaVZC58bc2CnNtiG1AQsxXshZ9qweOCnMsZgSmcBiD3QbgXiddsxb5 7OSB8hBxKK9mBnEjITYigWuq8DF4hvq5EQX40z1VTyHWxjGfN5wNORPm2HGZF2Bs 7wscUmauc96mfPXrKv+H7SkPPJaUVtR6QjG+ZK72zyVTlPJKCvwX5szGPwpoipyF xUQKnWpAn2rc8KZO4dNVoq9lP7xkc9iR5mt/d6ILa/POLd/vd2ZzZkM8ImQFfzYT II6Apo30c71QJGG9SGN42N0E4q2MmZ8nBVM4YUaFGT6nWsiGvVUw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers Date: Wed, 1 Sep 2021 12:09:39 +1000 Message-Id: <20210901020958.458454-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463168016100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 97 +++++++++++++++++++++++++++++++++------- 1 file changed, 81 insertions(+), 16 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce4c56c179..d7552dc377 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -39,15 +39,25 @@ static TCGv load_val; =20 #include "exec/gen-icount.h" =20 +/* + * If an operation is being performed on less than TARGET_LONG_BITS, + * it may require the inputs to be sign- or zero-extended; which will + * depend on the exact operation being performed. + */ +typedef enum { + EXT_NONE, + EXT_SIGN, + EXT_ZERO, +} DisasExtend; + typedef struct DisasContext { DisasContextBase base; /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - bool virt_enabled; + target_ulong misa; uint32_t opcode; uint32_t mstatus_fs; - target_ulong misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -55,6 +65,8 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + bool w; + bool virt_enabled; bool ext_ifencei; bool hlsx; /* vector extension */ @@ -64,7 +76,11 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + uint8_t ntemp; CPUState *cs; + TCGv zero; + /* Space for 3 operands plus 1 extra for address computation. */ + TCGv temp[4]; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -172,27 +188,64 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) } } =20 -/* Wrapper for getting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated +/* + * Wrappers for getting reg values. + * + * The $zero register does not have cpu_gpr[0] allocated -- we supply the + * constant zero as a source, and an uninitialized sink as destination. + * + * Further, we may provide an extension for word operations. */ -static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) +static TCGv temp_new(DisasContext *ctx) +{ + assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); + return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); +} + +static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) { + TCGv t; + if (reg_num =3D=3D 0) { - tcg_gen_movi_tl(t, 0); - } else { - tcg_gen_mov_tl(t, cpu_gpr[reg_num]); + return ctx->zero; } + + switch (ctx->w ? ext : EXT_NONE) { + case EXT_NONE: + return cpu_gpr[reg_num]; + case EXT_SIGN: + t =3D temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t =3D temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + } + g_assert_not_reached(); } =20 -/* Wrapper for setting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated. this is more for safety purposes, - * since we usually avoid calling the OP_TYPE_gen function if we see a wri= te to - * $zero - */ -static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t) +static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) +{ + tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE)); +} + +static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_nu= m) +{ + if (reg_num =3D=3D 0 || ctx->w) { + return temp_new(ctx); + } + return cpu_gpr[reg_num]; +} + +static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { - if (reg_num_dst !=3D 0) { - tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); + if (reg_num !=3D 0) { + if (ctx->w) { + tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); + } else { + tcg_gen_mov_tl(cpu_gpr[reg_num], t); + } } } =20 @@ -940,6 +993,11 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs =3D cs; + ctx->w =3D false; + ctx->ntemp =3D 0; + memset(ctx->temp, 0, sizeof(ctx->temp)); + + ctx->zero =3D tcg_constant_tl(0); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -961,6 +1019,13 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; + ctx->w =3D false; + + for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) { + tcg_temp_free(ctx->temp[i]); + ctx->temp[i] =3D NULL; + } + ctx->ntemp =3D 0; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { target_ulong page_start; --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463013016937.0121789823448; Tue, 31 Aug 2021 19:23:33 -0700 (PDT) Received: from localhost ([::1]:49768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFuV-00009W-Km for importer@patchew.org; Tue, 31 Aug 2021 22:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFj8-0006La-Gg for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463015068100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Most arithmetic does not require extending the inputs. Exceptions include division, comparison and minmax. Begin using ctx->w, which allows elimination of gen_addw, gen_subw, gen_mulw. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 69 +++++++------------------ target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++------ target/riscv/insn_trans/trans_rvi.c.inc | 39 ++++++++------ target/riscv/insn_trans/trans_rvm.c.inc | 16 +++--- 4 files changed, 64 insertions(+), 90 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d7552dc377..7dd2839288 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -230,7 +230,7 @@ static void gen_get_gpr(DisasContext *ctx, TCGv t, int = reg_num) tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE)); } =20 -static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_nu= m) +static TCGv dest_gpr(DisasContext *ctx, int reg_num) { if (reg_num =3D=3D 0 || ctx->w) { return temp_new(ctx); @@ -482,57 +482,31 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode-insn32.c.inc" =20 -static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { - TCGv source1; - source1 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); =20 - (*func)(source1, source1, a->imm); + func(dest, src1, a->imm); =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 -static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D tcg_constant_tl(a->imm); =20 - gen_get_gpr(ctx, source1, a->rs1); - tcg_gen_movi_tl(source2, a->imm); + func(dest, src1, src2); =20 - (*func)(source1, source1, source2); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 -static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_add_tl(ret, arg1, arg2); - tcg_gen_ext32s_tl(ret, ret); -} - -static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_sub_tl(ret, arg1, arg2); - tcg_gen_ext32s_tl(ret, ret); -} - -static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_mul_tl(ret, arg1, arg2); - tcg_gen_ext32s_tl(ret, ret); -} - static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { @@ -798,21 +772,16 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_add_tl(ret, arg1, arg2); } =20 -static bool gen_arith(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*func)(TCGv, TCGv, TCGv)) { - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D get_gpr(ctx, a->rs2, ext); =20 - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); + func(dest, src1, src2); =20 - (*func)(source1, source1, source2); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 260e15b47d..217a7d1f26 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -38,61 +38,61 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a) static bool trans_andn(DisasContext *ctx, arg_andn *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_andc_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl); } =20 static bool trans_orn(DisasContext *ctx, arg_orn *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_orc_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl); } =20 static bool trans_xnor(DisasContext *ctx, arg_xnor *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_eqv_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl); } =20 static bool trans_pack(DisasContext *ctx, arg_pack *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); + return gen_arith(ctx, a, EXT_NONE, gen_pack); } =20 static bool trans_packu(DisasContext *ctx, arg_packu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); + return gen_arith(ctx, a, EXT_NONE, gen_packu); } =20 static bool trans_packh(DisasContext *ctx, arg_packh *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); + return gen_arith(ctx, a, EXT_NONE, gen_packh); } =20 static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smin_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl); } =20 static bool trans_max(DisasContext *ctx, arg_max *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smax_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl); } =20 static bool trans_minu(DisasContext *ctx, arg_minu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umin_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl); } =20 static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umax_tl); + return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl); } =20 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) @@ -230,7 +230,7 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a) static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ REQUIRE_EXT(ctx, RVB); = \ - return gen_arith(ctx, a, gen_sh##SHAMT##add); = \ + return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); = \ } =20 GEN_TRANS_SHADD(1) @@ -262,14 +262,14 @@ static bool trans_packw(DisasContext *ctx, arg_packw = *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packw); + return gen_arith(ctx, a, EXT_NONE, gen_packw); } =20 static bool trans_packuw(DisasContext *ctx, arg_packuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packuw); + return gen_arith(ctx, a, EXT_NONE, gen_packuw); } =20 static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) @@ -404,7 +404,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, = \ { \ REQUIRE_64BIT(ctx); \ REQUIRE_EXT(ctx, RVB); \ - return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \ + return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \ } =20 GEN_TRANS_SHADD_UW(1) @@ -415,7 +415,7 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw = *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_add_uw); + return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } =20 static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index f1a5d8de56..bd80476852 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -230,7 +230,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a) =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { - return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } =20 static void gen_slt(TCGv ret, TCGv s1, TCGv s2) @@ -243,29 +243,31 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); } =20 - static bool trans_slti(DisasContext *ctx, arg_slti *a) { - return gen_arith_imm_tl(ctx, a, &gen_slt); + return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt); } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - return gen_arith_imm_tl(ctx, a, &gen_sltu); + return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu); } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) { - return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl); } + static bool trans_ori(DisasContext *ctx, arg_ori *a) { - return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl); } + static bool trans_andi(DisasContext *ctx, arg_andi *a) { - return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl); + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl); } + static bool trans_slli(DisasContext *ctx, arg_slli *a) { return gen_shifti(ctx, a, tcg_gen_shl_tl); @@ -283,12 +285,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) =20 static bool trans_add(DisasContext *ctx, arg_add *a) { - return gen_arith(ctx, a, &tcg_gen_add_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } =20 static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return gen_arith(ctx, a, &tcg_gen_sub_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -298,17 +300,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return gen_arith(ctx, a, &gen_slt); + return gen_arith(ctx, a, EXT_SIGN, gen_slt); } =20 static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return gen_arith(ctx, a, &gen_sltu); + return gen_arith(ctx, a, EXT_SIGN, gen_sltu); } =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return gen_arith(ctx, a, &tcg_gen_xor_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -323,18 +325,19 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) =20 static bool trans_or(DisasContext *ctx, arg_or *a) { - return gen_arith(ctx, a, &tcg_gen_or_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl); } =20 static bool trans_and(DisasContext *ctx, arg_and *a) { - return gen_arith(ctx, a, &tcg_gen_and_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl); } =20 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - return gen_arith_imm_tl(ctx, a, &gen_addw); + ctx->w =3D true; + return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) @@ -370,13 +373,15 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - return gen_arith(ctx, a, &gen_addw); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - return gen_arith(ctx, a, &gen_subw); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 0a4318f18e..013b3f7009 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -22,7 +22,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &tcg_gen_mul_tl); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } =20 static bool trans_mulh(DisasContext *ctx, arg_mulh *a) @@ -44,7 +44,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_mulhsu); + return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); } =20 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -66,33 +66,33 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_div); + return gen_arith(ctx, a, EXT_SIGN, gen_div); } =20 static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_divu); + return gen_arith(ctx, a, EXT_ZERO, gen_divu); } =20 static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_rem); + return gen_arith(ctx, a, EXT_SIGN, gen_rem); } =20 static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_remu); + return gen_arith(ctx, a, EXT_ZERO, gen_remu); } =20 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - - return gen_arith(ctx, a, &gen_mulw); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462300; x=1633054301; bh=25RoiPJRUM8/nB8GGz lGW2EvzjClmiFmjR4KFnO3OfM=; b=Qdee+w3yF0NnQ1/YXYvFa+tYr5DVc+PcPo 4ENUkD3ePNUYWoBYV1VY4pasBEOCpHD7SeA4xqwfajvowZJS1zjL5z5mSAeulCBM EvadoQYFroBXv0YykmH1Pgz4jGhmhWeoWzDaE/kZHSBkcBdheoFrHoQIy47MOo4i U9AtBvCzzjqU4Y76+4yZKpOvfz6N0e8q4e5Qpjv44CSdeS1Zb+9t1yk/CpgvfDZ5 XaHaRTWibdLVF/XxqNrtDWC/V++09czNVrjpBqYnoBoJDi87LAzx04RzeARI/Ts0 TGNpvwVzhqszDTdeKpG3FL+BdX0wp4KXkgosq5aQVhvOf4hev0rQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 16/33] target/riscv: Remove gen_arith_div* Date: Wed, 1 Sep 2021 12:09:41 +1000 Message-Id: <20210901020958.458454-17-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463034513100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use ctx->w and the enhanced gen_arith function. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 42 ------------------------- target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++----- 2 files changed, 8 insertions(+), 50 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7dd2839288..1855eacbac 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -507,48 +507,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i = *a, DisasExtend ext, return true; } =20 -static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) -{ - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_ext32s_tl(source2, source2); - - (*func)(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) -{ - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_ext32u_tl(source2, source2); - - (*func)(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_deposit_tl(ret, arg1, arg2, diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 013b3f7009..3d93b24c25 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - - return gen_arith_div_w(ctx, a, &gen_div); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_SIGN, gen_div); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - - return gen_arith_div_uw(ctx, a, &gen_divu); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_ZERO, gen_divu); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - - return gen_arith_div_w(ctx, a, &gen_rem); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_SIGN, gen_rem); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - - return gen_arith_div_uw(ctx, a, &gen_remu); + ctx->w =3D true; + return gen_arith(ctx, a, EXT_ZERO, gen_remu); } --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462305; x=1633054306; bh=2WlTrVAbj0SjSClXEj BSZtxaDgYclx08zJ0DTcYqRRs=; b=ZVyiEpmrCSX8W4+kUY+a7joTncbck8nOIP PPIH6l/GyTz5ZdMJIJYd6OsJfDuy2mO6BBDxf3hABkC1hnk91+X7NNdgArjOJKOq CAUinijSfgIbobXkg+6QWJAId92DtLpixeMmBtHYxkXO36gNP8gasNYYKF3vRQw4 BfXB1IBQ8TtMj0CEaPIp1SmY6l15ta8ZOojTTnMzSYMna0fYv3DrBFCe/L4tKJ1K PINKH52tO5x3VD25ypbwBUGkzrkoYGapHd5ksHaV/EYS95ilDlXvSibhuQBZ7RxJ /l7JVgEYNaPtbkip00uRTe8pN03DP6F46m1aKVSXdQZVNaqcCxjA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu Date: Wed, 1 Sep 2021 12:09:42 +1000 Message-Id: <20210901020958.458454-18-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463208073100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Split out gen_mulh and gen_mulhu and use the common helper. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvm.c.inc | 40 +++++++++++-------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 3d93b24c25..80552be7a3 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -25,20 +25,18 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } =20 -static bool trans_mulh(DisasContext *ctx, arg_mulh *a) +static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) { - REQUIRE_EXT(ctx, RVM); - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); + TCGv discard =3D tcg_temp_new(); =20 - tcg_gen_muls2_tl(source2, source1, source1, source2); + tcg_gen_muls2_tl(discard, ret, s1, s2); + tcg_temp_free(discard); +} =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; +static bool trans_mulh(DisasContext *ctx, arg_mulh *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, EXT_NONE, gen_mulh); } =20 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) @@ -47,20 +45,18 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu = *a) return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); } =20 -static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) +static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) { - REQUIRE_EXT(ctx, RVM); - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); + TCGv discard =3D tcg_temp_new(); =20 - tcg_gen_mulu2_tl(source2, source1, source1, source2); + tcg_gen_mulu2_tl(discard, ret, s1, s2); + tcg_temp_free(discard); +} =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, EXT_NONE, gen_mulhu); } =20 static bool trans_div(DisasContext *ctx, arg_div *a) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463307770240.2788185892739; Tue, 31 Aug 2021 19:28:27 -0700 (PDT) Received: from localhost ([::1]:37644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFzG-0002YL-Do for importer@patchew.org; Tue, 31 Aug 2021 22:28:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFjN-0006qr-AT for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462311; x=1633054312; bh=TWt63/u 8YF6okTanwbatY3CCNWHmbgABvqGooWU9INQ=; b=EtP0CAyZ0ZqZRsi77NR1ovc 7yynTmVPU0J5rpe/A5EWbjTmSuu/nu18i2Ug45r++ODdzg+CuWSpwiDSNs/oHXfm L39V9Dx+cYB5RXZAPznivPvI5taKreAORYuZJFNykYQcqWSA8uU4zXefVaXG/cpW qrI4fP1tXkLJEHpsnha0VXGxeUm19jeu1CCP1ynynnv+XHltjQx9jmy0TgfTYqzT vTZyCYDlS1tCuQhv9pq1mJkOaTiT1WQtAGCbHynMbhAeYHJP15yH7jNB9jo9tSPE nLCL/Owx82dIMNdanY7ujtsGMgNuRx7eER/A4kn7d//JA65q5iigqHwmZQ/sPzw= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 18/33] target/riscv: Move gen_* helpers for RVM Date: Wed, 1 Sep 2021 12:09:43 +1000 Message-Id: <20210901020958.458454-19-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463309082100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move these helpers near their use by the trans_* functions within insn_trans/trans_rvm.c.inc. Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 127 ------------------------ target/riscv/insn_trans/trans_rvm.c.inc | 127 ++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1855eacbac..7fbacfa6ee 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -249,133 +249,6 @@ static void gen_set_gpr(DisasContext *ctx, int reg_nu= m, TCGv t) } } =20 -static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv rl =3D tcg_temp_new(); - TCGv rh =3D tcg_temp_new(); - - tcg_gen_mulu2_tl(rl, rh, arg1, arg2); - /* fix up for one negative */ - tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(rl, rl, arg2); - tcg_gen_sub_tl(ret, rh, rl); - - tcg_temp_free(rl); - tcg_temp_free(rh); -} - -static void gen_div(TCGv ret, TCGv source1, TCGv source2) -{ - TCGv temp1, temp2, zero, one, mone, min; - - temp1 =3D tcg_temp_new(); - temp2 =3D tcg_temp_new(); - zero =3D tcg_constant_tl(0); - one =3D tcg_constant_tl(1); - mone =3D tcg_constant_tl(-1); - min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); - - /* - * If overflow, set temp2 to 1, else source2. - * This produces the required result of min. - */ - tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); - tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); - tcg_gen_and_tl(temp1, temp1, temp2); - tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2); - - /* - * If div by zero, set temp1 to -1 and temp2 to 1 to - * produce the required result of -1. - */ - tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1); - tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2); - - tcg_gen_div_tl(ret, temp1, temp2); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); -} - -static void gen_divu(TCGv ret, TCGv source1, TCGv source2) -{ - TCGv temp1, temp2, zero, one, max; - - temp1 =3D tcg_temp_new(); - temp2 =3D tcg_temp_new(); - zero =3D tcg_constant_tl(0); - one =3D tcg_constant_tl(1); - max =3D tcg_constant_tl(~0); - - /* - * If div by zero, set temp1 to max and temp2 to 1 to - * produce the required result of max. - */ - tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1); - tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); - tcg_gen_divu_tl(ret, temp1, temp2); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); -} - -static void gen_rem(TCGv ret, TCGv source1, TCGv source2) -{ - TCGv temp1, temp2, zero, one, mone, min; - - temp1 =3D tcg_temp_new(); - temp2 =3D tcg_temp_new(); - zero =3D tcg_constant_tl(0); - one =3D tcg_constant_tl(1); - mone =3D tcg_constant_tl(-1); - min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); - - /* - * If overflow, set temp1 to 0, else source1. - * This avoids a possible host trap, and produces the required result = of 0. - */ - tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); - tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); - tcg_gen_and_tl(temp1, temp1, temp2); - tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1); - - /* - * If div by zero, set temp2 to 1, else source2. - * This avoids a possible host trap, but produces an incorrect result. - */ - tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); - - tcg_gen_rem_tl(temp1, temp1, temp2); - - /* If div by zero, the required result is the original dividend. */ - tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); -} - -static void gen_remu(TCGv ret, TCGv source1, TCGv source2) -{ - TCGv temp, zero, one; - - temp =3D tcg_temp_new(); - zero =3D tcg_constant_tl(0); - one =3D tcg_constant_tl(1); - - /* - * If div by zero, set temp to 1, else source2. - * This avoids a possible host trap, but produces an incorrect result. - */ - tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2); - - tcg_gen_remu_tl(temp, source1, temp); - - /* If div by zero, the required result is the original dividend. */ - tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp); - - tcg_temp_free(temp); -} - static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { target_ulong next_pc; diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 80552be7a3..b89a85ad3a 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -39,6 +39,21 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) return gen_arith(ctx, a, EXT_NONE, gen_mulh); } =20 +static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv rl =3D tcg_temp_new(); + TCGv rh =3D tcg_temp_new(); + + tcg_gen_mulu2_tl(rl, rh, arg1, arg2); + /* fix up for one negative */ + tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(rl, rl, arg2); + tcg_gen_sub_tl(ret, rh, rl); + + tcg_temp_free(rl); + tcg_temp_free(rh); +} + static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); @@ -59,24 +74,136 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *= a) return gen_arith(ctx, a, EXT_NONE, gen_mulhu); } =20 +static void gen_div(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv temp1, temp2, zero, one, mone, min; + + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + mone =3D tcg_constant_tl(-1); + min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); + + /* + * If overflow, set temp2 to 1, else source2. + * This produces the required result of min. + */ + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); + tcg_gen_and_tl(temp1, temp1, temp2); + tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2); + + /* + * If div by zero, set temp1 to -1 and temp2 to 1 to + * produce the required result of -1. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1); + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2); + + tcg_gen_div_tl(ret, temp1, temp2); + + tcg_temp_free(temp1); + tcg_temp_free(temp2); +} + static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); return gen_arith(ctx, a, EXT_SIGN, gen_div); } =20 +static void gen_divu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv temp1, temp2, zero, one, max; + + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + max =3D tcg_constant_tl(~0); + + /* + * If div by zero, set temp1 to max and temp2 to 1 to + * produce the required result of max. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1); + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); + tcg_gen_divu_tl(ret, temp1, temp2); + + tcg_temp_free(temp1); + tcg_temp_free(temp2); +} + static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); return gen_arith(ctx, a, EXT_ZERO, gen_divu); } =20 +static void gen_rem(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv temp1, temp2, zero, one, mone, min; + + temp1 =3D tcg_temp_new(); + temp2 =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + mone =3D tcg_constant_tl(-1); + min =3D tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); + + /* + * If overflow, set temp1 to 0, else source1. + * This avoids a possible host trap, and produces the required result = of 0. + */ + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); + tcg_gen_and_tl(temp1, temp1, temp2); + tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1); + + /* + * If div by zero, set temp2 to 1, else source2. + * This avoids a possible host trap, but produces an incorrect result. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); + + tcg_gen_rem_tl(temp1, temp1, temp2); + + /* If div by zero, the required result is the original dividend. */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1); + + tcg_temp_free(temp1); + tcg_temp_free(temp2); +} + static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); return gen_arith(ctx, a, EXT_SIGN, gen_rem); } =20 +static void gen_remu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv temp, zero, one; + + temp =3D tcg_temp_new(); + zero =3D tcg_constant_tl(0); + one =3D tcg_constant_tl(1); + + /* + * If div by zero, set temp to 1, else source2. + * This avoids a possible host trap, but produces an incorrect result. + */ + tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2); + + tcg_gen_remu_tl(temp, source1, temp); + + /* If div by zero, the required result is the original dividend. */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp); + + tcg_temp_free(temp); +} + static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1630462318; x=1633054319; bh=dKAFS3e heCBnbpb0TnFg9L92fvkeRa2KTdl87DgO4bM=; b=EL8qgNWGGjj59UhkG5bhCM+ L1k4nIdy6yx62oJ1xP4Lr4RgpFWCVxxvS2e/x++0GhTe6cC8psSz+tBj/DviSeDZ XfyWQ+qSQtiP+azi4dhclR7f3PDpc/el/T1wV0bnb+HEJdEVx6tSqLBcv4igMFPh 5+OlWA9i9CRus8K3AOVtKETC/QLjntuV/FPHTomfEl8eyYhOa6FxKbmnoKHO4gwT TdzwftkKZzstrpGDRnRpX7HX1Rxr4Udx2filiLJxXYQ9PX2xcESE7IT5gMn9NX1u ZptgiaiVCtATkAcG7pINgEnlViQQAwm3x6OMD7n3Jpd6GIfOukRUQd/11jNghAA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 19/33] target/riscv: Move gen_* helpers for RVB Date: Wed, 1 Sep 2021 12:09:44 +1000 Message-Id: <20210901020958.458454-20-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463340918100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move these helpers near their use by the trans_* functions within insn_trans/trans_rvb.c.inc. Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 233 ----------------------- target/riscv/insn_trans/trans_rvb.c.inc | 234 ++++++++++++++++++++++++ 2 files changed, 234 insertions(+), 233 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7fbacfa6ee..09853530c4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -380,229 +380,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i= *a, DisasExtend ext, return true; } =20 -static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_deposit_tl(ret, arg1, arg2, - TARGET_LONG_BITS / 2, - TARGET_LONG_BITS / 2); -} - -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); - tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); - tcg_temp_free(t); -} - -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext8u_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); - tcg_temp_free(t); -} - -static void gen_sbop_mask(TCGv ret, TCGv shamt) -{ - tcg_gen_movi_tl(ret, 1); - tcg_gen_shl_tl(ret, ret, shamt); -} - -static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) -{ - TCGv t =3D tcg_temp_new(); - - gen_sbop_mask(t, shamt); - tcg_gen_or_tl(ret, arg1, t); - - tcg_temp_free(t); -} - -static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) -{ - TCGv t =3D tcg_temp_new(); - - gen_sbop_mask(t, shamt); - tcg_gen_andc_tl(ret, arg1, t); - - tcg_temp_free(t); -} - -static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) -{ - TCGv t =3D tcg_temp_new(); - - gen_sbop_mask(t, shamt); - tcg_gen_xor_tl(ret, arg1, t); - - tcg_temp_free(t); -} - -static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) -{ - tcg_gen_shr_tl(ret, arg1, shamt); - tcg_gen_andi_tl(ret, ret, 1); -} - -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool gen_grevi(DisasContext *ctx, arg_grevi *a) -{ - TCGv source1 =3D tcg_temp_new(); - TCGv source2; - - gen_get_gpr(ctx, source1, a->rs1); - - if (a->shamt =3D=3D (TARGET_LONG_BITS - 8)) { - /* rev8, byte swaps */ - tcg_gen_bswap_tl(source1, source1); - } else { - source2 =3D tcg_temp_new(); - tcg_gen_movi_tl(source2, a->shamt); - gen_helper_grev(source1, source1, source2); - tcg_temp_free(source2); - } - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - return true; -} - -#define GEN_SHADD(SHAMT) \ -static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ -{ \ - TCGv t =3D tcg_temp_new(); \ - \ - tcg_gen_shli_tl(t, arg1, SHAMT); \ - tcg_gen_add_tl(ret, t, arg2); \ - \ - tcg_temp_free(t); \ -} - -GEN_SHADD(1) -GEN_SHADD(2) -GEN_SHADD(3) - -static void gen_ctzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); - tcg_gen_ctzi_tl(ret, ret, 64); -} - -static void gen_clzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ext32u_tl(ret, arg1); - tcg_gen_clzi_tl(ret, ret, 64); - tcg_gen_subi_tl(ret, ret, 32); -} - -static void gen_cpopw(TCGv ret, TCGv arg1) -{ - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_ctpop_tl(ret, arg1); -} - -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext16s_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 16, 48); - tcg_temp_free(t); -} - -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, 16); - tcg_gen_deposit_tl(ret, arg2, t, 0, 16); - tcg_gen_ext32s_tl(ret, ret); - tcg_temp_free(t); -} - -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 =3D tcg_temp_new_i32(); - TCGv_i32 t2 =3D tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotr_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 =3D tcg_temp_new_i32(); - TCGv_i32 t2 =3D tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotl_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_grev(ret, arg1, arg2); -} - -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_gorcw(ret, arg1, arg2); -} - -#define GEN_SHADD_UW(SHAMT) \ -static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ -{ \ - TCGv t =3D tcg_temp_new(); \ - \ - tcg_gen_ext32u_tl(t, arg1); \ - \ - tcg_gen_shli_tl(t, t, SHAMT); \ - tcg_gen_add_tl(ret, t, arg2); \ - \ - tcg_temp_free(t); \ -} - -GEN_SHADD_UW(1) -GEN_SHADD_UW(2) -GEN_SHADD_UW(3) - -static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_add_tl(ret, arg1, arg2); -} - static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -701,16 +478,6 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *= a, return true; } =20 -static void gen_ctz(TCGv ret, TCGv arg1) -{ - tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); -} - -static void gen_clz(TCGv ret, TCGv arg1) -{ - tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); -} - static bool gen_unary(DisasContext *ctx, arg_r2 *a, void(*func)(TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 217a7d1f26..73f088be23 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -17,12 +17,23 @@ * this program. If not, see . */ =20 + +static void gen_clz(TCGv ret, TCGv arg1) +{ + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); +} + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); return gen_unary(ctx, a, gen_clz); } =20 +static void gen_ctz(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); +} + static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_EXT(ctx, RVB); @@ -53,18 +64,41 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl); } =20 +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_deposit_tl(ret, arg1, arg2, + TARGET_LONG_BITS / 2, + TARGET_LONG_BITS / 2); +} + static bool trans_pack(DisasContext *ctx, arg_pack *a) { REQUIRE_EXT(ctx, RVB); return gen_arith(ctx, a, EXT_NONE, gen_pack); } =20 +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); + tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); + tcg_temp_free(t); +} + static bool trans_packu(DisasContext *ctx, arg_packu *a) { REQUIRE_EXT(ctx, RVB); return gen_arith(ctx, a, EXT_NONE, gen_packu); } =20 +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_ext8u_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); + tcg_temp_free(t); +} + static bool trans_packh(DisasContext *ctx, arg_packh *a) { REQUIRE_EXT(ctx, RVB); @@ -107,6 +141,22 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h= *a) return gen_unary(ctx, a, tcg_gen_ext16s_tl); } =20 +static void gen_sbop_mask(TCGv ret, TCGv shamt) +{ + tcg_gen_movi_tl(ret, 1); + tcg_gen_shl_tl(ret, ret, shamt); +} + +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_or_tl(ret, arg1, t); + + tcg_temp_free(t); +} + static bool trans_bset(DisasContext *ctx, arg_bset *a) { REQUIRE_EXT(ctx, RVB); @@ -119,6 +169,16 @@ static bool trans_bseti(DisasContext *ctx, arg_bseti *= a) return gen_shifti(ctx, a, gen_bset); } =20 +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_andc_tl(ret, arg1, t); + + tcg_temp_free(t); +} + static bool trans_bclr(DisasContext *ctx, arg_bclr *a) { REQUIRE_EXT(ctx, RVB); @@ -131,6 +191,16 @@ static bool trans_bclri(DisasContext *ctx, arg_bclri *= a) return gen_shifti(ctx, a, gen_bclr); } =20 +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_xor_tl(ret, arg1, t); + + tcg_temp_free(t); +} + static bool trans_binv(DisasContext *ctx, arg_binv *a) { REQUIRE_EXT(ctx, RVB); @@ -143,6 +213,12 @@ static bool trans_binvi(DisasContext *ctx, arg_binvi *= a) return gen_shifti(ctx, a, gen_binv); } =20 +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) +{ + tcg_gen_shr_tl(ret, arg1, shamt); + tcg_gen_andi_tl(ret, ret, 1); +} + static bool trans_bext(DisasContext *ctx, arg_bext *a) { REQUIRE_EXT(ctx, RVB); @@ -155,6 +231,13 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *= a) return gen_shifti(ctx, a, gen_bext); } =20 +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shl_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + static bool trans_slo(DisasContext *ctx, arg_slo *a) { REQUIRE_EXT(ctx, RVB); @@ -167,6 +250,13 @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a) return gen_shifti(ctx, a, gen_slo); } =20 +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shr_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + static bool trans_sro(DisasContext *ctx, arg_sro *a) { REQUIRE_EXT(ctx, RVB); @@ -203,6 +293,28 @@ static bool trans_grev(DisasContext *ctx, arg_grev *a) return gen_shift(ctx, a, gen_helper_grev); } =20 +static bool gen_grevi(DisasContext *ctx, arg_grevi *a) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2; + + gen_get_gpr(ctx, source1, a->rs1); + + if (a->shamt =3D=3D (TARGET_LONG_BITS - 8)) { + /* rev8, byte swaps */ + tcg_gen_bswap_tl(source1, source1); + } else { + source2 =3D tcg_temp_new(); + tcg_gen_movi_tl(source2, a->shamt); + gen_helper_grev(source1, source1, source2); + tcg_temp_free(source2); + } + + gen_set_gpr(ctx, a->rd, source1); + tcg_temp_free(source1); + return true; +} + static bool trans_grevi(DisasContext *ctx, arg_grevi *a) { REQUIRE_EXT(ctx, RVB); @@ -226,6 +338,21 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *= a) return gen_shifti(ctx, a, gen_helper_gorc); } =20 +#define GEN_SHADD(SHAMT) \ +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t =3D tcg_temp_new(); \ + \ + tcg_gen_shli_tl(t, arg1, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADD(1) +GEN_SHADD(2) +GEN_SHADD(3) + #define GEN_TRANS_SHADD(SHAMT) = \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ @@ -237,6 +364,13 @@ GEN_TRANS_SHADD(1) GEN_TRANS_SHADD(2) GEN_TRANS_SHADD(3) =20 +static void gen_clzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(ret, arg1); + tcg_gen_clzi_tl(ret, ret, 64); + tcg_gen_subi_tl(ret, ret, 32); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -244,6 +378,12 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) return gen_unary(ctx, a, gen_clzw); } =20 +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); + tcg_gen_ctzi_tl(ret, ret, 64); +} + static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); @@ -251,6 +391,12 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) return gen_unary(ctx, a, gen_ctzw); } =20 +static void gen_cpopw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_ctpop_tl(ret, arg1); +} + static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); @@ -258,6 +404,14 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *= a) return gen_unary(ctx, a, gen_cpopw); } =20 +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_ext16s_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 16, 48); + tcg_temp_free(t); +} + static bool trans_packw(DisasContext *ctx, arg_packw *a) { REQUIRE_64BIT(ctx); @@ -265,6 +419,15 @@ static bool trans_packw(DisasContext *ctx, arg_packw *= a) return gen_arith(ctx, a, EXT_NONE, gen_packw); } =20 +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_shri_tl(t, arg1, 16); + tcg_gen_deposit_tl(ret, arg2, t, 0, 16); + tcg_gen_ext32s_tl(ret, ret); + tcg_temp_free(t); +} + static bool trans_packuw(DisasContext *ctx, arg_packuw *a) { REQUIRE_64BIT(ctx); @@ -349,6 +512,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *= a) return gen_shiftiw(ctx, a, gen_sro); } =20 +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -363,6 +544,24 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *= a) return gen_shiftiw(ctx, a, gen_rorw); } =20 +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); @@ -370,6 +569,12 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) return gen_shiftw(ctx, a, gen_rolw); } =20 +static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + gen_helper_grev(ret, arg1, arg2); +} + static bool trans_grevw(DisasContext *ctx, arg_grevw *a) { REQUIRE_64BIT(ctx); @@ -384,6 +589,12 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw= *a) return gen_shiftiw(ctx, a, gen_grevw); } =20 +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + gen_helper_gorcw(ret, arg1, arg2); +} + static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a) { REQUIRE_64BIT(ctx); @@ -398,6 +609,23 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw= *a) return gen_shiftiw(ctx, a, gen_gorcw); } =20 +#define GEN_SHADD_UW(SHAMT) \ +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t =3D tcg_temp_new(); \ + \ + tcg_gen_ext32u_tl(t, arg1); \ + \ + tcg_gen_shli_tl(t, t, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADD_UW(1) +GEN_SHADD_UW(2) +GEN_SHADD_UW(3) + #define GEN_TRANS_SHADD_UW(SHAMT) \ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ arg_sh##SHAMT##add_uw *a) \ @@ -411,6 +639,12 @@ GEN_TRANS_SHADD_UW(1) GEN_TRANS_SHADD_UW(2) GEN_TRANS_SHADD_UW(3) =20 +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_add_tl(ret, arg1, arg2); +} + static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) { REQUIRE_64BIT(ctx); --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463645483685.8764733779439; Tue, 31 Aug 2021 19:34:05 -0700 (PDT) Received: from localhost ([::1]:47704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG4i-0000v0-HJ for importer@patchew.org; Tue, 31 Aug 2021 22:34:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFjW-0007BT-W9 for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462322; x=1633054323; bh=UMvGT5HI8BBn/237WK oZV8oOW1OIUkNTSIPt6o4+VoU=; b=IDrs7uNHSqs/79aZZBAoToY5jLTfUm/RfZ pI99+bNRieV0rSbSFb6itV3VtsEotTP2sJLP1ysdyPNqtkffv7VV0SixvaPPjZAS wWXvzs9g9OLDTdywtov9Tjws1NfYAt5B9lZH2P4/4x1bbifuUMLC8DKTIih83U+V jolpzVkGZm4A84TssOUu5QLfdZczPlZ8a2ZQ00mLMNpu4ZnRrBoNqT5JiDNAoWED Kp4eVrynnv3npV0mwg1h/Nnau06nG1tpBLcCCa4au5ufvwt2TXqja/k8EGfpwDWX iVYh+3hyxR721HGezjjGOSRxRRIU2LXxJ+RRWavEv7iqJGO0HiQQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL 20/33] target/riscv: Add DisasExtend to gen_unary Date: Wed, 1 Sep 2021 12:09:45 +1000 Message-Id: <20210901020958.458454-21-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463647276100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use ctx->w for ctpopw, which is the only one that can re-use the generic algorithm for the narrow operation. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 14 ++++++-------- target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++--------------- 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 09853530c4..785e9e58cc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -478,17 +478,15 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift = *a, return true; } =20 -static bool gen_unary(DisasContext *ctx, arg_r2 *a, - void(*func)(TCGv, TCGv)) +static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*func)(TCGv, TCGv)) { - TCGv source =3D tcg_temp_new(); - - gen_get_gpr(ctx, source, a->rs1); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); =20 - (*func)(source, source); + func(dest, src1); =20 - gen_set_gpr(ctx, a->rd, source); - tcg_temp_free(source); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 73f088be23..e255678fff 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -26,7 +26,7 @@ static void gen_clz(TCGv ret, TCGv arg1) static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_clz); + return gen_unary(ctx, a, EXT_ZERO, gen_clz); } =20 static void gen_ctz(TCGv ret, TCGv arg1) @@ -37,13 +37,13 @@ static void gen_ctz(TCGv ret, TCGv arg1) static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_ctz); + return gen_unary(ctx, a, EXT_ZERO, gen_ctz); } =20 static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ctpop_tl); + return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } =20 static bool trans_andn(DisasContext *ctx, arg_andn *a) @@ -132,13 +132,13 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a) static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ext8s_tl); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); } =20 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ext16s_tl); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); } =20 static void gen_sbop_mask(TCGv ret, TCGv shamt) @@ -366,7 +366,6 @@ GEN_TRANS_SHADD(3) =20 static void gen_clzw(TCGv ret, TCGv arg1) { - tcg_gen_ext32u_tl(ret, arg1); tcg_gen_clzi_tl(ret, ret, 64); tcg_gen_subi_tl(ret, ret, 32); } @@ -375,7 +374,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_clzw); + return gen_unary(ctx, a, EXT_ZERO, gen_clzw); } =20 static void gen_ctzw(TCGv ret, TCGv arg1) @@ -388,20 +387,15 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_ctzw); -} - -static void gen_cpopw(TCGv ret, TCGv arg1) -{ - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_ctpop_tl(ret, arg1); + return gen_unary(ctx, a, EXT_NONE, gen_ctzw); } =20 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_cpopw); + ctx->w =3D true; + return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } =20 static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463475008855.7220449238747; Tue, 31 Aug 2021 19:31:15 -0700 (PDT) Received: from localhost ([::1]:43110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG1x-0006A7-LU for importer@patchew.org; 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s=dkim; t=1630462328; x=1633054329; bh=Fkim/Uv20ZPcmaaf0l grDhqiCCAn/TuW2tC3ijlFooI=; b=QklJvDO0QssEjJuSwtv+gen8eg38EM2uwO zhE3MWHThyvZhaIeyWMrwKk/EuPLJxKTgji/pezCzCbq8zTHsFq9xFEcB5y8UGO5 6/pgTKbLTSFfqR4eaMzGo/2vYmWSX7J77a3HUc0RlzcjPtKvhz1NZ82lQa+1wtJl mXjdCIQUk+OL2fk4+mGavs8cJqTyPN2pOK8dOR6+cmKjJxzQN1jIAYfFjsoxLI8x v8tg6eQaJuaxn9fapaEJ6e8VJoBt06kQ6ASUgZk5FOGnFDHrIhOI8cjWRuPH7vlx BOv2bP1hJZ+MlxgHGAb01NMg9d92TdSpR6Nwxrchgfs75tn+eOQA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 21/33] target/riscv: Use DisasExtend in shift operations Date: Wed, 1 Sep 2021 12:09:46 +1000 Message-Id: <20210901020958.458454-22-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463477134100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 110 +++++++++----------- target/riscv/insn_trans/trans_rvb.c.inc | 129 +++++++++++------------- target/riscv/insn_trans/trans_rvi.c.inc | 88 ++++------------ 3 files changed, 125 insertions(+), 202 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 785e9e58cc..e44254e878 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -99,6 +99,13 @@ static inline bool is_32bit(DisasContext *ctx) } #endif =20 +/* The word size for this operation. */ +static inline int oper_len(DisasContext *ctx) +{ + return ctx->w ? 32 : TARGET_LONG_BITS; +} + + /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -393,88 +400,58 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, Di= sasExtend ext, return true; } =20 -static bool gen_shift(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) -{ - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - (*func)(source1, source1, source2); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend = ext, + void (*func)(TCGv, TCGv, target_long)) { - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUState *cpu =3D ctx->cs; - CPURISCVState *env =3D cpu->env_ptr; + TCGv dest, src1; + int max_len =3D oper_len(ctx); =20 - return cpu_ldl_code(env, pc); -} - -static bool gen_shifti(DisasContext *ctx, arg_shift *a, - void(*func)(TCGv, TCGv, TCGv)) -{ - if (a->shamt >=3D TARGET_LONG_BITS) { + if (a->shamt >=3D max_len) { return false; } =20 - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); + dest =3D dest_gpr(ctx, a->rd); + src1 =3D get_gpr(ctx, a->rs1, ext); =20 - tcg_gen_movi_tl(source2, a->shamt); - (*func)(source1, source1, source2); + func(dest, src1, a->shamt); =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 -static bool gen_shiftw(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend = ext, + void (*func)(TCGv, TCGv, TCGv)) { - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); + TCGv dest, src1, src2; + int max_len =3D oper_len(ctx); + + if (a->shamt >=3D max_len) { + return false; + } =20 - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); + dest =3D dest_gpr(ctx, a->rd); + src1 =3D get_gpr(ctx, a->rs1, ext); + src2 =3D tcg_constant_tl(a->shamt); =20 - tcg_gen_andi_tl(source2, source2, 31); - (*func)(source1, source1, source2); - tcg_gen_ext32s_tl(source1, source1); + func(dest, src1, src2); =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 -static bool gen_shiftiw(DisasContext *ctx, arg_shift *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*func)(TCGv, TCGv, TCGv)) { - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - tcg_gen_movi_tl(source2, a->shamt); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv ext2 =3D tcg_temp_new(); =20 - (*func)(source1, source1, source2); - tcg_gen_ext32s_tl(source1, source1); + tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + func(dest, src1, ext2); =20 - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(ext2); return true; } =20 @@ -490,6 +467,15 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, Di= sasExtend ext, return true; } =20 +static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUState *cpu =3D ctx->cs; + CPURISCVState *env =3D cpu->env_ptr; + + return cpu_ldl_code(env, pc); +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index e255678fff..b97c3ca5da 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -160,13 +160,13 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bset(DisasContext *ctx, arg_bset *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_bset); + return gen_shift(ctx, a, EXT_NONE, gen_bset); } =20 static bool trans_bseti(DisasContext *ctx, arg_bseti *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_bset); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset); } =20 static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) @@ -182,13 +182,13 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bclr(DisasContext *ctx, arg_bclr *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_bclr); + return gen_shift(ctx, a, EXT_NONE, gen_bclr); } =20 static bool trans_bclri(DisasContext *ctx, arg_bclri *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_bclr); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr); } =20 static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) @@ -204,13 +204,13 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_binv(DisasContext *ctx, arg_binv *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_binv); + return gen_shift(ctx, a, EXT_NONE, gen_binv); } =20 static bool trans_binvi(DisasContext *ctx, arg_binvi *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_binv); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv); } =20 static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) @@ -222,13 +222,13 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) static bool trans_bext(DisasContext *ctx, arg_bext *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_bext); + return gen_shift(ctx, a, EXT_NONE, gen_bext); } =20 static bool trans_bexti(DisasContext *ctx, arg_bexti *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_bext); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } =20 static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) @@ -241,13 +241,13 @@ static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_slo(DisasContext *ctx, arg_slo *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_slo); + return gen_shift(ctx, a, EXT_NONE, gen_slo); } =20 static bool trans_sloi(DisasContext *ctx, arg_sloi *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_slo); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); } =20 static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) @@ -260,82 +260,65 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_sro(DisasContext *ctx, arg_sro *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_sro); + return gen_shift(ctx, a, EXT_ZERO, gen_sro); } =20 static bool trans_sroi(DisasContext *ctx, arg_sroi *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_sro); + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); } =20 static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, tcg_gen_rotr_tl); + return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); } =20 static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, tcg_gen_rotr_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); } =20 static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, tcg_gen_rotl_tl); + return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } =20 static bool trans_grev(DisasContext *ctx, arg_grev *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_helper_grev); + return gen_shift(ctx, a, EXT_NONE, gen_helper_grev); } =20 -static bool gen_grevi(DisasContext *ctx, arg_grevi *a) +static void gen_grevi(TCGv dest, TCGv src, target_long shamt) { - TCGv source1 =3D tcg_temp_new(); - TCGv source2; - - gen_get_gpr(ctx, source1, a->rs1); - - if (a->shamt =3D=3D (TARGET_LONG_BITS - 8)) { + if (shamt =3D=3D TARGET_LONG_BITS - 8) { /* rev8, byte swaps */ - tcg_gen_bswap_tl(source1, source1); + tcg_gen_bswap_tl(dest, src); } else { - source2 =3D tcg_temp_new(); - tcg_gen_movi_tl(source2, a->shamt); - gen_helper_grev(source1, source1, source2); - tcg_temp_free(source2); + gen_helper_grev(dest, src, tcg_constant_tl(shamt)); } - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - return true; } =20 static bool trans_grevi(DisasContext *ctx, arg_grevi *a) { REQUIRE_EXT(ctx, RVB); - - if (a->shamt >=3D TARGET_LONG_BITS) { - return false; - } - - return gen_grevi(ctx, a); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi); } =20 static bool trans_gorc(DisasContext *ctx, arg_gorc *a) { REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_helper_gorc); + return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc); } =20 static bool trans_gorci(DisasContext *ctx, arg_gorci *a) { REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_helper_gorc); + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc); } =20 #define GEN_SHADD(SHAMT) \ @@ -433,77 +416,88 @@ static bool trans_bsetw(DisasContext *ctx, arg_bsetw = *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bset); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_bset); } =20 static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_bset); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset); } =20 static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bclr); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_bclr); } =20 static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_bclr); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr); } =20 static bool trans_binvw(DisasContext *ctx, arg_binvw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_binv); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_binv); } =20 static bool trans_binviw(DisasContext *ctx, arg_binviw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_binv); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv); } =20 static bool trans_bextw(DisasContext *ctx, arg_bextw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bext); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_bext); } =20 static bool trans_slow(DisasContext *ctx, arg_slow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_slo); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_slo); } =20 static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_slo); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); } =20 static bool trans_srow(DisasContext *ctx, arg_srow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_sro); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_ZERO, gen_sro); } =20 static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_sro); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); } =20 static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) @@ -528,14 +522,16 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_rorw); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_rorw); } =20 static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_rorw); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } =20 static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) @@ -560,47 +556,40 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_rolw); -} - -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_grev(ret, arg1, arg2); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, gen_rolw); } =20 static bool trans_grevw(DisasContext *ctx, arg_grevw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_grevw); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev); } =20 static bool trans_greviw(DisasContext *ctx, arg_greviw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_grevw); -} - -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_gorcw(ret, arg1, arg2); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev); } =20 static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_gorcw); + ctx->w =3D true; + return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc); } =20 static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_gorcw); + ctx->w =3D true; + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc); } =20 #define GEN_SHADD_UW(SHAMT) \ diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index bd80476852..e4726e618c 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -270,17 +270,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a) =20 static bool trans_slli(DisasContext *ctx, arg_slli *a) { - return gen_shifti(ctx, a, tcg_gen_shl_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } =20 static bool trans_srli(DisasContext *ctx, arg_srli *a) { - return gen_shifti(ctx, a, tcg_gen_shr_tl); + return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); } =20 static bool trans_srai(DisasContext *ctx, arg_srai *a) { - return gen_shifti(ctx, a, tcg_gen_sar_tl); + return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); } =20 static bool trans_add(DisasContext *ctx, arg_add *a) @@ -295,7 +295,7 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a) =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) { - return gen_shift(ctx, a, &tcg_gen_shl_tl); + return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) @@ -315,12 +315,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a) =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) { - return gen_shift(ctx, a, &tcg_gen_shr_tl); + return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } =20 static bool trans_sra(DisasContext *ctx, arg_sra *a) { - return gen_shift(ctx, a, &tcg_gen_sar_tl); + return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } =20 static bool trans_or(DisasContext *ctx, arg_or *a) @@ -343,31 +343,22 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw = *a) static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - return gen_shiftiw(ctx, a, tcg_gen_shl_tl); + ctx->w =3D true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - TCGv t =3D tcg_temp_new(); - gen_get_gpr(ctx, t, a->rs1); - tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); - /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(t, t); - gen_set_gpr(ctx, a->rd, t); - tcg_temp_free(t); - return true; + ctx->w =3D true; + return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); } =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - TCGv t =3D tcg_temp_new(); - gen_get_gpr(ctx, t, a->rs1); - tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); - gen_set_gpr(ctx, a->rd, t); - tcg_temp_free(t); - return true; + ctx->w =3D true; + return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); } =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) @@ -387,65 +378,22 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; + ctx->w =3D true; + return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; + ctx->w =3D true; + return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - TCGv source1 =3D tcg_temp_new(); - TCGv source2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); - - /* - * first, trick to get it to act like working on 32 bits (get rid of - * upper 32, sign extend to fill space) - */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - - return true; + ctx->w =3D true; + return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } =20 static bool trans_fence(DisasContext *ctx, arg_fence *a) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463771603751.9827789116404; Tue, 31 Aug 2021 19:36:11 -0700 (PDT) Received: from localhost ([::1]:51690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG6k-0003e8-Ju for importer@patchew.org; Tue, 31 Aug 2021 22:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFjj-0007Pu-Ur for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462334; x=1633054335; bh=D7cKtAsSC5vzXpL6Qc dCBJqs+dg9FCiXrFk9rhQcOR0=; b=eqwN/etlUaWi0Lhx9E9/MTMu1E4vojYrjL NXQ1Hl3ZiFVJYbHZahkzdQci3hA34FNLVcoW8By8K5BELxDpyGbjvbvq/BDbIcCk JUnqBxUcZjEotlNyamHs9DNmN8oXp/cxQ+mGbkuIBMlon0huyHX0DzJpTlo05M6H Iw3uluHNbPZWhZpTqzW4SzrImR/gylQ1gXJOyEuqDf9aaHUkkEqvMHdRoB49DMKX UeRRwi8TNqG7mRHiCYFN9bVpfHFihoXLKDnOmQzg7weOpyQHGXa1UCBvlnP8nsUo +mYX5dSRWb7K5rek9GhOEKtkUwmkkVejkItfy1jVzZA2TkrV0C2A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 22/33] target/riscv: Use extracts for sraiw and srliw Date: Wed, 1 Sep 2021 12:09:47 +1000 Message-Id: <20210901020958.458454-23-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463773713100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These operations can be done in one instruction on some hosts. Signed-off-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index e4726e618c..9e8d99be51 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw = *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } =20 +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); ctx->w =3D true; - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); ctx->w =3D true; - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463593688106.09778456309584; Tue, 31 Aug 2021 19:33:13 -0700 (PDT) Received: from localhost ([::1]:46136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG3s-0008Hv-98 for importer@patchew.org; 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s=dkim; t=1630462341; x=1633054342; bh=ujTVEvvtKaYYHlia7+ 3yZCVIGg84nF/Tt9DFiNXfIvU=; b=loBkRDJEtacpsgqSX4pBI45NIEBdajrqJq WoiVK4wRcGrTz9/LK7Vreci1sNdiND72ggg4qx8zh7W18NkAX8X937F/xfXUQPb2 nfai0UHuBqNrnK4KghMAScO3ZsdmOhk/fS83zvp8NnopIP4ZeVsc1IuJlkGIqS3I FG6N4QkC6Qs2a6eq5LTCK5cKDXkZUJaiRIsH3FEEI6yUD7J/C/4D9csfHShqnTdL yaiXNKkw1P64uYdPvyXXzo+t2kjfhUixSWFoMRZc61lU2PsLf4j79zsEjnQSIqTj o2VDOg3yDtM/S/lV5JvHQcSVPRt0PZ14gWQHAEjGABpwy1MrWSRA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 23/33] target/riscv: Use get_gpr in branches Date: Wed, 1 Sep 2021 12:09:48 +1000 Message-Id: <20210901020958.458454-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463594416100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Narrow the scope of t0 in trans_jalr. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 9e8d99be51..a5249e71c2 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) =20 static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { - /* no chaining with JALR */ TCGLabel *misaligned =3D NULL; - TCGv t0 =3D tcg_temp_new(); - =20 - gen_get_gpr(ctx, cpu_pc, a->rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 if (!has_ext(ctx, RVC)) { + TCGv t0 =3D tcg_temp_new(); + misaligned =3D gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + tcg_temp_free(t0); } =20 if (a->rd !=3D 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); } + + /* No chaining with JALR. */ lookup_and_goto_ptr(ctx); =20 if (misaligned) { @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } ctx->base.is_jmp =3D DISAS_NORETURN; =20 - tcg_temp_free(t0); return true; } =20 static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l =3D gen_new_label(); - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - gen_get_gpr(ctx, source2, a->rs2); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_SIGN); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_SIGN); =20 - tcg_gen_brcond_tl(cond, source1, source2, l); + tcg_gen_brcond_tl(cond, src1, src2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ =20 if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) } ctx->base.is_jmp =3D DISAS_NORETURN; =20 - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; } =20 --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463832699777.2599389019899; Tue, 31 Aug 2021 19:37:12 -0700 (PDT) Received: from localhost ([::1]:54868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG7j-0005tS-JY for importer@patchew.org; Tue, 31 Aug 2021 22:37:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFjz-0007fW-VW for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462346; x=1633054347; bh=teTRhQ/O0z0CBsIvCa P6Z6InQHVT7BTVYSYbDPouYJ8=; b=ALvYySwHoV4csRftbcFerf+0t7abifcizL Bd/D+5ATdtj6PFi3qq3dX+sGxo7M2tTLxYV0r/WMqCHw55q8co4H21Zo9cXI1oYJ gL0KLZMtvRFWlKJMsAF2Igih4y/iNPbYR2K6oPBFxfOkuyJ2BdsCj4eJbi/TD3PJ ynj5TMM+qRRFj4jPx8d0J5EQ6AYBys80VgiCYtgWrofYKzsTAB0Pd2pWy3FsQvxQ D11lbR2rId17C3+ZQKum+zFyWzlLFawRffRkK+080NhDAT/gjrHQtf8AfcREnaID 8HO8OohRl37VHhWMPd+GmCZWlhhZoexp7OP3ylyfryrSQupczJ7g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store Date: Wed, 1 Sep 2021 12:09:49 +1000 Message-Id: <20210901020958.458454-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463834290100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20210823195529.560295-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 38 +++++++++++++------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index a5249e71c2..76454fb7e2 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -138,15 +138,17 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) =20 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(ctx, a->rd, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -177,19 +179,19 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); - gen_get_gpr(ctx, dat, a->rs2); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); - tcg_temp_free(t0); - tcg_temp_free(dat); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } =20 - static bool trans_sb(DisasContext *ctx, arg_sb *a) { return gen_store(ctx, a, MO_SB); --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463003835311.6554979840661; Tue, 31 Aug 2021 19:23:23 -0700 (PDT) Received: from localhost ([::1]:49314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLFuM-0008IO-Sy for importer@patchew.org; Tue, 31 Aug 2021 22:23:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFjw-0007bL-FJ for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462352; x=1633054353; bh=jiKOZJRaBXBKcFzhnr RqXaoj0xRlXy+gX5m8el1Ul2k=; b=PnIc+5cpmZm/8N5WoZ3looZ3wCmShx5ltb 6k2x1DeddEG2ZJ3HTLhyI/qpl61sj6XkFDrJ4Sxw8vqVdhxGcrLav2Ry2c37fA1s 5ofs0ASh25HkvwITvxDtAvjdYu1oSH5aZQvU97D8UCXsn+0iiiNddDyuVgLCWNdI RlFfpa33te/PG7Tu/nO4iaqKx9B4X99DhRoEheQ87Rv1UCx1A0/aFJOo9Qftkugx rpvasVPa9qBv5+0zN6URd42C3zero3eL0MeRzB0BFQzhNvTD9Ot51jLK6yCOSk3g re/7HE9T+n7br54V3g68w7Bwq3/blVDrviEao/PH82GCeQqj78XQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation Date: Wed, 1 Sep 2021 12:09:50 +1000 Message-Id: <20210901020958.458454-26-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463005939100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We distinguish write-only by passing ret_value as NULL. Signed-off-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-17-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6d7f2c2a95..16bd859121 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -937,9 +937,12 @@ static RISCVException rmw_vsip(CPURISCVState *env, int= csrno, /* Shift the S bits to their VS bit location in mip */ int ret =3D rmw_mip(env, 0, ret_value, new_value << 1, (write_mask << 1) & vsip_writable_mask & env->hidele= g); - *ret_value &=3D VS_MODE_INTERRUPTS; - /* Shift the VS bits to their S bit location in vsip */ - *ret_value >>=3D 1; + + if (ret_value) { + *ret_value &=3D VS_MODE_INTERRUPTS; + /* Shift the VS bits to their S bit location in vsip */ + *ret_value >>=3D 1; + } return ret; } =20 @@ -956,7 +959,9 @@ static RISCVException rmw_sip(CPURISCVState *env, int c= srno, write_mask & env->mideleg & sip_writable_mask); } =20 - *ret_value &=3D env->mideleg; + if (ret_value) { + *ret_value &=3D env->mideleg; + } return ret; } =20 @@ -1072,8 +1077,9 @@ static RISCVException rmw_hvip(CPURISCVState *env, in= t csrno, int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hvip_writable_mask); =20 - *ret_value &=3D hvip_writable_mask; - + if (ret_value) { + *ret_value &=3D hvip_writable_mask; + } return ret; } =20 @@ -1084,8 +1090,9 @@ static RISCVException rmw_hip(CPURISCVState *env, int= csrno, int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); =20 - *ret_value &=3D hip_writable_mask; - + if (ret_value) { + *ret_value &=3D hip_writable_mask; + } return ret; } =20 --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463924355438.2410312734719; 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s=dkim; t=1630462358; x=1633054359; bh=BdJ5OyVoB6zkr4E8rR JEZRH54d4QzXjXusnhSAYb7HI=; b=cnn1UQEOzmW4ptJkPquRz9IfYHCz3OBfe/ UfwbVImrF0Qadwsmb5Qf/Oi7ritXtdy6B26Qvvn8wt5GzHnh9+LRMcosQPMh/78W Xkj6lQg1DwFlkKye6VFeTgUGcH7BysZ73S/KGDLHxkOxoUp8y43/lUgNmLJ8dGj8 kfGWPxeXRA/1bsXXrO+6rBLICgC8IeD5meVdPd0GU+aTIgEFWefGlncnmcLLbfYm t7M61iSfGybwmwqhsaOIEeS04qpKa5TZ/LULTNt0k+mD8uu6WgqEsWSUY68LW01D bhx29hruqBq1D8mcK7ff5x/4KlMW3DbvZbgvCUvkFQ2rCxa3pqHg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 26/33] target/riscv: Fix hgeie, hgeip Date: Wed, 1 Sep 2021 12:09:51 +1000 Message-Id: <20210901020958.458454-27-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463925583100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We failed to write into *val for these read functions; replace them with read_zero. Only warn about unsupported non-zero value when writing a non-zero value. Signed-off-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-18-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 16bd859121..50a2c3a3b4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1124,17 +1124,12 @@ static RISCVException write_hcounteren(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException read_hgeie(CPURISCVState *env, int csrno, - target_ulong *val) -{ - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return RISCV_EXCP_NONE; -} - static RISCVException write_hgeie(CPURISCVState *env, int csrno, target_ulong val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + if (val) { + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + } return RISCV_EXCP_NONE; } =20 @@ -1165,17 +1160,12 @@ static RISCVException write_htinst(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException read_hgeip(CPURISCVState *env, int csrno, - target_ulong *val) -{ - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return RISCV_EXCP_NONE; -} - static RISCVException write_hgeip(CPURISCVState *env, int csrno, target_ulong val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + if (val) { + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + } return RISCV_EXCP_NONE; } =20 @@ -1601,10 +1591,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, [CSR_HIE] =3D { "hie", hmode, read_hie, writ= e_hie }, [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_zero, writ= e_hgeie }, [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, - [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, writ= e_hgeip }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_zero, writ= e_hgeip }, [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462363; x=1633054364; bh=JAw6/S/6EyKwEChkxj R/Y/V/J1bHPL4fMoB8EXHbWjI=; b=k8zw+/xFwel0V8XLiYHDj6D496quMXC6Qh /9Tujmw3bQ2AKhowWd2fuGdqaOlCpQOWcxDKJSL9cBRqQbxqj11aDuj3CGnxXWbl KywNREiNJz8ZsB3U/n9I2Dqj0WISjBamzFm8pGtXh61lIKEZiUh7vFgC1aQIRG+o cZ8mCBOHRqSeI9lpdfP3izYQgcbQ8S6tclyh2uvXe6MOXrwp+NZ76TQiUREEclGK rXUPyZxUvEuvxw2dor7LOQnK32Wtx1+3OIIJfmFAj+40kQ/OnhkNoek8/AY5J9+V HLcJCcw9r5E1VqdIAeg4M4/ruXjCvbuJR1/tEYbyfoZM0y5yRzkA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 27/33] target/riscv: Reorg csr instructions Date: Wed, 1 Sep 2021 12:09:52 +1000 Message-Id: <20210901020958.458454-28-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463180720100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 =3D=3D 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/helper.h | 6 +- target/riscv/op_helper.c | 18 +-- target/riscv/insn_trans/trans_rvi.c.inc | 174 +++++++++++++++++------- 3 files changed, 132 insertions(+), 66 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 415e37bc37..460eee9988 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -65,9 +65,9 @@ DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Special functions */ -DEF_HELPER_3(csrrw, tl, env, tl, tl) -DEF_HELPER_4(csrrs, tl, env, tl, tl, tl) -DEF_HELPER_4(csrrc, tl, env, tl, tl, tl) +DEF_HELPER_2(csrr, tl, env, int) +DEF_HELPER_3(csrw, void, env, int, tl) +DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3c48e739ac..ee7c24efe7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -37,11 +37,10 @@ void helper_raise_exception(CPURISCVState *env, uint32_= t exception) riscv_raise_exception(env, exception, 0); } =20 -target_ulong helper_csrrw(CPURISCVState *env, target_ulong src, - target_ulong csr) +target_ulong helper_csrr(CPURISCVState *env, int csr) { target_ulong val =3D 0; - RISCVException ret =3D riscv_csrrw(env, csr, &val, src, -1); + RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, 0); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -49,23 +48,20 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ul= ong src, return val; } =20 -target_ulong helper_csrrs(CPURISCVState *env, target_ulong src, - target_ulong csr, target_ulong rs1_pass) +void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - target_ulong val =3D 0; - RISCVException ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src = : 0); + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, -1); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); } - return val; } =20 -target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, - target_ulong csr, target_ulong rs1_pass) +target_ulong helper_csrrw(CPURISCVState *env, int csr, + target_ulong src, target_ulong write_mask) { target_ulong val =3D 0; - RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src := 0); + RISCVException ret =3D riscv_csrrw(env, csr, &val, src, write_mask); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 76454fb7e2..920ae0edb3 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -426,80 +426,150 @@ static bool trans_fence_i(DisasContext *ctx, arg_fen= ce_i *a) return true; } =20 -#define RISCV_OP_CSR_PRE do {\ - source1 =3D tcg_temp_new(); \ - csr_store =3D tcg_temp_new(); \ - dest =3D tcg_temp_new(); \ - rs1_pass =3D tcg_temp_new(); \ - gen_get_gpr(ctx, source1, a->rs1); \ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \ - tcg_gen_movi_tl(rs1_pass, a->rs1); \ - tcg_gen_movi_tl(csr_store, a->csr); \ - gen_io_start();\ -} while (0) - -#define RISCV_OP_CSR_POST do {\ - gen_set_gpr(ctx, a->rd, dest); \ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \ - exit_tb(ctx); \ - ctx->base.is_jmp =3D DISAS_NORETURN; \ - tcg_temp_free(source1); \ - tcg_temp_free(csr_store); \ - tcg_temp_free(dest); \ - tcg_temp_free(rs1_pass); \ -} while (0) +static bool do_csr_post(DisasContext *ctx) +{ + /* We may have changed important cpu state -- exit to main loop. */ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + exit_tb(ctx); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} + +static bool do_csrr(DisasContext *ctx, int rd, int rc) +{ + TCGv dest =3D dest_gpr(ctx, rd); + TCGv_i32 csr =3D tcg_constant_i32(rc); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrr(dest, cpu_env, csr); + gen_set_gpr(ctx, rd, dest); + return do_csr_post(ctx); +} + +static bool do_csrw(DisasContext *ctx, int rc, TCGv src) +{ + TCGv_i32 csr =3D tcg_constant_i32(rc); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrw(cpu_env, csr, src); + return do_csr_post(ctx); +} + +static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mas= k) +{ + TCGv dest =3D dest_gpr(ctx, rd); + TCGv_i32 csr =3D tcg_constant_i32(rc); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_csrrw(dest, cpu_env, csr, src, mask); + gen_set_gpr(ctx, rd, dest); + return do_csr_post(ctx); +} =20 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrw(dest, cpu_env, source1, csr_store); - RISCV_OP_CSR_POST; - return true; + TCGv src =3D get_gpr(ctx, a->rs1, EXT_NONE); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any of t= he + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw(ctx, a->csr, src); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; + /* + * If rs1 =3D=3D 0, the insn shall not write to the csr at all, nor + * cause any of the side effects that might occur on a csr write. + * Note that if rs1 specifies a register other than x0, holding + * a zero value, the instruction will still attempt to write the + * unmodified value back to the csr and will cause side effects. + */ + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); + return do_csrrw(ctx, a->rd, a->csr, ones, mask); } =20 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; + /* + * If rs1 =3D=3D 0, the insn shall not write to the csr at all, nor + * cause any of the side effects that might occur on a csr write. + * Note that if rs1 specifies a register other than x0, holding + * a zero value, the instruction will still attempt to write the + * unmodified value back to the csr and will cause side effects. + */ + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv mask =3D get_gpr(ctx, a->rs1, EXT_ZERO); + return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); } =20 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store); - RISCV_OP_CSR_POST; - return true; + TCGv src =3D tcg_constant_tl(a->rs1); + + /* + * If rd =3D=3D 0, the insn shall not read the csr, nor cause any of t= he + * side effects that might occur on a csr read. + */ + if (a->rd =3D=3D 0) { + return do_csrw(ctx, a->csr, src); + } + + TCGv mask =3D tcg_constant_tl(-1); + return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; + /* + * If rs1 =3D=3D 0, the insn shall not write to the csr at all, nor + * cause any of the side effects that might occur on a csr write. + * Note that if rs1 specifies a register other than x0, holding + * a zero value, the instruction will still attempt to write the + * unmodified value back to the csr and will cause side effects. + */ + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv ones =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw(ctx, a->rd, a->csr, ones, mask); } =20 static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) { - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; + /* + * If rs1 =3D=3D 0, the insn shall not write to the csr at all, nor + * cause any of the side effects that might occur on a csr write. + * Note that if rs1 specifies a register other than x0, holding + * a zero value, the instruction will still attempt to write the + * unmodified value back to the csr and will cause side effects. + */ + if (a->rs1 =3D=3D 0) { + return do_csrr(ctx, a->rd, a->csr); + } + + TCGv mask =3D tcg_constant_tl(a->rs1); + return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask); } --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462368; x=1633054369; bh=sWmBwJwLtxFRNIwO20 RvmCwHJuEQv09yP0QcAYcSYqE=; b=qwiMhJP3OgWhUTOuPw8L3Y97W0gj3xnQqU Xh4PT6tAVlkUTQoIBdr1NDRoN3LIxh0jlZcCOMCQ4LwRvKfrrBQ/NRR7YFxXc2kR vEk3ZrEVNs092EUOwVta99DaXVfE5IJfB36TyhP7X1i7etVdpkI5Kq3qUaFmHVq6 QR0Kx5KvrKlAjW2rC2TBAaOANKt7mUtwSC8hoyOwQnDfZMs05+prF5VY5YUiJGcM d1ldset9+q5CSR58klOCw+sfHA4JjQwz9VtqW136GQ+gfef15RUW3sGSo04eLmNy 6xoBtiFdsK+p/6DMjOS4z3clvag5Z9o9mhKXV6TmGnVMVYeVtrPg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 28/33] target/riscv: Use {get,dest}_gpr for RVA Date: Wed, 1 Sep 2021 12:09:53 +1000 Message-Id: <20210901020958.458454-29-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463317451100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-20-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 47 ++++++++++--------------- 1 file changed, 19 insertions(+), 28 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 3cc3c3b073..6ea07d89b0 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -18,11 +18,10 @@ * this program. If not, see . */ =20 -static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) +static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 =3D tcg_temp_new(); - /* Put addr in load_res, data in load_val. */ - gen_get_gpr(ctx, src1, a->rs1); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -30,33 +29,33 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic= *a, MemOp mop) if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } + + /* Put addr in load_res, data in load_val. */ tcg_gen_mov_tl(load_res, src1); gen_set_gpr(ctx, a->rd, load_val); =20 - tcg_temp_free(src1); return true; } =20 -static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) +static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 =3D tcg_temp_new(); - TCGv src2 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); + TCGv dest, src1, src2; TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - gen_get_gpr(ctx, src1, a->rs1); + src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 - gen_get_gpr(ctx, src2, a->rs2); /* * Note that the TCG atomic primitives are SC, * so we can ignore AQ/RL along this path. */ - tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, + dest =3D dest_gpr(ctx, a->rd); + src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2, ctx->mem_idx, mop); - tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); - gen_set_gpr(ctx, a->rd, dat); + tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val); + gen_set_gpr(ctx, a->rd, dest); tcg_gen_br(l2); =20 gen_set_label(l1); @@ -65,8 +64,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, MemOp mop) * provide the memory barrier implied by AQ/RL. */ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); - tcg_gen_movi_tl(dat, 1); - gen_set_gpr(ctx, a->rd, dat); + gen_set_gpr(ctx, a->rd, tcg_constant_tl(1)); =20 gen_set_label(l2); /* @@ -75,9 +73,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, MemOp mop) */ tcg_gen_movi_tl(load_res, -1); =20 - tcg_temp_free(dat); - tcg_temp_free(src1); - tcg_temp_free(src2); return true; } =20 @@ -85,17 +80,13 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), MemOp mop) { - TCGv src1 =3D tcg_temp_new(); - TCGv src2 =3D tcg_temp_new(); - - gen_get_gpr(ctx, src1, a->rs1); - gen_get_gpr(ctx, src2, a->rs2); + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - (*func)(src2, src1, src2, ctx->mem_idx, mop); + func(dest, src1, src2, ctx->mem_idx, mop); =20 - gen_set_gpr(ctx, a->rd, src2); - tcg_temp_free(src1); - tcg_temp_free(src2); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462373; x=1633054374; bh=UkYP+R8GR9rDdHFoS7 1xp7/peSpQJfKki2BleBjjKCY=; b=CunSoqMhG2/oqcHGoruKBPVxONkIuSYYqH YRAtzx+d9N5ETCLk3Rh5Ctao6N5l9OkhsBa6JgiVhvDFbQgYFCFegeD0Xfs+/pL5 r1uJxcPdSUBgaOtwtL8uFVCyaVciN9a8C/qJk5GSmAhas13NQUYMOcv8gp89HFMg 2GOc3UMwCd8PY/cgEPHqBQITkNDr5dVFTsKcD3bjjyAgf0dudnSRtRaxxJt9JjdM FHvfhtlVMUeOOFdW/a1WpvXDqATSWgZAN67aK8Fte3f5DoOt2/OUtwZHpWAMFtHO hMzmhvpYPi7fECnF4n9RPtvRen+6wmYQZGSOrqmFR9ebjp2wOYrg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL 29/33] target/riscv: Use gen_shift_imm_fn for slli_uw Date: Wed, 1 Sep 2021 12:09:54 +1000 Message-Id: <20210901020958.458454-30-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630464026160100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Always use tcg_gen_deposit_z_tl; the special case for shamt >=3D 32 is handled there. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-21-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvb.c.inc | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index b97c3ca5da..b72e76255c 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -635,21 +635,14 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_u= w *a) return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } =20 +static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt) +{ + tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - sham= t)); +} + static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - - TCGv source1 =3D tcg_temp_new(); - gen_get_gpr(ctx, source1, a->rs1); - - if (a->shamt < 32) { - tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); - } else { - tcg_gen_shli_tl(source1, source1, a->shamt); - } - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(source1); - return true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163046415085711.977511455525473; Tue, 31 Aug 2021 19:42:30 -0700 (PDT) Received: from localhost ([::1]:39740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLGCr-0006Pp-MF for importer@patchew.org; Tue, 31 Aug 2021 22:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFkb-00088a-TH for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462377; x=1633054378; bh=5wftx+o7evGhs10Z/n zzR9iXrhTvQn8bUulU3pJ4mHc=; b=EvSjInPZfALTmS4JqgipeWEKz/tEJFE1tW JnoGhyz5CKHARD3q2Ypu7AnAfzK82wwvHKQjdtKgQrClMLYmuaAamwjjRM9I+2yA n79z1h7DdPDMSV8sZOfVhMJd2UuNDCCItm+j/DZPy4niGS4n2ZB7fvSthemaNUxe J3/DIUqCGaiCz3XBKV2/A7aTear5MfnnX/YOX7P33ge6Tg4ixaBaLA930DenqzjR Ly9bMYiHXYyjIJRxEs83dsOyNAQgW4M2fQ7gduRYXgrfwjTu+tmH5YkTeSOr6WYm /qEIgPEPL3bFisQNOi0ugRy4Sj+B38/jvycpAAAhti4yE+TfDZDg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 30/33] target/riscv: Use {get,dest}_gpr for RVF Date: Wed, 1 Sep 2021 12:09:55 +1000 Message-Id: <20210901020958.458454-31-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630464151476100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-22-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.c.inc | 146 ++++++++++++------------ 1 file changed, 70 insertions(+), 76 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index fb9f7f9c00..bddbd418d9 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -25,32 +25,43 @@ =20 static bool trans_flw(DisasContext *ctx, arg_flw *a) { + TCGv_i64 dest; + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + dest =3D cpu_fpr[a->rd]; + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); + gen_nanbox_s(dest, dest); =20 - tcg_temp_free(t0); mark_fs_dirty(ctx); return true; } =20 static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); =20 - tcg_gen_addi_tl(t0, t0, a->imm); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D tcg_temp_new(); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); =20 - tcg_temp_free(t0); return true; } =20 @@ -271,12 +282,11 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcv= t_w_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -285,12 +295,11 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fc= vt_wu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -300,17 +309,15 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 #if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); + tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); #else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); #endif =20 - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); - + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -318,10 +325,11 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -329,10 +337,11 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -340,10 +349,11 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -352,13 +362,10 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fcl= ass_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - - gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); - - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_fclass_s(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -367,15 +374,12 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcv= t_s_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -384,15 +388,12 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fc= vt_s_wu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -402,15 +403,12 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_= w_x *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 - tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -420,11 +418,11 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcv= t_l_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -434,11 +432,11 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fc= vt_lu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -448,14 +446,12 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcv= t_s_l *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } =20 @@ -465,13 +461,11 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fc= vt_s_lu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630464241330228.56873916374263; Tue, 31 Aug 2021 19:44:01 -0700 (PDT) Received: from localhost ([::1]:42280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLGEK-00087P-44 for importer@patchew.org; Tue, 31 Aug 2021 22:44:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFkd-0008F6-L2 for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462383; x=1633054384; bh=bq60etOujt67A50MJ0 KRr7ZLPRi0VU4eZGFMugjbot4=; b=WCzFC9veC5OBfli80B3YI+f8KVgx8OeB4F gmXBI/By1EUcCL64bDJfqvUeY3IREiPIcuMcmU5fOUOkD2nTLtExqttYjVJ8BloD 8/baBZWnZhwIATm5J/mH1M42LNlHMM5qF87w+bn+0Hg67keVnChyqShvunIUg2UJ BpUGmxATt62GAyl7FVStO9fskI2iSRN1KBynfRXzgNaRY9wyN8lR7iDMkECx5QbF +ql62iKaaseLNRm1XrHeKRXE41+S0n2iTg0pISZ0hsy3ZqdOzUSQRu2BZNtTuqmw Mip1qeugvYmP25XtEcj9pW4BsVXIhAfZzHVOGfnpJJ2YgMXF5GRQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Bin Meng , Alistair Francis Subject: [PULL 31/33] target/riscv: Use {get,dest}_gpr for RVD Date: Wed, 1 Sep 2021 12:09:56 +1000 Message-Id: <20210901020958.458454-32-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630464242531100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-23-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvd.c.inc | 125 ++++++++++++------------ 1 file changed, 60 insertions(+), 65 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 11b9b3f90b..db9ae15755 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -20,30 +20,40 @@ =20 static bool trans_fld(DisasContext *ctx, arg_fld *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } =20 static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); =20 - tcg_temp_free(t0); return true; } =20 @@ -252,11 +262,10 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -265,11 +274,10 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -278,11 +286,10 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -291,10 +298,10 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fcl= ass_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_fclass_d(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -303,12 +310,11 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcv= t_w_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -317,12 +323,11 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fc= vt_wu_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -331,12 +336,10 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcv= t_d_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); return true; @@ -347,12 +350,10 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fc= vt_d_wu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); return true; @@ -364,11 +365,11 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcv= t_l_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -378,11 +379,11 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -406,12 +407,11 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcv= t_d_l *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src); + mark_fs_dirty(ctx); return true; } @@ -422,12 +422,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fc= vt_d_lu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src); + mark_fs_dirty(ctx); return true; } @@ -439,11 +438,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d= _x *a) REQUIRE_EXT(ctx, RVD); =20 #ifdef TARGET_RISCV64 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_mov_tl(cpu_fpr[a->rd], t0); - tcg_temp_free(t0); + tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE)); mark_fs_dirty(ctx); return true; #else --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630464344248576.5233751495473; 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s=dkim; t=1630462388; x=1633054389; bh=eqvAQz0 yt9ZA64gD7mwsbxLf6rZukeixkBbUSonaMRA=; b=FuTzvIG12phCQuzkBL0KI/O id5cTejKdz0jlhDpogkvNU3aBicjSW8R30+bauriyDdKnSkjMYBdJe6pEzp1NLTg uN6kRxgsW6AdpQ0Zxo+7vAGjzkS0usHJhVpRpucbytGtldcE6sJGcJ3ITtwoAQDI 1R+N9HOmSxUz9mz1dyJ/KKVsUQ9nOOn71bV+kscIEqfnWE6d60s0R6vCm+bfmpXA 5I1XNsrsPSJDsamA2nR97/wmhgXnLtYRN8h0JGTPmkE9BE2uAMKSKXH0U1rL5O1y 5LzxfhDeF5llpPCHAWjf1WOMi7DhLq/jNRsJsTZtCOjWg7oE2o87an+PInjykhg= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 32/33] target/riscv: Tidy trans_rvh.c.inc Date: Wed, 1 Sep 2021 12:09:57 +1000 Message-Id: <20210901020958.458454-33-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630464345626100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-24-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvh.c.inc | 266 +++++------------------- 2 files changed, 57 insertions(+), 210 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f09f8d5faf..2cd921d51c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -42,6 +42,7 @@ &j imm rd &r rd rs1 rs2 &r2 rd rs1 +&r2_s rs1 rs2 &s imm rs1 rs2 &u imm rd &shift shamt rs1 rd diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 585eb1d87e..ecbf77ff9c 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -17,281 +17,139 @@ */ =20 #ifndef CONFIG_USER_ONLY -static void check_access(DisasContext *ctx) { +static bool check_access(DisasContext *ctx) +{ if (!ctx->hlsx) { if (ctx->virt_enabled) { generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); } else { generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } + return false; } + return true; } #endif =20 -static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) +static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) { - REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else +#ifdef CONFIG_USER_ONLY return false; +#else + if (check_access(ctx)) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); + gen_set_gpr(ctx, a->rd, dest); + } + return true; #endif } =20 -static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); - gen_set_gpr(ctx, a->rd, t1); + return do_hlv(ctx, a, MO_SB); +} =20 - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else - return false; -#endif +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +{ + REQUIRE_EXT(ctx, RVH); + return do_hlv(ctx, a, MO_TESW); } =20 static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else - return false; -#endif + return do_hlv(ctx, a, MO_TESL); } =20 static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else - return false; -#endif + return do_hlv(ctx, a, MO_UB); } =20 static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); - gen_set_gpr(ctx, a->rd, t1); + return do_hlv(ctx, a, MO_TEUW); +} =20 - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) +{ +#ifdef CONFIG_USER_ONLY return false; +#else + if (check_access(ctx)) { + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); + int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); + } + return true; #endif } =20 static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - gen_get_gpr(ctx, dat, a->rs2); - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); - - tcg_temp_free(t0); - tcg_temp_free(dat); - return true; -#else - return false; -#endif + return do_hsv(ctx, a, MO_SB); } =20 static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - gen_get_gpr(ctx, dat, a->rs2); - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); - - tcg_temp_free(t0); - tcg_temp_free(dat); - return true; -#else - return false; -#endif + return do_hsv(ctx, a, MO_TESW); } =20 static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - gen_get_gpr(ctx, dat, a->rs2); - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); - - tcg_temp_free(t0); - tcg_temp_free(dat); - return true; -#else - return false; -#endif + return do_hsv(ctx, a, MO_TESL); } =20 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else - return false; -#endif + return do_hlv(ctx, a, MO_TEUL); } =20 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - -#ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -#else - return false; -#endif + return do_hlv(ctx, a, MO_TEQ); } =20 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); + return do_hsv(ctx, a, MO_TEQ); +} =20 #ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - gen_get_gpr(ctx, dat, a->rs2); - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); - - tcg_temp_free(t0); - tcg_temp_free(dat); +static bool do_hlvx(DisasContext *ctx, arg_r2 *a, + void (*func)(TCGv, TCGv_env, TCGv)) +{ + if (check_access(ctx)) { + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + func(dest, cpu_env, addr); + gen_set_gpr(ctx, a->rd, dest); + } return true; -#else - return false; -#endif } +#endif =20 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; + return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu); #else return false; #endif @@ -301,19 +159,7 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_= wu *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - check_access(ctx); - - gen_get_gpr(ctx, t0, a->rs1); - - gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); - gen_set_gpr(ctx, a->rd, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; + return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu); #else return false; #endif --=20 2.31.1 From nobody Sun Apr 28 09:04:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630463604462375.61294457622887; Tue, 31 Aug 2021 19:33:24 -0700 (PDT) Received: from localhost ([::1]:46334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLG43-0008PB-BU for importer@patchew.org; Tue, 31 Aug 2021 22:33:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLFkg-0008LW-Dt for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630462393; x=1633054394; bh=f68pj3zRW2+3ElTjnK ouroMiut64+yHKHm+jnF2hZtg=; b=edzpSodFURrLcBDdzr0LmDf6uzTkZdxg+V Q+/wzXhQvWBcOH4DDJWPlqRB8ysgcv9cNJI1Dq5IY/Cpat2ldv1qIvxmj7MtaslU T3lu39d0yYKX9jaJTYgaajmHD5ogNNw8+ZTMOKYzDAN9B0oH7M5mg6X2foognUsT FwIyCJ74bUSyKymvIIM2G5BVnxZTncnwTPGCx/25IbUpTeTv9gHI88mCaX4eGiZo 4YX6lolbckwCfx7vs8o1Dj+MxujDwlqEWzli53BbcSv17AS7SEJfnmRIrWcacBJ5 SkivuCMgTqmOsk17I3+hsAvMnwofe5QBu9KBM/yp69jV5CZTCFKA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL 33/33] target/riscv: Use {get,dest}_gpr for RVV Date: Wed, 1 Sep 2021 12:09:58 +1000 Message-Id: <20210901020958.458454-34-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> References: <20210901020958.458454-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=871df42ed=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630463604995100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Remove gen_get_gpr, as the function becomes unused. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210823195529.560295-25-richard.henderson@linaro.org Signed-off-by: Alistair Francis --- target/riscv/translate.c | 13 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 74 +++++++------------------ 2 files changed, 26 insertions(+), 61 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e44254e878..e356fc6c46 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -232,11 +232,6 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, Di= sasExtend ext) g_assert_not_reached(); } =20 -static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) -{ - tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE)); -} - static TCGv dest_gpr(DisasContext *ctx, int reg_num) { if (reg_num =3D=3D 0 || ctx->w) { @@ -637,9 +632,11 @@ void riscv_translate_init(void) { int i; =20 - /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ - /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing= */ - /* registers, unless you specifically block reads/writes to reg 0 */ + /* + * cpu_gpr[0] is a placeholder for the zero register. Do not use it. + * Use the gen_set_gpr and get_gpr helper functions when accessing reg= s, + * unless you specifically block reads/writes to reg 0. + */ cpu_gpr[0] =3D NULL; =20 for (i =3D 1; i < 32; i++) { diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index de580c493c..fa451938f1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -27,27 +27,22 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl = *a) return false; } =20 - s2 =3D tcg_temp_new(); - dst =3D tcg_temp_new(); + s2 =3D get_gpr(ctx, a->rs2, EXT_ZERO); + dst =3D dest_gpr(ctx, a->rd); =20 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { - s1 =3D tcg_temp_new(); - gen_get_gpr(ctx, s1, a->rs1); + s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } - gen_get_gpr(ctx, s2, a->rs2); gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); lookup_and_goto_ptr(ctx); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(s1); - tcg_temp_free(s2); - tcg_temp_free(dst); return true; } =20 @@ -60,23 +55,20 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvl= i *a) } =20 s2 =3D tcg_constant_tl(a->zimm); - dst =3D tcg_temp_new(); + dst =3D dest_gpr(ctx, a->rd); =20 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ if (a->rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { - s1 =3D tcg_temp_new(); - gen_get_gpr(ctx, s1, a->rs1); + s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(s1); - tcg_temp_free(dst); return true; } =20 @@ -173,7 +165,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, =20 dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); - base =3D tcg_temp_new(); + base =3D get_gpr(s, rs1, EXT_NONE); =20 /* * As simd_desc supports at most 256 bytes, and in this implementation, @@ -184,7 +176,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, */ desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -192,7 +183,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, =20 tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); - tcg_temp_free(base); gen_set_label(over); return true; } @@ -330,12 +320,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t r= s1, uint32_t rs2, =20 dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); - base =3D tcg_temp_new(); - stride =3D tcg_temp_new(); + base =3D get_gpr(s, rs1, EXT_NONE); + stride =3D get_gpr(s, rs2, EXT_NONE); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(s, base, rs1); - gen_get_gpr(s, stride, rs2); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -343,8 +331,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, =20 tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); - tcg_temp_free(base); - tcg_temp_free(stride); gen_set_label(over); return true; } @@ -458,10 +444,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1= , uint32_t vs2, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); - base =3D tcg_temp_new(); + base =3D get_gpr(s, rs1, EXT_NONE); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -471,7 +456,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); - tcg_temp_free(base); gen_set_label(over); return true; } @@ -589,10 +573,9 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint= 32_t data, =20 dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); - base =3D tcg_temp_new(); + base =3D get_gpr(s, rs1, EXT_NONE); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); =20 @@ -600,7 +583,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint3= 2_t data, =20 tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); - tcg_temp_free(base); gen_set_label(over); return true; } @@ -665,10 +647,9 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint3= 2_t vs2, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); - base =3D tcg_temp_new(); + base =3D get_gpr(s, rs1, EXT_NONE); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); =20 - gen_get_gpr(s, base, rs1); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -678,7 +659,6 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32= _t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); - tcg_temp_free(base); gen_set_label(over); return true; } @@ -862,8 +842,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - src1 =3D tcg_temp_new(); - gen_get_gpr(s, src1, rs1); + src1 =3D get_gpr(s, rs1, EXT_NONE); =20 data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -879,7 +858,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); - tcg_temp_free(src1); gen_set_label(over); return true; } @@ -905,15 +883,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2s= Fn *gvec_fn, =20 if (a->vm && s->vl_eq_vlmax) { TCGv_i64 src1 =3D tcg_temp_new_i64(); - TCGv tmp =3D tcg_temp_new(); =20 - gen_get_gpr(s, tmp, a->rs1); - tcg_gen_ext_tl_i64(src1, tmp); + tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN)); gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 tcg_temp_free_i64(src1); - tcg_temp_free(tmp); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1398,16 +1373,13 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, G= VecGen2sFn32 *gvec_fn, =20 if (a->vm && s->vl_eq_vlmax) { TCGv_i32 src1 =3D tcg_temp_new_i32(); - TCGv tmp =3D tcg_temp_new(); =20 - gen_get_gpr(s, tmp, a->rs1); - tcg_gen_trunc_tl_i32(src1, tmp); + tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE)); tcg_gen_extract_i32(src1, src1, 0, s->sew + 3); gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 tcg_temp_free_i32(src1); - tcg_temp_free(tmp); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1665,8 +1637,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 - s1 =3D tcg_temp_new(); - gen_get_gpr(s, s1, a->rs1); + s1 =3D get_gpr(s, a->rs1, EXT_SIGN); =20 if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), @@ -1690,7 +1661,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) tcg_temp_free_i64(s1_i64); } =20 - tcg_temp_free(s1); gen_set_label(over); return true; } @@ -2412,7 +2382,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) =20 mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - dst =3D tcg_temp_new(); + dst =3D dest_gpr(s, a->rd); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); @@ -2423,7 +2393,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *= a) =20 tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); - tcg_temp_free(dst); return true; } return false; @@ -2443,7 +2412,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) =20 mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - dst =3D tcg_temp_new(); + dst =3D dest_gpr(s, a->rd); desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); @@ -2454,7 +2423,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr = *a) =20 tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); - tcg_temp_free(dst); return true; } return false; @@ -2638,7 +2606,7 @@ static void vec_element_loadi(DisasContext *s, TCGv_i= 64 dest, static bool trans_vext_x_v(DisasContext *s, arg_r *a) { TCGv_i64 tmp =3D tcg_temp_new_i64(); - TCGv dest =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(s, a->rd); =20 if (a->rs1 =3D=3D 0) { /* Special case vmv.x.s rd, vs2. */ @@ -2648,10 +2616,10 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *= a) int vlmax =3D s->vlen >> (3 + s->sew); vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); } + tcg_gen_trunc_i64_tl(dest, tmp); gen_set_gpr(s, a->rd, dest); =20 - tcg_temp_free(dest); tcg_temp_free_i64(tmp); return true; } --=20 2.31.1