From nobody Thu May 9 00:06:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163031218880215.839712869051823; Mon, 30 Aug 2021 01:29:48 -0700 (PDT) Received: from localhost ([::1]:60240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mKcfr-0007zN-Qu for importer@patchew.org; Mon, 30 Aug 2021 04:29:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKcee-0005iy-Uo; Mon, 30 Aug 2021 04:28:32 -0400 Received: from esa11.hc1455-7.c3s2.iphmx.com ([207.54.90.137]:19038) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKced-0000sQ-94; Mon, 30 Aug 2021 04:28:32 -0400 Received: from unknown (HELO yto-r1.gw.nic.fujitsu.com) ([218.44.52.217]) by esa11.hc1455-7.c3s2.iphmx.com with ESMTP; 30 Aug 2021 17:28:27 +0900 Received: from yto-m1.gw.nic.fujitsu.com (yto-nat-yto-m1.gw.nic.fujitsu.com [192.168.83.64]) by yto-r1.gw.nic.fujitsu.com (Postfix) with ESMTP id 89F211013A9; Mon, 30 Aug 2021 17:28:26 +0900 (JST) Received: from yto-om2.fujitsu.com (yto-om2.o.css.fujitsu.com [10.128.89.163]) by yto-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id C215FC9CE0; Mon, 30 Aug 2021 17:28:25 +0900 (JST) Received: from localhost.localdomain (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om2.fujitsu.com (Postfix) with ESMTP id A15E24006D7DE; Mon, 30 Aug 2021 17:28:25 +0900 (JST) IronPort-SDR: KAOLC2sIx6gclmkwRmNh+JZOYjtostHh4lOLio+N8cevDjDIxFjXezLYXrrFtRia1MLAFQr7yT 86DjG4SpZeNqMAf6EuM2c0Ibl5mC6KzWM/6IM9prgCTF3lTNfD8Qr+s6jjbGhK67YtrlhaHiq7 LfD+MsAXeY5IkYNoGJuY50AGfJv0hVLkote4aptdA8sIb3vLJ6Q1bEq1WDUDlrN1K3fvOJwJk+ Lr5kLkKR2oaC2pNbcr+tgMvmzFBC9H8plh4tO/G+QeVAoku6pL7cVOFWvR7Ki2+1CY9PAZ2HCY 7Ycgo8ma9vT+7z7FVQgtH7LS X-IronPort-AV: E=McAfee;i="6200,9189,10091"; a="21965020" X-IronPort-AV: E=Sophos;i="5.84,362,1620658800"; d="scan'208";a="21965020" From: Shuuichirou Ishii To: peter.maydell@linaro.org, drjones@redhat.com, qemu-arm@nongnu.org Subject: [PATCH v5 1/3] target-arm: Add support for Fujitsu A64FX Date: Mon, 30 Aug 2021 17:28:18 +0900 Message-Id: <20210830082820.2690275-2-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> References: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=207.54.90.137; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa11.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_NEUTRAL=0.779 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630312191115100002 Content-Type: text/plain; charset="utf-8" Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector length= s. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones --- target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2f0cbddab5..15245a60a8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -841,10 +841,58 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL); } =20 +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + aarch64_add_sve_properties(obj); + bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); + set_bit(0, cpu->sve_vq_supported); /* 128bit */ + set_bit(1, cpu->sve_vq_supported); /* 256bit */ + set_bit(3, cpu->sve_vq_supported); /* 512bit */ + + /* TODO: Add A64FX specific HPC extension registers */ +} + static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, }; =20 --=20 2.27.0 From nobody Thu May 9 00:06:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630312370210653.2335439367121; Mon, 30 Aug 2021 01:32:50 -0700 (PDT) Received: from localhost ([::1]:37276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mKcil-0003JD-V5 for importer@patchew.org; Mon, 30 Aug 2021 04:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKcef-0005jA-Lj; Mon, 30 Aug 2021 04:28:33 -0400 Received: from esa8.hc1455-7.c3s2.iphmx.com ([139.138.61.253]:46844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKced-0000sm-VV; Mon, 30 Aug 2021 04:28:33 -0400 Received: from unknown (HELO yto-r3.gw.nic.fujitsu.com) ([218.44.52.219]) by esa8.hc1455-7.c3s2.iphmx.com with ESMTP; 30 Aug 2021 17:28:28 +0900 Received: from yto-m2.gw.nic.fujitsu.com (yto-nat-yto-m2.gw.nic.fujitsu.com [192.168.83.65]) by yto-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 91D606DAAA; Mon, 30 Aug 2021 17:28:27 +0900 (JST) Received: from yto-om2.fujitsu.com (yto-om2.o.css.fujitsu.com [10.128.89.163]) by yto-m2.gw.nic.fujitsu.com (Postfix) with ESMTP id D1DEDC5545; Mon, 30 Aug 2021 17:28:26 +0900 (JST) Received: from localhost.localdomain (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om2.fujitsu.com (Postfix) with ESMTP id A8B444006D7E3; Mon, 30 Aug 2021 17:28:26 +0900 (JST) IronPort-SDR: QkU9eZXq4F8Uty1t7g7M/Fq6w6zxCUSZV+wQDZK+aaklBSH9fQoxlCxyXoDmap+ZZuaYuMRilw qOXojqBj+piyp9Al+tsrff/+UR90qOnKt1vKq+pAytU6Dv47cS5pv+D4dDPS+bzwbu4OurYuX9 KRwIheKuNbPzHk/DMzFrgO2sAectJn4YV0ROfeQjCT+tFpOksAhTs8imzPsY3xsWAsQo0J37t3 Moc/BlBz4AnQuG9G0eTmEzkzRNedJvakNfCNylWkC9/vIH47p7fT1qW7G835FAkJh1psJauJGN kfeJ2wMkBmxF4mWbVIvCxcgl X-IronPort-AV: E=McAfee;i="6200,9189,10091"; a="30216397" X-IronPort-AV: E=Sophos;i="5.84,362,1620658800"; d="scan'208";a="30216397" From: Shuuichirou Ishii To: peter.maydell@linaro.org, drjones@redhat.com, qemu-arm@nongnu.org Subject: [PATCH v5 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Date: Mon, 30 Aug 2021 17:28:19 +0900 Message-Id: <20210830082820.2690275-3-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> References: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=139.138.61.253; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa8.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_NEUTRAL=0.779 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630312371050100001 Content-Type: text/plain; charset="utf-8" Add -cpu a64fx to use A64FX processor when -machine virt option is specifie= d. In addition, add a64fx to the Supported guest CPU types in the virt.rst doc= ument. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 59acf0eeaf..850787495b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 86c8a4ca3d..3fa4295a78 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -200,6 +200,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; --=20 2.27.0 From nobody Thu May 9 00:06:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630312189201836.4777389945887; Mon, 30 Aug 2021 01:29:49 -0700 (PDT) Received: from localhost ([::1]:60254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mKcfr-0007zj-Tx for importer@patchew.org; Mon, 30 Aug 2021 04:29:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKcef-0005jE-Sy; Mon, 30 Aug 2021 04:28:33 -0400 Received: from esa1.hc1455-7.c3s2.iphmx.com ([207.54.90.47]:41725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mKcee-0000u2-CY; Mon, 30 Aug 2021 04:28:33 -0400 Received: from unknown (HELO oym-r2.gw.nic.fujitsu.com) ([210.162.30.90]) by esa1.hc1455-7.c3s2.iphmx.com with ESMTP; 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d="scan'208";a="42326706" From: Shuuichirou Ishii To: peter.maydell@linaro.org, drjones@redhat.com, qemu-arm@nongnu.org Subject: [PATCH v5 3/3] tests/arm-cpu-features: Add A64FX processor related Date: Mon, 30 Aug 2021 17:28:20 +0900 Message-Id: <20210830082820.2690275-4-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> References: <20210830082820.2690275-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.54.90.47; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa1.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630312191114100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones --- tests/qtest/arm-cpu-features.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..90a87f0ea9 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -473,6 +473,19 @@ static void test_query_cpu_model_expansion(const void = *data) assert_has_feature_enabled(qts, "cortex-a57", "pmu"); assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); =20 + assert_has_feature_enabled(qts, "a64fx", "pmu"); + assert_has_feature_enabled(qts, "a64fx", "aarch64"); + /* + * A64FX does not support any other vector lengths besides those + * that are enabled by default(128bit, 256bits, 512bit). + */ + assert_has_feature_enabled(qts, "a64fx", "sve"); + assert_sve_vls(qts, "a64fx", 0xb, NULL); + assert_error(qts, "a64fx", "cannot enable sve384", + "{ 'sve384': true }"); + assert_error(qts, "a64fx", "cannot enable sve640", + "{ 'sve640': true }"); + sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 --=20 2.27.0