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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id d4sm3934597wrz.35.2021.08.26.11.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 11:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1630001232; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6hV9/zziKNEk7s6VzPpMvb9Nml78ruzqt2otDpuWxAs=; b=Fphm2E3hYa0fm+7iLKIYsSMfPy//etaAbmp9wg87lGE3iko+iLcg18SkKh1q+flxKJwtRj D2NZs8GJ+/RRfuheXq9qF+9fRgqrBkaO34seXa+N2eTAsBuuVw/v77Ud7ftYRmotEYvMq2 lsYx+edOTKpm8mVXjFqwh2/f/FPOzzo= X-MC-Unique: 9d1A2ozPPFOcbv2mEkx7OQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6hV9/zziKNEk7s6VzPpMvb9Nml78ruzqt2otDpuWxAs=; b=pdAasDGR4MZUgBnLjNPYJckOgC/WJwVHWMw+xthGkypLaVGHFRt4MYLPhpWsnVmLm1 /KDJLYCq7aNxp2SY5X8ajP04wLpFtdLui0F8e53mwXk7ykEUP7Jwb34rsnAJHd/9V7ZY lqrcSv559E91GCUPZl0NUMU/ABaDmUezXy6vjjXI0VLgZPtHUfaQhxMPcPunBRrgWR0P y0Bb7FZIIpOJ0NB1qK2odHEEtqiT0K8Rpa0KewpLZcN67IpvtOSIwYHYo/FUYoVM0sAM LAqLN48+bNS/4vE6d6BOkYHqgiiRMdGpzQbL3crrMrjn02eB6Q8TFHgBCg/6IKHayhhH 1d6g== X-Gm-Message-State: AOAM533LOWPlQWqhGcSgJBtLDddL6xdheTHoQMaGHtN1lQmbmt53lsMo UbBYiA3sIJKbobPandhmsiCcGXW1VM0Lp+5/iLHqQDZ89pmS0eghF06Tz+InPPkCVilURMd43LV wDiUNKSkqX7PYkw== X-Received: by 2002:a05:6000:9:: with SMTP id h9mr5812790wrx.396.1630001230295; Thu, 26 Aug 2021 11:07:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOOy+Rb53rsNo9rgQv6a5bBsB9kj5286pXqc1RTwbrNwYOjhYGGZJmt5qX2pV2bYyWzX5Stg== X-Received: by 2002:a05:6000:9:: with SMTP id h9mr5812774wrx.396.1630001230156; Thu, 26 Aug 2021 11:07:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix Date: Thu, 26 Aug 2021 20:07:03 +0200 Message-Id: <20210826180704.2131949-2-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210826180704.2131949-1-philmd@redhat.com> References: <20210826180704.2131949-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1630001279497100001 QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q' suffix for 64-bit accesses. Rename the current 'll' suffix to have the GIC dist accessors better match the rest of the codebase. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_dist.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index b65f56f9035..7e9b393d9ab 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -763,8 +763,8 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, } } =20 -static MemTxResult gicd_writell(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -779,8 +779,8 @@ static MemTxResult gicd_writell(GICv3State *s, hwaddr o= ffset, } } =20 -static MemTxResult gicd_readll(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static MemTxResult gicd_readq(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -812,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset= , uint64_t *data, r =3D gicd_readl(s, offset, data, attrs); break; case 8: - r =3D gicd_readll(s, offset, data, attrs); + r =3D gicd_readq(s, offset, data, attrs); break; default: r =3D MEMTX_ERROR; @@ -854,7 +854,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offse= t, uint64_t data, r =3D gicd_writel(s, offset, data, attrs); break; case 8: - r =3D gicd_writell(s, offset, data, attrs); + r =3D gicd_writeq(s, offset, data, attrs); break; default: r =3D MEMTX_ERROR; --=20 2.31.1 From nobody Sat Apr 27 14:55:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1630001240; cv=none; d=zohomail.com; s=zohoarc; b=Vs43Z9f0HyriKbOUqIerWz63vpG5eHm7aVt/kd6ohnem2IBTVDaxm0vfCa8M8/P0wehQdNdQHqscpiwcz4IjC7emt484PEf4Ek22zS3oD0HjAk14JbzXEfVBxFKpC6fL1bkYjv8UiNR9IgryIg6DMNvGeDwZJXc8YQm/5xSA1QU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1630001240; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=UeA6PdglE6wY86lrN/FXDAYFAzUV/D1nakMN0ezsWcU=; b=ZeVp+dD6g0efe5r/uyEQRZdbZnUYOLYannv7hsIC/7KPqHhRDPjM0wxUIx2W5PgaqCm3cY/WHMfvaVrCpo8pQJAYSEGodgkzlJTRn9Nfr+NCLpF05OKiZv3xCJk3C6qLVs1G/meyJTRgDQfdhwDIr8zCeexuD+f0GxWkasnYCOU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.zohomail.com with SMTPS id 1630001240550857.8612680279726; Thu, 26 Aug 2021 11:07:20 -0700 (PDT) Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-6-81wNZYgTN-qsImUgnQ2xHA-1; Thu, 26 Aug 2021 14:07:16 -0400 Received: by mail-wr1-f70.google.com with SMTP id t15-20020a5d42cf000000b001565f9c9ee8so1130868wrr.2 for ; Thu, 26 Aug 2021 11:07:16 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id i17sm2213101wrc.38.2021.08.26.11.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 11:07:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1630001239; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UeA6PdglE6wY86lrN/FXDAYFAzUV/D1nakMN0ezsWcU=; b=URO70r/oz9NFWCvZI7yehCFsCpIzomqCq+V6IZwKiw8Q+XxQePN3l0SicKZLLwBBs4bCxt mNSH3y832lTG45Ie6+A/IrH4zSsQp8Xv5awbRPD03zLj3MM/QfRhTv1ETD1pAr2Gl8Ae4f 8hpk74C/j4SkMax+cmnL2lw6r3nEvwc= X-MC-Unique: 81wNZYgTN-qsImUgnQ2xHA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UeA6PdglE6wY86lrN/FXDAYFAzUV/D1nakMN0ezsWcU=; b=bQbXfScdmiN0S3XNYcDVx1Y2dd0YsdN9n6XixEKnXp6onMP/AU6luzqAT1HNWnQHDb pkkNFil1tmsgHHaV5e8uj4NBhBlkgE0BHznt0pYPo1XAhH1FPXV9VhVjtPXWcbIupHdL xWVYH3+JWsOM2Q7y0rzGkP/2Lq+CWosfQfsHv/Tri4Xg1gs/D80D9mywtL0WAl/EVcDY 4g47CEJz8PSZ72oeGG/KNUnjWwNemgq3xATDTcxZvfaWKRKHHkwgX+oPAsbFbMwJG7Oy /orY/vRuEdoaiB/JkjRD39bkyjEWlwR+6OSpnJHEQJWa8RRcHfnpYStQcA3UzCphbmqC oVrg== X-Gm-Message-State: AOAM532wzjAPDoGwNI00wmS9FWmBlgWRP89bF3gyqYHUdqhNSn4Esye9 9nW8i6KeeHmX3O5tfDVfqS/uBI+Rb8kgvDdAFM2GC3yzmjpXRri3uF2LeHJm8ux4B+zHOhtjDKx nKL+nnvBHHKwc1A== X-Received: by 2002:a05:600c:4f4d:: with SMTP id m13mr15677103wmq.179.1630001235026; Thu, 26 Aug 2021 11:07:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSxsgjIyMcNJd5fPc/HZB/XWUVuBQG7XfddONL8GXi0XIjhttYnAE2RVAb/qDMCHC/EkrgUA== X-Received: by 2002:a05:600c:4f4d:: with SMTP id m13mr15677070wmq.179.1630001234595; Thu, 26 Aug 2021 11:07:14 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans Date: Thu, 26 Aug 2021 20:07:04 +0200 Message-Id: <20210826180704.2131949-3-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210826180704.2131949-1-philmd@redhat.com> References: <20210826180704.2131949-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1630001282959100001 Quoting Peter Maydell: These MEMTX_* aren't from the memory transaction API functions; they're just being used by gicd_readl() and friends as a way to indicate a success/failure so that the actual MemoryRegionOps read/write fns like gicv3_dist_read() can log a guest error. Arguably this is a bit of a misuse of the MEMTX_* constants and perhaps we should have gicd_readl etc return a bool instead. Follow his suggestion and replace the MEMTX_* constants by boolean values, simplifying a bit the gicv3_dist_read() / gicv3_dist_write() handlers. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_dist.c | 201 +++++++++++++++++++++------------------ 1 file changed, 106 insertions(+), 95 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 7e9b393d9ab..5beb7c4235a 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -262,8 +262,21 @@ static void gicd_write_irouter(GICv3State *s, MemTxAtt= rs attrs, int irq, gicv3_update(s, irq, 1); } =20 -static MemTxResult gicd_readb(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +/** + * gicd_readb + * gicd_readw + * gicd_readl + * gicd_readq + * gicd_writeb + * gicd_writew + * gicd_writel + * gicd_writeq + * + * Return %true if the operation succeeded, %false otherwise. + */ + +static bool gicd_readb(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Most GICv3 distributor registers do not support byte accesses. */ switch (offset) { @@ -273,17 +286,17 @@ static MemTxResult gicd_readb(GICv3State *s, hwaddr o= ffset, /* This GIC implementation always has affinity routing enabled, * so these registers are all RAZ/WI. */ - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: *data =3D gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writeb(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writeb(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Most GICv3 distributor registers do not support byte accesses. */ switch (offset) { @@ -293,25 +306,25 @@ static MemTxResult gicd_writeb(GICv3State *s, hwaddr = offset, /* This GIC implementation always has affinity routing enabled, * so these registers are all RAZ/WI. */ - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int irq =3D offset - GICD_IPRIORITYR; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } gicd_write_ipriorityr(s, attrs, irq, value); gicv3_update(s, irq, 1); - return MEMTX_OK; + return true; } default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_readw(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readw(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETS= PI_NSR * support 16 bit accesses, and those registers are all part of the @@ -319,11 +332,11 @@ static MemTxResult gicd_readw(GICv3State *s, hwaddr o= ffset, * implement (ie for us GICD_TYPER.MBIS =3D=3D 0), so for us they are * reserved. */ - return MEMTX_ERROR; + return false; } =20 -static MemTxResult gicd_writew(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writew(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETS= PI_NSR * support 16 bit accesses, and those registers are all part of the @@ -331,11 +344,11 @@ static MemTxResult gicd_writew(GICv3State *s, hwaddr = offset, * implement (ie for us GICD_TYPER.MBIS =3D=3D 0), so for us they are * reserved. */ - return MEMTX_ERROR; + return false; } =20 -static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readl(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Almost all GICv3 distributor registers are 32-bit. * Note that WO registers must return an UNKNOWN value on reads, @@ -363,7 +376,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, } else { *data =3D s->gicd_ctlr; } - return MEMTX_OK; + return true; case GICD_TYPER: { /* For this implementation: @@ -387,61 +400,61 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, =20 *data =3D (1 << 25) | (1 << 24) | (sec_extn << 10) | (0xf << 19) | itlinesnumber; - return MEMTX_OK; + return true; } case GICD_IIDR: /* We claim to be an ARM r0p0 with a zero ProductID. * This is the same as an r0p0 GIC-500. */ *data =3D gicv3_iidr(); - return MEMTX_OK; + return true; case GICD_STATUSR: /* RAZ/WI for us (this is an optional register and our implementat= ion * does not track RO/WO/reserved violations to report them to the = guest) */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: { int irq; =20 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { *data =3D 0; - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGROUPR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } *data =3D *gic_bmp_ptr32(s->group, irq); - return MEMTX_OK; + return true; } case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ISENABLER); - return MEMTX_OK; + return true; case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ICENABLER); - return MEMTX_OK; + return true; case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge= 1, offset - GICD_ISPENDR); - return MEMTX_OK; + return true; case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge= 2, offset - GICD_ICPENDR); - return MEMTX_OK; + return true; case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, offset - GICD_ISACTIVER); - return MEMTX_OK; + return true; case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: *data =3D gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, offset - GICD_ICACTIVER); - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int i, irq =3D offset - GICD_IPRIORITYR; @@ -452,12 +465,12 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, value |=3D gicd_read_ipriorityr(s, attrs, i); } *data =3D value; - return MEMTX_OK; + return true; } case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: /* RAZ/WI since affinity routing is always enabled */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_ICFGR ... GICD_ICFGR + 0xff: { /* Here only the even bits are used; odd bits are RES0 */ @@ -466,7 +479,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } =20 /* Since our edge_trigger bitmap is one bit per irq, we only need @@ -478,7 +491,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, value =3D extract32(value, (irq & 0x1f) ? 16 : 0, 16); value =3D half_shuffle32(value) << 1; *data =3D value; - return MEMTX_OK; + return true; } case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: { @@ -489,16 +502,16 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, * security enabled and this is an NS access */ *data =3D 0; - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGRPMODR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } *data =3D *gic_bmp_ptr32(s->grpmod, irq); - return MEMTX_OK; + return true; } case GICD_NSACR ... GICD_NSACR + 0xff: { @@ -507,7 +520,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { *data =3D 0; - return MEMTX_OK; + return true; } =20 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { @@ -515,17 +528,17 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, * security enabled and this is an NS access */ *data =3D 0; - return MEMTX_OK; + return true; } =20 *data =3D s->gicd_nsacr[irq / 16]; - return MEMTX_OK; + return true; } case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: /* RAZ/WI since affinity routing is always enabled */ *data =3D 0; - return MEMTX_OK; + return true; case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: { uint64_t r; @@ -537,26 +550,26 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr o= ffset, } else { *data =3D (uint32_t)r; } - return MEMTX_OK; + return true; } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ *data =3D gicv3_idreg(offset - GICD_IDREGS); - return MEMTX_OK; + return true; case GICD_SGIR: /* WO registers, return unknown value */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read from WO register at offset " TARGET_FMT_plx "\n", __func__, offset); *data =3D 0; - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writel(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Almost all GICv3 distributor registers are 32-bit. Note that * RO registers must ignore writes, not abort. @@ -600,68 +613,68 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, s->gicd_ctlr &=3D ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); } gicv3_full_update(s); - return MEMTX_OK; + return true; } case GICD_STATUSR: /* RAZ/WI for our implementation */ - return MEMTX_OK; + return true; case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: { int irq; =20 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGROUPR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } *gic_bmp_ptr32(s->group, irq) =3D value; gicv3_update(s, irq, 32); - return MEMTX_OK; + return true; } case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ISENABLER, value); - return MEMTX_OK; + return true; case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, offset - GICD_ICENABLER, value); - return MEMTX_OK; + return true; case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, offset - GICD_ISPENDR, value); - return MEMTX_OK; + return true; case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, offset - GICD_ICPENDR, value); - return MEMTX_OK; + return true; case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, offset - GICD_ISACTIVER, value); - return MEMTX_OK; + return true; case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, offset - GICD_ICACTIVER, value); - return MEMTX_OK; + return true; case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: { int i, irq =3D offset - GICD_IPRIORITYR; =20 if (irq < GIC_INTERNAL || irq + 3 >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 for (i =3D irq; i < irq + 4; i++, value >>=3D 8) { gicd_write_ipriorityr(s, attrs, i, value); } gicv3_update(s, irq, 4); - return MEMTX_OK; + return true; } case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: /* RAZ/WI since affinity routing is always enabled */ - return MEMTX_OK; + return true; case GICD_ICFGR ... GICD_ICFGR + 0xff: { /* Here only the odd bits are used; even bits are RES0 */ @@ -669,7 +682,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, uint32_t mask, oldval; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 /* Since our edge_trigger bitmap is one bit per irq, our input @@ -687,7 +700,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr of= fset, oldval =3D *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); value =3D (oldval & ~mask) | (value & mask); *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) =3D value; - return MEMTX_OK; + return true; } case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: { @@ -697,16 +710,16 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, /* RAZ/WI if security disabled, or if * security enabled and this is an NS access */ - return MEMTX_OK; + return true; } /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ irq =3D (offset - GICD_IGRPMODR) * 8; if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } *gic_bmp_ptr32(s->grpmod, irq) =3D value; gicv3_update(s, irq, 32); - return MEMTX_OK; + return true; } case GICD_NSACR ... GICD_NSACR + 0xff: { @@ -714,41 +727,41 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, int irq =3D (offset - GICD_NSACR) * 4; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { /* RAZ/WI if security disabled, or if * security enabled and this is an NS access */ - return MEMTX_OK; + return true; } =20 s->gicd_nsacr[irq / 16] =3D value; /* No update required as this only affects access permission check= s */ - return MEMTX_OK; + return true; } case GICD_SGIR: /* RES0 if affinity routing is enabled */ - return MEMTX_OK; + return true; case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: /* RAZ/WI since affinity routing is always enabled */ - return MEMTX_OK; + return true; case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: { uint64_t r; int irq =3D (offset - GICD_IROUTER) / 8; =20 if (irq < GIC_INTERNAL || irq >=3D s->num_irq) { - return MEMTX_OK; + return true; } =20 /* Write half of the 64-bit register */ r =3D gicd_read_irouter(s, attrs, irq); r =3D deposit64(r, (offset & 7) ? 32 : 0, 32, value); gicd_write_irouter(s, attrs, irq, r); - return MEMTX_OK; + return true; } case GICD_IDREGS ... GICD_IDREGS + 0x2f: case GICD_TYPER: @@ -757,14 +770,14 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr = offset, qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " TARGET_FMT_plx "\n", __func__, offset); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset, - uint64_t value, MemTxAttrs attrs) +static bool gicd_writeq(GICv3State *s, hwaddr offset, + uint64_t value, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -773,14 +786,14 @@ static MemTxResult gicd_writeq(GICv3State *s, hwaddr = offset, case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: irq =3D (offset - GICD_IROUTER) / 8; gicd_write_irouter(s, attrs, irq, value); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 -static MemTxResult gicd_readq(GICv3State *s, hwaddr offset, - uint64_t *data, MemTxAttrs attrs) +static bool gicd_readq(GICv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) { /* Our only 64-bit registers are GICD_IROUTER */ int irq; @@ -789,9 +802,9 @@ static MemTxResult gicd_readq(GICv3State *s, hwaddr off= set, case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: irq =3D (offset - GICD_IROUTER) / 8; *data =3D gicd_read_irouter(s, attrs, irq); - return MEMTX_OK; + return true; default: - return MEMTX_ERROR; + return false; } } =20 @@ -799,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset= , uint64_t *data, unsigned size, MemTxAttrs attrs) { GICv3State *s =3D (GICv3State *)opaque; - MemTxResult r; + bool r; =20 switch (size) { case 1: @@ -815,11 +828,11 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offs= et, uint64_t *data, r =3D gicd_readq(s, offset, data, attrs); break; default: - r =3D MEMTX_ERROR; + r =3D false; break; } =20 - if (r =3D=3D MEMTX_ERROR) { + if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); @@ -829,19 +842,18 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offs= et, uint64_t *data, * trigger the guest-error logging but don't return it to * the caller, or we'll cause a spurious guest data abort. */ - r =3D MEMTX_OK; *data =3D 0; } else { trace_gicv3_dist_read(offset, *data, size, attrs.secure); } - return r; + return MEMTX_OK; } =20 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) { GICv3State *s =3D (GICv3State *)opaque; - MemTxResult r; + bool r; =20 switch (size) { case 1: @@ -857,11 +869,11 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr off= set, uint64_t data, r =3D gicd_writeq(s, offset, data, attrs); break; default: - r =3D MEMTX_ERROR; + r =3D false; break; } =20 - if (r =3D=3D MEMTX_ERROR) { + if (!r) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); @@ -871,11 +883,10 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr off= set, uint64_t data, * trigger the guest-error logging but don't return it to * the caller, or we'll cause a spurious guest data abort. */ - r =3D MEMTX_OK; } else { trace_gicv3_dist_write(offset, data, size, attrs.secure); } - return r; + return MEMTX_OK; } =20 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) --=20 2.31.1