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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PuYwv7IQju2UavvbdJU5w8adZg7ikn6rO+blWY/QnVE=; b=KitbIkLzpunuiB/OC3v5pDTWcSHD9+lkygwzUC8Dxont/8jbEgSmAOIWAOwpA6+FTN U65H6NOX2OPljLzYQ6WxL3hB2Q7rdA/roKamIgEzzmlJ4UAPmN6YVFl8rCZYBor2QzOu /1CZYQ2DEsYqyiQQaTAK53bKB3kRFLrCqipee/g0biJ3AieoyxezdYJ69/dv+bSvFRtO cyHAmrGq2m4jsGVK0GpY4e9znAj5lVAI+FJPX4ZoK09PtiHq6g+VHQKKUwmhGHWg9eD2 Rj/SbUb2yJl8qPGtFsflgJbKxt1hPado67QMQ+WTKaRjAQJSgX3fumlUp5tc0OD7n5ct VXIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PuYwv7IQju2UavvbdJU5w8adZg7ikn6rO+blWY/QnVE=; b=ZdMm1IkVi4jTJDu/a2cuGG4QIGQeLRfZhrUtlBNHWVo7IoU4mUuGB8i5LLsCYWpWzf qYZr/HtOlITCZKZm3VeKMYnhwBEBh2Q4D6LkJx9iNjHRW3tmQ7yugImzN5MlQsSZKeB4 /Y1p/gv+AnT2VoI4DS0mbE4tbhiUxGZQy+KXDzedW/7Be31gfmbVBpdZxdNeLFMeoJaw 9424XnuLK0YkbKj++Xaqwob2QxkXjUVq1oFzRXOp6fmlU9rEkJbgO4nFLIE1A9pA4qHZ WVNBUQ6emBkGOw4EKW8M+ZwlzD5WFgYtLNjHpv+p7ZKa8GPzowXjQMMHtBZEZ/ZdFeC6 sqgw== X-Gm-Message-State: AOAM532OZf9t59FR+dTdb35HOpSitCmd3YHA9c/5DSCcF32LitgTkUQY PG/w3qw7SMLdpil59lu4+J1Bvxk1YMB/ag== X-Google-Smtp-Source: ABdhPJz1/buW42MU2mKFMic9/L1gXfxyPB/El/nREG9KNiPd2lE5jpiAyw3m921ko0bsGCu6csKzYQ== X-Received: by 2002:a5d:5447:: with SMTP id w7mr3958082wrv.137.1629983860768; Thu, 26 Aug 2021 06:17:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/18] target/arm: Implement MVE VCVT between single and half precision Date: Thu, 26 Aug 2021 14:17:23 +0100 Message-Id: <20210826131725.22449-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985934343100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT instruction which converts between single and half precision floating point. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: make do_vcvt_sh/do_vcvt_hs functions, not macros --- target/arm/helper-mve.h | 5 +++ target/arm/mve.decode | 8 ++++ target/arm/mve_helper.c | 81 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 14 +++++++ 4 files changed, 108 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6d4052a5269..f6345c7abbe 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -182,6 +182,11 @@ DEF_HELPER_FLAGS_4(mve_vcvt_rm_uh, TCG_CALL_NO_WG, voi= d, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_rm_ss, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(mve_vcvt_rm_us, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) =20 +DEF_HELPER_FLAGS_3(mve_vcvtb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtb_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 410ea746fcf..32de4af3170 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -221,6 +221,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op # The VSHLL T2 encoding is not a @2op pattern, but is here because it # overlaps what would be size=3D0b11 VMULH/VRMULH { + VCVTB_SH 111 0 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_nosz + VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma = size=3D2 =20 VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -235,6 +237,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTB_HS 111 1 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_no= sz + VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 =20 VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -247,6 +251,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_SH 111 0 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D2 VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h @@ -260,6 +266,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_HS 111 1 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a793199fbee..1ed76ac5ed8 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3332,3 +3332,84 @@ DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_to= shh) DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) + +/* + * VCVT between halfprec and singleprec. As usual for halfprec + * conversions, FZ16 is ignored and AHP is observed. + */ +static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) +{ + uint16_t *d =3D vd; + uint32_t *m =3D vm; + uint16_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fz =3D get_flush_to_zero(base_fpst); + set_flush_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & 1)) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float32_to_float16(m[H4(e)], ieee, fpst); + mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); + } + set_flush_to_zero(old_fz, base_fpst); + mve_advance_vpt(env); +} + +static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) +{ + uint32_t *d =3D vd; + uint16_t *m =3D vm; + uint32_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fiz =3D get_flush_inputs_to_zero(base_fpst); + set_flush_inputs_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & (1 << (top * 2)))) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); + mergemask(&d[H4(e)], r, mask); + } + set_flush_inputs_to_zero(old_fiz, base_fpst); + mve_advance_vpt(env); +} + +void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 1); +} +void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 1); +} diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e80a55eb62e..194ef99cc74 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -627,6 +627,20 @@ DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) =20 +#define DO_VCVT_SH(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, gen_helper_mve_##FN); \ + } \ + +DO_VCVT_SH(VCVTB_SH, vcvtb_sh) +DO_VCVT_SH(VCVTT_SH, vcvtt_sh) +DO_VCVT_SH(VCVTB_HS, vcvtb_hs) +DO_VCVT_SH(VCVTT_HS, vcvtt_hs) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1