From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984363; cv=none; d=zohomail.com; s=zohoarc; b=FBvRq+hy2YGMx16EB55KJlFHY/dCHCNWwYkRP1A2jcHTg6W8Npg9rGi5WexrzIRaWfTQhudDgCb1f9zotm92+J7eT/cYk/q+KQ/VPJrwxao3MuzfLWgWgs0WcRICxuTH4LUpeOGs3royjPGYfwe7mntX57GKb2OEWRkIj/owaBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984363; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p1XI+jRVlOTUm8Ez3cTwjjeA2El6WaD6xfoJn4dKlxk=; b=W9OZwJm6xm0A+ecDIkbzWqaGsKePsgOPtYeUT/e+c5jkqt3Zt5T5QOCN6NvOTOy0S6Us3BPNHvSysOCBbYnb5MtlmwH6V8vkInAlJB3ORja/jerbqw6SQ3sSkBhoDBSFm+DkgoOCQCVFspIOkVmLCEJHXg8ESJJmRX5lV67nN6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984363068747.8399714735106; Thu, 26 Aug 2021 06:26:03 -0700 (PDT) Received: from localhost ([::1]:47452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFOM-0005BC-0h for importer@patchew.org; Thu, 26 Aug 2021 09:26:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFG9-0005ga-MJ for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:33 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:50959) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFG6-0004u5-5B for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:33 -0400 Received: by mail-wm1-x335.google.com with SMTP id m2so1859992wmm.0 for ; Thu, 26 Aug 2021 06:17:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=p1XI+jRVlOTUm8Ez3cTwjjeA2El6WaD6xfoJn4dKlxk=; b=HIiXYpfRAQxwLaCFZiy5T3qfkLXsWljTEvA9SBoqEyhTd52D3VOK0DLKI3VA9d5xeb 7jn1w+fwnLUmcphFRo7ukZ7URFkvT0sa3d3Dx3LsgQZyZ0/0W6f5gDkZDIi+5W2/qqUd JjDsv2KoVtzzQtFRGNvfSWgzh/ZpQo1nKW54bt6chyl/7lb7ooElAnnYPuiGqWL3T7cf Qkpa4XZu15rJ3k6mfCdrH3sV0ahRWqSRDCU6Oe4DfnZGeEPpFeiGfK757COtmbOK+hEW 0/n3GCkS7zlg2DeZxFe7mX+0o3uc7g0ZXI68Rq6geqzUDE8anZrtJkIEU/tZiC3/iqeZ sm+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p1XI+jRVlOTUm8Ez3cTwjjeA2El6WaD6xfoJn4dKlxk=; b=W5BSX3XkrytSRjXRpvXhA0AdB67+teLEOFA36lqdY1GQmaqro1J4YNcGa9TF5DIlP8 ohDHLN/0gRmrXujhNHdY2ZRNNEo1XlswEQzvIbAqS+H1CXAW+Nz9wKi9PWO+D3VvoM+l oeMOyuK+XyX67yqd6Kqaxg2hvPDE+waKbIIHQ45w+vmWdlHEEII8zGgz31UBI/nWVRPk FyX3aJV+RjP4rcAci5388Ru3pIJcBDx94QfmjlpgLQJSZj9QjhajNcn22H4MloyApbcx i3H3Yh5z3BHMjKs+kbOjz3cIljwZr2r6P1q2opQ80gIZQ7Fnw2U0pFjZvciLTqI497dr Zi4g== X-Gm-Message-State: AOAM533MwCYvakwvTV2c4GjosKd1+w3iJ8qfEBYsFe+HLds4E14MQp9f TWAFFPLZLQrxm5BNpRkxfj6YMA== X-Google-Smtp-Source: ABdhPJwklQsEVX5dviUPf7Mx7z7pV+7RweDrC/G81MVorxMRiZRAeJBpVij32WLcbrC/czOhDVJjyw== X-Received: by 2002:a7b:cb89:: with SMTP id m9mr14380404wmi.123.1629983848532; Thu, 26 Aug 2021 06:17:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/18] target/arm: Implement MVE VADD (floating-point) Date: Thu, 26 Aug 2021 14:17:08 +0100 Message-Id: <20210826131725.22449-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985625881100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use float16/float32 type; add DO_2OP_FP_ALL macro to invoke DO_2OP_FP for both float16 and float32 --- target/arm/helper-mve.h | 3 +++ target/arm/translate.h | 6 ++++++ target/arm/mve.decode | 10 ++++++++++ target/arm/mve_helper.c | 40 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 17 ++++++++++++++++ target/arm/translate-neon.c | 6 ------ 6 files changed, 76 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 3db9b15f121..32fd2e1f9be 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -410,6 +410,9 @@ DEF_HELPER_FLAGS_4(mve_vhcadd270b, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vhcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) =20 +DEF_HELPER_FLAGS_4(mve_vfaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfadds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 241596c5bda..8636c20c3b4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -181,6 +181,12 @@ static inline int rsub_8(DisasContext *s, int x) return 8 - x; } =20 +static inline int neon_3same_fp_size(DisasContext *s, int x) +{ + /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ + return MO_32 - x; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 87446816293..e211cb016c6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -26,6 +26,10 @@ # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit %size_28 28:1 !function=3Dplus_1 =20 +# 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit, +# like Neon FP insns. +%2op_fp_size 20:1 !function=3Dneon_3same_fp_size + # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 =20 @@ -118,6 +122,9 @@ =20 @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 +@2op_fp .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -615,3 +622,6 @@ VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1= 0 0 .... @vcmp_scalar VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar + +# 2-operand FP +VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c2826eb5f9f..abca7c0b2ab 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" +#include "fpu/softfloat.h" =20 static uint16_t mve_eci_mask(CPUARMState *env) { @@ -2798,3 +2799,42 @@ DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) + +/* + * 2-operand floating point. Note that if an element is partially + * predicated we must do the FP operation to update the non-predicated + * bytes, but we must be careful to avoid updating the FP exception + * state unless byte 0 of the element was unpredicated. + */ +#define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_2OP_FP_ALL(OP, FN) \ + DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ + DO_2OP_FP(OP##s, 4, float32, float32_##FN) + +DO_2OP_FP_ALL(vfadd, add) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 78229c44c68..d2c40ede564 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -831,6 +831,23 @@ static bool trans_VSBCI(DisasContext *s, arg_2op *a) return do_2op(s, a, gen_helper_mve_vsbci); } =20 +#define DO_2OP_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ + { \ + static MVEGenTwoOpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2op(s, a, fns[a->size]); \ + } + +DO_2OP_FP(VADD_fp, vfadd) + static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) { diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index c53ab20fa48..dd43de558e4 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -28,12 +28,6 @@ #include "translate.h" #include "translate-a32.h" =20 -static inline int neon_3same_fp_size(DisasContext *s, int x) -{ - /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ - return MO_32 - x; -} - /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984529; cv=none; d=zohomail.com; s=zohoarc; b=DF4GTNUH8D63w9dfyDTjBX/zjjdi1L3oxb0f8sGEIsDq3CW3XCyXEHxcjDO5O9JjSGWywn5ECBR9MsjR5ERyLkarawyIvKwZejBl180qfcBQAeAGzSEaQ6MRz1TsahwHwNk+lgMECTmmARWDW4Y9yYg1cZS1i5WooTGU8LrLkiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984529; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i35Lsr/dn1GODrzYN0U582ydyfLQGp/hvCXCCo2NUrA=; b=T7WRFpz+qFYInIDS1iEY5HzZGX9txSpdEqhuzVPXfDQVJ6Uya4G7G1xl67IHJFX7TZjyeOPQdHtYrZ6+eOjkYyuE15g6/VpoifaNsVtke2WEVJHIf48plF+TIlOCtZV+oZWVSeoKvnejMocXD7nAgW8LmUEX9H88JpYUw1ef/5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984529198244.42742686541328; Thu, 26 Aug 2021 06:28:49 -0700 (PDT) Received: from localhost ([::1]:55118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFR1-0002Ec-Nc for importer@patchew.org; Thu, 26 Aug 2021 09:28:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFG9-0005h9-TC for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:33 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFG6-0004uq-SA for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:33 -0400 Received: by mail-wr1-x435.google.com with SMTP id h4so5015796wro.7 for ; Thu, 26 Aug 2021 06:17:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=i35Lsr/dn1GODrzYN0U582ydyfLQGp/hvCXCCo2NUrA=; b=vaNMDH3KI+7Ye0fdPLWsSE+pVz+xGjaivRVCqR2pfr73Wfy7AlQHLUJchnmy9ibp5F nGMGepYLZMAJQiqK7KD0Ac7N8VSXhUGJGrgKYlG9T9YAcXuNlbY++C0y4GjWGtV0OhYh Plw5KGG9c3MirogKm5g+NnS8epq2K+Cvojky0sVNcDZ3+2KukQgHZZPkzRz0rylZpDlf 1nFvGnBWHENDrr6YzJ6CWmFbhh314vq3UD2NXLWacqgJ0BYXz+3GRUMKi71LtOVJAmVU BqrWDsUUkc55I4uPQVu1L9khf4kkwBDzkfZ83ihAK64wVlLjmfmRrfcQmXpC0ZifMYZA nedA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i35Lsr/dn1GODrzYN0U582ydyfLQGp/hvCXCCo2NUrA=; b=ODws34BozWYbPMmCXvjay8yE5A8rWkvF5yXAycC/moD10j1wyel6IbwBkqqDp8ObYJ tK6IJsQ2tEut9yQIhPUpLsX10VDGpd/bZxBl+gA2+TKyoLnlIeQJB/XWdUgBOrhDQPuX 70y5+lVEDKYQywuWsW2G9Ukthtpbb7q86zEtdfGCYlYfi4JEfTZ3g1SdmYJUTWMMywwI WQMMDq99+DBqAo9W9J0ajYtLHRWqPhfp6tG1gqokoMIATtytm1w8mOwG35NYplIAvtYX bhIqj+QD02xERKI0sSkebTrFB0W7egeOV2D11VTK8+IcLmbykdrZb/caGAD3swicCDw6 TwAQ== X-Gm-Message-State: AOAM5322gHkTpoOEvofTd7S0AqoTK3gP4Wf+OKVB+qPJ9nWVxoFkyVZr LlKADGDa0ezr1W2gpeEukijHSg== X-Google-Smtp-Source: ABdhPJxRnUA0Bc0cnFCED3/cw2XQ4DYq6vHfqCs5SYjZcnXMd0f418BvwaQ9LRkUwefgwWgdjercIA== X-Received: by 2002:a05:6000:234:: with SMTP id l20mr3908366wrz.359.1629983849374; Thu, 26 Aug 2021 06:17:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/18] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM Date: Thu, 26 Aug 2021 14:17:09 +0100 Message-Id: <20210826131725.22449-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629984650660100001 Content-Type: text/plain; charset="utf-8" Implement more simple 2-operand floating point MVE insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use DO_2OP_FP_ALL --- target/arm/helper-mve.h | 15 +++++++++++++++ target/arm/mve.decode | 6 ++++++ target/arm/mve_helper.c | 16 ++++++++++++++++ target/arm/translate-mve.c | 5 +++++ 4 files changed, 42 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 32fd2e1f9be..370876d7934 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -413,6 +413,21 @@ DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, voi= d, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfadds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vfsubh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfsubs, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmuls, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfabdh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfabds, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmaxnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index e211cb016c6..cdbfaa4245b 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -625,3 +625,9 @@ VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1= 1 0 .... @vcmp_scalar =20 # 2-operand FP VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp +VSUB_fp 1110 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp +VMUL_fp 1111 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 1 ... 0 @2op_fp +VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp + +VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp +VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index abca7c0b2ab..d6bc686c985 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2838,3 +2838,19 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) DO_2OP_FP(OP##s, 4, float32, float32_##FN) =20 DO_2OP_FP_ALL(vfadd, add) +DO_2OP_FP_ALL(vfsub, sub) +DO_2OP_FP_ALL(vfmul, mul) + +static inline float16 float16_abd(float16 a, float16 b, float_status *s) +{ + return float16_abs(float16_sub(a, b, s)); +} + +static inline float32 float32_abd(float32 a, float32 b, float_status *s) +{ + return float32_abs(float32_sub(a, b, s)); +} + +DO_2OP_FP_ALL(vfabd, abd) +DO_2OP_FP_ALL(vmaxnm, maxnum) +DO_2OP_FP_ALL(vminnm, minnum) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d2c40ede564..98282335820 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -847,6 +847,11 @@ static bool trans_VSBCI(DisasContext *s, arg_2op *a) } =20 DO_2OP_FP(VADD_fp, vfadd) +DO_2OP_FP(VSUB_fp, vfsub) +DO_2OP_FP(VMUL_fp, vfmul) +DO_2OP_FP(VABD_fp, vfabd) +DO_2OP_FP(VMAXNM, vmaxnm) +DO_2OP_FP(VMINNM, vminnm) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eizX5mzw+zXUKyLOIS3qpwRZ3tLAja9d8BhMd5VZPjw=; b=k8RnV7iAfXdNmp3TtvIKl6N2oovDrS4tOZt2EzHxwMDosM4K64MjkG76EHptXZuqN/ jLcsj/SYmONF3fKEgiW+SV6ZU9fZEzE6vD36ouzGWVSRAs5HLwhhpzo9OehZ6HIP6xdD EvfRBdtj55CKWg9mzmsnf23pwHAgGKhHm8w1wtsLHZuPcfTGH+n8Oq3U1f/a5z2Tlv4V k0nM8ycySkuUn6a4b8s87ScmXqH/RT7EByma9UH9Qgi/vBldbUXZweCb07kJd+ML5Ws6 Prrmbye+WdC5p+116KcIsXuUqVcb4KATfInF37zHMkVgsspZyiWA00ysqzlGpz94ggok Z9nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eizX5mzw+zXUKyLOIS3qpwRZ3tLAja9d8BhMd5VZPjw=; b=sEoJBwg1KzE/8GxS5IGavOu04+YW+DxeUzWyilxmx/mHOhzKuKI+Su82slFpztIZVi v7/jFcG6hQeJBiv7YxJA0Uuis/ZexJcvIydePrTFoHUs4DiouYmLygC0mzRN0br11zB5 vP7tqMlgU/5yMIRLFWVHPWow3gvnyTq5Lrg954jeweqkOMxDyb203milcV05LD7UIb7V //+Hr41FMPzZhID8E+YN8a3vEoKaW7NH/BdGy3VrslPu+CrDm3jUoFKrZjFn4Vq2wz0W l0Hv89yxR/cvqTpW/4Wb7g7oeBcRV4gFIqis3qKMy718vdeJ0sHd30t1sEAwMoMpfYQM XFiA== X-Gm-Message-State: AOAM532DO53xqLSvkBru060AyyCoWlGFnyvyb+MapDYaPai835m1PfUq Da8+YrAH/U5aKbPxx5y63k3lItL+6D1Jdg== X-Google-Smtp-Source: ABdhPJxO93fDA5ZalivGOY0IWgF5ntqLPD0PVLhasYK/oddj0d5ofs8Kt7lWKzC9Ota+PHergx7E6Q== X-Received: by 2002:adf:edc2:: with SMTP id v2mr3907116wro.255.1629983850252; Thu, 26 Aug 2021 06:17:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/18] target/arm: Implement MVE VCADD Date: Thu, 26 Aug 2021 14:17:10 +0100 Message-Id: <20210826131725.22449-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629984501252100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz =3D=3D 1 && Qd =3D=3D Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use float16/float32 --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 8 ++++++++ target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 +++- 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 370876d7934..42eba8ea96d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -428,6 +428,12 @@ DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vfcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vfcadd270s, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index cdbfaa4245b..c728c7089ac 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -29,6 +29,8 @@ # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit, # like Neon FP insns. %2op_fp_size 20:1 !function=3Dneon_3same_fp_size +# VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit +%2op_fp_size_rev 20:1 !function=3Dplus_1 =20 # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 @@ -125,6 +127,9 @@ @2op_fp .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size =20 +@2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size_rev + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -631,3 +636,6 @@ VABD_fp 1111 1111 0 . 1 . ... 0 ... 0 1101 . = 1 . 0 ... 0 @2op_fp =20 VMAXNM 1111 1111 0 . 0 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . 1 . 1 ... 0 @2op_fp + +VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d6bc686c985..2cc8b3e11b7 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2854,3 +2854,43 @@ static inline float32 float32_abd(float32 a, float32= b, float_status *s) DO_2OP_FP_ALL(vfabd, abd) DO_2OP_FP_ALL(vmaxnm, maxnum) DO_2OP_FP_ALL(vminnm, minnum) + +#define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r[16 / ESIZE]; \ + uint16_t tm, mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + /* Calculate all results first to avoid overwriting inputs */ \ + for (e =3D 0, tm =3D mask; e < 16 / ESIZE; e++, tm >>=3D ESIZE) { = \ + if ((tm & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + r[e] =3D 0; \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(tm & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + if (!(e & 1)) { \ + r[e] =3D FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ + } else { \ + r[e] =3D FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ + } \ + } \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + mergemask(&d[H##ESIZE(e)], r[e], mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) +DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) +DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) +DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 98282335820..6203e3ff916 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -852,6 +852,8 @@ DO_2OP_FP(VMUL_fp, vfmul) DO_2OP_FP(VABD_fp, vfabd) DO_2OP_FP(VMAXNM, vmaxnm) DO_2OP_FP(VMINNM, vminnm) +DO_2OP_FP(VCADD90_fp, vfcadd90) +DO_2OP_FP(VCADD270_fp, vfcadd270) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) @@ -883,7 +885,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar = *a, return true; } =20 -#define DO_2OP_SCALAR(INSN, FN) \ +#define DO_2OP_SCALAR(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ { \ static MVEGenTwoOpScalarFn * const fns[] =3D { \ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984190; cv=none; d=zohomail.com; s=zohoarc; b=SYbBNxZKxvkiN3Qi133eq4DXR8oxRm3FsbrxRzXsFRWbJq8CSXdOEgdOf2w1Rgwz4lTqQIYl9c5R9rvfdxZeQPxWcRZQKWgwBlecLmJIp02SyG9RVSLmfUn+XmEpyy7xs9n100Mgxp/pxTG7+G+yMbuFLRZuyRWhnjzIuk0OWGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984190; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ItEzC5PA3uc2UUoeZfT2CHL8fSkv/wfJCEM2696skY0=; b=UgaumTAJ2ww8dfBO36cphG9QUUBdaF5zqSiRrIP4zmMULsBhS4I0EBtB71KSlZzXuGCge68jH5zogapVJKVyYkM9YL3krX6vxdkZH09Hhh6rIf7W9oAZc1JhddGOzsEmW7mzkD2k1cc4mv+6ajBG643xIVun+6U977vwz6rbzIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984190261749.6480226586618; Thu, 26 Aug 2021 06:23:10 -0700 (PDT) Received: from localhost ([::1]:38604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFLZ-00074P-5x for importer@patchew.org; Thu, 26 Aug 2021 09:23:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGA-0005jD-Mb for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:34 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:38735) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFG8-0004vu-F9 for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:34 -0400 Received: by mail-wr1-x436.google.com with SMTP id u16so5038392wrn.5 for ; Thu, 26 Aug 2021 06:17:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ItEzC5PA3uc2UUoeZfT2CHL8fSkv/wfJCEM2696skY0=; b=d5rwnW0Jtiiss2d88+P1m6eJeqQflMA6ZAo317ji7ST9S6bdcyRSKYsHkGk/j3oQu3 k89/KAkQvRT6XZLMpVA7TLFxs3knOoDov9HcvdYdF4uoPoVpyBMckqT6WQj9rnNafX93 PgH6oguH9xy6lUhjzBiReWQn1/bK6dSjtE4SKff3RXIB1qMMwPQU3bjARvBWBlPQ0ZID Or2LQnppD27LgjFfeBShbet8auxknKtiJh7bqTUL4yRn1dFozqglsYUUEzTrVv0BWhud MDYVPIsC3PrR+TpwFLX0608oUnXiLtZODui/0JOEcecajNBu+yISxQWTNg4Xy0hMcAut xucw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ItEzC5PA3uc2UUoeZfT2CHL8fSkv/wfJCEM2696skY0=; b=k3vy2Vi2YzvblADnVPAKqgtjGOBIAEALYJ8DYDdI2kYTnmlaBeAptpBkpt7TKCalsl XpSKQlez9+OuTfSh4W/Sbouz1PB2DVsQZ3TeNmb1HbmapVK4BnDERdGRJ8S/8nN5/txS uo2FDnHx0/nMFre82LynRvsB7NaOZUCW+JrJsJuH3ZPT28sJB/iHop+Uj2Zqg92hjPn8 n5Bp+rDkVJrlr7Vj/utn0YoitvUlf6V5UR5JfR1GvlDcU+TBy69OWijRVPrjN6pzbmoB DHSPO+LWvB13mD9nMA29g1Kln8oTKe7mvmkCL11Mxp3Z8QFD6mch7JezjNQ+jPx3WA0V PdjA== X-Gm-Message-State: AOAM533T9qlL9fwEBxOwgMCE46CXUh1vuHE/7qdyGjwR3y5U1xKz2zNY lyVY/3aYhjDro1B2cNf4ARQa+A== X-Google-Smtp-Source: ABdhPJy7d3Yp/j3PoUotITNHVrYYZRnRgkzd2cdEsoyAwS6ETvSx4ITjF4QbU4lDuu8nLLX9XxwRWQ== X-Received: by 2002:adf:b7c1:: with SMTP id t1mr4006068wre.387.1629983851038; Thu, 26 Aug 2021 06:17:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/18] target/arm: Implement MVE VFMA and VFMS Date: Thu, 26 Aug 2021 14:17:11 +0100 Message-Id: <20210826131725.22449-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985526204100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VFMA and VFMS insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use float16/float32 types; pass CHS bool to DO_VFMA rather than fn macro, as suggested by rth --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 48 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 42eba8ea96d..c230610d25c 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -434,6 +434,12 @@ DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) DEF_HELPER_FLAGS_4(mve_vfcadd270s, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) =20 +DEF_HELPER_FLAGS_4(mve_vfmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vfmsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vfmss, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c728c7089ac..3a2056f6b34 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -639,3 +639,6 @@ VMINNM 1111 1111 0 . 1 . ... 0 ... 0 1111 . = 1 . 1 ... 0 @2op_fp =20 VCADD90_fp 1111 1100 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev + +VFMA 1110 1111 0 . 0 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp +VFMS 1110 1111 0 . 1 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2cc8b3e11b7..d7f250a4455 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2894,3 +2894,40 @@ DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, floa= t16_add) DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) + +#define DO_VFMA(OP, ESIZE, TYPE, CHS) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D n[H##ESIZE(e)]; \ + if (CHS) { \ + r =3D TYPE##_chs(r); \ + } \ + r =3D TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ + 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VFMA(vfmah, 2, float16, false) +DO_VFMA(vfmas, 4, float32, false) +DO_VFMA(vfmsh, 2, float16, true) +DO_VFMA(vfmss, 4, float32, true) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6203e3ff916..d61abc6d46f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -854,6 +854,8 @@ DO_2OP_FP(VMAXNM, vmaxnm) DO_2OP_FP(VMINNM, vminnm) DO_2OP_FP(VCADD90_fp, vfcadd90) DO_2OP_FP(VCADD270_fp, vfcadd270) +DO_2OP_FP(VFMA, vfma) +DO_2OP_FP(VFMS, vfms) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984725; cv=none; d=zohomail.com; s=zohoarc; b=EU05TEDDT7pylNSukcrlWu3C1VnjLrJyiYW7blt78O5yoh3U3SW7mftVCL+k+fjJVo9Tj+gG02/SZxnI6BxnhHP0YuN2H03dxH16zhKDgWHraYv6Zu9/dYCMAmcb9WA4N5xfIrShRU09PjL9Xz9oKdtYluLBulWJA7LtEa7oOmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984725; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hXJ0uUJGqF6S2O8dTr0+fHt3Q/Gr0XXJWtw5XhCtum4=; b=NLsX5cx2YIpnLfEeSyenzy6ARtYc2k0uZFUluryjYd0A7u+gvc8zjoSSkO2KM6LlU11TE3DpvcdSGVTn0zSGbwCTlH5chGUd6bbzplsX+Wp9MZKFdVseMkzH/FM/6RsA46cg0OfHoKuD4+SP2DfGqWG66JQE/vhoBtER0frnWHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984725866598.4198081181297; Thu, 26 Aug 2021 06:32:05 -0700 (PDT) Received: from localhost ([::1]:34762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFUC-0007uG-7e for importer@patchew.org; Thu, 26 Aug 2021 09:32:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGD-0005lg-5v for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:38 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:37662) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFG9-0004xR-RQ for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:36 -0400 Received: by mail-wm1-x335.google.com with SMTP id c8-20020a7bc008000000b002e6e462e95fso6872937wmb.2 for ; Thu, 26 Aug 2021 06:17:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hXJ0uUJGqF6S2O8dTr0+fHt3Q/Gr0XXJWtw5XhCtum4=; b=aixF26TUifqN25v1jA3YhNlwzzH3Q6UU+I+78Eird3atpNEWKlvN1+M1CYpJRhCthJ rOKOc+v3q38vvoIfpdz7KhVRcJpc5A156VS4/+VOHqmhpTTujnuSgryLXdtaUiRtbTp6 i8UPxE7vopAi/FxcuZnh+87RJ29dk6PtBn/pA1WliyyrAYIh32bkvIehUCNSpECestne 2xvGJhvThbULorotzRbfGyzoFZUYRsF553F6KeldYB9dxBxuth2XM5tHV8C5COOh665E hXz2dGOBLZYMHttyDKGK8ckwxkKByVORvR63v2VjYQ4FPzav55nPr7hRskIrr7R3QWgE CRFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hXJ0uUJGqF6S2O8dTr0+fHt3Q/Gr0XXJWtw5XhCtum4=; b=N3AQFiyb/SBOM2LjQN6XdXDxrio/okHPW3dubbLx+FL1+njFl33l7nJdnUHBDUHYuP 3yWtrrSrTUjLOKsxtW428zcmeK0OH7Jvr2YqRa8iwttJVevKFu+aOWh70vTajlvWqOp9 GqlOdO3Y7DnGKWbhdaWKjwdyoWLapFfGWi8w6tBlu6Jl9rnQ/J0s/3f8XjsdXKNRFI6z YOw9vVG14TCHPvsAh+Ny3Gv3+nmW744z4OHxUT1/pfSghTykU80LgN2X2OQk2BHIr2Cj 1yENsDTOQuruIdKEZn3rXJVXBsI9gJBVU/DiZUEzZ6/GjEskTHddliWEFbl8mj+eyFgy ACqg== X-Gm-Message-State: AOAM530O2Lz+AH1fN0D+rKa/glSZ717WsYlUCjYeP2ues8ABvl7N9wsH 9Caw4KWyUSNhoYgvylk+EyGsQVXp5xKnAA== X-Google-Smtp-Source: ABdhPJxL5nfx4FhS0GRbreHHcOjeVJ7Eoj1Yn7K3cJF7CleFMEeOg8b56vmij2LE08BBOFOGguVCjg== X-Received: by 2002:a05:600c:22d3:: with SMTP id 19mr3639564wmg.36.1629983851888; Thu, 26 Aug 2021 06:17:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/18] target/arm: Implement MVE VCMUL and VCMLA Date: Thu, 26 Aug 2021 14:17:12 +0100 Message-Id: <20210826131725.22449-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629984847057100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCMUL and VCMLA insns. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use float* types, avoid passing in CHS function --- target/arm/helper-mve.h | 18 ++++++++ target/arm/mve.decode | 35 ++++++++++++---- target/arm/mve_helper.c | 86 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 8 ++++ 4 files changed, 139 insertions(+), 8 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index c230610d25c..73950403bc3 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -440,6 +440,24 @@ DEF_HELPER_FLAGS_4(mve_vfmas, TCG_CALL_NO_WG, void, en= v, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfmsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfmss, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vcmul0h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul0s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul180h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul180s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmul270s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vcmla0h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla0s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla180h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla180s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcmla270s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 3a2056f6b34..403381eef61 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -286,15 +286,29 @@ VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 .= 1 . 1 ... 0 @2op_rev VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev =20 -VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op -VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op -VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op -VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +{ + VCMUL0 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 0 @2op_sz28 + VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op + VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op +} =20 -VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op -VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op -VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op -VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +{ + VCMUL180 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 0 @2op_sz28 + VQDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op + VQDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op +} + +{ + VCMUL90 111 . 1110 0 . 11 ... 0 ... 0 1110 . 0 . 0 ... 1 @2op_sz28 + VQRDMLADH 111 0 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op + VQRDMLSDH 111 1 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op +} + +{ + VCMUL270 111 . 1110 0 . 11 ... 0 ... 1 1110 . 0 . 0 ... 1 @2op_sz28 + VQRDMLADHX 111 0 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op + VQRDMLSDHX 111 1 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op +} =20 VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 @@ -642,3 +656,8 @@ VCADD270_fp 1111 1101 1 . 0 . ... 0 ... 0 1000 . = 1 . 0 ... 0 @2op_fp_size_ =20 VFMA 1110 1111 0 . 0 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp VFMS 1110 1111 0 . 1 . ... 0 ... 0 1100 . 1 . 1 ... 0 @2op_fp + +VCMLA0 1111 110 00 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA90 1111 110 01 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA180 1111 110 10 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev +VCMLA270 1111 110 11 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d7f250a4455..e478408fddd 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2931,3 +2931,89 @@ DO_VFMA(vfmah, 2, float16, false) DO_VFMA(vfmas, 4, float32, false) DO_VFMA(vfmsh, 2, float16, true) DO_VFMA(vfmss, 4, float32, true) + +#define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + TYPE r0, r1, e1, e2, e3, e4; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst0, *fpst1; \ + float_status scratch_fpst; \ + /* We loop through pairs of elements at a time */ \ + for (e =3D 0; e < 16 / ESIZE; e +=3D 2, mask >>=3D ESIZE * 2) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) =3D=3D 0) { = \ + continue; \ + } \ + fpst0 =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 = : \ + &env->vfp.standard_fp_status; \ + fpst1 =3D fpst0; \ + if (!(mask & 1)) { \ + scratch_fpst =3D *fpst0; \ + fpst0 =3D &scratch_fpst; \ + } \ + if (!(mask & (1 << ESIZE))) { \ + scratch_fpst =3D *fpst1; \ + fpst1 =3D &scratch_fpst; \ + } \ + switch (ROT) { \ + case 0: \ + e1 =3D m[H##ESIZE(e)]; \ + e2 =3D n[H##ESIZE(e)]; \ + e3 =3D m[H##ESIZE(e + 1)]; \ + e4 =3D n[H##ESIZE(e)]; \ + break; \ + case 1: \ + e1 =3D TYPE##_chs(m[H##ESIZE(e + 1)]); \ + e2 =3D n[H##ESIZE(e + 1)]; \ + e3 =3D m[H##ESIZE(e)]; \ + e4 =3D n[H##ESIZE(e + 1)]; \ + break; \ + case 2: \ + e1 =3D TYPE##_chs(m[H##ESIZE(e)]); \ + e2 =3D n[H##ESIZE(e)]; \ + e3 =3D TYPE##_chs(m[H##ESIZE(e + 1)]); \ + e4 =3D n[H##ESIZE(e)]; \ + break; \ + case 3: \ + e1 =3D m[H##ESIZE(e + 1)]; \ + e2 =3D n[H##ESIZE(e + 1)]; \ + e3 =3D TYPE##_chs(m[H##ESIZE(e)]); \ + e4 =3D n[H##ESIZE(e + 1)]; \ + break; \ + default: \ + g_assert_not_reached(); \ + } \ + r0 =3D FN(e2, e1, d[H##ESIZE(e)], fpst0); \ + r1 =3D FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ + mergemask(&d[H##ESIZE(e)], r0, mask); \ + mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) +#define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) + +#define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) +#define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) + +DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) +DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) +DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) +DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) +DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) +DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) +DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) +DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) + +DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) +DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) +DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) +DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) +DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) +DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) +DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) +DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d61abc6d46f..d62ed1fc295 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -856,6 +856,14 @@ DO_2OP_FP(VCADD90_fp, vfcadd90) DO_2OP_FP(VCADD270_fp, vfcadd270) DO_2OP_FP(VFMA, vfma) DO_2OP_FP(VFMS, vfms) +DO_2OP_FP(VCMUL0, vcmul0) +DO_2OP_FP(VCMUL90, vcmul90) +DO_2OP_FP(VCMUL180, vcmul180) +DO_2OP_FP(VCMUL270, vcmul270) +DO_2OP_FP(VCMLA0, vcmla0) +DO_2OP_FP(VCMLA90, vcmla90) +DO_2OP_FP(VCMLA180, vcmla180) +DO_2OP_FP(VCMLA270, vcmla270) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984894; cv=none; d=zohomail.com; s=zohoarc; b=CUSzmZMgErI0XiMhjRbB+tgBeL4kfU45e7pqBuIGLWs3zvZNHFaLqFGTXzpEYHPNTKBvq7TcJx9GB9JUd77VpzfCqiLxf8j3vRyWfYsdTBrNI6pM9hho6ALWci9I5PDb32xNdbG0z5CTeT3wQ+VLfdMNkFAhSd9vg2bSXYH7ibI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8O21K1IilhVzj+bzP20ikUdMzycJM1qc6/UnoM+AkTc=; b=uads03W7a4kMXqnY5yj8amGzWCqtGvnLNu6bBuseL8nAhjwWCIwVdmTKIexLcOiIGJ H9HDDYiRmkSvmqhJXSE7s2dOh4fNqVaR9kO5LHv4O9wRfcT8B1HJ0I13OFd/u1ayCaB4 crQasECmIGWsVLU9JI5h+S96qBdHS6vLPNRs14V6TzSvq16Rntem+ixafpe5rMo2VlrR R/p83+BuOZHMdq2mxJVAtwjaubPEDINm7nN/GdYYFePihhF7U8MSiOm8gvv3rugJDu1t /QOJ6JnsrzU2RVP6r1JburAkEVfaAMof0pRV8ggkclB8XK3abixKw9xkmqc9JzfuoD1O ZsZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8O21K1IilhVzj+bzP20ikUdMzycJM1qc6/UnoM+AkTc=; b=Y3JywG/L6iyJ1HsjsQd5hfK9jNTfjoJQAweVEYcIrEKp533TRmvHrpz7Z7R/cUZlEK 8fPfIzYBPkcZKElMblHznP2cO5RxZXHqxuKnqFDUljWY0it7u21ZqOrACiery1MjdyGe PMITM45TEuyai+63xDNBE2ebmduznJ+j8uKmpsWH8tM9nIJSpWyKNXNaUyGmytZ49a86 AO9qS3B1amEv5opNV+odtIldMDq9AlKqLgvg89U/Qsl/OL3Z1/CLAZVZM3WJCiYtaah8 8G7ucQWP6H2aiPbyDkvXCs89y0vroHU09JY0mo+WvNQXJmSKxbdu2D+lCwDhNnM89A6W IO1A== X-Gm-Message-State: AOAM530zeLqiUdf5w+RD/4Es/snZA8feFlb055VpN81ID6dKu3aHYyr7 SDZPLkhFYIIqaXkkROX1MPWoAGeGlMyvqg== X-Google-Smtp-Source: ABdhPJxwjYKPzbmTTKqAwH6BTx9lUkbcwK3i/xeyPno2j5lpNNro0rQxsNXGcX8Pa7GO2s4pizEGnA== X-Received: by 2002:adf:9063:: with SMTP id h90mr4011691wrh.121.1629983852678; Thu, 26 Aug 2021 06:17:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/18] target/arm: Implement MVE VMAXNMA and VMINNMA Date: Thu, 26 Aug 2021 14:17:13 +0100 Message-Id: <20210826131725.22449-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985015935100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but the destination register must be the same as one of the source registers. We defer the decode of the size in bit 28 to the individual insn patterns rather than doing it in the format, because otherwise we would have a single insn pattern that overlapped with two groups (eg VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn patterns per insn seems clearer than a complex multilevel nesting of overlapping and non-overlapping groups. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use DO_2OP_FP_ALL macro --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 11 +++++++++++ target/arm/mve_helper.c | 23 +++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 42 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 73950403bc3..57ab3f7b59f 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -428,6 +428,12 @@ DEF_HELPER_FLAGS_4(mve_vmaxnms, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnmh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminnms, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vmaxnmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxnmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vminnmah, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminnmas, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vfcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vfcadd90s, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 403381eef61..b0622e1f62c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -130,6 +130,11 @@ @2op_fp_size_rev .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qn qm=3D%qm size=3D%2op_fp_size_rev =20 +# 2-operand, but Qd and Qn share a field. Size is in bit 28, but we +# don't decode it in this format +@vmaxnma .... .... .... .... .... .... .... .... &2op \ + qd=3D%qd qn=3D%qd qm=3D%qm + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -199,6 +204,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op # The VSHLL T2 encoding is not a @2op pattern, but is here because it # overlaps what would be size=3D0b11 VMULH/VRMULH { + VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma = size=3D2 + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -211,6 +218,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -221,6 +230,7 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D2 VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 @@ -233,6 +243,7 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index e478408fddd..a6ad894414a 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2855,6 +2855,29 @@ DO_2OP_FP_ALL(vfabd, abd) DO_2OP_FP_ALL(vmaxnm, maxnum) DO_2OP_FP_ALL(vminnm, minnum) =20 +static inline float16 float16_maxnuma(float16 a, float16 b, float_status *= s) +{ + return float16_maxnum(float16_abs(a), float16_abs(b), s); +} + +static inline float32 float32_maxnuma(float32 a, float32 b, float_status *= s) +{ + return float32_maxnum(float32_abs(a), float32_abs(b), s); +} + +static inline float16 float16_minnuma(float16 a, float16 b, float_status *= s) +{ + return float16_minnum(float16_abs(a), float16_abs(b), s); +} + +static inline float32 float32_minnuma(float32 a, float32 b, float_status *= s) +{ + return float32_minnum(float32_abs(a), float32_abs(b), s); +} + +DO_2OP_FP_ALL(vmaxnma, maxnuma) +DO_2OP_FP_ALL(vminnma, minnuma) + #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ void HELPER(glue(mve_, OP))(CPUARMState *env, \ void *vd, void *vn, void *vm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d62ed1fc295..4d702da808d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -864,6 +864,8 @@ DO_2OP_FP(VCMLA0, vcmla0) DO_2OP_FP(VCMLA90, vcmla90) DO_2OP_FP(VCMLA180, vcmla180) DO_2OP_FP(VCMLA270, vcmla270) +DO_2OP_FP(VMAXNMA, vmaxnma) +DO_2OP_FP(VMINNMA, vminnma) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7pXSqEbTOZyV/ZOun+vfAXrbcR65ur8jsORWu+DjPSw=; b=Jo1TvPzDkaR+O2R9XWgrIK+Ao0ZeNsxki24Z16eyrGFrkQ0D9f4yiBp9NUy6Ljmage gOLIbWU0tvsO1XNhMGdnimyWm3OYvfSoITTZS9z0vlna2EiL9TVIPnSCzWlhrwFy8bRW btIpbFzEbVFZJKlZLycPRW/raHFTk6uty5IU9rWe7jnHEv6yTcUE4c68+IreJ/8UHMQ6 dGHK8UdmP6DT+G2MVR/cB04RWu2Be+v/9AJAxV3bjjkQa2soBQYBrhpfe60WjV6gA3DJ oedZaaFIIEsCaJCxAAClXqezbTQSjnZzW08it2EFKw8UMY0h5Bq68/+dQN9DkBjwKjYS I/9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7pXSqEbTOZyV/ZOun+vfAXrbcR65ur8jsORWu+DjPSw=; b=La53VLQ7jI4DOicxBzWhvAu+Hi6N9/V9U1cdVZHq+hSkym/eypd9D7Oat5qRGilnKr 5RvyAf9hX4j+PviH5GDsXAqy4Jmx0YUyWiWYDbW5FUp3B5nVJyQmc+F7jp9qClp4Cdpr slwlSJoEx7kcHn/M55L3S5N7IPTfmKwobXGsvllJCEVke9cLRr0ssPNAUJCAvwAIcu4C Hf3NGWQ7MAeCi6A4fbt8LRrko3TrFZklZJZYij2iObSkpEaYSJk1yOcIdAPVKi8Rt5t7 sL9YKRqIsptbq0+CnF6YqL2UOcjZDTpcOPHmQnWHOs0bqhfQTTbM0O53/HIRdRVgx3wZ 0v7g== X-Gm-Message-State: AOAM5324NXfMuniXFxjO8hQH8TcEKgrdz15Z1gDM0tfJVIffq+TqFhO5 RpnhVGvfIpo1kMQQTHPIh0FlecoVUTb8rg== X-Google-Smtp-Source: ABdhPJz0YcehCn/k0FniNowG1yCi/ySlFXU1axTE5clxEeWgC2DYfMyAq6I8fO44884eXmLGvii1UQ== X-Received: by 2002:adf:82b1:: with SMTP id 46mr3876914wrc.217.1629983853448; Thu, 26 Aug 2021 06:17:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/18] target/arm: Implement MVE scalar fp insns Date: Thu, 26 Aug 2021 14:17:14 +0100 Message-Id: <20210826131725.22449-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985161590100001 Content-Type: text/plain; charset="utf-8" Implement the MVE scalar floating point insns VADD, VSUB and VMUL. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: add and use DO_2OP_FP_SCALAR_ALL macro; use float* types --- target/arm/helper-mve.h | 9 +++++++++ target/arm/mve.decode | 27 +++++++++++++++++++++------ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 20 ++++++++++++++++++++ 4 files changed, 85 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 57ab3f7b59f..091ec4b4270 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -800,3 +800,12 @@ DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarw, TCG_CALL_NO_WG,= void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfsub_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfmul_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index b0622e1f62c..5ba8b6deeaa 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -31,6 +31,8 @@ %2op_fp_size 20:1 !function=3Dneon_3same_fp_size # VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit %2op_fp_size_rev 20:1 !function=3Dplus_1 +# FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit +%2op_fp_scalar_size 28:1 !function=3Dneon_3same_fp_size =20 # 1imm format immediate %imm_28_16_0 28:1 16:3 0:4 @@ -135,6 +137,9 @@ @vmaxnma .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qd qm=3D%qm =20 +@2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \ + qd=3D%qd qn=3D%qn size=3D%2op_fp_scalar_size + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -471,10 +476,17 @@ VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . = 100 .... @2scalar VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar } =20 -VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar -VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar -VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar -VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +{ + VADD_fp_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 100 .... @2op_fp_sc= alar + VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar + VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar +} + +{ + VSUB_fp_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 100 .... @2op_fp_sc= alar + VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar + VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +} =20 { VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar @@ -490,8 +502,11 @@ VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 1= 00 .... @2scalar size=3D%size_28 } =20 -VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar -VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar +{ + VMUL_fp_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 110 .... @2op_fp_sc= alar + VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar + VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar +} =20 # The U bit (28) is don't-care because it does not affect the result VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a6ad894414a..b49975fdc01 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3040,3 +3040,38 @@ DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) + +#define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE r, m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_2OP_FP_SCALAR_ALL(OP, FN) \ + DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ + DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) + +DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) +DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) +DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4d702da808d..bc4b3f840a0 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -960,6 +960,26 @@ static bool trans_VQDMULLT_scalar(DisasContext *s, arg= _2scalar *a) return do_2op_scalar(s, a, fns[a->size]); } =20 + +#define DO_2OP_FP_SCALAR(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ + { \ + static MVEGenTwoOpScalarFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2op_scalar(s, a, fns[a->size]); \ + } + +DO_2OP_FP_SCALAR(VADD_fp_scalar, vfadd_scalar) +DO_2OP_FP_SCALAR(VSUB_fp_scalar, vfsub_scalar) +DO_2OP_FP_SCALAR(VMUL_fp_scalar, vfmul_scalar) + static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenLongDualAccOpFn *fn) { --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984914; cv=none; d=zohomail.com; s=zohoarc; b=Y3jSvPhvkBYZRc0vuFPJlzXEfrT72w95JHHl9ZGBvjuXt1+pp+b7jCQ2vObqJkQKy7fvlag8cqX242eZ3KEQjPwa6ub/5vYstUZI+dYXZ92bxazPYHhXjEgWJGheWl0p0mNsipoqwWpO/+omzE+Us6eE2autt1uPg67KWMFtAuM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984914; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IX63UH9elFIfzzmCD48DW45+4bO0eMwENm0AzIDl4+w=; b=Cjui+8ICWYnYB1rfUZHX4+UQ4Y3hTe1TarU4Y3aYA7tsXAMCVjUMWtNEjNyNZxZXYixReL1b1wXopLO+1cgxkUifjenV4/2UQpFeFv4Q+pJ1HZpyzhfD5+g1nPIek3HNHzjy2y7jiaA+PX2z47lZLJS52sjEG5noUymvSgZrim4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984914054236.03662748691897; Thu, 26 Aug 2021 06:35:14 -0700 (PDT) Received: from localhost ([::1]:43426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFXE-0005x6-UC for importer@patchew.org; Thu, 26 Aug 2021 09:35:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGI-0005nQ-CV for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:45 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGC-00050f-G7 for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:40 -0400 Received: by mail-wr1-x436.google.com with SMTP id h4so5016258wro.7 for ; Thu, 26 Aug 2021 06:17:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IX63UH9elFIfzzmCD48DW45+4bO0eMwENm0AzIDl4+w=; b=LGhDpF77kx5RGKyXZlSumTghVTPhmkLL2pbD4DtpafKV7dagF2feoAxzP4blfCHHyD AyoN7xIk+zzdbHgsIDD34CD1JkmwV4StBRR8f6sKZWn3LncHPAKYwupORRLs1ytdDPyb aeHAsROcxfn88ubllLMT1Oe+QlLf6vTMz2kOYlutf7knrGb5UqkG4cL/cE+2nfa6q0+E sgLnZ9u79RDyz5br8tHiuiFvB3W6LEMa87I/QF63E/OMfT5pRa0yT9qJ9VUcKXe2vblg WFkTyzOqL2SMNwb8oRyb2b1000aq74nvMACB8YyOAVphUDbU0datem+i4HcZkr2cyANn YQ5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IX63UH9elFIfzzmCD48DW45+4bO0eMwENm0AzIDl4+w=; b=fycrHnxuREwMRlfVNspqs7mdNE0AagddGy6goOLQuNtlaHduIl2LvRDZW5QyW6rgM8 0QFxUEzvf/tmypN9UQx/3F5WgVaYFr3wcw9hwRh+2KfMcf/FDkquJMvLpHEhekdn/pKa LR/SLetBjbMovbeNJ9MdWbKnHQxUSjM0D1aQa2MZm/tyaPuRIyeMuFbfB0GJoC/gWC+0 64tQ2tgyCyPMEQ1md/c2Awyg2VuoZ7SdlZ3uRnhZ2UNBACkTxbFK7RaGVRD5vjpLf822 XrX9lO3NJIapjOjaifwN0n+VbOoCS89llZbs8/dhExufJHkcGwph5Ro5JkblQlpm+aYC cBxQ== X-Gm-Message-State: AOAM531KZ/7GqDGGbqP0fbpL1+8GDpsGTWoOaNiqOB72gw1BBKoHwUyI ClLfnIvSzndZdkvCBQ5ZofxHpCeRs0Au2g== X-Google-Smtp-Source: ABdhPJxwPWCSyByGdmVB6VkrQIb7Xxbcb5KjvEWcOX5pxeHlup9UmvuepuFfpeWDAV9yXBhq92mL3A== X-Received: by 2002:adf:fa82:: with SMTP id h2mr3965464wrr.195.1629983854274; Thu, 26 Aug 2021 06:17:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/18] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS Date: Thu, 26 Aug 2021 14:17:15 +0100 Message-Id: <20210826131725.22449-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985035297100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp-with-scalar VFMA and VFMAS insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: use float* types --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 14 +++++++++++--- target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 091ec4b4270..cb7b6423239 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -809,3 +809,9 @@ DEF_HELPER_FLAGS_4(mve_vfsub_scalars, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vfmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfmul_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vfma_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vfma_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) + +DEF_HELPER_FLAGS_4(mve_vfmas_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) +DEF_HELPER_FLAGS_4(mve_vfmas_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 5ba8b6deeaa..d2bd6815bc3 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -508,9 +508,17 @@ VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 1= 00 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar } =20 -# The U bit (28) is don't-care because it does not affect the result -VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar -VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar +{ + VFMA_scalar 111 . 1110 0 . 11 ... 1 ... 0 1110 . 100 .... @2op_fp_sc= alar + # The U bit (28) is don't-care because it does not affect the result + VMLA 111 - 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar +} + +{ + VFMAS_scalar 111 . 1110 0 . 11 ... 1 ... 1 1110 . 100 .... @2op_fp_sc= alar + # The U bit (28) is don't-care because it does not affect the result + VMLAS 111 - 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar +} =20 VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b49975fdc01..36f0910b856 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3075,3 +3075,40 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) + +#define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE r, m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +/* VFMAS is vector * vector + scalar, so swap op2 and op3 */ +#define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) +#define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) + +/* VFMA is vector * scalar + vector */ +DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) +DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) +DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) +DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index bc4b3f840a0..3627ba227f2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -979,6 +979,8 @@ static bool trans_VQDMULLT_scalar(DisasContext *s, arg_= 2scalar *a) DO_2OP_FP_SCALAR(VADD_fp_scalar, vfadd_scalar) DO_2OP_FP_SCALAR(VSUB_fp_scalar, vfsub_scalar) DO_2OP_FP_SCALAR(VMUL_fp_scalar, vfmul_scalar) +DO_2OP_FP_SCALAR(VFMA_scalar, vfma_scalar) +DO_2OP_FP_SCALAR(VFMAS_scalar, vfmas_scalar) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenLongDualAccOpFn *fn) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984365; cv=none; d=zohomail.com; s=zohoarc; b=OTF8fg02ZE8yMVWiCjDOpWC4MXOub2gCiXVcRcNC6ux9YB4mPb0Pvc8cKORapHrKykM28eKxo0ClbGanWXTuIZLW7Zwnh5buqjcSpuOwpeItLpolVjmbKQAxqzhncryrgSz8oeLW8TezeNMitwJtzhVtlT+ZbO4K6JPDzWMbPdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984365; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=gLtizFcLz+ckOHJztmKMfb4x2hkCTyjbQSrsJ4i5nF1v1IzQrz1Y1Dxg1cs4uEtLoIWxcZVoI5QPnnXII+Efa347CZPHGyz54+0liSAt5nWDmCyuWTIHUpe0p0Z7guzudtaEoeRWJ+OIWC1Y+1aLAj/1Os9P0C8DoiM+6sktL9E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984365355272.6926913221114; Thu, 26 Aug 2021 06:26:05 -0700 (PDT) Received: from localhost ([::1]:47682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFOO-0005Kv-9Y for importer@patchew.org; Thu, 26 Aug 2021 09:26:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGI-0005nO-Ao for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:45 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34687) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGC-00051a-Fy for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:40 -0400 Received: by mail-wr1-x429.google.com with SMTP id h13so5065253wrp.1 for ; Thu, 26 Aug 2021 06:17:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=uV7gnocg7QyoQ0SZEor8AWM3Qdw+JYPG2LcEXM/w3vp2ZUwg4Jmf374e57dbU7EFCr E53k3yNqo1qhUTMsLbuCIiasAnjjMfX1piRBL9+0h60A/OIOEmM2vEwsK40gbujyM0lH rQwJiZmNG1I2zz6ZJZYHwVUMZ6WYqhhTD+BgYrzrhdxo6WJJLiz5Qgcf3NQuzldGB12X sGNnROf0iLv6XPIxyEKl6vSlK2ElFKSgY7pSPf+re4go36Eo5rTZj30g3M+N2f83Ishg oDqkKCCRBZmdHdEF7hWn3j6ioMFSDg27aZxGQxffMx+Cnv5gTTZ7Irkd7rtvrOO3AVnN smwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DvhXlYYlfomJDUJCbAefggwT30WTKJdIb0Q3AVXh8mM=; b=K/7hZtLlyK/IObFdRtXaChewRxGCLpAwzQlCC6QmrQG3JLFJzPlRnXysdZBPDN5HVz s9CAHrm0txk/2J2XsPjZLiTRfM7ZK9X+ASiI2lUKkPmNMRc3rIhCrdg1lG3du71Isw+V Ug88tBtuDjsuduo8mIUNXeYCWkApR80cXmiTPSqx6gRaV2nr8pw1hRof5z+Lp3tFdqjj b5vePEj45PBMKpzzh+nq9qbr10T2zgdSjCTFtL5wF3Vrt767G8OuZcDpf2ONu6fH/TG/ aikDPvzk1o7fhK1LT+u5l4YOff6I8XT0z9M5p0/yes2/z3zxN/jhJoG1Y4MzUFnWpMIx 1C5A== X-Gm-Message-State: AOAM532wGZjHVqz2omqG7B5Z4LxNpKrAIf0wR9RNtGSeYKU+NT7sPmHm i9bSHhkHCSFr7tNjTgAHY/YXwA== X-Google-Smtp-Source: ABdhPJyArABX/7DWyhsQOI2w0W1grkTMzPOdXFCIw5G3dDUMiHXv8qU4k+YB1g1lAyaJVBrHoQzC9A== X-Received: by 2002:adf:ec8b:: with SMTP id z11mr3986340wrn.122.1629983854977; Thu, 26 Aug 2021 06:17:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/18] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode Date: Thu, 26 Aug 2021 14:17:16 +0100 Message-Id: <20210826131725.22449-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629984486522100001 Content-Type: text/plain; charset="utf-8" In commit a777d6033447a we added an assertion to parts_silence_nan() that prohibits calling float*_silence_nan() when in default-NaN mode. This ties together a property of the output ("do we generate a default NaN when the result is a NaN?") with an operation on an input ("silence this input NaN"). It's true that most of the time when in default-NaN mode you won't need to silence an input NaN, because you can just produce the default NaN as the result instead. But some functions like float*_maxnum() are defined to be able to work with quiet NaNs, so silencing an input SNaN is still reasonable. In particular, the upcoming implementation of MVE VMAXNMV would fall over this assertion if we didn't delete it. Delete the assertion. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 12467bb9bba..f2ad0f335e6 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -198,7 +198,6 @@ static void parts128_default_nan(FloatParts128 *p, floa= t_status *status) static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) { g_assert(!no_signaling_nans(status)); - g_assert(!status->default_nan_mode); =20 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984190; cv=none; d=zohomail.com; s=zohoarc; b=VFy2irjd3jl+IekKmOTReJI3bAHS+ND2VCQfoDtzjVCIC5WK1Ss3atJMEUkBZQzwDBID6MLNRTY7sFd9JwLiby2qhTC8MKPjm8Xk2DJ/dMYlEEhJOger6GwvlRve67na7Vc6+rOkZzoWORZ7bwX3Oycj9Ciu4YPOiiNqm05Yyk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984190; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GqNkD7rCn8BUcvF+3qh6Mr1+B40tHXPMIKKLqa+QiR4=; b=Gr0MW+20armJV4LzNhMCwSH4iOA+5TNRd1wuBP80X1IE7pdyYld+YDFKIIEZ+CotKo3TdOWO2AJjSqAAJ07bd7UN3BFzQ7YJiglcsU1xZooqWfoUitpLuFw4XYq2D6fOtZPUWabLFPu40D7IJb/pIZg2cC0f3vkkI4W3Ni16+80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984190638295.4580741782397; Thu, 26 Aug 2021 06:23:10 -0700 (PDT) Received: from localhost ([::1]:38624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFLZ-00075Z-Jd for importer@patchew.org; Thu, 26 Aug 2021 09:23:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGK-0005nY-DU for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:45 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:56022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGE-00051q-4u for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:42 -0400 Received: by mail-wm1-x334.google.com with SMTP id g135so1810463wme.5 for ; Thu, 26 Aug 2021 06:17:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GqNkD7rCn8BUcvF+3qh6Mr1+B40tHXPMIKKLqa+QiR4=; b=xmmrXUypaJnY2HuUr5lSsQ02C8ve+IWbbctUZBV2SEwZXXL5mL5V3WGaxO2X8oBU/e XeZgtLrwEMHwj0RqcOjh99KHPPdGU8jJd1wetMPEcN4YAQNKaL6vKmmO8Hy4BUoWLg21 1x1FXM7iyLjaPdhgqnWzPlQo/CpiRqDDAKkfDNxUb3wN30wVPYHF6uHw9JywRnDmb8sP K1ZGceQf0upuW+h6r+fPOknxWNd/Nl2KSfJ87ozfihdvFXmSisCPmme1Zj/xzoe029T4 EpF8Z9i0DjmMj/uUQvtMbXnRc5sciWkfvEpiM7NUJShAH4juMNvkUXvBSTcbixvpTKKh f79w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GqNkD7rCn8BUcvF+3qh6Mr1+B40tHXPMIKKLqa+QiR4=; b=N52VFr0FXXRB4EalwC8gvE2ixcdjDymm+IABL27adK9hVh1Ufp5kP98NZtgt1zeBEa gDk6+cPdp9De/cq1t8cIByJWibIQz8kqr66IUKcJ/T2HyndEhmh6NmCKDJSg7e0aGHQs bHGJ2/vzFSg7DA6c6TqKI3nIx35F08x1YDHtvQnwMWh4KLgC3AvM/5HUWR7KPuFCPiay hiZNrGRkGeWhweOoNvwzhA+HhO3OZwuPhmAB0iLtBZoNpz0SOq05zK/Ud6cWnweHjHsH d7EhWoGZ+hZzK1aj4RO7J7NZktRcnJQyrivzZNU0wJJyMF7nRi/KlejdlF7I2+2WdlCw wzCA== X-Gm-Message-State: AOAM5305HAE3lYbsPdZ4jHjRq0tZh1cRETdXaCMYJn9l55b6gnBCx+m4 IH9C1vLrC77bBjzqnf0rcNnyS5g39dK1OQ== X-Google-Smtp-Source: ABdhPJzWUM3gcXmvqZJv4sn8Y1t3qR+KzDYQPHAo04p1PfyVm2MOqkb1l3ydixx8SDKrHp1P7bJmtQ== X-Received: by 2002:a7b:cc16:: with SMTP id f22mr14133423wmh.99.1629983855776; Thu, 26 Aug 2021 06:17:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector Date: Thu, 26 Aug 2021 14:17:17 +0100 Message-Id: <20210826131725.22449-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629986428589100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These calculate the maximum or minimum of floating point elements across a vector, starting with a value in a general purpose register and returning the result there. The pseudocode silences a possible SNaN in the accumulating result on every iteration (by calling FPConvertNaN), but we do it only on the input ra, because if none of the inputs to float*_maxnum or float*_minnum are SNaNs then the result can't be an SNaN. Note that we can't use the float*_maxnuma() etc functions we defined earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute value of the starting general-purpose register value, which could be negative. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: use float* types only --- target/arm/helper-mve.h | 12 +++++++++++ target/arm/mve.decode | 12 +++++++++++ target/arm/mve_helper.c | 44 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 20 +++++++++++++++++ 4 files changed, 88 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index cb7b6423239..47fd18dddbf 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -614,6 +614,18 @@ DEF_HELPER_FLAGS_3(mve_vminavb, TCG_CALL_NO_WG, i32, e= nv, ptr, i32) DEF_HELPER_FLAGS_3(mve_vminavh, TCG_CALL_NO_WG, i32, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vminavw, TCG_CALL_NO_WG, i32, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vmaxnmvh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxnmvs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vminnmvh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminnmvs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vmaxnmavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxnmavs, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vminnmavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminnmavs, TCG_CALL_NO_WG, i32, env, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d2bd6815bc3..1a18c3b8eeb 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -137,6 +137,10 @@ @vmaxnma .... .... .... .... .... .... .... .... &2op \ qd=3D%qd qn=3D%qd qm=3D%qm =20 +# Here also we don't decode the bit 28 size in the format to avoid +# awkward nested overlap groups +@vmaxnmv .... .... .... .... rda:4 .... .... .... &vmaxv qm=3D%qm + @2op_fp_scalar .... .... .... .... .... .... .... rm:4 &2scalar \ qd=3D%qd qn=3D%qn size=3D%2op_fp_scalar_size =20 @@ -440,6 +444,10 @@ VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 = . 0 ... 1 @vmladav_nosz VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_n= osz =20 { + VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D2 + VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D2 VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv @@ -449,6 +457,10 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 = . 0 ... 1 @vmladav_nosz } =20 { + VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv s= ize=3D1 + VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv s= ize=3D1 VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_n= osz diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 36f0910b856..52e5a8f2a8b 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3112,3 +3112,47 @@ DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float= 16_muladd) DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) + +/* Floating point max/min across vector. */ +#define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ + uint32_t ra_in) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *m =3D vm; \ + TYPE ra =3D (TYPE)ra_in; \ + float_status *fpst =3D (ESIZE =3D=3D 2) ? \ + &env->vfp.standard_fp_status_f16 : \ + &env->vfp.standard_fp_status; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + if (mask & 1) { \ + TYPE v =3D m[H##ESIZE(e)]; \ + if (TYPE##_is_signaling_nan(ra, fpst)) { \ + ra =3D TYPE##_silence_nan(ra, fpst); \ + float_raise(float_flag_invalid, fpst); \ + } \ + if (TYPE##_is_signaling_nan(v, fpst)) { \ + v =3D TYPE##_silence_nan(v, fpst); \ + float_raise(float_flag_invalid, fpst); \ + } \ + if (ABS) { \ + v =3D TYPE##_abs(v); \ + } \ + ra =3D FN(ra, v, fpst); \ + } \ + } \ + mve_advance_vpt(env); \ + return ra; \ + } \ + +#define NOP(X) (X) + +DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) +DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) +DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) +DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) +DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) +DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) +DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) +DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 3627ba227f2..4e2aa2cae2d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1806,6 +1806,26 @@ DO_VMAXV(VMINV_S, vminvs) DO_VMAXV(VMINV_U, vminvu) DO_VMAXV(VMINAV, vminav) =20 +#define DO_VMAXV_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ + { \ + static MVEGenVADDVFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vmaxv(s, a, fns[a->size]); \ + } + +DO_VMAXV_FP(VMAXNMV, vmaxnmv) +DO_VMAXV_FP(VMINNMV, vminnmv) +DO_VMAXV_FP(VMAXNMAV, vmaxnmav) +DO_VMAXV_FP(VMINNMAV, vminnmav) + static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) { /* Absolute difference accumulated across vector */ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984566; cv=none; d=zohomail.com; s=zohoarc; b=BDMFBaabc/geV2b3goykPvWH99JpsHyF0WeCk6jxuoQlr0kAJn7moH1blGY50SusxRnmjR1yL3fb9hG0HosMVAWm57UWdgSYEOpGdEq2qccotfEgdpzzDOPegL9DN0DkHXzvfAK3igo1HkdVag7w0pEt1aUVglLKC5Uv1O7ktrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984566; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mfamHtdFPlP/R6iQ+VFMxT63nZJoG0XuYjj5ksHMeHA=; b=PsANRDpDlo+qKAFf2Gi7HfLOxQzSpx7VzvtH/TQjiCUmwk8MF/WySXPZBThAg2ooFn6eRG17IxpT5GBsjb6iVolgGva5Phn76XXG1RQWh+9aHJUzQnWhH0WLl63QIJioLj2sN7dSWUN6fmHCVaFzIQE8BxeRVEmXgnBKC7/6FQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984566754796.0530335298799; Thu, 26 Aug 2021 06:29:26 -0700 (PDT) Received: from localhost ([::1]:57894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFRd-0004EF-Jz for importer@patchew.org; Thu, 26 Aug 2021 09:29:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGJ-0005nV-UP for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:45 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGE-000537-5s for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:42 -0400 Received: by mail-wr1-x42f.google.com with SMTP id h13so5065392wrp.1 for ; Thu, 26 Aug 2021 06:17:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mfamHtdFPlP/R6iQ+VFMxT63nZJoG0XuYjj5ksHMeHA=; b=l8h7EMEREd8y1zYGg2JXeS6eg7LZthFWgaUdWcoH1ah8e4QTnt2/fjofnVJqKbF/lx W/VaDhPqgHi0YLWX/CeyNE7SIoKl3foxTNT/Eg03iJJYK/j1LTG+IV1SQxGHM7iu/ch+ 8es1gK13IPFjSBAga9cVEeSJH6NRJN04aEEQ4N2T1KMqKAJdipIRTTAjGTMXVrLyUOBM Ij1EtvHukossBZpEyyMvWIn5BPF7FUzfDCzyvlnH+BXUTHm8XOkHlgqOHYBRM5sOvBZS XzXJ3Ks3ead8Xq7mK+R/RBxOLbHxB/vLq896wWCRZXYfor4fcI1PT72FKLtJ8PcXQIuj 9fog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mfamHtdFPlP/R6iQ+VFMxT63nZJoG0XuYjj5ksHMeHA=; b=lcEi2ZnZlNE4/99zfEEkIyadNFq1TNVDPvUO5J1MzCMUBZNlm/pFfc5g8zjcCA31HX j6InCuNF2GMdkozUbaQl4OQf4fbF2JKnKEzhXMrOa6ieG9+v9gG1Nu7G9MC19eO0dTSx jZKnNwmKk2XqHMR5d1AJH3sNnE0sSaLchH2XaBczqFiVFZ/k0XUQmUETJf6h/TnOvR4X PpHSmiPXFGW31USrq74Uf9yuvHl/aUmnRs8vM1CO/YLLWn6UyJYSFGlFrmiLR1lCQcu9 c1JfRaD7/bNBoRhnTNQV2m8dB/o7koQVvSzVsQf+xvw0zWM3Fch3MIzQkIO7pEzxYLck V7Kg== X-Gm-Message-State: AOAM53129DBY2a43nQ4GbNzWZOTKbVjTQTToSr0Ng/bI44nKC7oX3vrl Wmb0sgkXxEuzauK8Di43YLnv6Zn/1HuBiw== X-Google-Smtp-Source: ABdhPJx//30F/b0DVdCXnuecS8WRnqiatVBpgWWp8UFnojgofDRkiQvFoGK4eXTiSrsc4lJ8I1qezQ== X-Received: by 2002:a5d:570c:: with SMTP id a12mr3936689wrv.117.1629983856630; Thu, 26 Aug 2021 06:17:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/18] target/arm: Implement MVE fp vector comparisons Date: Thu, 26 Aug 2021 14:17:18 +0100 Message-Id: <20210826131725.22449-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985758088100001 Content-Type: text/plain; charset="utf-8" Implement the MVE fp vector comparisons VCMP and VPT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: use float* types --- target/arm/helper-mve.h | 18 +++++++++++ target/arm/mve.decode | 39 +++++++++++++++++++---- target/arm/mve_helper.c | 64 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 22 +++++++++++++ 4 files changed, 137 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 47fd18dddbf..0c15c531641 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -813,6 +813,24 @@ DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG,= void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vfcmpeqh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpeqs, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpneh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpnes, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpgeh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpges, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmplth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmplts, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpgth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 1a18c3b8eeb..7767ecae2ac 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -124,6 +124,9 @@ @vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \ mask=3D%mask_22_13 =20 +@vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ + qm=3D%qm size=3D%2op_fp_scalar_size mask=3D%mask_22_13 + @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 @2op_fp .... .... .... .... .... .... .... .... &2op \ @@ -663,17 +666,41 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1= 100 rdm:4 qd=3D%qd # Comparisons. We expand out the conditions which are split across # encodings T1, T2, T3 and the fc bits. These include VPT, which is # effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero. -VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp -VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp +{ + VCMPEQ_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp_fp + VCMPEQ 111 1 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp +} + +{ + VCMPNE_fp 111 . 1110 0 . 11 ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp_fp + VCMPNE 111 1 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp +} + +{ + VCMPGE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp_fp + VCMPGE 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp +} + +{ + VCMPLT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp_fp + VCMPLT 111 1 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp +} + +{ + VCMPGT_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp_fp + VCMPGT 111 1 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp +} + +{ + VCMPLE_fp 111 . 1110 0 . 11 ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp= _fp + VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp +} + { VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp } -VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp -VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp -VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp -VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp =20 { VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 52e5a8f2a8b..07a1ab88814 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3156,3 +3156,67 @@ DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_= maxnum) DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) + +/* FP compares; note that all comparisons signal InvalidOp for QNaNs */ +#define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ + { \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + bool r; \ + for (e =3D 0; e < 16 / ESIZE; e++, emask <<=3D ESIZE) { = \ + if ((mask & emask) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & (1 << (e * ESIZE)))) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +/* + * Some care is needed here to get the correct result for the unordered ca= se. + * Architecturally EQ, GE and GT are defined to be false for unordered, but + * the NE, LT and LE comparisons are defined as simple logical inverses of + * EQ, GE and GT and so they must return true for unordered. The softfloat + * comparison functions float*_{eq,le,lt} all return false for unordered. + */ +#define DO_GE16(X, Y, S) float16_le(Y, X, S) +#define DO_GE32(X, Y, S) float32_le(Y, X, S) +#define DO_GT16(X, Y, S) float16_lt(Y, X, S) +#define DO_GT32(X, Y, S) float32_lt(Y, X, S) + +DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq) +DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq) + +DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq) +DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq) + +DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16) +DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32) + +DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16) +DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32) + +DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16) +DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32) + +DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16) +DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4e2aa2cae2d..da14a6f790e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1758,6 +1758,28 @@ DO_VCMP(VCMPLT, vcmplt) DO_VCMP(VCMPGT, vcmpgt) DO_VCMP(VCMPLE, vcmple) =20 +#define DO_VCMP_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ + { \ + static MVEGenCmpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vcmp(s, a, fns[a->size]); \ + } + +DO_VCMP_FP(VCMPEQ_fp, vfcmpeq) +DO_VCMP_FP(VCMPNE_fp, vfcmpne) +DO_VCMP_FP(VCMPGE_fp, vfcmpge) +DO_VCMP_FP(VCMPLT_fp, vfcmplt) +DO_VCMP_FP(VCMPGT_fp, vfcmpgt) +DO_VCMP_FP(VCMPLE_fp, vfcmple) + static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) { /* --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984064; cv=none; d=zohomail.com; s=zohoarc; b=LOosh3K0msym7SsH1WhnYHtrdqsL36jYPJ7cCzqdDseMe+60SlD8hXfxpT4P2gxcctwjqFsRgZ6vGVS2gFv3JHdMJRWK/ikBQxyntBeOT1C8c7rEzx4H552QIq4Urd50FaqLHSpTLksb5mcA3uAlQLFOtoUJLR3pv+qJZfyxaLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984064; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xs6B7+cZoPUy7Z4wp0c6zsRI40KRsbDMVrcBCVg/eUo=; b=CwrYYXvv6CHLiVRo4YYzgtkcU7TCWPHty08SH13ngBx0jqb74SiOqGZTpaCFE9e4Sbi2UkWNcbhCZVk5rFvet4JufT1Y/e9D/FwIm7CufdvKP2RW2eRSJVzoOgVvbofIP9dq0FwI/kxGOLqlSxWpUo0dJ6eYqc1UOsPjSPzngLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984064295160.80836521533536; Thu, 26 Aug 2021 06:21:04 -0700 (PDT) Received: from localhost ([::1]:59060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFJX-0001iJ-76 for importer@patchew.org; Thu, 26 Aug 2021 09:21:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGL-0005nb-3W for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:45 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:45746) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGE-00053k-Uh for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:44 -0400 Received: by mail-wr1-x434.google.com with SMTP id n5so4964492wro.12 for ; Thu, 26 Aug 2021 06:17:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xs6B7+cZoPUy7Z4wp0c6zsRI40KRsbDMVrcBCVg/eUo=; b=IurItslKxny7se0/kF5lUrK07EraA3//Js1xUB0a66cwRtu5yKJRHQSlBugCZhfJRC 3yR4WqdNslgltqWLEV+noQZmHsLTOPAu7p04Wero0CNG3HdCPbGR4q3ov+mmPH1GwSLq fHQ6PrFj6AQ6xqwwsyfW6yDzqwhRnGNbC9z5hr1ReuEMM2f+qkgA+Msbqw3ofpZbIYuM A8Z34uzUd+w++0sN81Zpq0rMKxzrs2uSjeH4LD7B+OBPoVYkapoQxmy2l5ctKr1X7DqX 8Icc1/RzeNokp9lWg1WPekZ6J+l2ZE8bMfCcJxBpVHE9Df4crwttTw2B2DXRWk3uxWlV F8MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xs6B7+cZoPUy7Z4wp0c6zsRI40KRsbDMVrcBCVg/eUo=; b=J775caOcvke91QWPvZuMB+aiaGV5HaJN9AYIPFnkVR7Tdsvohu3/hBS5kevDzZkrqh 9Tg5m4AnfX2d9GZlLjV1y/69YXyvUmtPNGqab3DIv0e/xNW78ddCe9ZRm2DdgeWma+UL 1/dzED3Tru6ZFjdrZTUa0AabKYYavVD6RStgSn1bX+Vbb4ce8vEj4N9QgkOs1sjBK1bl +w9xTcgszq7Ee0/7RD5ZFYg4JZ3ySgD7cShxu3YyFsng1xNS5FcAz00T6BupnuT/AT5A iXPaIcLPXyUH4Z4pJyV1exVfVdsWnKDR7n1IkLVpgdmCId9gtwJdOzBms1/em6+xdarF lXyw== X-Gm-Message-State: AOAM530ZAyXz14F+JtbFJtd4ErcxceTWk22vQPGJicZ6v8EolcIN94FK 6Av4Hc8y4Kn8g9ZW4/e0NibNALS9XeT8cg== X-Google-Smtp-Source: ABdhPJzSGc0ghPpSU+20WMaeLCns5OurNkGI6HBNpygNzapDmRd7XBrNOXNW3z8ZVcZIuF2b2+fUQw== X-Received: by 2002:a5d:4564:: with SMTP id a4mr3813332wrc.81.1629983857483; Thu, 26 Aug 2021 06:17:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/18] target/arm: Implement MVE fp scalar comparisons Date: Thu, 26 Aug 2021 14:17:19 +0100 Message-Id: <20210826131725.22449-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985452132100002 Content-Type: text/plain; charset="utf-8" Implement the MVE fp scalar comparisons VCMP and VPT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Use float* types --- target/arm/helper-mve.h | 18 +++++++++++ target/arm/mve.decode | 61 +++++++++++++++++++++++++++++-------- target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++-------- target/arm/translate-mve.c | 14 +++++++++ 4 files changed, 131 insertions(+), 24 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 0c15c531641..9ee841cdf01 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -831,6 +831,24 @@ DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void,= env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpne_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpge_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmplt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vfcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i3= 2) +DEF_HELPER_FLAGS_3(mve_vfcmple_scalars, TCG_CALL_NO_WG, void, env, ptr, i3= 2) + DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 7767ecae2ac..aa113279dc5 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -127,6 +127,11 @@ @vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \ qm=3D%qm size=3D%2op_fp_scalar_size mask=3D%mask_22_13 =20 +# Bit 28 is a 2op_fp_scalar_size bit, but we do not decode it in this +# format to avoid complicated overlapping-instruction-groups +@vcmp_fp_scalar .... .... .... qn:3 . .... .... .... rm:4 &vcmp_scalar \ + mask=3D%mask_22_13 + @vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm =20 @2op_fp .... .... .... .... .... .... .... .... &2op \ @@ -400,8 +405,10 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 = 0 1 0000 @vdup size=3D2 VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup } { - VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup - VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup + VCMPGT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_s= calar size=3D2 + VCMPLE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_s= calar size=3D2 + VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup + VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup } =20 # multiply-add long dual accumulate @@ -472,8 +479,17 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 = . 0 ... 1 @vmladav_nosz =20 # Scalar operations =20 -VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar -VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +{ + VCMPEQ_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VCMPNE_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar +} + +{ + VCMPLT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_s= calar size=3D2 + VCMPGE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_s= calar size=3D2 + VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +} =20 { VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar @@ -703,17 +719,38 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1= 100 rdm:4 qd=3D%qd } =20 { - VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 - VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask= _22_13 - VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_sca= lar + VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 + VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mas= k_22_13 + VCMPEQ_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0100 .... @vcmp_scalar } -VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_sca= lar + +{ + VCMPNE_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1100 .... @vcmp_scalar +} + +{ + VCMPGT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_sc= alar size=3D1 + VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0110 .... @vcmp_scalar +} + +{ + VCMPLE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_sc= alar size=3D1 + VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1110 .... @vcmp_scalar +} + +{ + VCMPGE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_sc= alar size=3D1 + VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0100 .... @vcmp_scalar +} +{ + VCMPLT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_sc= alar size=3D1 + VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1100 .... @vcmp_scalar +} + VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_sca= lar VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_sca= lar -VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_sca= lar -VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar -VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar -VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar =20 # 2-operand FP VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 07a1ab88814..891926c124d 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3191,6 +3191,44 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_= minnum) mve_advance_vpt(env); \ } =20 +#define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + uint32_t rm) \ + { \ + TYPE *n =3D vn; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + bool r; \ + for (e =3D 0; e < 16 / ESIZE; e++, emask <<=3D ESIZE) { = \ + if ((mask & emask) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & (1 << (e * ESIZE)))) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +#define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ + DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) + /* * Some care is needed here to get the correct result for the unordered ca= se. * Architecturally EQ, GE and GT are defined to be false for unordered, but @@ -3203,20 +3241,20 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32= _minnum) #define DO_GT16(X, Y, S) float16_lt(Y, X, S) #define DO_GT32(X, Y, S) float32_lt(Y, X, S) =20 -DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq) -DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq) +DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) +DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) =20 -DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq) -DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq) +DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) +DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) =20 -DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16) -DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32) +DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) +DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) =20 -DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16) -DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32) +DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) +DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) =20 -DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16) -DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32) +DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) +DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) =20 -DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16) -DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32) +DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) +DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index da14a6f790e..e8a3dec6683 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1771,6 +1771,20 @@ DO_VCMP(VCMPLE, vcmple) return false; \ } \ return do_vcmp(s, a, fns[a->size]); \ + } \ + static bool trans_##INSN##_scalar(DisasContext *s, \ + arg_vcmp_scalar *a) \ + { \ + static MVEGenScalarCmpFn * const fns[] =3D { \ + NULL, \ + gen_helper_mve_##FN##_scalarh, \ + gen_helper_mve_##FN##_scalars, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_vcmp_scalar(s, a, fns[a->size]); \ } =20 DO_VCMP_FP(VCMPEQ_fp, vfcmpeq) --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pP1HYcQAmHtGvPDwqo06dz6Z2GRnOyeYZE6eTi7ZdmU=; b=p+X//1TwMrK8ccUscW2ri6rHY18V8NzJgfXBljh3NQS3wxXR8Kv3H/edzWj99akr1i e2cnmsA6vJ+gcruKpxhHdC9mcus/N9qaQ4Yc7HsDyJTt5KhzRv36ZN+QcgRFmAC67cCW 3OpA+Yka+v9fgCIqHoDrThYlbruWwBhSJ/thPCLSWknKJHZAkaZU6cpEUppXhuV5fuF/ FSoL2E3XyqF0XNcnDSdTUEqDZ1G+IQgZ1DffqVt0ycVVj+iWlgIWQCxJWqvVuqzbuJjo up72GEzlsqzg0iM0YOT8W17+WaGgCiC3LUlK24jCMMDyum0wi0TKD0DmW2oTzf0Yp9Qs JGjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pP1HYcQAmHtGvPDwqo06dz6Z2GRnOyeYZE6eTi7ZdmU=; b=XbTLXKAK4D5Mt5peKyBEvpCvP93vNzwb72jp1oLbs81KY5nPeBVvdEP87IzYrMlQhq TyGGrAG3UcVhq79AnQFqxJYBguiTdGk9/Td8B4Ys0KeHNWEi8No9jjau4iuRfXK6Re57 fpWqh8K+R++3NjxbBqNhx0GGN9qrRlT0tsTr9ZZsKZwRiJDLw6svW7NBjY3rJcGyH1Yq IMXTLTOgNHP4B2n5HOCojG73HV8+bZD95nnfc1M4Mp4ma4nxm4K9JZg1JSqPV0ne43++ t0k7QdwpRqfJjdVNy0HgnNqJe8scbADqD+VzjuZl0HiKc2YpK8rk6OI/CaDf29jKGPXQ 7N+g== X-Gm-Message-State: AOAM532mWfR0nbbYR/5NGPDshv8UInTj4HYGx+nvSaJDXF72pmrPA/8M lj/a3hc45hRPzRrfK6uYPDn+iTqVwBnOVg== X-Google-Smtp-Source: ABdhPJzDjGuOG1UCNrgyaQkvhx75Oee0EQECcc9xxf2EJdDJb4AeJdzXkDXVHrn46GaClB2QNL9BIw== X-Received: by 2002:adf:e604:: with SMTP id p4mr3977858wrm.37.1629983858264; Thu, 26 Aug 2021 06:17:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/18] target/arm: Implement MVE VCVT between floating and fixed point Date: Thu, 26 Aug 2021 14:17:20 +0100 Message-Id: <20210826131725.22449-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629984926571100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT insns which convert between floating and fixed point. As with the Neon equivalents, these use essentially the same constant encoding as right-shift-by-immediate. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 9 +++++++++ target/arm/mve.decode | 19 +++++++++++++++++++ target/arm/mve_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 18 ++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 9ee841cdf01..f3c2b43bf43 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -863,3 +863,12 @@ DEF_HELPER_FLAGS_4(mve_vfma_scalars, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vfmas_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) DEF_HELPER_FLAGS_4(mve_vfmas_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_4(mve_vcvt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_hs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_hu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_sf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_uf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_fs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vcvt_fu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index aa113279dc5..d9fcc42d36d 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -771,3 +771,22 @@ VCMLA0 1111 110 00 . 1 . ... 0 ... 0 1000 .= 1 . 0 ... 0 @2op_fp_size_ VCMLA90 1111 110 01 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCMLA180 1111 110 10 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev VCMLA270 1111 110 11 . 1 . ... 0 ... 0 1000 . 1 . 0 ... 0 @2op_fp= _size_rev + +# floating-point <-> fixed-point conversions. Naming convention: +# VCVT_, S =3D signed int, U =3D unsigned int, H =3D halfprec, F= =3D singleprec +@vcvt .... .... .. 1 ..... .... .. 1 . .... .... &2shift \ + qd=3D%qd qm=3D%qm shift=3D%rshift_i5 size=3D2 +@vcvt_f16 .... .... .. 11 .... .... .. 0 . .... .... &2shift \ + qd=3D%qd qm=3D%qm shift=3D%rshift_i4 size=3D1 + +VCVT_SH_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 +VCVT_UH_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt_f16 + +VCVT_HS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 +VCVT_HU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt_f16 + +VCVT_SF_fixed 1110 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt +VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt + +VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt +VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 891926c124d..d829ffe12d6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3258,3 +3258,39 @@ DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float3= 2, DO_GT32) =20 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) + +#define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ + uint32_t shift) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], shift, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) +DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) +DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) +DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) +DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) +DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) +DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) +DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e8a3dec6683..9269dbc3324 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1439,6 +1439,24 @@ DO_2SHIFT(VRSHRI_U, vrshli_u, true) DO_2SHIFT(VSRI, vsri, false) DO_2SHIFT(VSLI, vsli, false) =20 +#define DO_2SHIFT_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2shift(s, a, gen_helper_mve_##FN, false); \ + } + +DO_2SHIFT_FP(VCVT_SH_fixed, vcvt_sh) +DO_2SHIFT_FP(VCVT_UH_fixed, vcvt_uh) +DO_2SHIFT_FP(VCVT_HS_fixed, vcvt_hs) +DO_2SHIFT_FP(VCVT_HU_fixed, vcvt_hu) +DO_2SHIFT_FP(VCVT_SF_fixed, vcvt_sf) +DO_2SHIFT_FP(VCVT_UF_fixed, vcvt_uf) +DO_2SHIFT_FP(VCVT_FS_fixed, vcvt_fs) +DO_2SHIFT_FP(VCVT_FU_fixed, vcvt_fu) + static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, MVEGenTwoOpShiftFn *fn) { --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629985190; cv=none; d=zohomail.com; s=zohoarc; b=bwdjwR+2DJZtDiz4HNHHkuKdbfruCNiqMOExRiL97J9pA5w88rLxf9O+v90cl7xXQc38t1kEI6Fxn7U5mwomEF8Rl3gg6466JQaIHBs4wXtbbc9xA0gWRkrKqyd3qyY1/56kr3AF9LK/vOLh4cjVBj/cgFgWTvPMC2S6snwHkNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629985190; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bkuWlzNSI2yuRBQTkDjmPVrmm9Ffu+LTHOZ/atHURyg=; b=QKVGNcjEiE2AuRMZhjh17Y4w/mj1CidrAmDhMYd74JI6sI+Da9GevnToJLjFec9IaVnFLVhAJV+Khyt1zZqxwNRd4HXuLuQPhhgKFJtzP1FfJA5Gy4Yoe+zxMydDLaK2Gx21glhVUSCRONHCDdRiIEMUi/Mf3CLzo4JpBGEvFXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629985190905951.9463959634094; Thu, 26 Aug 2021 06:39:50 -0700 (PDT) Received: from localhost ([::1]:55498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFbh-0005uT-SL for importer@patchew.org; Thu, 26 Aug 2021 09:39:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGN-0005qU-JD for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:48 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:39680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGI-00055e-0p for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:47 -0400 Received: by mail-wr1-x435.google.com with SMTP id z4so5022038wrr.6 for ; Thu, 26 Aug 2021 06:17:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bkuWlzNSI2yuRBQTkDjmPVrmm9Ffu+LTHOZ/atHURyg=; b=QSyyflhOUYN+l/ld38/IqEv7jqYjFUWX2aeYLRBAtZ2fB3xY5sBO5lRo7l6AK7rp9/ q3T3E7JZlkm4GJH8piQy7INyod3dxfSt7cB057PTFOF16Ku6Sq+cXaRahFlrm55TcJa4 nnJt7y6PesfZDyKDCa9ccy5yl3qUpOxYWW52N0G9+PVdgbWH8Orhy8Kk5Xnu8e8p7SCJ 4BQ1q2etgIDpxAziEWYOn+t6Uq/E9ZoISjL0o047piny3lzvyOMzvaLJv8q/7N5HVo1i j70hKlaEfEUo4Ve/WPCdMCsnp8+4LSrNENFeyb9z8igAPyx3L6OMo5OqvIRE6JCGJluo sv0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bkuWlzNSI2yuRBQTkDjmPVrmm9Ffu+LTHOZ/atHURyg=; b=Pb389gzPlxmiQUnRtFH9IoP8reL7BDbYXZz8DLm5EZNidFq0+IWAQ8AVQWdJP2K1+q v7YPEFRZIkZ7GL8+z5X1sc7ZoXHH2UCYOeQNxeLBhB9K5fJDCiBWRpBZmGlPuUWguadl zfkJKWLC2DoNhxn+h0g3BlNJFAyVNuMjHTZdV/BXhDZCqi9WchitoEG1ycfvFsmrLWUj pJwzxLHrdC5z0r/sSqR+6JaVvWKaQw4cjWPnwzRbaHPvOP9WH+Wqz395eX0V+LtY9OWQ SCbTjLjMvrgkyc9DZdSqTdb6Gqwxme9yGxXfMDaS65usgKzuvtnBChZ4lt4SNK/lt2Y1 htBQ== X-Gm-Message-State: AOAM531y+kHXRFkY9U3I3hu936W9B5bJzI3UvsbBXNrk/bRW9ahvOAS7 08Oxy6jET10IbjaLrnbzUdnflnb7Q00mjA== X-Google-Smtp-Source: ABdhPJwGclcnnYQe98kFhn9W6rgrqKs3LCeWEnos6SE3xeoPNfGSAw2DkU8h1azMZQCTpl6FN3wHaw== X-Received: by 2002:a5d:51ca:: with SMTP id n10mr3876460wrv.119.1629983859042; Thu, 26 Aug 2021 06:17:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/18] target/arm: Implement MVE VCVT between fp and integer Date: Thu, 26 Aug 2021 14:17:21 +0100 Message-Id: <20210826131725.22449-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985312105100001 Content-Type: text/plain; charset="utf-8" Implement the MVE "VCVT (between floating-point and integer)" insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 7 +++++++ target/arm/translate-mve.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d9fcc42d36d..9a40ff9f43c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -790,3 +790,10 @@ VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01= . 1 ... 0 @vcvt =20 VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt + +# VCVT between floating point and integer (halfprec and single); +# VCVT_, S =3D signed int, U =3D unsigned int, F =3D float +VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op +VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op +VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op +VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 9269dbc3324..351033af1ec 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -543,6 +543,38 @@ DO_1OP(VQNEG, vqneg) DO_1OP(VMAXA, vmaxa) DO_1OP(VMINA, vmina) =20 +/* + * For simple float/int conversions we use the fixed-point + * conversion helpers with a zero shift count + */ +#define DO_VCVT(INSN, HFN, SFN) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##HFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##SFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] =3D { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VCVT(VCVT_SF, vcvt_sh, vcvt_sf) +DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf) +DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) +DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629984536; cv=none; d=zohomail.com; s=zohoarc; b=OczOz4aWoyUi8kCgNkSAWxgAfRtxX3mTO2LyNRreE92j+DjygMv/l00T/+5hTnrL4U/KuibudCEdtKIxQWBUbKRV5XrTZU9YmV3R5OAs5PofjLT6ShK4EWRq4v9ZtYSfrVFbCdcIRlYLvMIc3dcpVYnhqK9POflxgYBLHLeLKUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629984536; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aPwZlZ+FcfCF18SiaZV3J9Dj2i/qKu0DetW7U/gVdig=; b=nhKxLIgBjgSrQFDcfd/4vrEM14jGtPBmFinKNzbvd46/MJhEzUo6aySRl7hdt7pa+lAiWDRmoCgmLO1OO/apAPmgW8chCFTRs8UcetRKdt6t+etrIKwv88HEfbLIj7761uuL1CfsBkWqojoapptKRIqFGktUiO5A5pTcyoBldgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629984536917460.2352235426987; Thu, 26 Aug 2021 06:28:56 -0700 (PDT) Received: from localhost ([::1]:55396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mJFR9-0002SU-O3 for importer@patchew.org; Thu, 26 Aug 2021 09:28:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mJFGM-0005qR-OD for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:47 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mJFGI-00056V-3O for qemu-devel@nongnu.org; Thu, 26 Aug 2021 09:17:46 -0400 Received: by mail-wr1-x429.google.com with SMTP id v10so5040577wrd.4 for ; Thu, 26 Aug 2021 06:17:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aPwZlZ+FcfCF18SiaZV3J9Dj2i/qKu0DetW7U/gVdig=; b=nT0VpmgriOT6oKk7xoejJHi7lQsEFh+nq4CtyBzNr6vrYwVNL/IXURh17qHGfmHMqV 4XgGqxi4lAtQGFyupBPJyfMTbSIze8T3BrxhP4nLTLBrDyrCuGHY7mW+IPL1+yz3Ejgm gcaOvIrptOGWocJ+zL0fWrM/1Fvn1Xh4Nl4xwxSW69Xxl2N7oOvz/9elLjER4hKEQa0z FHdsxZblZRxhYA++TppaiPZ36DT//mq5bDi83ixGKnoPBs5Qm5IAIE4Re4M8PSzV6M4H X0u3sK0bnk9k9MGXmzDOaN1I9chvOyn4aStmlG0fXXNytfzjwX8dEyrcnF8q48Vd834O fQlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aPwZlZ+FcfCF18SiaZV3J9Dj2i/qKu0DetW7U/gVdig=; b=LsyYCE5IKdNdkoXg92Ju2lgAtaOfbUHoS5NcIl/RNCPxRtr2ZOSQ9weU74Es0rj1OP rQwXHWZqIjjjMw1aFL9y6J/oFqy+NRBhOHW/bYQvtPa6uSx88ivDjGDYrhrghiHfaIMe fmAT+RvVGQ+L9QoZtIC8stdUeiimQ5jwJCPV0Z/KLMU19XXOrWuPbIjna0aV1R1SJFH0 UH+pnIigTFw6fpSj1prqu8M7hNx3yJOX5UWzrWygpdsK8cgR44FCI2SAg9dJ9h3kS1l0 5Tp/BivCi7fjv/tFaa+X+o7X/TIGgjP+Z1iD2G4K1LIjKvxCSjNXNrcLoY+XEMH9EdcC vXJA== X-Gm-Message-State: AOAM533N2r3zupiAsCK19CA9y1pyBse0DiGnKKCV6KO/yk4kY+ig0Gbw 6pu5BYOWHVVRhPIo6/v8Tt8+TuAsOKndWg== X-Google-Smtp-Source: ABdhPJxOIGzfpnSVeGmOTiw4mNLk3FFhUwBYC/l0DK6sUVeK2wGP/jjJLTWS5x9Txi2uwtYNV/hk5A== X-Received: by 2002:a5d:6e0c:: with SMTP id h12mr4019571wrz.334.1629983859935; Thu, 26 Aug 2021 06:17:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/18] target/arm: Implement MVE VCVT with specified rounding mode Date: Thu, 26 Aug 2021 14:17:22 +0100 Message-Id: <20210826131725.22449-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985740117100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT which converts from floating-point to integer using a rounding mode specified by the instruction. We implement this similarly to the Neon equivalents, by passing the required rounding mode as an extra integer parameter to the helper functions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 ++++ target/arm/mve.decode | 10 ++++++++ target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++ target/arm/translate-mve.c | 52 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f3c2b43bf43..6d4052a5269 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -177,6 +177,11 @@ DEF_HELPER_FLAGS_3(mve_vminab, TCG_CALL_NO_WG, void, e= nv, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vminah, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vminaw, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vcvt_rm_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_ss, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vcvt_rm_us, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 9a40ff9f43c..410ea746fcf 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -797,3 +797,13 @@ VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 = 1 . 0 ... 0 @1op VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op + +# VCVT from floating point to integer with specified rounding mode +VCVTAS 1111 1111 1 . 11 .. 11 ... 000 00 0 1 . 0 ... 0 @1op +VCVTAU 1111 1111 1 . 11 .. 11 ... 000 00 1 1 . 0 ... 0 @1op +VCVTNS 1111 1111 1 . 11 .. 11 ... 000 01 0 1 . 0 ... 0 @1op +VCVTNU 1111 1111 1 . 11 .. 11 ... 000 01 1 1 . 0 ... 0 @1op +VCVTPS 1111 1111 1 . 11 .. 11 ... 000 10 0 1 . 0 ... 0 @1op +VCVTPU 1111 1111 1 . 11 .. 11 ... 000 10 1 1 . 0 ... 0 @1op +VCVTMS 1111 1111 1 . 11 .. 11 ... 000 11 0 1 . 0 ... 0 @1op +VCVTMU 1111 1111 1 . 11 .. 11 ... 000 11 1 1 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d829ffe12d6..a793199fbee 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3294,3 +3294,41 @@ DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) + +/* VCVT with specified rmode */ +#define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vm, uint32_t rmode) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + float_status *base_fpst =3D (ESIZE =3D=3D 2) ? = \ + &env->vfp.standard_fp_status_f16 : \ + &env->vfp.standard_fp_status; \ + uint32_t prev_rmode =3D get_float_rounding_mode(base_fpst); \ + set_float_rounding_mode(rmode, base_fpst); \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D base_fpst; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], 0, fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + set_float_rounding_mode(prev_rmode, base_fpst); \ + mve_advance_vpt(env); \ + } + +DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) +DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) +DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) +DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 351033af1ec..e80a55eb62e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -49,6 +49,7 @@ typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i3= 2); typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i32); +typedef void MVEGenVCVTRmodeFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -575,6 +576,57 @@ DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf) DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) =20 +static bool do_vcvt_rmode(DisasContext *s, arg_1op *a, + enum arm_fprounding rmode, bool u) +{ + /* + * Handle VCVT fp to int with specified rounding mode. + * This is a 1op fn but we must pass the rounding mode as + * an immediate to the helper. + */ + TCGv_ptr qd, qm; + static MVEGenVCVTRmodeFn * const fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_mve_vcvt_rm_sh, gen_helper_mve_vcvt_rm_uh }, + { gen_helper_mve_vcvt_rm_ss, gen_helper_mve_vcvt_rm_us }, + { NULL, NULL }, + }; + MVEGenVCVTRmodeFn *fn =3D fns[a->size][u]; + + if (!dc_isar_feature(aa32_mve_fp, s) || + !mve_check_qreg_bank(s, a->qd | a->qm) || + !fn) { + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +#define DO_VCVT_RMODE(INSN, RMODE, U) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + return do_vcvt_rmode(s, a, RMODE, U); \ + } \ + +DO_VCVT_RMODE(VCVTAS, FPROUNDING_TIEAWAY, false) +DO_VCVT_RMODE(VCVTAU, FPROUNDING_TIEAWAY, true) +DO_VCVT_RMODE(VCVTNS, FPROUNDING_TIEEVEN, false) +DO_VCVT_RMODE(VCVTNU, FPROUNDING_TIEEVEN, true) +DO_VCVT_RMODE(VCVTPS, FPROUNDING_POSINF, false) +DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) +DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) +DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PuYwv7IQju2UavvbdJU5w8adZg7ikn6rO+blWY/QnVE=; b=KitbIkLzpunuiB/OC3v5pDTWcSHD9+lkygwzUC8Dxont/8jbEgSmAOIWAOwpA6+FTN U65H6NOX2OPljLzYQ6WxL3hB2Q7rdA/roKamIgEzzmlJ4UAPmN6YVFl8rCZYBor2QzOu /1CZYQ2DEsYqyiQQaTAK53bKB3kRFLrCqipee/g0biJ3AieoyxezdYJ69/dv+bSvFRtO cyHAmrGq2m4jsGVK0GpY4e9znAj5lVAI+FJPX4ZoK09PtiHq6g+VHQKKUwmhGHWg9eD2 Rj/SbUb2yJl8qPGtFsflgJbKxt1hPado67QMQ+WTKaRjAQJSgX3fumlUp5tc0OD7n5ct VXIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PuYwv7IQju2UavvbdJU5w8adZg7ikn6rO+blWY/QnVE=; b=ZdMm1IkVi4jTJDu/a2cuGG4QIGQeLRfZhrUtlBNHWVo7IoU4mUuGB8i5LLsCYWpWzf qYZr/HtOlITCZKZm3VeKMYnhwBEBh2Q4D6LkJx9iNjHRW3tmQ7yugImzN5MlQsSZKeB4 /Y1p/gv+AnT2VoI4DS0mbE4tbhiUxGZQy+KXDzedW/7Be31gfmbVBpdZxdNeLFMeoJaw 9424XnuLK0YkbKj++Xaqwob2QxkXjUVq1oFzRXOp6fmlU9rEkJbgO4nFLIE1A9pA4qHZ WVNBUQ6emBkGOw4EKW8M+ZwlzD5WFgYtLNjHpv+p7ZKa8GPzowXjQMMHtBZEZ/ZdFeC6 sqgw== X-Gm-Message-State: AOAM532OZf9t59FR+dTdb35HOpSitCmd3YHA9c/5DSCcF32LitgTkUQY PG/w3qw7SMLdpil59lu4+J1Bvxk1YMB/ag== X-Google-Smtp-Source: ABdhPJz1/buW42MU2mKFMic9/L1gXfxyPB/El/nREG9KNiPd2lE5jpiAyw3m921ko0bsGCu6csKzYQ== X-Received: by 2002:a5d:5447:: with SMTP id w7mr3958082wrv.137.1629983860768; Thu, 26 Aug 2021 06:17:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/18] target/arm: Implement MVE VCVT between single and half precision Date: Thu, 26 Aug 2021 14:17:23 +0100 Message-Id: <20210826131725.22449-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985934343100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCVT instruction which converts between single and half precision floating point. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: make do_vcvt_sh/do_vcvt_hs functions, not macros --- target/arm/helper-mve.h | 5 +++ target/arm/mve.decode | 8 ++++ target/arm/mve_helper.c | 81 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 14 +++++++ 4 files changed, 108 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6d4052a5269..f6345c7abbe 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -182,6 +182,11 @@ DEF_HELPER_FLAGS_4(mve_vcvt_rm_uh, TCG_CALL_NO_WG, voi= d, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_rm_ss, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(mve_vcvt_rm_us, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) =20 +DEF_HELPER_FLAGS_3(mve_vcvtb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtb_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcvtt_hs, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 410ea746fcf..32de4af3170 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -221,6 +221,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op # The VSHLL T2 encoding is not a @2op pattern, but is here because it # overlaps what would be size=3D0b11 VMULH/VRMULH { + VCVTB_SH 111 0 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_nosz + VMAXNMA 111 0 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma = size=3D2 =20 VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -235,6 +237,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTB_HS 111 1 1110 0 . 11 1111 ... 0 1110 0 0 . 0 ... 1 @1op_no= sz + VMAXNMA 111 1 1110 0 . 11 1111 ... 0 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 =20 VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b @@ -247,6 +251,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_SH 111 0 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 0 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D2 VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h @@ -260,6 +266,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op } =20 { + VCVTT_HS 111 1 1110 0 . 11 1111 ... 1 1110 0 0 . 0 ... 1 @1op_nosz + VMINNMA 111 1 1110 0 . 11 1111 ... 1 1110 1 0 . 0 ... 1 @vmaxnma= size=3D1 VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a793199fbee..1ed76ac5ed8 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3332,3 +3332,84 @@ DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_to= shh) DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) + +/* + * VCVT between halfprec and singleprec. As usual for halfprec + * conversions, FZ16 is ignored and AHP is observed. + */ +static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) +{ + uint16_t *d =3D vd; + uint32_t *m =3D vm; + uint16_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fz =3D get_flush_to_zero(base_fpst); + set_flush_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & 1)) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float32_to_float16(m[H4(e)], ieee, fpst); + mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); + } + set_flush_to_zero(old_fz, base_fpst); + mve_advance_vpt(env); +} + +static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) +{ + uint32_t *d =3D vd; + uint16_t *m =3D vm; + uint32_t r; + uint16_t mask =3D mve_element_mask(env); + bool ieee =3D !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP); + unsigned e; + float_status *fpst; + float_status scratch_fpst; + float_status *base_fpst =3D &env->vfp.standard_fp_status; + bool old_fiz =3D get_flush_inputs_to_zero(base_fpst); + set_flush_inputs_to_zero(false, base_fpst); + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { + if ((mask & MAKE_64BIT_MASK(0, 4)) =3D=3D 0) { + continue; + } + fpst =3D base_fpst; + if (!(mask & (1 << (top * 2)))) { + /* We need the result but without updating flags */ + scratch_fpst =3D *fpst; + fpst =3D &scratch_fpst; + } + r =3D float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); + mergemask(&d[H4(e)], r, mask); + } + set_flush_inputs_to_zero(old_fiz, base_fpst); + mve_advance_vpt(env); +} + +void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_sh(env, vd, vm, 1); +} +void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 0); +} +void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) +{ + do_vcvt_hs(env, vd, vm, 1); +} diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e80a55eb62e..194ef99cc74 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -627,6 +627,20 @@ DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) =20 +#define DO_VCVT_SH(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, gen_helper_mve_##FN); \ + } \ + +DO_VCVT_SH(VCVTB_SH, vcvtb_sh) +DO_VCVT_SH(VCVTT_SH, vcvtt_sh) +DO_VCVT_SH(VCVTB_HS, vcvtb_hs) +DO_VCVT_SH(VCVTT_HS, vcvtt_hs) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AcdAYe4UKe0yqe1e/LyFr+Aew3hd7YeEn7Z4eVbDvMM=; b=R6AxDmatdm9TiM5WfRTElgQHqkvjrVdtmcRaO73QukF4L6GRkncuIMUAp3Mv437YM3 WT4X+bJmA+cUf+CzmYgdaVv8HdnQl8O5v5xcPDAbPaINXlekdKaxOhHy6SeD+ljayQwV yq+dIsfNoL0BZ394oXN6iPv107+WvAZOTpLgChJ0OgxveTydAG23B4NvViCvtX38mlDJ P/pZyNHZKKpMBsdEyUwP4Y7PsDsZEClv2AqPRD8Jl0nGjCMCh0mB3q5kzcNXe0p1mNGB Oddh9XF+pR/0cdBxBH6KAczS1W+0M9st3Urg6iQU+mXPBAROAzsAXWFEJ7PxQ06Jr7Ln Bdww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AcdAYe4UKe0yqe1e/LyFr+Aew3hd7YeEn7Z4eVbDvMM=; b=iZLkvn/hlc89KXEjlRUTBMrLqSLGb38toi2bBjm7jHUu2sB7g/gg+8UANQTEIJ2lsV u6g7tKlsy69fekvoO1+uem5nWHL9FafRe3sZ9tU4WVy3MGv+ieAfuLdHTJETsfjfV3OM CABLZRzFuwWrkoHVuRXVkQLAEjQmNNfxRJjiGp5XJnuubMwNp3B+fA5vZ8H1tOZXtFUw Gi1A0nNnKety2B35LeiB3miE6pkRetMB7o/xthxtLH460m/xPuPRnpYSo8wJQ/g/gAyb /LCJj1BJ4KL+0CpI9WA/6QR22ZVjJsAedl8VNE85UQ29dnHt2hjMdDRUHWOu1aGvIurD ohLg== X-Gm-Message-State: AOAM533T4HuwdzGPfnwiHN1PL6PUpdCGCN4oB/aiz7HHOtf+FqnV9GIX FnMky5ZycSUFpn2zVvEfZcDUMw== X-Google-Smtp-Source: ABdhPJzeNet2WOSGFZFNCY00h380ZLXhRo1ThUahYXhMpmM9ngdpjbFFtpIygS1EOtKoBMjubLSPtw== X-Received: by 2002:a5d:424c:: with SMTP id s12mr4043245wrr.268.1629983861570; Thu, 26 Aug 2021 06:17:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/18] target/arm: Implement MVE VRINT insns Date: Thu, 26 Aug 2021 14:17:24 +0100 Message-Id: <20210826131725.22449-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985153565100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VRINT insns, which round floating point inputs to integer values, leaving them in floating point format. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: use float* types --- target/arm/helper-mve.h | 6 +++++ target/arm/mve.decode | 7 ++++++ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++ target/arm/translate-mve.c | 45 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f6345c7abbe..76bd25006d8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -882,3 +882,9 @@ DEF_HELPER_FLAGS_4(mve_vcvt_sf, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_uf, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_fs, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vcvt_fu, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vrint_rm_h, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vrint_rm_s, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_3(mve_vrintx_h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrintx_s, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 32de4af3170..72b93bfcaa3 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -815,3 +815,10 @@ VCVTPS 1111 1111 1 . 11 .. 11 ... 000 10 0 = 1 . 0 ... 0 @1op VCVTPU 1111 1111 1 . 11 .. 11 ... 000 10 1 1 . 0 ... 0 @1op VCVTMS 1111 1111 1 . 11 .. 11 ... 000 11 0 1 . 0 ... 0 @1op VCVTMU 1111 1111 1 . 11 .. 11 ... 000 11 1 1 . 0 ... 0 @1op + +VRINTN 1111 1111 1 . 11 .. 10 ... 001 000 1 . 0 ... 0 @1op +VRINTX 1111 1111 1 . 11 .. 10 ... 001 001 1 . 0 ... 0 @1op +VRINTA 1111 1111 1 . 11 .. 10 ... 001 010 1 . 0 ... 0 @1op +VRINTZ 1111 1111 1 . 11 .. 10 ... 001 011 1 . 0 ... 0 @1op +VRINTM 1111 1111 1 . 11 .. 10 ... 001 101 1 . 0 ... 0 @1op +VRINTP 1111 1111 1 . 11 .. 10 ... 001 111 1 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1ed76ac5ed8..846962bf4c5 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -3333,6 +3333,12 @@ DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_to= uhh) DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) =20 +#define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) +#define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) + +DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) +DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) + /* * VCVT between halfprec and singleprec. As usual for halfprec * conversions, FZ16 is ignored and AHP is observed. @@ -3413,3 +3419,32 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd= , void *vm) { do_vcvt_hs(env, vd, vm, 1); } + +#define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + TYPE r; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + float_status *fpst; \ + float_status scratch_fpst; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if ((mask & MAKE_64BIT_MASK(0, ESIZE)) =3D=3D 0) { = \ + continue; \ + } \ + fpst =3D (ESIZE =3D=3D 2) ? &env->vfp.standard_fp_status_f16 := \ + &env->vfp.standard_fp_status; \ + if (!(mask & 1)) { \ + /* We need the result but without updating flags */ \ + scratch_fpst =3D *fpst; \ + fpst =3D &scratch_fpst; \ + } \ + r =3D FN(m[H##ESIZE(e)], fpst); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) +DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 194ef99cc74..2ed91577ec8 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -641,6 +641,51 @@ DO_VCVT_SH(VCVTT_SH, vcvtt_sh) DO_VCVT_SH(VCVTB_HS, vcvtb_hs) DO_VCVT_SH(VCVTT_HS, vcvtt_hs) =20 +#define DO_VRINT(INSN, RMODE) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_h(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))= ); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_s(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))= ); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] =3D { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) +DO_VRINT(VRINTZ, FPROUNDING_ZERO) +DO_VRINT(VRINTM, FPROUNDING_NEGINF) +DO_VRINT(VRINTP, FPROUNDING_POSINF) + +static bool trans_VRINTX(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vrintx_h, + gen_helper_mve_vrintx_s, + NULL, + }; + if (!dc_isar_feature(aa32_mve_fp, s)) { + return false; + } + return do_1op(s, a, fns[a->size]); +} + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ --=20 2.20.1 From nobody Thu May 9 02:16:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i17sm1341908wrc.38.2021.08.26.06.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dlNDMB/8L65w3rYQrh4g4+ZBy9+++yz/Uc57+3Riqgs=; b=Dpu1HB6ZYs0R/dAonCyPjLR1P4ojBS4pAN2sPnw+rDp5eVsz6TO7GRJFBOjQfFiSWX sz1uADaU3gT7sy82XLVhO15Yo99jHaebTVYXGIUGXHpXkefoO0dvzy4mEm232wSqW28r 1LiQrhRNQcPht+9111eAE7s/nUplYsZjvEkBU6X41+ucXoKO1pHVjDpl6a5eTtziyEua rtkpRVVgv/07QdN0TrzxzG++bAYTIRUjN67bYeiQlz7x6jp0UstycQebLKS+7QcrM6O+ E1YTQvcmkdgVxbLNtse8I0T2ZY2q+VHB55ftxgRfz5MdCjgpOeCBjtY1owmAbfBHJeJS IL8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dlNDMB/8L65w3rYQrh4g4+ZBy9+++yz/Uc57+3Riqgs=; b=AHrUBLaNSZAymmxT7wjS8rRsBJhi6IzVHXJaT8paUz9gESYQw++6Hcurw2xHagO38u Lq2gUNhCkY3jOuFUBp1qaEUzFCm/0NMpCqA1sqcx1SK2MdII2ARkLz59LlnYxxfZhs/v GPiaN/fzbNlAqRHgEXz7tmUp2N8jd41s4deYwsve8P8bqyPAly2PGfP7p/mhmJoC8DRl O+w8VEzoFKq1SANJvwpX5HLk7CWaj6Te2ZNRE7PSzfWH5pAQed3AUoum+wmL4eTuYvLX 34/USYDRMcymzlOZ6hd8Xgk/xwVsavdqtBD2u3PKhHVIh7ayfBMDvCbPkGiTuhKJJ76n ItuA== X-Gm-Message-State: AOAM533bLXIsCYTG6wmrwzlCjYIl5ZkvdSIQ7uxLhJEii4aSGaZLCJeW CYHbqP3f9XPBfjor1ylyCiSOwbXrImtcwg== X-Google-Smtp-Source: ABdhPJx6CvtW827ANz+Y8d7nLV0owr56erSSj1FAgbEw2bDH7nY/eqd9J1ViEsnyl+mmyh61HkuxBw== X-Received: by 2002:a05:6000:1864:: with SMTP id d4mr4120140wri.250.1629983862266; Thu, 26 Aug 2021 06:17:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/18] target/arm: Enable MVE in Cortex-M55 Date: Thu, 26 Aug 2021 14:17:25 +0100 Message-Id: <20210826131725.22449-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210826131725.22449-1-peter.maydell@linaro.org> References: <20210826131725.22449-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629985583510100001 Content-Type: text/plain; charset="utf-8" We now have a complete MVE emulation, so we can enable it in our Cortex-M55 model by setting the ID registers to match those of a Cortex-M55 with full MVE support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ed444bf436a..33cc75af57d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -654,12 +654,9 @@ static void cortex_m55_initfn(Object *obj) cpu->revidr =3D 0; cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; - /* - * These are the MVFR* values for the FPU, no MVE configuration; - * we will update them later when we implement MVE - */ + /* These are the MVFR* values for the FPU + full MVE configuration */ cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12100011; + cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; cpu->isar.id_pfr0 =3D 0x20000030; cpu->isar.id_pfr1 =3D 0x00000230; --=20 2.20.1