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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id b10sm18177167wrt.43.2021.08.25.06.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 06:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W6xnaiIUmUl+DsFrI4M2FV6+eRUriPvolShiSG06CRw=; b=Of4+7bWpePA1p05JWfqf9XLA6pPrwoe7Yoiivv9KTNgRkKAjSX8FjrwO1UeAjo/oZ9 8Ix3u/nvHwRcKb0cFP9LYx7NU+Fltg/Up+GlZdPIsInYIWwZvX1WUlrBJ24kpLXYZA0e 8iV8GEZ1UjRMohgRWbz/NjLVf7HzWNFy71GUmIk8dH60KojLQKVTNiLJDvN+lj8Vh3qA Xl+aI8xXClyUtb9u6SnyhGsOSlt5PPvYSyyQZ7mJJLDOnOlkMKiP0v01/HtjnN4yHQR3 3mEaGeClk1hMuWn2U1wYfT8mIEqRAxLnVLTV8G+i67ywrmFDSuImUheeeUHzT2UWK3uA q0Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=W6xnaiIUmUl+DsFrI4M2FV6+eRUriPvolShiSG06CRw=; b=nRluP7NYk95UJALP2FnjbsMvjgK1S7BSgDchO+42EAn/22IEad8G/k+5nJlmyq6rUx ZNif/BRuIf3a1chColsxZr4ZozHmwOlKgEUNtRAw+2ihAp9HNSI7sBjyXad79zc4ZVt1 X+PWjHXAm1vXSLJI+mwINyd8S5ic3sXr925D2aCbH9mwvyvWTbdbR23Ef3UtkNJSSUjt kmTgt++mpNQcQurS6OJZdQ3LcekbSOBn2oUpXzMEjRC/nqt4ZATz002XN0kxEZi4QLcB 1TRmGGDYd+CC/DtITBTXrTZfioOVLjaw/KevenReOXhg3HYqnQIEtYoy8U+/pXUW7bL/ vj6g== X-Gm-Message-State: AOAM5308Hta1UUAmnoIa299oedfB61OktktjQn8MYAbk6Tc6SC5++RXF 0qR4zNFP92ExZf1GrL+T75M= X-Google-Smtp-Source: ABdhPJz3iJB80guNEn2n9wMvOM2+aJXH0V3n72ALqaROFaVkTEaQGPbG6+Nl/NjgSORCNKtxI5xLcw== X-Received: by 2002:a1c:7e8a:: with SMTP id z132mr9131781wmc.75.1629896557724; Wed, 25 Aug 2021 06:02:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Subject: [PULL 05/28] target/mips: Rename 'rtype' as 'r' Date: Wed, 25 Aug 2021 15:01:48 +0200 Message-Id: <20210825130211.1542338-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210825130211.1542338-1-f4bug@amsat.org> References: <20210825130211.1542338-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1629896567593100001 We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 4 +-- target/mips/tcg/rel6.decode | 4 +-- target/mips/tcg/tx79.decode | 14 ++++---- target/mips/tcg/msa_translate.c | 4 +-- target/mips/tcg/rel6_translate.c | 4 +-- target/mips/tcg/tx79_translate.c | 62 ++++++++++++++++---------------- 6 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bf132e36b9b..74d99f6862c 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -11,11 +11,11 @@ # - The MIPS64 SIMD Architecture Module, Revision 1.12 # (Document Number: MD00868-1D-MSA64-AFP-01.12) =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 &msa_bz df wt s16 =20 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz =20 diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index ed069c51662..d6989cf56e8 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -14,9 +14,9 @@ # The MIPS64 Instruction Set Reference Manual, Revision 6.06 # (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 03a25a5096d..57d87a2076a 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -11,20 +11,20 @@ # when creating helpers common to those for the individual # instruction patterns. =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 -&itype base rt offset +&i base rt offset =20 ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 -@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=3D0 -@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 -@rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 -@rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r sa=3D0 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &r sa=3D0 rs=3D0 +@rs ...... rs:5 ..... .......... ...... &r sa=3D0 rt= =3D0 rd=3D0 +@rd ...... .......... rd:5 ..... ...... &r sa=3D0 rs=3D0 r= t=3D0 =20 -@ldst ...... base:5 rt:5 offset:16 &itype +@ldst ...... base:5 rt:5 offset:16 &i =20 ########################################################################### =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index eed2eca6c92..8170a8df26b 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -2261,12 +2261,12 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } =20 -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } =20 -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS !=3D 64) { return false; diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_transl= ate.c index ae2e023a817..d631851258a 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -23,12 +23,12 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) return true; } =20 -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } =20 -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS !=3D 64) { return false; diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 395d6afa1f1..6d51fe17c1a 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -64,28 +64,28 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) * MTLO1 rs Move To LO1 Register */ =20 -static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFHI1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_HI[1], a->rd); =20 return true; } =20 -static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFLO1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_LO[1], a->rd); =20 return true; } =20 -static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTHI1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_HI[1], a->rs); =20 return true; } =20 -static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTLO1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_LO[1], a->rs); =20 @@ -116,7 +116,7 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Wo= rd */ =20 -static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, void (*gen_logic_i64)(TCGv_i64, TCGv_i64,= TCGv_i64)) { TCGv_i64 ax, bx; @@ -146,19 +146,19 @@ static bool trans_parallel_arith(DisasContext *ctx, a= rg_rtype *a, } =20 /* Parallel Subtract Byte */ -static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBB(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64); } =20 /* Parallel Subtract Halfword */ -static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBH(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64); } =20 /* Parallel Subtract Word */ -static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBW(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64); } @@ -189,25 +189,25 @@ static bool trans_PSUBW(DisasContext *ctx, arg_rtype = *a) */ =20 /* Parallel And */ -static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +static bool trans_PAND(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_and_i64); } =20 /* Parallel Or */ -static bool trans_POR(DisasContext *ctx, arg_rtype *a) +static bool trans_POR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_or_i64); } =20 /* Parallel Exclusive Or */ -static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PXOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); } =20 /* Parallel Not Or */ -static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PNOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); } @@ -237,7 +237,7 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PCEQW rd, rs, rt Parallel Compare for Equal Word */ =20 -static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_compare(DisasContext *ctx, arg_r *a, TCGCond cond, unsigned wlen) { TCGv_i64 c0, c1, ax, bx, t0, t1, t2; @@ -286,37 +286,37 @@ static bool trans_parallel_compare(DisasContext *ctx,= arg_rtype *a, } =20 /* Parallel Compare for Greater Than Byte */ -static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); } =20 /* Parallel Compare for Equal Byte */ -static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); } =20 /* Parallel Compare for Greater Than Halfword */ -static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); } =20 /* Parallel Compare for Equal Halfword */ -static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); } =20 /* Parallel Compare for Greater Than Word */ -static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); } =20 /* Parallel Compare for Equal Word */ -static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); } @@ -334,7 +334,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) * SQ rt, offset(base) Store Quadword */ =20 -static bool trans_LQ(DisasContext *ctx, arg_itype *a) +static bool trans_LQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0; TCGv addr; @@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } =20 -static bool trans_SQ(DisasContext *ctx, arg_itype *a) +static bool trans_SQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv addr =3D tcg_temp_new(); @@ -437,7 +437,7 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) */ =20 /* Parallel Pack to Word */ -static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) +static bool trans_PPACW(DisasContext *ctx, arg_r *a) { TCGv_i64 a0, b0, t0; =20 @@ -473,7 +473,7 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i6= 4 a, TCGv_i64 b) tcg_gen_deposit_i64(dh, a, b, 0, 32); } =20 -static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) +static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen) { TCGv_i64 ax, bx; =20 @@ -514,19 +514,19 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_rtype= *a, unsigned wlen) } =20 /* Parallel Extend Lower from Byte */ -static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLB(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 8); } =20 /* Parallel Extend Lower from Halfword */ -static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLH(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 16); } =20 /* Parallel Extend Lower from Word */ -static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; =20 @@ -549,7 +549,7 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *= a) } =20 /* Parallel Extend Upper from Word */ -static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; =20 @@ -593,7 +593,7 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *= a) */ =20 /* Parallel Copy Halfword */ -static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +static bool trans_PCPYH(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -615,7 +615,7 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) } =20 /* Parallel Copy Lower Doubleword */ -static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYLD(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -638,7 +638,7 @@ static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) } =20 /* Parallel Copy Upper Doubleword */ -static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYUD(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -657,7 +657,7 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) } =20 /* Parallel Rotate 3 Words Left */ -static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) +static bool trans_PROT3W(DisasContext *ctx, arg_r *a) { TCGv_i64 ax; =20 --=20 2.31.1