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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DkSKucbRVfZaukjnVODkmhOBvmBFYtKFjtgssow2x4M=; b=grIijKxBBCp71b61W9eHjT+WKK6suKIsXOcswYxPn9CTAaujW9N1uOmnrKMUv+MQHe Gp7M1YpylbN8GNBZjibR3IqxdBZjfAgflMGkA5i5nJaU5v5h6UiM6a4mCXkCqhqXx2sB x3D8p4SYBf+Q5Inyr4HcEyeXGlBPWg6in1kbr3VMsLOaj/J+npZjSgiOa1UCNhhcMvYI WKuWW9dZsdTsANeXmcsOJzf+t/Ob1GTblZXvQaknv8q0K0FV6ir4BMLtyECGO+COEJBa 0DrBpc2wmYdWxonaz/8Z72psQTvXYPEj9jkilT088Colvuqka99u4pcvm/5DGH4dehNV nOKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DkSKucbRVfZaukjnVODkmhOBvmBFYtKFjtgssow2x4M=; b=K+vtiIheuU8IbVe1UkswjXad452geLeDI7EJjwkMF+n52/k+0+LuS5ac3+yyg/r7Og g8UcxaOzBlNxSMERO5uGgH1Tdq2NV/N5EDydtN8JGGI6zUZPZ1/0p22AYfyOu4/GqbAb FQTvnVlNu/q/ciOSmNVCD1KQU+8AxW0O1K3rvr34CtOw5BMslv3B77CT060GJ/QSh3J9 A+umTN/T9UhKv9azHrmdlCPPog7lcHHebTbMBbVAuNtPC3t6yN0u2LW28DjtqlXeTqpi PpsXkTSvh0Id5CFpNN/FB7uTTfVqsZnnpHLTCROfjxxOzAxnE+it1r0uyTs5HZTSLvmd puiw== X-Gm-Message-State: AOAM530ZV7RTRo7l2ZWX9SnNEInTPVND7wcWroK6QbXV+HBNFfq44KUF Q7gThpRrm539lQ20W8hkO4RrgxAEmrkk6w== X-Google-Smtp-Source: ABdhPJzOX0yzdGRJ8EWPvC2CsvXDQW0S+RtiBLQgmR86YD9zvaeFVfclXMtxcWT/2EUVHLwDSKViBA== X-Received: by 2002:a5d:5983:: with SMTP id n3mr14866454wri.227.1629887767922; Wed, 25 Aug 2021 03:36:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/44] target/arm: Implement M-profile trapping on division by zero Date: Wed, 25 Aug 2021 11:35:27 +0100 Message-Id: <20210825103534.6936-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889203190100003 Content-Type: text/plain; charset="utf-8" Unlike A-profile, for M-profile the UDIV and SDIV insns can be configured to raise an exception on division by zero, using the CCR DIV_0_TRP bit. Implement support for setting this bit by making the helper functions raise the appropriate exception. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210730151636.17254-3-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/helper.h | 4 ++-- target/arm/helper.c | 19 +++++++++++++++++-- target/arm/m_helper.c | 4 ++++ target/arm/translate.c | 4 ++-- 5 files changed, 26 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d50..5cf8996ae3c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -54,6 +54,7 @@ #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ +#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 248569b0cd8..aee8f0019b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -6,8 +6,8 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32) DEF_HELPER_3(sub_saturate, i32, env, i32, i32) DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32) -DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) =20 #define PAS_OP(pfx) \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e9c2a2cf8c..56c520cf8e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9345,6 +9345,18 @@ uint32_t HELPER(sxtb16)(uint32_t x) return res; } =20 +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + uint32_t HELPER(uxtb16)(uint32_t x) { uint32_t res; @@ -9353,9 +9365,10 @@ uint32_t HELPER(uxtb16)(uint32_t x) return res; } =20 -int32_t HELPER(sdiv)(int32_t num, int32_t den) +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) { if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } if (num =3D=3D INT_MIN && den =3D=3D -1) { @@ -9364,9 +9377,10 @@ int32_t HELPER(sdiv)(int32_t num, int32_t den) return num / den; } =20 -uint32_t HELPER(udiv)(uint32_t num, uint32_t den) +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) { if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } return num / den; @@ -9567,6 +9581,7 @@ void arm_log_exception(int idx) [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 20761c94877..47903b3dc35 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2252,6 +2252,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNALIGNED_MASK; break; + case EXCP_DIVBYZERO: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_DIVBYZERO_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secur= e); diff --git a/target/arm/translate.c b/target/arm/translate.c index 804a53279bd..115aa768b6a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7992,9 +7992,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); if (u) { - gen_helper_udiv(t1, t1, t2); + gen_helper_udiv(t1, cpu_env, t1, t2); } else { - gen_helper_sdiv(t1, t1, t2); + gen_helper_sdiv(t1, cpu_env, t1, t2); } tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); --=20 2.20.1