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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=m3w3Ow7urHFvFZW+mQsIR7ooKiNtRVZse42MclMGtaw=; b=OPTbOkKjy/FtPtH+7fAGyk6XJWKtXz4CthArruwOdNfzDVbL3B2UzFcYVgj02UaSMy xFoWpm57tTGQvF7pCoxrbEow2Ge2ndUB0tuDlJrMUmL23n/itwsKJakRbLvFZSfQISjy 6ZmOLwBmmFkQDsVJsuLFfy7dgcf41NU9qQDmsv3VmUnnxBDjNLuxlsMlohrHydIozm+z fnbHJNTfAHvO98wWKddRL62gtNYmwN6MbW5sPWH6fEUdWck57ffyuC26mGlONx8mLRiV XAitN+PDrTWltDjq/+ntkqXDiWBNN2X4kZId/d2hFsapUozbPAgK1E6vLRylfImVoySu D7rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m3w3Ow7urHFvFZW+mQsIR7ooKiNtRVZse42MclMGtaw=; b=eAsSDkWlNHtUCuH+3/BcwhXsIkbRC+175gPLDK5RqKTLfSa8UCfPNsyOAOkmm6hyfF uUEm2nwxKuyOte20dZDSjQKcYwFuCLbwftuxyRuWcbT0fBK2u/EK6rRP9X7731E4UqA/ vovCxqVYR2LcuyU2b/Neqp1C+KRQ8cWrIufJuGcclcKwbAqtj7S4dEY7ZTV51pbqyplZ SIM1ixcxmHDboc/XKbjI/r1IPIH0MSbNHlWIUUQIU19M9YL4rb5eflo15SABSRWG9IIE s4TTQ0KjPukc5GPvQ8LavhkX0m0l53TbHqkxBvI1qUNJugdxBT0j1vshbatoY3wVEN3u f6FA== X-Gm-Message-State: AOAM533xUvi4sdFHOnI3C9fdAb70XYhLn6W7zUex21LBP7lOqgoPXy5W P5M2l6Kl/AH4hxlQrf57TEq2pLW1dzPUbw== X-Google-Smtp-Source: ABdhPJyyD7EVZ0t/gN/S2tFibtnUBchqZjmM2knErCWiYhCdtDdYb6JyQbcrK0Ui8/8JUrkzwijXlQ== X-Received: by 2002:a7b:c956:: with SMTP id i22mr2812357wml.82.1629887763739; Wed, 25 Aug 2021 03:36:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/44] target/arm: Implement MVE VCTP Date: Wed, 25 Aug 2021 11:35:22 +0100 Message-Id: <20210825103534.6936-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889047116100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so as to predicate any element at index Rn or greater is predicated. As with VPNOT, this insn itself is predicable and subject to beatwise execution. The calculation of the mask is the same as is used to determine ltpmask in mve_element_mask(), but we precalculate masklen in generated code to avoid having to have 4 helpers specialized by size. We put the decode line in with the low-overhead-loop insns in t32.decode because it's logically part of that collection of insn patterns, even though it is an MVE only insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 2 ++ target/arm/translate-a32.h | 1 + target/arm/t32.decode | 1 + target/arm/mve_helper.c | 20 ++++++++++++++++++++ target/arm/translate-mve.c | 2 +- target/arm/translate.c | 33 +++++++++++++++++++++++++++++++++ 6 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 8cb941912fc..b6cf3f0c94d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env,= ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env) =20 +DEF_HELPER_FLAGS_2(mve_vctp, TCG_CALL_NO_WG, void, env, i32) + DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 6f4d65ddb00..88f15df60e8 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -48,6 +48,7 @@ long neon_element_offset(int reg, int element, MemOp memo= p); void gen_rev16(TCGv_i32 dest, TCGv_i32 var); void clear_eci_state(DisasContext *s); bool mve_eci_check(DisasContext *s); +void mve_update_eci(DisasContext *s); void mve_update_and_store_eci(DisasContext *s); bool mve_skip_vmov(DisasContext *s, int vn, int index, int size); =20 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 2d47f31f143..78fadef9d62 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -748,5 +748,6 @@ BL 1111 0. .......... 11.1 ............ = @branch24 # This is DLSTP DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001 } + VCTP 1111 0 0000 0 size:2 rn:4 1110 1000 0000 0001 ] } diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c22a00c5ed6..1752555a218 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2218,6 +2218,26 @@ void HELPER(mve_vpnot)(CPUARMState *env) mve_advance_vpt(env); } =20 +/* + * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, + * otherwise set according to value of Rn. The calculation of + * newmask here works in the same way as the calculation of the + * ltpmask in mve_element_mask(), but we have pre-calculated + * the masklen in the generated code. + */ +void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) +{ + uint16_t mask =3D mve_element_mask(env); + uint16_t eci_mask =3D mve_eci_mask(env); + uint16_t newmask; + + assert(masklen <=3D 16); + newmask =3D masklen ? MAKE_64BIT_MASK(0, masklen) : 0; + newmask &=3D mask; + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci= _mask); + mve_advance_vpt(env); +} + #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index cc2e58cfe2f..865d5acbe76 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -93,7 +93,7 @@ bool mve_eci_check(DisasContext *s) } } =20 -static void mve_update_eci(DisasContext *s) +void mve_update_eci(DisasContext *s) { /* * The helper function will always update the CPUState field, diff --git a/target/arm/translate.c b/target/arm/translate.c index 80c282669f0..804a53279bd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8669,6 +8669,39 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a) return true; } =20 +static bool trans_VCTP(DisasContext *s, arg_VCTP *a) +{ + /* + * M-profile Create Vector Tail Predicate. This insn is itself + * predicated and is subject to beatwise execution. + */ + TCGv_i32 rn_shifted, masklen; + + if (!dc_isar_feature(aa32_mve, s) || a->rn =3D=3D 13 || a->rn =3D=3D 1= 5) { + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + /* + * We pre-calculate the mask length here to avoid having + * to have multiple helpers specialized for size. + * We pass the helper "rn <=3D (1 << (4 - size)) ? (rn << size) : 16". + */ + rn_shifted =3D tcg_temp_new_i32(); + masklen =3D load_reg(s, a->rn); + tcg_gen_shli_i32(rn_shifted, masklen, a->size); + tcg_gen_movcond_i32(TCG_COND_LEU, masklen, + masklen, tcg_constant_i32(1 << (4 - a->size)), + rn_shifted, tcg_constant_i32(16)); + gen_helper_mve_vctp(cpu_env, masklen); + tcg_temp_free_i32(masklen); + tcg_temp_free_i32(rn_shifted); + mve_update_eci(s); + return true; +} =20 static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { --=20 2.20.1