From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887815; cv=none; d=zohomail.com; s=zohoarc; b=VmkVUzbzbGjMeHlfkDxERIvYMdqXRlsUI/1DY+vmAy/SVeBofAN4SYTbUhrxlhXgcnCfTRsXMQIz9yDJBos4cQ8QfzikbE8e/18BwekJe3BLJfN2mRQY6ZDAGmQ9q8i0FZGLDfult970hql7gt/stS80qLaM0h/Xdb9zdNyM/UU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887815; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=znndHHEoxoWMeYC4H5uF/7NDy7y5s/e+PfCtHxh/c/4=; b=Tr6YARjVC8meFYFLShdCNLRHYiF0qaqdHKeB3g1FPbS5CYjVGdsJr5NuHyPnL0XPpLqZNpvMw4TX3UEBno93n0sWP1m55ugeY/io3dxXdOjNrnVUF5wGPEKFoZTji5DGjjY5jCRvUg7URkTgmL9oAGPF4Rt+mzIB5nSh8omx/S4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629887815832801.2125421864205; Wed, 25 Aug 2021 03:36:55 -0700 (PDT) Received: from localhost ([::1]:39926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqH8-0005Wa-BX for importer@patchew.org; Wed, 25 Aug 2021 06:36:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqFx-0002gp-9F for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:41 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:38413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFv-0005Dr-Og for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:40 -0400 Received: by mail-wm1-x335.google.com with SMTP id d22-20020a1c1d16000000b002e7777970f0so3911646wmd.3 for ; Wed, 25 Aug 2021 03:35:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=znndHHEoxoWMeYC4H5uF/7NDy7y5s/e+PfCtHxh/c/4=; b=ObpU1rLDXh5iamhOA2vqOeowcZO2Nhm6bmenwZOCIIStdF0onSnGDhpb1hJ0jKIxso 4b80agjk3YSo9vsiyCtlDbpRcqQjVqRy8ZUA31Nq19k5UjZpNGCdJSbB5KCICXrmWQ+f TmJBAJYgR99w5BuewByOsBSnKkJGEOnoLJTmHrCRCaw/40ps4xO0GKm5izvnSJ6YN6vb ADWKA3badzufyqV6I+22lP40rJFPZhHR620c/vnpPJd5wk4xvcVBphkPTBgxprkHiMXn orojj2o//JJnnehudWeOG3FNcrL4GgXGl6s6jRtAYzTKZRdrYV03sy6XxAGXsMVPg0Qp qnBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=znndHHEoxoWMeYC4H5uF/7NDy7y5s/e+PfCtHxh/c/4=; b=Ubl/EZZx/IcVtnr8raTBfa3KmOBRH2FQMlFILf+VbxVRF3N2gc3TgiJvip8PUqJs1u ge+oQ0tZVBB45yrTorVrcm3VTjLsDHvc7akw1yHrpOUxF+WlWoStuPYW6+almTIOqpaw lsAOKyYvREJD3ol0QkpBqXvSM9zT4tyWGfX99y9nhOg5TluASp05dMJ29667S2WEfzPO JoLA+Qljlp+5BJV9fTepiqp1yKumj4yye9B6es2FmRyS9iXgf6RzU76CSaF931pUqNOL 1yGFosJL5SHukp7EyIn+JMPZ04Al7/GK7gN7sICjOFZOXrMZni+cg0WFRAs8Nv3cG9lO ZDGg== X-Gm-Message-State: AOAM5320nK6pPOzXKZa1gh3XD7HjMUisT0SGT4eK7RfhqdeStse7CRb+ FDikNmyUjSgzltKH30ErAhbWcd0QQEt+AA== X-Google-Smtp-Source: ABdhPJwV6yssGyO72xqWFb/6fxDbQ63XmKLUadlXQ8yup+xoBxUzbDNgU6Wx6U6bGfwNBHf67BQW/w== X-Received: by 2002:a1c:7f94:: with SMTP id a142mr8631887wmd.34.1629887737447; Wed, 25 Aug 2021 03:35:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL Date: Wed, 25 Aug 2021 11:34:51 +0100 Message-Id: <20210825103534.6936-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887816799100001 Content-Type: text/plain; charset="utf-8" Although the architecture doesn't define it as an alias, VMOVL (vector move long) is encoded as a VSHLL with a zero shift. Add a comment in the decode file noting that we handle VMOVL as part of VSHLL. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 595d97568eb..fa9d921f933 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -364,6 +364,8 @@ VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1= . 1 ... 0 @2_shr_h VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w =20 # VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file +# Note that VMOVL is encoded as "VSHLL with a zero shift count"; we +# implement it that way rather than special-casing it in the decode. VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll= _b VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll= _h =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887821; cv=none; d=zohomail.com; s=zohoarc; b=ghg8sLN9pjHIJ7mLv8jWldvjHpAvzlaCzL2UvF6AazK93/79MCgpVIV9iW9FxFC2jS7plPnyHj/kTdAZKcKvAMF5age3ILIWNFidaaEtKXo+6gEiYoNqsfW9lbr6Ngr5NJyaceyfCea66ZA7UvIHO08AT45OwWZsL4+8w6c+ees= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887821; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X46IYmwDa0Vu+Tiq/N7j9UCGpxEaqTWhGbb7xdBU5TU=; b=P+K9YGGSOtHHGny/ZI0VMu4gOvdkgT51P37gfKestWYEqxcIUyEznFSxIY9iGe5RKqGa+I/fpl5m0DrIBrAKqxjJsHU+U010q4weoM8mvl2Q0C30bEIOC83BGJ03O3iHhmg75kEYK4evHs4X7VJvvpVJEW6KM6YHCPiqHpdhyW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629887821129318.49367391939677; Wed, 25 Aug 2021 03:37:01 -0700 (PDT) Received: from localhost ([::1]:40046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqHE-0005az-0M for importer@patchew.org; Wed, 25 Aug 2021 06:37:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqFy-0002hw-Ed for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:42 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFw-0005Em-0Q for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:42 -0400 Received: by mail-wr1-x42c.google.com with SMTP id u16so35668817wrn.5 for ; Wed, 25 Aug 2021 03:35:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X46IYmwDa0Vu+Tiq/N7j9UCGpxEaqTWhGbb7xdBU5TU=; b=X/m7ikXAgSy7LphyiTEgZRpVREXqQNT+qXf170Jvvv6FBa8s24fJxClFTODQ+3n6Ws m7siw6sYorG7xAc3ht6Q75jtOxMl4TlQmkkj8v4Cd8MghDrPOABqkEU866uJ0o+dN/Yq NLmB/Z/oPAUNU6ah49EvvSBHaYmip66yuJ2xjzYmGFRcydekLAnf4F8zW0gODdpVP13W MDNfsNWpN2+PuT5oaOtYtch7qu6puDUhnRgl9Nd0QJlhEoVCVcr9HQgg6DwN8e6HJTXZ DMfuC8jGffCQcKmqkNRHjjn3r6nOvpTUnHSuC89bD3DKUhBFYz9PNN2olVzOtRsuLz4T EJXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X46IYmwDa0Vu+Tiq/N7j9UCGpxEaqTWhGbb7xdBU5TU=; b=EZHRnyYOoH3MqcA8yrOFTvJ3n4lHmSz4QlzveGHAnrwLnxGrQZfDMoEkSFZKC6tZyb I638xZ+vNgV3M8GTwkdANbDwgT+B7t/IbnuazbKNztzCu+BHqZ7OllnLCNJ2RKmFv3rH Ou6TskWYX6VCEoOPJ4VU5frNimvKeTxMENcY7F9wGiiNJhoWGijmoFx1oYA0qm8Zqlgx /pGhMfyOghuJSS39UP8eWBoOiwLuI36EbkQs91dbbA8kFII77b2PMS63D2wvvcwsjLHC 8JvnNqSMlyGCk00ChyV4D3x5A6JiYtNR/mkQyubrLppDqgra+3mRjgGpij9tut6t6aUv Wddw== X-Gm-Message-State: AOAM5316EEwPnBLmTU8BC9+hDC1GjqFfcjg7erYLRJJnRPkHs5S7oy6K Smwr+j8mPN4oZUXBo7fPQ2VweiDNAJIFoA== X-Google-Smtp-Source: ABdhPJxtr0eF1/m2LYk6qNiCB0t6Wl4FTl80LtV7Drl3K9NvUcxqn61QzB3H7D/DHzUhElFsK239hA== X-Received: by 2002:adf:b347:: with SMTP id k7mr21927125wrd.239.1629887738053; Wed, 25 Aug 2021 03:35:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/44] target/arm: Print MVE VPR in CPU dumps Date: Wed, 25 Aug 2021 11:34:52 +0100 Message-Id: <20210825103534.6936-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887823113100001 Content-Type: text/plain; charset="utf-8" Include the MVE VPR register value in the CPU dumps produced by arm_cpu_dump_state() if we are printing FPU information. This makes it easier to interpret debug logs when predication is active. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2866dd76588..a82e39dd97f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1017,6 +1017,9 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) i, v); } qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); + if (cpu_isar_feature(aa32_mve, cpu)) { + qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); + } } } =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887916; cv=none; d=zohomail.com; s=zohoarc; b=Rvu91+BCMrR5e0+8VJ8biMivtOlyVNfPwPGOv65wjKpVTAZt6rexkiqX7d1abHajYg12pc+af4CbfxPrc2JAgmprX9iUeqdPRiM3MDqrYF9baKg5uecOPziiw1kxcf+oG+NqdmjLY07CYznpMf3XYo7JlDuj8RjW/dgyhcsD2kQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887916; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ovX+gLRUpgJWlCmrIqEwOljYQFDSIUjvrCkTGsB1Bic=; b=L7mHXJiEvnZUPkzGIgbFiuz79Hs2KXL5k4rcX/25qnfCAs74pRAQwD932GPLntuRRWCfTY0pggm2ji5KU9rvj2PCN2xJto1ymKrqz6mViSIuYRiGCkjBRW8f9POpN61Hcil+bxmAK3pz1TfxolKt0rxG5lkYiXZbqu6ogYEIKeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629887916545491.32548284147936; Wed, 25 Aug 2021 03:38:36 -0700 (PDT) Received: from localhost ([::1]:48258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqIl-0002lX-Ei for importer@patchew.org; Wed, 25 Aug 2021 06:38:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqFy-0002i0-I1 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:42 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:40510) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFw-0005FQ-9c for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:42 -0400 Received: by mail-wm1-x32c.google.com with SMTP id x2-20020a1c7c02000000b002e6f1f69a1eso3916776wmc.5 for ; Wed, 25 Aug 2021 03:35:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ovX+gLRUpgJWlCmrIqEwOljYQFDSIUjvrCkTGsB1Bic=; b=GkNx3mW3FavAqcSmL0s0NmrFV9jXOqoMjklEv/Z2FFOcKWfRApXTBuLT2AWwkBa5mh XweJHcUIrN13RLcthXK5c9GKJzVAeBDqUp4RZWBAoDswVLCtxu/M51LiZvd+GD7xdJXf lD2+Ptm7GkiOdJUktBOdjv+H9rU3tJLP/uNOYuECLAXC1WAqT3pd/qe1z0dlut9V8u4N uRzbxLUfQpZ/mYy0REpl/7YKtNprpXoT9r8i0O5xgXh/9MAi3kJkT3Fkks2t4z3LTYi2 7jXhNfMe+zon3SQy5oW6gdLO41LZsSSRn4OIOVInaYxIRQEZ1aeAFdUVuWhboZxeejSg ysNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ovX+gLRUpgJWlCmrIqEwOljYQFDSIUjvrCkTGsB1Bic=; b=Gp/zHqc8sjhKQZE4cSGfI9NeYvR0OWqz1ZI8dht+EU6AvOH+UtYQa3gZJ24HwLGV7B VhEpAlWGH7xLSWxFZkQ/0n26a4fZd69AiXAVjYGVDHVp4J1n0qCcf98J5+/l1bBO5DYh BdQQyp40u+3lGwwQHMk/VTPlj/4XgXOw8rf29fD3GQgFX+NLqnwn1cZU+ZtP+AQD8Ovg +1abkX6U/hGxkoJlT8HZz2WASghr4BmgWL/KrJlwFeE2G8E3kEFcJRl2lBDTW9mrTr74 S5/8vENIMjPgVuBz4M38FpTGixqSba9gRyCeoNEGmnxjEBDdtuONVoSsR2ky7KscqLRE 8APg== X-Gm-Message-State: AOAM5335Ww2ayg0pAeOLpZ4jGj/krBwzjLglYZvPu088BBJ3ZLMgs9JW plMLpSVYUaxy6kfGwog+UopD1MnQm4Asmg== X-Google-Smtp-Source: ABdhPJxymnLlIsbwvbSYtcn+snUH8bpJdwGIa81oS5hgXtoGymlh/ZCLOLo/1OQY7miEgv8WVkY3CA== X-Received: by 2002:a7b:c956:: with SMTP id i22mr2810595wml.82.1629887738769; Wed, 25 Aug 2021 03:35:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by
Date: Wed, 25 Aug 2021 11:34:53 +0100 Message-Id: <20210825103534.6936-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887917717100001 Content-Type: text/plain; charset="utf-8" In the MVE shift-and-insert insns, we special case VSLI by 0 and VSRI by
. VSRI by
means "don't update the destination", which is what we've implemented. However VSLI by 0 is "set destination to the input", so we don't want to use the same special-casing that we do for VSRI by
. Since the generic logic gives the right answer for a shift by 0, just use that. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index db5d6220854..f14fa914b68 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1279,11 +1279,12 @@ DO_2SHIFT_S(vrshli_s, DO_VRSHLS) uint16_t mask; \ uint64_t shiftmask; \ unsigned e; \ - if (shift =3D=3D 0 || shift =3D=3D ESIZE * 8) { = \ + if (shift =3D=3D ESIZE * 8) { = \ /* \ - * Only VSLI can shift by 0; only VSRI can shift by
. \ - * The generic logic would give the right answer for 0 but \ - * fails for
. \ + * Only VSRI can shift by
; it should mean "don't \ + * update the destination". The generic logic can't handle \ + * this because it would try to shift by an out-of-range \ + * amount, so special case it here. \ */ \ goto done; \ } \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888155; cv=none; d=zohomail.com; s=zohoarc; b=gi/Iu3UzUf4AIWhUtvC86sPdWtOu8liROwr9sHOm5Y7NA37pEvyyYKO3zVqQxlJg4o2HPWVpKmXoqQiDdKg5F9aSviqV4GNrVTNODxFVrdOTfj7PoMRUGKd6pCxlNI7cb5vBTjHsgXamvZdR1pZkGUmEe+GqJxNNMArud3dsUvI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888155; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2AKLx+FAZSEHTDgotUySXrnfQs5xm57wonDC26WVk28=; b=N7G4b5LtCquVL2skBNN0T4X4FGG2ocIIQ3X83+nvEUFs67PaVRxLuCPnBYGNnwIfKeZv85S2GqPb2661OOl/Zc/DkPUmvHisBQQ2DA/PttQtRRSW+7sA9/jZ2kNqdXpyv/vVet527K2pCoV7K2xQPW25ZvtkwgntOvdsAGBaRW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888155755908.7422203955355; Wed, 25 Aug 2021 03:42:35 -0700 (PDT) Received: from localhost ([::1]:36488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqMc-0005YI-C0 for importer@patchew.org; Wed, 25 Aug 2021 06:42:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG0-0002ol-L7 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:46858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFw-0005Fl-UG for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: by mail-wr1-x429.google.com with SMTP id f5so35618160wrm.13 for ; Wed, 25 Aug 2021 03:35:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2AKLx+FAZSEHTDgotUySXrnfQs5xm57wonDC26WVk28=; b=fmBA4Xw6AqYFEkMqpmR+skkqbQwxJdO4/iYbpeMmwjvjzmPDRg9WJc29DmiU6qE4Sc KxyvZ+ig66NlNPSKW1WydpFXqg4+EgKD1tnJmE46tt+lRsxmZPA0qMgc5yQ4CxX8YxNM ghPFmArJ2njMDQ2P0B6Np7nvfndhKUG+Pn41jDbaVvJavxpSXKHb7gIVYVe5r80kbX8Z li6fQbM02RwibD1naerWqL1iLWBb4ENcGt5U1xFkVBktmtWHHd6GJ8RxjNT/JUjICiQw u2aSB3mLrZSkP3WYZXpCqtOljmgSP2OlR9uT3tr+59b/AdqfWbqY2UbFHTmoBO2F2CmJ 5rpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2AKLx+FAZSEHTDgotUySXrnfQs5xm57wonDC26WVk28=; b=Xext1ApqlsUGgh8F3hUlRSkYwvOExDdE3J8xwlAOB/AnpJl4bY0HABuC06KuO2+yWJ dl+LiC1YTwP4ElObDw4JVMGD4uy6YjJ6aphqnExyhHLuHykdFaLe+UnRDP35gE54FQ9z dsZpE8NEkiUh9ZagKpgPbLcaMB6fWZ4z/Mhr+guKMyZ3utWmOIn5wlI65yVz+5CUDSWo UQ+qYcInohTmMJ3Q0G726ZvHE0yBg4eZqBs4Llkx+wZHclWCyUkdHrm4hP1diu0Ub1zP 0844zwtCSRZi9ivZBB8u0vbKwSCKpIJE0+l9ilyVMI+t+g9dWEGuSQhpohORSQG1rXxP actQ== X-Gm-Message-State: AOAM533L3sWOeoXyQFQivROm2lnBnikjkjfgcKPrWWvmKmnpLuTwt9L2 fWrxmGEBaLW7JChnTjdKjE6yg7kffG1Lyg== X-Google-Smtp-Source: ABdhPJy6WpeGxymio4FcUprMVAaP0eeqRT1lh/6gdlymlec/3dmZ6OXsySjG/9UP7dCYR9JMo1U64A== X-Received: by 2002:adf:f991:: with SMTP id f17mr11535965wrr.56.1629887739372; Wed, 25 Aug 2021 03:35:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/44] target/arm: Fix signed VADDV Date: Wed, 25 Aug 2021 11:34:54 +0100 Message-Id: <20210825103534.6936-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888157175100001 Content-Type: text/plain; charset="utf-8" A cut-and-paste error meant we handled signed VADDV like unsigned VADDV; fix the type used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index f14fa914b68..82151b06200 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1182,9 +1182,9 @@ DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) return ra; \ } \ =20 -DO_VADDV(vaddvsb, 1, uint8_t) -DO_VADDV(vaddvsh, 2, uint16_t) -DO_VADDV(vaddvsw, 4, uint32_t) +DO_VADDV(vaddvsb, 1, int8_t) +DO_VADDV(vaddvsh, 2, int16_t) +DO_VADDV(vaddvsw, 4, int32_t) DO_VADDV(vaddvub, 1, uint8_t) DO_VADDV(vaddvuh, 2, uint16_t) DO_VADDV(vaddvuw, 4, uint32_t) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887823; cv=none; d=zohomail.com; s=zohoarc; b=QI4PlneX93NvP9qGivXkxuW9HuPrntfgB69ihHMY2YotM5/5CUV1BD35HxYGKrFVm5ImHk6cTsNqk++hHf0vczxd/LO4crCV+L58J55MliPGUIV8HCUIvUYKKyl1uEYwF+e8octB9ORjM+kB26dwbaGnSNPi4IQesFMX8/pzATc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887823; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AdQbpZh4Nsn4ZEWXMN8/5MXfv9l4tGOGQ949NSeXfXg=; b=doK8h1pHDpGB5BPjZAoEYwqQzivSbYdY+jSjeEfygPs8iN2owfHEFFgKgbCkgv0mlgx6n8SGdQg5eqlvXVFbX/8YhxcSNFd5+nhaDUJaRU4onEfEsDafoYGNcbhARAo9ukuhofHmSGWR9RoL/gHvVBrNcv1/S3XhRwYbeCWzK78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162988782398053.533538668975325; Wed, 25 Aug 2021 03:37:03 -0700 (PDT) Received: from localhost ([::1]:40356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqHG-0005nX-JP for importer@patchew.org; Wed, 25 Aug 2021 06:37:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqFz-0002m1-UH for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:43 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:37475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFx-0005Ft-H9 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:43 -0400 Received: by mail-wm1-x335.google.com with SMTP id c8-20020a7bc008000000b002e6e462e95fso3921116wmb.2 for ; Wed, 25 Aug 2021 03:35:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AdQbpZh4Nsn4ZEWXMN8/5MXfv9l4tGOGQ949NSeXfXg=; b=Sb2kzKedAI20nwsZqEpzaLIlrTxfpyLtft6cetmP2ACPMIcE924qu3jwL3Ix8fSCwq 4kfxBJnIcaSH3V4YKAo6+5oyD5lM2OL4NxAxH8pft4IXIiFsq/gesoiOIoSAKUqVutX5 4zxNYR6LgJxOzu2WPUOy9VuLYnE8ezBKYhGQqY/V4yxLxiqKEs1OF4Yz2ne/gf9QtF4F mhOQj6bVpP+Ni1YDSaevAYxGfJ4y1BnTsELxtQhyvrxK7uUfB6cMfvzJxnQFJ9MKTkH/ m4DkjbDSPWe4ywgINIlBAu5ayXVgiI+dMMC+Z0ESS4Xhh8is2SEY1YCvEW1g7P73mP8p 0B7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AdQbpZh4Nsn4ZEWXMN8/5MXfv9l4tGOGQ949NSeXfXg=; b=SydBe0GAkgaO1ciCH8tOiyl+w40SCWjbCsacgFCI+/8cy5J7bqCM7bRLe2DcM3tP1A QSMwtN9gdE79mAtaFn0QIR837Prc7r+tytat/ND2nJrBY8l2i3A3f1afUblVujeA1Cpd L5emzuVKGprSYG0S3WWsEVKr4qvdJ8s8VUQafuNvgBDFcvYJwj3S4xQpnJs8qPI1zgSa oTsxdMwxGmtacerjud72ynOINsLBR6MgmgWGduDMKM158H8pW8sFnL34+mhUqrWyd953 xyNQ3pcvEFSRuljmnEIMdYWbGaEYSGg3t8NBtCFan22BIYUaRBmzGk+Rmm4O+12CUV1n vRlw== X-Gm-Message-State: AOAM532I88i3r9XZp6S+CqwCDU3SCwQGYI8yDQTg1pbT+flFis5crMdj Pww5XRlnz4O9XyE4E0m4wZqE3SR6JZInXg== X-Google-Smtp-Source: ABdhPJyomkbti62gZqlzJ1sAxjLMkj1PrR+QYRz5hIYvQYw/FD0JY7Du0Q0uKWUUucK9KkDguW29jA== X-Received: by 2002:a1c:9d8f:: with SMTP id g137mr4155016wme.187.1629887740069; Wed, 25 Aug 2021 03:35:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations Date: Wed, 25 Aug 2021 11:34:55 +0100 Message-Id: <20210825103534.6936-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887825086100005 Content-Type: text/plain; charset="utf-8" In the MVE helpers for the narrowing operations (DO_VSHRN and DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for the 'top' versions of the insn. This is because the loop works over the double-sized input elements and shifts the predicate mask by that many bits each time, but when we write out the half-sized output we must look at the mask bits for whichever half of the element we are writing to. Correct this by shifting the whole mask right by ESIZE bits for the 'top' insns. This allows us also to simplify the saturation bit checking (where we had noticed that we needed to look at a different mask bit for the 'top' insn.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 82151b06200..847ef5156ad 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1358,6 +1358,7 @@ DO_VSHLL_ALL(vshllt, true) TYPE *d =3D vd; \ uint16_t mask =3D mve_element_mask(env); \ unsigned le; \ + mask >>=3D ESIZE * TOP; \ for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { \ TYPE r =3D FN(m[H##LESIZE(le)], shift); \ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ @@ -1419,11 +1420,12 @@ static inline int32_t do_sat_bhs(int64_t val, int64= _t min, int64_t max, uint16_t mask =3D mve_element_mask(env); \ bool qc =3D false; \ unsigned le; \ + mask >>=3D ESIZE * TOP; \ for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { \ bool sat =3D false; \ TYPE r =3D FN(m[H##LESIZE(le)], shift, &sat); \ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ - qc |=3D sat && (mask & 1 << (TOP * ESIZE)); \ + qc |=3D sat & mask & 1; \ } \ if (qc) { \ env->vfp.qc[0] =3D qc; \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887917; cv=none; d=zohomail.com; s=zohoarc; b=MiC6QX7HKQu5NihNnYXRtJYZTZYocps/NZIzyqhC6MzKmUDiU8RS/eV0C7YPKRSZSUcuW9WZ5hiwtXPrdE14HE5fycG7ZP/9xXehWE0BR0+Npqqj8KDePNpsnzqvxdlRgYI4clpD+LjsFNMznRdiXQXkCWaR0IZ1KhI63MSXm+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887917; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SngGo1vVY/dtcXAMZ+FWnV5QnI/yJF6vZ4XQ33WiT+w=; b=CExWNeTBaV/4uAkD+3usreDJSAqTyo04H9+GJcF+P2htNRAjE/vY6AOXLDNMxXHEwwJbM0mRNYZoV3G3g7jCrJYYKlDcccaLBfotUHcBrB/aIS4eQHf3co4Cy6gkQh8IapRBZBhEmgoYDBIevS3sd+5+0PB74qk0HnGhqQJr5rs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629887917522830.6851102868854; Wed, 25 Aug 2021 03:38:37 -0700 (PDT) Received: from localhost ([::1]:48320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqIm-0002nl-D9 for importer@patchew.org; Wed, 25 Aug 2021 06:38:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG0-0002mh-3J for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:42575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFy-0005G5-2M for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:43 -0400 Received: by mail-wr1-x434.google.com with SMTP id q11so8711981wrr.9 for ; Wed, 25 Aug 2021 03:35:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SngGo1vVY/dtcXAMZ+FWnV5QnI/yJF6vZ4XQ33WiT+w=; b=pZdogSgJ/TB3lZjG1JLJWkiEBT1JGwqd4sSClEMumLC32SPTF1YMGZcVouXtANP8p+ Jku87yUA4OFrDKGcbw7AZ2AOIVKUdbvCDQZ08fG/kwguB9s/s9eHdBz1g51DV+XGa4or fYPWkqYLIXqeddMS8ko2JsRgjLR7k8RYAwY+U17ojbeC/9yvJgU4+W0JssOwCF5cUcRw m2dbfZ5rTiCOxqjKTLk6IYB8JeoUc3DubXJr1HhtYfDoGxdQrWnR8yKWgwkprVRfkVy9 QzBnz3dyj6UlXcj9tAoXTUml9JTz/+gS93etdnOxNPEDpEPeSBCOGkRT2JAEQLitsqO5 mVdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SngGo1vVY/dtcXAMZ+FWnV5QnI/yJF6vZ4XQ33WiT+w=; b=F/8nxOg/i0NXbIjJsmnYsJfW4lZHJ7AznBkXd6XBDKV0fqYpUD4wNNtydJMjMohoIc K1a13Zy27MBqV5IykA2drcT5EEf+/hnMvQaRw7hVL63JxVjLu21R811kA8TIfLWjBODU 1ydOc0FPT36tOMUBCPBYatV/PlnNWxZ9u44kEdoUaMz56PCMjQ/8cfs9odOMhTgvWQer h1HX7qNthN4h+5S/GqfeKKQO+6b2Wgr+4ky/bsAdjX5d/mwtm5k59FScCqFnM7E+vaio ScCGrP1GBUat7qkPdkEXRI28pBQiNftZuqnthWI6s3UzIQyAK/CC0b6/93tNNiw6Ggb/ 2Bqw== X-Gm-Message-State: AOAM532qxQkZxGVJOZ4T5ojHH7WFtc2t8znf+TgroUD7joW0BK6Csnce 6TdoYPNrrVEOXCsUsGFz+7TpO1he8eLEEA== X-Google-Smtp-Source: ABdhPJzjPd4x78JWdF/S5lz1D1zQJUNFVVe56APqXRMgV/LGbQbmZ9SAUOJ2753CA6eDw3wUaLD/MA== X-Received: by 2002:a5d:5983:: with SMTP id n3mr14864356wri.227.1629887740722; Wed, 25 Aug 2021 03:35:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/44] target/arm: Fix 48-bit saturating shifts Date: Wed, 25 Aug 2021 11:34:56 +0100 Message-Id: <20210825103534.6936-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887919566100005 Content-Type: text/plain; charset="utf-8" In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge cases wrong and failed to saturate correctly: (1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs() does to obtain the saturated most-negative and most-positive 48-bit signed values for the large-shift-left case. This gives (1 << 47) for saturate-to-most-negative, but we weren't sign-extending this value to the 64-bit output as the pseudocode requires. (2) For left shifts by less than 48, we copied the "8/16 bit" code from do_sqrshl_bhs() and do_uqrshl_bhs(). This doesn't do the right thing because it assumes the C type we're working with is at least twice the number of bits we're saturating to (so that a shift left by bits-1 can't shift anything off the top of the value). This isn't true for bits =3D=3D 48, so we would incorrectly return 0 rather than the most-positive value for situations like "shift (1 << 44) right by 20". Instead check for saturation by doing the shift and signextend and then testing whether shifting back left again gives the original value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 847ef5156ad..5730b48f35e 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1576,9 +1576,8 @@ static inline int64_t do_sqrshl48_d(int64_t src, int6= 4_t shift, } return src >> -shift; } else if (shift < 48) { - int64_t val =3D src << shift; - int64_t extval =3D sextract64(val, 0, 48); - if (!sat || val =3D=3D extval) { + int64_t extval =3D sextract64(src << shift, 0, 48); + if (!sat || src =3D=3D (extval >> shift)) { return extval; } } else if (!sat || src =3D=3D 0) { @@ -1586,7 +1585,7 @@ static inline int64_t do_sqrshl48_d(int64_t src, int6= 4_t shift, } =20 *sat =3D 1; - return (1ULL << 47) - (src >=3D 0); + return src >=3D 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); } =20 /* Operate on 64-bit values, but saturate at 48 bits */ @@ -1609,9 +1608,8 @@ static inline uint64_t do_uqrshl48_d(uint64_t src, in= t64_t shift, return extval; } } else if (shift < 48) { - uint64_t val =3D src << shift; - uint64_t extval =3D extract64(val, 0, 48); - if (!sat || val =3D=3D extval) { + uint64_t extval =3D extract64(src << shift, 0, 48); + if (!sat || src =3D=3D (extval >> shift)) { return extval; } } else if (!sat || src =3D=3D 0) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888049; cv=none; d=zohomail.com; s=zohoarc; b=SIt6BSN9J4OiCzGXrLL69quHcfcVvZ4pnnlW3Eme5hn0udBwHnxUwO+LaWT2LUZiYraWXial7d2FnwBip+0G7dNEyqEEn7VB/KbM3ZPdN4oMjA/t/fMB0ZWj2cn/uon8oM4c82hX8wGTihTsDl+TuV03LWv1KhVELD787ziZaz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888049; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sUJ1aC1phOvDbqezcommWBZIEjhB/McSlKBhbLrt+C0=; b=b+GrxHJVXNJ/3AKsbbEOG76nQrH+wKdw7gAi87hDJMsFZU1agZPKEk28rF5jL8pMz/U2Nj+eVC0mZsUqbKjH1ZORIkQvawX5Bw0xslO7QkusWSOLYy1StVghfEJyGV3oAaX7/OhBmY4B7w2JZRtj4fJijRO5iZMNkI9wThVoxmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888049566161.24048054553123; Wed, 25 Aug 2021 03:40:49 -0700 (PDT) Received: from localhost ([::1]:56498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqKu-0008Qw-6B for importer@patchew.org; Wed, 25 Aug 2021 06:40:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG0-0002oI-Fk for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:37465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFy-0005H0-QC for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: by mail-wm1-x32a.google.com with SMTP id c8-20020a7bc008000000b002e6e462e95fso3921163wmb.2 for ; Wed, 25 Aug 2021 03:35:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sUJ1aC1phOvDbqezcommWBZIEjhB/McSlKBhbLrt+C0=; b=ooy6h3zQPvYteRWIrvCUxuE4UAmETQENJtEt/Qxa+8zEg2MjnlUjrwsFKAicFO4ulF urGFfchDMxINuCZOe7qky4EULzBdGKayfQ8K4Gc6UK4+a0t3y5db0+bAI3HS4A8VReMs 9jjz/b2zISUto7sG2+X0uWKm9d4TO2hYoumEJzRq1lsm57knXDiavcLzwk7dnetERvqt /JgOvVeqP0NhVaKbIXVQsIF/5iP0tbrTkMo1Bo138n0don/bd34d6IYXvaH7DvcIb8Wg R4aSLHmfhrzXZn4y2oHGAnO4/Zf/M5UhPK+fBEIv86RQ/tUOPtFKZDYSb44sapmJafWm qP1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sUJ1aC1phOvDbqezcommWBZIEjhB/McSlKBhbLrt+C0=; b=Xu7EyWBEe4OHSNISDl9xjEUbc0Ucu16a+K0qBFfpBgDsPbmh4728hLwkcrK0+kojTe IqyOsHMmHtrjXYROsgt5KvxfKRCFbT24kIo9wzpKJ9EZ2DXlGF7uVsVGcIVUrqmfNPW6 QSmZXf4TFoNlvDvrMnYscC7N1hJE+4qpW8tLAyzFUubhd0UpkwyfyEDyX9LjxlzrcLEp EqiJpd/r1iIp9ZlRfoNFjnxQRzvscxRWnCSrHDcBqU9FROJdaOiKia/WFW6aHFmoxqym aCCClnBUjeZs7jAPnGhYo7z1VUO7yC09mtQquT+sG3GxZf4YQWWUu1Hu5YaPnbBrlWP9 HOiQ== X-Gm-Message-State: AOAM5331TY9Jd3twnD7X1HciFfdyez7n5UiNni6xtnPaq16ke1qzwn0r TVZ5/7TqGND276SO/tCSCBeVoepW79A8ng== X-Google-Smtp-Source: ABdhPJxpLRhce8PCadLl/UPuXRCt33tnycWcPhcRiOtR+qnFsspyTywa7i3dv3ZSjRgzyzbPb6WGVg== X-Received: by 2002:a1c:e912:: with SMTP id q18mr8615384wmc.21.1629887741381; Wed, 25 Aug 2021 03:35:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts Date: Wed, 25 Aug 2021 11:34:57 +0100 Message-Id: <20210825103534.6936-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888050862100001 Content-Type: text/plain; charset="utf-8" We got an edge case wrong in the 48-bit SQRSHRL implementation: if the shift is to the right, although it always makes the result smaller than the input value it might not be within the 48-bit range the result is supposed to be if the input had some bits in [63..48] set and the shift didn't bring all of those within the [47..0] range. Handle this similarly to the way we already do for this case in do_uqrshl48_d(): extend the calculated result from 48 bits, and return that if not saturating or if it doesn't change the result; otherwise fall through to return a saturated value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 5730b48f35e..1a4b2ef8075 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1563,6 +1563,8 @@ uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64= _t n, uint32_t shift) static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, bool round, uint32_t *sat) { + int64_t val, extval; + if (shift <=3D -48) { /* Rounding the sign bit always produces 0. */ if (round) { @@ -1572,9 +1574,14 @@ static inline int64_t do_sqrshl48_d(int64_t src, int= 64_t shift, } else if (shift < 0) { if (round) { src >>=3D -shift - 1; - return (src >> 1) + (src & 1); + val =3D (src >> 1) + (src & 1); + } else { + val =3D src >> -shift; + } + extval =3D sextract64(val, 0, 48); + if (!sat || val =3D=3D extval) { + return extval; } - return src >> -shift; } else if (shift < 48) { int64_t extval =3D sextract64(src << shift, 0, 48); if (!sat || src =3D=3D (extval >> shift)) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888268; cv=none; d=zohomail.com; s=zohoarc; b=AiECTwfG8RpVBN+Z5EPGNd3vyzBeZvR5rt5J6zcowCYY8iB2x9lTsx35L63lQlpF8edbFQNPzsvimq234pHaPyYf8kU2BS3sFb90eymmuz6vLt04LXCl92j3nNRF6UX3zGB/jAMKyPMc1Vv2T+crDAzib8fR+owQdijJI8bb830= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888268; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lutAo5Z1ewFuThzfMPVLqlhd9Ml/H60A8yYUE67fuT0=; b=ijcJ1svBBPKh48DRWAfXrJUFww/xplFMDyndzXqmoEDFGnMN9q7ZXiPBM5OOGKgZjPEjiTPSDJ3Jzj8/8OmV4mOLkSbPHXMxRnKU3dJyYhgA4wiWjmZz3ZAIy3YjcwSM61Vl3l5K/eijeV+xOQOOSyYL5Xefvdut5tE8dwg46oM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888268548630.8331173894541; Wed, 25 Aug 2021 03:44:28 -0700 (PDT) Received: from localhost ([::1]:44670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqOR-0002j4-6L for importer@patchew.org; Wed, 25 Aug 2021 06:44:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG1-0002qk-5S for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:45 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:55833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqFz-0005Hw-Bb for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:44 -0400 Received: by mail-wm1-x32f.google.com with SMTP id g135so5368693wme.5 for ; Wed, 25 Aug 2021 03:35:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lutAo5Z1ewFuThzfMPVLqlhd9Ml/H60A8yYUE67fuT0=; b=mm9tNkR9OIqyJPFUrZnvmil8drl/kr+K0iJQ1KY1Yh0uO3mMqhed4zoNvc/WtRWCiZ uw/bx1hrZsjjvNui9DXdsT/UToTp+YmZXrn2IzIG9JYHWCb9WcJZxM1KJGwipkRGhG9O KqLKd1w0r+Q9jsDvlY8QHWPch22RdP7LqYNpxrQwHxxGeWReKRHFg2xlSkz2rteDGKPd rJAUtIa/bjPHhdyhvFYSx5ugPIt4jmFdfNl7/muiMBIcttjpEoj32+RMo4ZIgC73rg8T +9Z3Jw0V58N1W7JTLzJYfgWWeqdL+s5VqUlxyQPWgCvkvrzxc6JAUItVrIKhoQCBGglL DJPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lutAo5Z1ewFuThzfMPVLqlhd9Ml/H60A8yYUE67fuT0=; b=RI+T3nLeWAa8LXZMr9rcCHcyOviw/MKuE2DVVPvvHSDS/Xm45CkdY3vCN18/vUEHdE fHpWVl/dtLbHrtJBN1bgUAqf8cUiGcVvcwY6gS9HI2gSFNGEqdSuijqOsqWmRTVHsgz7 rnaFpXikAVND16q3y5UducqkjWZJSRT2grCtuPkPZO5MKOhb/ZPInTiDBVx/6qo1qecC wV3GN11rQklqWnHAkONKnGFL4mr/8SOEgSzblw9DH+v0qddd7u/5zSs+XUbYrVuKrO/f bTOSvtXqc99pd7wXo3G+gQyhSn5FGN2hN+PGiCs6B/pgCpoxfkD1LSD11xiIEWQHIlGh XQdA== X-Gm-Message-State: AOAM531X0E8vSdZjPdQydOtR9lhacOsQc4uEFvmR3WLE6zIUmMISQWij bLsK4v8yqE+pBmFfVYGdpFsPwvl0qtZgQw== X-Google-Smtp-Source: ABdhPJyoqpRoUAA3lhHKCv7Kbsc+t1sHDAcpx8uzZ1/n4TC9taB6MhmR2rmfKYUzuaHCUmyz5f38og== X-Received: by 2002:a1c:2285:: with SMTP id i127mr2892743wmi.64.1629887742017; Wed, 25 Aug 2021 03:35:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0 Date: Wed, 25 Aug 2021 11:34:58 +0100 Message-Id: <20210825103534.6936-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888269785100001 Content-Type: text/plain; charset="utf-8" In mve_element_mask(), we calculate a mask for tail predication which should have a number of 1 bits based on the value of LR. However, our MAKE_64BIT_MASK() macro has undefined behaviour when passed a zero length. Special case this to give the all-zeroes mask we require. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1a4b2ef8075..bc67b86e700 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -64,7 +64,8 @@ static uint16_t mve_element_mask(CPUARMState *env) */ int masklen =3D env->regs[14] << env->v7m.ltpsize; assert(masklen <=3D 16); - mask &=3D MAKE_64BIT_MASK(0, masklen); + uint16_t ltpmask =3D masklen ? MAKE_64BIT_MASK(0, masklen) : 0; + mask &=3D ltpmask; } =20 if ((env->condexec_bits & 0xf) =3D=3D 0) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887920; cv=none; d=zohomail.com; s=zohoarc; b=btpgnjZqBWAL/wTuVjw6XhrLX0n6YEP7JcaPOciQHliOXa9MwxLkA1C+ei7838lNHDMMEXgeKCQXb28BQkbk5WiNfJLsAd1B6JKTevwCytz3oyZCLK5BA040v7rAKk38mqpa/j4CrDrCQz5tqexKvwb/b8/2BHsGxvusXCJI37g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629887920; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NumtafSnEiF4kjNIFtDKTqX8sKZowsVsCRz2Ds8yzEc=; b=Ve5Bb+6MnhxIW5p0WZembL0fRtPkbDTsX3BZhImjr5sblr7T4N2XB5NRlXMfNKwWrOMAT5nIgNYUTmqbqOpM7utyski6pPe5qxCTfAW9hVKrWoThLqUsgwj8+4Z9smTM7/FlmUD/GLKshiOagoPlrB9UlhtzA2MAoG198HYdTvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629887920419731.0605289706647; Wed, 25 Aug 2021 03:38:40 -0700 (PDT) Received: from localhost ([::1]:48698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqIp-00032u-D4 for importer@patchew.org; Wed, 25 Aug 2021 06:38:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG1-0002t9-SB for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:45 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:51070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG0-0005IK-0E for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:45 -0400 Received: by mail-wm1-x32f.google.com with SMTP id m2so3047727wmm.0 for ; Wed, 25 Aug 2021 03:35:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NumtafSnEiF4kjNIFtDKTqX8sKZowsVsCRz2Ds8yzEc=; b=Q00bWC1j9AxWPShu8c6Quhs4xblHUmAJJhkVuPgzaO95Ei/jr7ef0xXqJ0wLGaxhv/ xUh0aZtc7GNoqhmWOFkzmBXHBn76n6vlSafL/xzf1rSLhPBCHZALHR5HC5jjEWiI3KeS tvKf8zU3gPYQfkp72enQizATqwSYexagGo6Rlke1JhLK5Fcy9SlDBBa5Pp6ZtgYt78M6 2dm7rZVYruMhWU2IfrwSn+pv7+vOvk/BtKF7is24Nyw185PV1Qi350D36pKEomHc6rW8 CMpqYz53Ew7+BQyxhnRyAYVe+Ri0uocAUbZMkCJPLa1SViZkkIA/Mh1T5ExU7+vz3lEd AEeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NumtafSnEiF4kjNIFtDKTqX8sKZowsVsCRz2Ds8yzEc=; b=E61aZSujrFwYA+f6UIYPef+8Cyr4wF2E0yVKzZ2akB0qSKpO3PvR0arwbOAOhbmGvd emBsgYtTWyC9QBFwpGH91Dy2/DVdyB9bck1YUkrMSXvG2pfH4tbaQ291pbKOn8CwGf+X +ItzJGAuYagcrZ1ZWyBzqwASltHqB5OMuc3402LuqaTg9/tndwvU/5/rXE2685Ky+Plv N7gZN28NVQjtQnOuu21a9wXhwI+pHRU9CHt1ci2fIpy1/zCiKhXhZo5JrUGAXGM3ulQD iyyIcq0gioCV/wMRoFfWYWdrWOp4MvxPLWVDSUT9cSyMQBhRgN9rlJ0vt/qE1EcObYj+ hh9A== X-Gm-Message-State: AOAM5327UhQxJNBqz4kmXInmpsdQ6+bCQNDunf1zEDsQ2i3sOFVvccLR jYs5NJkeIUB3G2/wz7AB4YiI9Vw8VDj6yg== X-Google-Smtp-Source: ABdhPJxXbaS7qKc4rPyRA31pivBts9PUFYXPqLMIRwHKPxaofUXo3bZzTcuOpwl+dTDeZh1WdVp40Q== X-Received: by 2002:a05:600c:4b92:: with SMTP id e18mr8442566wmp.156.1629887742685; Wed, 25 Aug 2021 03:35:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/44] target/arm: Factor out mve_eci_mask() Date: Wed, 25 Aug 2021 11:34:59 +0100 Message-Id: <20210825103534.6936-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887921877100002 Content-Type: text/plain; charset="utf-8" In some situations we need a mask telling us which parts of the vector correspond to beats that are not being executed because of ECI, separately from the combined "which bytes are predicated away" mask. Factor this mask calculation out of mve_element_mask() into its own function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 58 ++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index bc67b86e700..ffff280726d 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -26,6 +26,35 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" =20 +static uint16_t mve_eci_mask(CPUARMState *env) +{ + /* + * Return the mask of which elements in the MVE vector correspond + * to beats being executed. The mask has 1 bits for executed lanes + * and 0 bits where ECI says this beat was already executed. + */ + int eci; + + if ((env->condexec_bits & 0xf) !=3D 0) { + return 0xffff; + } + + eci =3D env->condexec_bits >> 4; + switch (eci) { + case ECI_NONE: + return 0xffff; + case ECI_A0: + return 0xfff0; + case ECI_A0A1: + return 0xff00; + case ECI_A0A1A2: + case ECI_A0A1A2B0: + return 0xf000; + default: + g_assert_not_reached(); + } +} + static uint16_t mve_element_mask(CPUARMState *env) { /* @@ -68,30 +97,11 @@ static uint16_t mve_element_mask(CPUARMState *env) mask &=3D ltpmask; } =20 - if ((env->condexec_bits & 0xf) =3D=3D 0) { - /* - * ECI bits indicate which beats are already executed; - * we handle this by effectively predicating them out. - */ - int eci =3D env->condexec_bits >> 4; - switch (eci) { - case ECI_NONE: - break; - case ECI_A0: - mask &=3D 0xfff0; - break; - case ECI_A0A1: - mask &=3D 0xff00; - break; - case ECI_A0A1A2: - case ECI_A0A1A2B0: - mask &=3D 0xf000; - break; - default: - g_assert_not_reached(); - } - } - + /* + * ECI bits indicate which beats are already executed; + * we handle this by effectively predicating them out. + */ + mask &=3D mve_eci_mask(env); return mask; } =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888412; cv=none; d=zohomail.com; s=zohoarc; b=XeZKqV0nvyt3Xh/4DKoXrnrynIftb0MYMOojmJBko87p74EJIpRBr8bgZC0M+izCHO+FalTk9kGB1opbMW6m5M00gufReu7zaPpaC5ZVqs1mqYtaeox5VNAJVTS8r2nr6N1W6Pgev2Yorg5Y2PqaYbHP39KQ6KZjJvjkJoofI1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888412; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8qIE5oE1JZoICFhq6qSEMy1TMT2jNqxyN7BxrEyKPnk=; b=aUC8KGvfJEXkhYLoFeJxY09kWNKarepdqptLIDkUzJKRay1VOAkbYfhaMAI36r+zdLPpgcl4hM4vEs4WCCqGv5UZRc0fKyLPL6Lgnt8H3XDcICasJYI6voMOgTkmCw23t7GehMHPnmXiqrcftzpFWH7zEjtUypo4c/apf7kGCXo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888412755736.8063201969111; Wed, 25 Aug 2021 03:46:52 -0700 (PDT) Received: from localhost ([::1]:52942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqQl-0008MK-Ic for importer@patchew.org; Wed, 25 Aug 2021 06:46:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG2-0002vI-EI for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:46 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:52899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG0-0005IS-Op for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:46 -0400 Received: by mail-wm1-x332.google.com with SMTP id f10so14670999wml.2 for ; Wed, 25 Aug 2021 03:35:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8qIE5oE1JZoICFhq6qSEMy1TMT2jNqxyN7BxrEyKPnk=; b=dd9Ds+meriI9xZTes2q/4EeCeLljWB7PI2jqoIDVO/2ar0+PAD0hK8Rx7MZukZUi7T B+NCEJouOQcBaIZOkzDGOfMDpWovpFsWH7V1CarhNeUkbrEFpD+B9X3sxcMWtwULe0zm zgA1FNe54XfiYnpoUMmGg9x+Fx+75TrZZRWYM92yPooZ5HhhGNRf9GDfcjSg/u1vAfBi 3xXjEFGGmomaJYtKGrsBBmxkew/PiQo29nRFcSJYqAPBwKyUbtmH+BeyQqLl502sCrtP 3wXaCUEvIf1Jq9/FkOV3B0iVo7Hcal2uKjK7pQa1U0y9JNdROInSbPcGlYpZRiCHPKLj Z24A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qIE5oE1JZoICFhq6qSEMy1TMT2jNqxyN7BxrEyKPnk=; b=C6finHRiNK1ZArTENtMMt+XKgYloCipWz+cgd1HgZ1RMkkA69/ntwxOQKB87RL/TPl /ooK6WlUKVVOD1QZX4YzkYmlNfmzDs8+Xfr2bQLxJWtt5w7fmLQJPgkfe81EbOdKjNBu JDJ2LME25jtdOp3cr2boO1e+dDT2eOyNI7TT4jA0LJ9NPZJUejVud5YaoHTiK6zCmtum +KHsO/NllRBDlKDPB4aovuFNGLZap4EyTGF23RPEiO1eUKq+54FnhJ14tlDNjpFcncwl F+kHb7ZIOm+tfss2B8hUq0gyRc1V3DmBuRT1UJX1UjfcdqWm+u9oGdyGv+/F4XV6hSLZ IK6w== X-Gm-Message-State: AOAM533DB+lCchZNJbHNocuWMmWvy2ALtptJe4UpE1yg8vRYlsW7LuZM LWVBW0zWfq6N6vRjvwVpGOsOsbQ7KXgQSw== X-Google-Smtp-Source: ABdhPJxHp7pOyKPLlGTBmA1Q04TiIVgDV3i0N9AO2VIoFf0z1CPA0vgDAeGEgKyYYQmRXo1fp5A2Dw== X-Received: by 2002:a1c:28b:: with SMTP id 133mr3303473wmc.138.1629887743294; Wed, 25 Aug 2021 03:35:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero Date: Wed, 25 Aug 2021 11:35:00 +0100 Message-Id: <20210825103534.6936-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888414984100001 Content-Type: text/plain; charset="utf-8" We were not paying attention to the ECI state when advancing the VPT state. Architecturally, VPT state advance happens for every beat (see the pseudocode VPTAdvance()), so on every beat the 4 bits of VPR.P0 corresponding to the current beat are inverted if required, and at the end of beats 1 and 3 the VPR MASK fields are updated. This means that if the ECI state says we should not be executing all 4 beats then we need to skip some of the updating of the VPR that we currently do in mve_advance_vpt(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ffff280726d..bc89ce94d5a 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -110,6 +110,8 @@ static void mve_advance_vpt(CPUARMState *env) /* Advance the VPT and ECI state if necessary */ uint32_t vpr =3D env->v7m.vpr; unsigned mask01, mask23; + uint16_t inv_mask; + uint16_t eci_mask =3D mve_eci_mask(env); =20 if ((env->condexec_bits & 0xf) =3D=3D 0) { env->condexec_bits =3D (env->condexec_bits =3D=3D (ECI_A0A1A2B0 <<= 4)) ? @@ -121,17 +123,25 @@ static void mve_advance_vpt(CPUARMState *env) return; } =20 + /* Invert P0 bits if needed, but only for beats we actually executed */ mask01 =3D FIELD_EX32(vpr, V7M_VPR, MASK01); mask23 =3D FIELD_EX32(vpr, V7M_VPR, MASK23); - if (mask01 > 8) { - /* high bit set, but not 0b1000: invert the relevant half of P0 */ - vpr ^=3D 0xff; + /* Start by assuming we invert all bits corresponding to executed beat= s */ + inv_mask =3D eci_mask; + if (mask01 <=3D 8) { + /* MASK01 says don't invert low half of P0 */ + inv_mask &=3D ~0xff; } - if (mask23 > 8) { - /* high bit set, but not 0b1000: invert the relevant half of P0 */ - vpr ^=3D 0xff00; + if (mask23 <=3D 8) { + /* MASK23 says don't invert high half of P0 */ + inv_mask &=3D ~0xff00; } - vpr =3D FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); + vpr ^=3D inv_mask; + /* Only update MASK01 if beat 1 executed */ + if (eci_mask & 0xf0) { + vpr =3D FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); + } + /* Beat 3 always executes, so update MASK23 */ vpr =3D FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); env->v7m.vpr =3D vpr; } --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888053; cv=none; d=zohomail.com; s=zohoarc; b=XJxSZIst6xmnNG6thuQmGW9SIWGrXa/zQGUhx9d0rSQQp3FkX9lYO/sY1/D/gJsusyZ+2OVahpA01Fyqc8Jl191pAxRFHFaTwR8Ilu4jG2+1RzbVDKXTTFWqd8wfM3tK6/TrtAI96I73fDZdj7UTzUi/xcCgG2qmlv96mlJM/aM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888053; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9E2l5jElzoIn6FznnRlfJdbmRFg2UKvriErGukFqqJw=; b=Ws4RC9MEcQIawcs92jCYFciCg0ZKBkqIJZ0zdsKpXOYXPnNdoLY+ukxajjtT3F6TSx+hQCcb1pfH7tLuAh1meiQtRjkhxdoQaUU7ao9+b/pioCVuOEm4ULqICa1dFL/n1oDtiqpaAfWsX9ts+ADugOjVP1uH2l5ixo6MeQECXCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888053492797.1302740101332; Wed, 25 Aug 2021 03:40:53 -0700 (PDT) Received: from localhost ([::1]:56966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqKy-0000IX-AN for importer@patchew.org; Wed, 25 Aug 2021 06:40:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG2-0002xO-Ut for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:46 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52900) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG1-0005JR-AK for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:46 -0400 Received: by mail-wm1-x333.google.com with SMTP id f10so14671029wml.2 for ; Wed, 25 Aug 2021 03:35:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9E2l5jElzoIn6FznnRlfJdbmRFg2UKvriErGukFqqJw=; b=TU+AfCyYyJYKUWRUXygLCb+TM4h4M4jcIgELPafzxB5GIAy1ZGohxs70BRiVk4yEx0 w+LMKNmclvbRwN7zgOz7/jgHzF05bu1G1juYHdafCkBP6M2Z5JfZEvEBCXF5eY6N3ypp 5oWtds75vbMn1hU4j8Wlidi5T3nPTEE/rQHeRqaQdoGDawd+4xj0+XLBUCzdsdWNSbmm bvEsDXXYO5ZCRqRgdo/UM22RjrYhtI8H/qToUwIPS6uwoWsCFvQWN4RjWzvzTNUpZ3gD 1XLjjJKaZ8+pe7X9v0HasvvllvEXs8z9+YCS3Ad6nFPnQ2aKOl+yu+VsqHLPG1xyGAzO 5Qjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9E2l5jElzoIn6FznnRlfJdbmRFg2UKvriErGukFqqJw=; b=VUWovSiMgoBbIaEEjAH91HonLeXi1opUyJvv5k38cSFUYFuZY0Vp5P41G/GRdGVsF8 2YshvuYTBPYoTFrxalPTjX5lDMI/o+ogBmn+0YDa1JyaDbsuvNyxtTN14vukJ/KstB/f sFC3bfOnLnofETJfcMha8FkrjiTn2L1WeSSiWM3vgJlh3NwlGij7HlYYyJrLKyc0/lZu LDRtdt7D10ephr/TGGNpOdKXgbgKTQgs57b30jVgBY0SMx8XJxcE1SGafanWxuMJ/7Cc f8Kcyb/RHmPZBiXE6aRRjk7w7pEVhWke20xRpsX1ZXVjFM8LbVKlfSIfuvctt9tPZdnG ESbw== X-Gm-Message-State: AOAM530H5H7Q+sxxhTKYAabKkxmXYC0r8SQ+zq/BbWSSbxwfutMtCLiJ l8OIBuO2hlDFuxdpvju/CuoXQFK1fMJ39A== X-Google-Smtp-Source: ABdhPJxRV9/u3qncI0KKNZmfTXCUBJVATGsFZAn/y2U/mYk7rNbI1420YwkP79ChE6ArMrMhkpQTYQ== X-Received: by 2002:a05:600c:4a23:: with SMTP id c35mr8511925wmp.140.1629887743921; Wed, 25 Aug 2021 03:35:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements Date: Wed, 25 Aug 2021 11:35:01 +0100 Message-Id: <20210825103534.6936-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888055207100001 Content-Type: text/plain; charset="utf-8" For vector loads, predicated elements are zeroed, instead of retaining their previous values (as happens for most data processing operations). This means we need to distinguish "beat not executed due to ECI" (don't touch destination element) from "beat executed but predicated out" (zero destination element). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index bc89ce94d5a..be8b9545317 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -146,12 +146,13 @@ static void mve_advance_vpt(CPUARMState *env) env->v7m.vpr =3D vpr; } =20 - +/* For loads, predicated lanes are zeroed instead of keeping their old val= ues */ #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ { \ TYPE *d =3D vd; \ uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ unsigned b, e; \ /* \ * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ @@ -159,8 +160,9 @@ static void mve_advance_vpt(CPUARMState *env) * then take an exception. \ */ \ for (b =3D 0, e =3D 0; b < 16; b +=3D ESIZE, e++) { = \ - if (mask & (1 << b)) { \ - d[H##ESIZE(e)] =3D cpu_##LDTYPE##_data_ra(env, addr, GETPC= ()); \ + if (eci_mask & (1 << b)) { \ + d[H##ESIZE(e)] =3D (mask & (1 << b)) ? \ + cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ } \ addr +=3D MSIZE; \ } \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888178; cv=none; d=zohomail.com; s=zohoarc; b=Yr1kMShmUTtj+LaW4ECGRdKVSRlAdMKosPQQC20Ab8ErCNgiD5JEK4nb2OASC8Pg3BcyS6bW97U0xLfdKiCz6rjTcsOIgr0hNyrSPy6L3SD3hlMUDZTs3UKQUlDTsyFwd27tPkIRLLfdp29dEb7tuRhuE6mg0kNPdrVdThX1b6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888178; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r9xp+d/e9bbwwMEOsVgj3Bb2KxRODXZsL3alV4Ml4i0=; b=StFtU7cbgOg7lbVOyBK2Aoy5i15r6RnXwgWDFmg4M3cyI14f5ZSK0ghdylcFDNuUfvu+WY+xIYKW0NSbTEqH4FYjfCZSoMv+I76QsVj0wlDb+RY/C/mS6QrkfP/ZnGa8VuJutWPgPHZXhj3Sp+4GO547hAZyFJlvs4+Edgodzo0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888178257295.7491373069797; Wed, 25 Aug 2021 03:42:58 -0700 (PDT) Received: from localhost ([::1]:37082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqMz-0005wc-1a for importer@patchew.org; Wed, 25 Aug 2021 06:42:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG4-00033N-Dn for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:48 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG2-0005Ks-73 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id h4so5481036wro.7 for ; Wed, 25 Aug 2021 03:35:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=r9xp+d/e9bbwwMEOsVgj3Bb2KxRODXZsL3alV4Ml4i0=; b=aPsNC6Swy+5wSQHICBhHXiUQ0POPpQ8JPxlG7fznwn4VQnYEF7lvP6lES9zM739gX0 8+O03NaRevNQzD0yRP+3gnUHCxoHzaEW/ul1q2T7wmkd82HpxGUx0e9f1IXWTTDRuDyi nYXCeC4+pz2b+bol4wWgW6IHgvi2gBRcC9C3dlC3nver7L8NPk6VhNyP2ERgaDx2ksCG 6W+uSBp8mzl2qXoPerulJ5i58hWrv6p6ymQZCLOTN4WhM0bUpkjxj83xnBdbvQxH/W2D YfnYBW7huERzlRChWVi8ApyQCpBmyAjQj+CCGJt7GKy33DsZo4FjAlHA/01F77h82bPK yaPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r9xp+d/e9bbwwMEOsVgj3Bb2KxRODXZsL3alV4Ml4i0=; b=VzYIGtNtrGphD+GtSCjaMRsKAlpCCdA8/kFFNkUbCnLC1DqmmECa/WTsC2L37xY3hO qbqXDUBy/VWCiXrpfk0etR693WW3XAJrG6rU7n/qxyiAC0BztqtG+gzVegPwfEWKcoTt bTgQc+sM0gwdKn042KPjBJfuVOvqIFNPhXPDMQKDbenrZXQIWc7dC3LuPEkEy+nGlASn Zqkec5kVkBjyV7lH51Gsm5W6UHmE813H9HCfBxdUREPJ49eERQ1t6YR/WbU3uB/cY9zh 461rHfUrH1Udp8Z7PwFqQoAfpk8qHDf9O42Dxhln4tLqO6Tq2NSoZmBUepl9ipr3VmiY C9sQ== X-Gm-Message-State: AOAM533kkFD4SREPAXHwDKdS3l7tRmaSMsfeFPRXzdCKCgU+R3wLFrf8 jAq4rnd33Lr7lJu3+MS/L3Dmm+9ejYACKQ== X-Google-Smtp-Source: ABdhPJxFTLe/1QlmI8EF9COTG9rdATCIQamdGUV7J0Shodt8alex2zi2D2AsFPgKm+BmXeOSGz+mnw== X-Received: by 2002:a5d:64e6:: with SMTP id g6mr13426471wri.288.1629887744657; Wed, 25 Aug 2021 03:35:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/44] target/arm: Implement MVE VMULL (polynomial) Date: Wed, 25 Aug 2021 11:35:02 +0100 Message-Id: <20210825103534.6936-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888178792100005 Content-Type: text/plain; charset="utf-8" Implement the MVE VMULL (polynomial) insn. Unlike Neon, this comes in two flavours: 8x8->16 and a 16x16->32. Also unlike Neon, the inputs are in either the low or the high half of each double-width element. The assembler for this insn indicates the size with "P8" or "P16", encoded into bit 28 as size =3D 0 or 1. We choose to follow the same encoding as VQDMULL and decode this into a->size as MO_16 or MO_32 indicating the size of the result elements. This then carries through to the helper function names where it then matches up with the existing pmull_h() which does an 8x8->16 operation and a new pmull_w() which does the 16x16->32. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++++ target/arm/vec_internal.h | 11 +++++++++++ target/arm/mve.decode | 14 ++++++++++---- target/arm/mve_helper.c | 16 ++++++++++++++++ target/arm/translate-mve.c | 28 ++++++++++++++++++++++++++++ target/arm/vec_helper.c | 14 +++++++++++++- 6 files changed, 83 insertions(+), 5 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 56e40844ad9..84adfb21517 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -145,6 +145,11 @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vmullpbh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullpth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullpbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullptw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vqdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 865d2139447..2a335582906 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -206,4 +206,15 @@ int16_t do_sqrdmlah_h(int16_t, int16_t, int16_t, bool,= bool, uint32_t *); int32_t do_sqrdmlah_s(int32_t, int32_t, int32_t, bool, bool, uint32_t *); int64_t do_sqrdmlah_d(int64_t, int64_t, int64_t, bool, bool); =20 +/* + * 8 x 8 -> 16 vector polynomial multiply where the inputs are + * in the low 8 bits of each 16-bit element +*/ +uint64_t pmull_h(uint64_t op1, uint64_t op2); +/* + * 16 x 16 -> 32 vector polynomial multiply where the inputs are + * in the low 16 bits of each 32-bit element + */ +uint64_t pmull_w(uint64_t op1, uint64_t op2); + #endif /* TARGET_ARM_VEC_INTERNALS_H */ diff --git a/target/arm/mve.decode b/target/arm/mve.decode index fa9d921f933..de079ec517d 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -173,10 +173,16 @@ VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 .= 1 . 0 ... 0 @2op VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op =20 -VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op -VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op -VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op -VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op +{ + VMULLP_B 111 . 1110 0 . 11 ... 1 ... 0 1110 . 0 . 0 ... 0 @2op_sz28 + VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op + VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op +} +{ + VMULLP_T 111 . 1110 0 . 11 ... 1 ... 1 1110 . 0 . 0 ... 0 @2op_sz28 + VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op + VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op +} =20 VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index be8b9545317..91fb346d7e5 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -481,6 +481,22 @@ DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) =20 +/* + * Polynomial multiply. We can always do this generating 64 bits + * of the result at a time, so we don't need to use DO_2OP_L. + */ +#define VMULLPH_MASK 0x00ff00ff00ff00ffULL +#define VMULLPW_MASK 0x0000ffff0000ffffULL +#define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK) +#define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8) +#define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK) +#define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16) + +DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH) +DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH) +DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW) +DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW) + /* * Because the computation type is at least twice as large as required, * these work for both signed and unsigned source types. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index a2a45036a0b..d318f34b2bc 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -464,6 +464,34 @@ static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) return do_2op(s, a, fns[a->size]); } =20 +static bool trans_VMULLP_B(DisasContext *s, arg_2op *a) +{ + /* + * Note that a->size indicates the output size, ie VMULL.P8 + * is the 8x8->16 operation and a->size is MO_16; VMULL.P16 + * is the 16x16->32 operation and a->size is MO_32. + */ + static MVEGenTwoOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vmullpbh, + gen_helper_mve_vmullpbw, + NULL, + }; + return do_2op(s, a, fns[a->size]); +} + +static bool trans_VMULLP_T(DisasContext *s, arg_2op *a) +{ + /* a->size is as for trans_VMULLP_B */ + static MVEGenTwoOpFn * const fns[] =3D { + NULL, + gen_helper_mve_vmullpth, + gen_helper_mve_vmullptw, + NULL, + }; + return do_2op(s, a, fns[a->size]); +} + /* * VADC and VSBC: these perform an add-with-carry or subtract-with-carry * of the 32-bit elements in each lane of the input vectors, where the diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 034f6b84f78..17fb1583622 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2028,11 +2028,23 @@ static uint64_t expand_byte_to_half(uint64_t x) | ((x & 0xff000000) << 24); } =20 -static uint64_t pmull_h(uint64_t op1, uint64_t op2) +uint64_t pmull_w(uint64_t op1, uint64_t op2) { uint64_t result =3D 0; int i; + for (i =3D 0; i < 16; ++i) { + uint64_t mask =3D (op1 & 0x0000000100000001ull) * 0xffffffff; + result ^=3D op2 & mask; + op1 >>=3D 1; + op2 <<=3D 1; + } + return result; +} =20 +uint64_t pmull_h(uint64_t op1, uint64_t op2) +{ + uint64_t result =3D 0; + int i; for (i =3D 0; i < 8; ++i) { uint64_t mask =3D (op1 & 0x0001000100010001ull) * 0xffff; result ^=3D op2 & mask; --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629887919; cv=none; d=zohomail.com; s=zohoarc; b=kz0ymN9eheMRvFKNt3eYx3NBiIJX9Bxtrw1uyESsnNZPMns3rgzD2mwDxH8BLWBhzGC3uYOgbQe6/Tjd59V0j2cj9OhA9v7PqPR399uMrp7aA4HRFGy49waBn9SYPVFi+xTZD8JDEpyXt+oal+MEU3tpsR8jE2syf/qCKQRof0M= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sBt+Er2ORY6pTVXoQlImPIKKZV4cWhSFl3FktQ7/5BI=; b=iTb8HlsD8UjuMuHWal30LixJro95RcJe0k/+nB/SoE5kR7GwM3XDmCLFzh0tjhBUm6 y1R6G2kUr4HFXotvVX69RkmTtGNk/AaGTdRrvBrDf+fSDJ7nLMxCSlhOnvUGpdVv9evn p1F3U18QKVpvlCUwRp3ortbqyiqY3wyNlP80HXZsn8BPneUFz512cTNr70ADjAgd5haV 84DZ5LnH6xzPr7CjBXoqnsWBBHL2KACT3XOeYT98DRM2hruswMbmA2D57rOHu/+HD9HA O/bXikRA4XWymfT4F1a7se6dORRcaMO18XYSoMNj2f0ZW3W4P9tQC45/Lsvr8Ckp1aay OyOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sBt+Er2ORY6pTVXoQlImPIKKZV4cWhSFl3FktQ7/5BI=; b=sGxjglcNukNoRa4+D/HR/pLDFs6QCm3oFlnXb5Bft30Qr7MrNzzSnr1dPg8X8P9h3Y XlKb4/RSIXrdygPdlYBvzJhkBUK0RPWuzXTyAwnBe9rPyOvwKSVDX3TCNpCf81skCCzn a0nK7+MjimvZbkdGjtfCwplt7pNTDrf24MiG4kUW8HFmLeAQL0kW99u+UI62cmcB1G+v qJia5fouzlbUP1yV8KXdsXXFo7FOUndUlWRcT6mYeHdVsCjbk+1O2PsOiEuCMcI3dk44 xT0L4aXkgKjzZaOQbsfe/AT9OCisbfL0aVUOH7jBqnxez818GP8OojH/Ecl4miH/XNWS 8TUg== X-Gm-Message-State: AOAM532owcBUbClowgaqfEpK3157+jDLr+hTtR+y07n3fRxcOvHZJz05 mdeqP8UjrKs+WyYHQlO3fVIE+AwB7FV6Eg== X-Google-Smtp-Source: ABdhPJzGrcTpnESnKrheK7diQmHOjWesloKUyNSme8I7XGrZUZ8dtr0KK9t2S8PmKR3Vm5pzNK4u5Q== X-Received: by 2002:a5d:490d:: with SMTP id x13mr22970924wrq.412.1629887745469; Wed, 25 Aug 2021 03:35:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns Date: Wed, 25 Aug 2021 11:35:03 +0100 Message-Id: <20210825103534.6936-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629887921849100001 Content-Type: text/plain; charset="utf-8" Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP, VIWDUP and VDWDUP. These fill the elements of a vector with successively incrementing values, starting at the offset specified in a general purpose register. The final value of the offset is written back to this register. The wrapping variants take a second general purpose register which specifies the point where the count should wrap back to 0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 12 ++++ target/arm/mve.decode | 25 ++++++++ target/arm/mve_helper.c | 63 +++++++++++++++++++ target/arm/translate-mve.c | 120 +++++++++++++++++++++++++++++++++++++ 4 files changed, 220 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 84adfb21517..b9af03cc03b 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -35,6 +35,18 @@ DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, en= v, ptr, i32) =20 DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vidupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) +DEF_HELPER_FLAGS_4(mve_viduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) +DEF_HELPER_FLAGS_4(mve_vidupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) + +DEF_HELPER_FLAGS_5(mve_viwdupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) +DEF_HELPER_FLAGS_5(mve_viwduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) +DEF_HELPER_FLAGS_5(mve_viwdupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) + +DEF_HELPER_FLAGS_5(mve_vdwdupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) +DEF_HELPER_FLAGS_5(mve_vdwduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) +DEF_HELPER_FLAGS_5(mve_vdwdupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i= 32) + DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index de079ec517d..88c9c18ebf1 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -35,6 +35,8 @@ &2scalar qd qn rm size &1imm qd imm cmode op &2shift qd qm shift size +&vidup qd rn size imm +&viwdup qd rn rm size imm =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -259,6 +261,29 @@ VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 = 0 1 0000 @vdup size=3D0 VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size= =3D1 VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size= =3D2 =20 +# Incrementing and decrementing dup + +# VIDUP, VDDUP format immediate: 1 << (immh:imml) +%imm_vidup 7:1 0:1 !function=3Dvidup_imm + +# VIDUP, VDDUP registers: Rm bits [3:1] from insn, bit 0 is 1; +# Rn bits [3:1] from insn, bit 0 is 0 +%vidup_rm 1:3 !function=3Dtimes_2_plus_1 +%vidup_rn 17:3 !function=3Dtimes_2 + +@vidup .... .... . . size:2 .... .... .... .... .... \ + qd=3D%qd imm=3D%imm_vidup rn=3D%vidup_rn &vidup +@viwdup .... .... . . size:2 .... .... .... .... .... \ + qd=3D%qd imm=3D%imm_vidup rm=3D%vidup_rm rn=3D%vidup_rn &= viwdup +{ + VIDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 111 . @vidup + VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup +} +{ + VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup + VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup +} + # multiply-add long dual accumulate # rdahi: bits [3:1] from insn, bit 0 is 1 # rdalo: bits [3:1] from insn, bit 0 is 0 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 91fb346d7e5..38b4181db2a 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1695,3 +1695,66 @@ uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32= _t n, uint32_t shift) { return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); } + +#define DO_VIDUP(OP, ESIZE, TYPE, FN) \ + uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ + uint32_t offset, uint32_t imm) \ + { \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + mergemask(&d[H##ESIZE(e)], offset, mask); \ + offset =3D FN(offset, imm); \ + } \ + mve_advance_vpt(env); \ + return offset; \ + } + +#define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ + uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ + uint32_t offset, uint32_t wrap, \ + uint32_t imm) \ + { \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + mergemask(&d[H##ESIZE(e)], offset, mask); \ + offset =3D FN(offset, wrap, imm); \ + } \ + mve_advance_vpt(env); \ + return offset; \ + } + +#define DO_VIDUP_ALL(OP, FN) \ + DO_VIDUP(OP##b, 1, int8_t, FN) \ + DO_VIDUP(OP##h, 2, int16_t, FN) \ + DO_VIDUP(OP##w, 4, int32_t, FN) + +#define DO_VIWDUP_ALL(OP, FN) \ + DO_VIWDUP(OP##b, 1, int8_t, FN) \ + DO_VIWDUP(OP##h, 2, int16_t, FN) \ + DO_VIWDUP(OP##w, 4, int32_t, FN) + +static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) +{ + offset +=3D imm; + if (offset =3D=3D wrap) { + offset =3D 0; + } + return offset; +} + +static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) +{ + if (offset =3D=3D 0) { + offset =3D wrap; + } + offset -=3D imm; + return offset; +} + +DO_VIDUP_ALL(vidup, DO_ADD) +DO_VIWDUP_ALL(viwdup, do_add_wrap) +DO_VIWDUP_ALL(vdwdup, do_sub_wrap) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d318f34b2bc..a220521c00b 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -25,6 +25,11 @@ #include "translate.h" #include "translate-a32.h" =20 +static inline int vidup_imm(DisasContext *s, int x) +{ + return 1 << x; +} + /* Include the generated decoder */ #include "decode-mve.c.inc" =20 @@ -36,6 +41,8 @@ typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_= ptr, TCGv_i32); typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); +typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i3= 2); +typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i= 32, TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -1059,3 +1066,116 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC = *a) mve_update_eci(s); return true; } + +static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn) +{ + TCGv_ptr qd; + TCGv_i32 rn; + + /* + * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP). + * This fills the vector with elements of successively increasing + * or decreasing values, starting from Rn. + */ + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { + return false; + } + if (a->size =3D=3D MO_64) { + /* size 0b11 is another encoding */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + rn =3D load_reg(s, a->rn); + fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); + store_reg(s, a->rn, rn); + tcg_temp_free_ptr(qd); + mve_update_eci(s); + return true; +} + +static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn) +{ + TCGv_ptr qd; + TCGv_i32 rn, rm; + + /* + * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP) + * This fills the vector with elements of successively increasing + * or decreasing values, starting from Rn. Rm specifies a point where + * the count wraps back around to 0. The updated offset is written back + * to Rn. + */ + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { + return false; + } + if (!fn || a->rm =3D=3D 13 || a->rm =3D=3D 15) { + /* + * size 0b11 is another encoding; Rm =3D=3D 13 is UNPREDICTABLE; + * Rm =3D=3D 13 is VIWDUP, VDWDUP. + */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + rn =3D load_reg(s, a->rn); + rm =3D load_reg(s, a->rm); + fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); + store_reg(s, a->rn, rn); + tcg_temp_free_ptr(qd); + tcg_temp_free_i32(rm); + mve_update_eci(s); + return true; +} + +static bool trans_VIDUP(DisasContext *s, arg_vidup *a) +{ + static MVEGenVIDUPFn * const fns[] =3D { + gen_helper_mve_vidupb, + gen_helper_mve_viduph, + gen_helper_mve_vidupw, + NULL, + }; + return do_vidup(s, a, fns[a->size]); +} + +static bool trans_VDDUP(DisasContext *s, arg_vidup *a) +{ + static MVEGenVIDUPFn * const fns[] =3D { + gen_helper_mve_vidupb, + gen_helper_mve_viduph, + gen_helper_mve_vidupw, + NULL, + }; + /* VDDUP is just like VIDUP but with a negative immediate */ + a->imm =3D -a->imm; + return do_vidup(s, a, fns[a->size]); +} + +static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a) +{ + static MVEGenVIWDUPFn * const fns[] =3D { + gen_helper_mve_viwdupb, + gen_helper_mve_viwduph, + gen_helper_mve_viwdupw, + NULL, + }; + return do_viwdup(s, a, fns[a->size]); +} + +static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a) +{ + static MVEGenVIWDUPFn * const fns[] =3D { + gen_helper_mve_vdwdupb, + gen_helper_mve_vdwduph, + gen_helper_mve_vdwdupw, + NULL, + }; + return do_viwdup(s, a, fns[a->size]); +} --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888307; cv=none; d=zohomail.com; s=zohoarc; b=FLduhIRCpmLBr7CRG+i+9F5oQqNYGtZ/f/cXzEj4akpb19oRf6fSgeMhlvjt+6qzr8t5FVXmmdE8o5x/swn3c4UdkRltiBO0H3PVtUtUQtYktZ2HamKogRGRfeBvOL7HhrlGnFznG6Xei8cswYpAF0wL2TxZU/IV+FSGsozWMvs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888307; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lONbbID3VHlgzJU0nIMD9RpteXWbXJ5QRJzmueidsYM=; b=TQPPjtJ4YHmWnqmFPg5+afKOG9Gn0QoFEaTTxKIsolPnzK9Stx0r9IMLcw5OR16IaiW0dXI1Lo8PICkMxS6S1ZNSkxp4YD61gQJncdbCoHw8UGHF4QldLd5tfXFdOZ/YVkLW9grSzHCduH49CuSRlqvZw22uehXRl76jZuaYBLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888307091998.3656381880645; Wed, 25 Aug 2021 03:45:07 -0700 (PDT) Received: from localhost ([::1]:48372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqP4-0005Bp-4G for importer@patchew.org; Wed, 25 Aug 2021 06:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG6-0003AJ-22 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:50 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34418) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG4-0005MW-AM for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:49 -0400 Received: by mail-wr1-x42a.google.com with SMTP id h13so35715687wrp.1 for ; Wed, 25 Aug 2021 03:35:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lONbbID3VHlgzJU0nIMD9RpteXWbXJ5QRJzmueidsYM=; b=uwYaC7pRbu1AyEl8+tiB3Oa4VgvqBku08puYh37GvnfuSKc5JhxpQqgtDaLrYB2IGf aaXCdO/GtuPfYwUW28eBbzw4v2UWghAs5Hca+YQ67hkUnJFe+a3mtvuR4VJ3TdF7QXQJ KjxZnsR3052OI8eItAuF8DUcPs1bo3df+Qb5/l052WDD/84LP64obTJgPzYjrX1uJ8dj AF5i/t03F/3ou4hz1LbqfNkd0Etw8oSkxRci6LzxNcX3K08eTQqmcyoItMkxfm6GSbxe yluMQA9avDyTLQZKCYsfzfTuSCXWDXNTq7UOIRux/Ruipd8Ko8sI9baaHKkEBSdwYWU5 McTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lONbbID3VHlgzJU0nIMD9RpteXWbXJ5QRJzmueidsYM=; b=fvlBP4XwKfrAFprmXYCqfLOacXc0l4R2kbnr8t8MSLpZPHXcT9oWTNrc6wYgAcy5V4 BTek2W0Qv6XzHT2r/POxsWcuoWWcashXUaTb7YJKzxV/m/L9MSpQ6U2mrveIGuQkseTg 2CLsmEqxppV5S9UJQRqMDXCLKcpk4DBHToZzXGyCBOOVaFZ+v0epssmidpstJnx8uQfR uIQKrF3tbSe8mdLscJtfMHAMsWz3xz3u2PxCOt+eu8qnNu0Z4BYR9tYnLP1q+23qi34o P5Vlq2DYELMH3NNaMpzyjFtOhiiT9rvfLhuqcrvOmXn2jvlf85wH6rhBgceak92G+4NX G5dg== X-Gm-Message-State: AOAM531mUKmhCEFGFJPaktlxLt5FxFHQ6I+36e6Ld1IYdd/vLADj+2K/ ZgueZDsADixdwxkf14o/goMSFdofza1zpw== X-Google-Smtp-Source: ABdhPJwPCX+QovSk4xeuJMnZxZbOm/rhfcosbuW1WHUux3y+ZgKAlFtfJb5fV2T2+KaXdysO3Wn/5Q== X-Received: by 2002:a5d:638d:: with SMTP id p13mr18698667wru.223.1629887746950; Wed, 25 Aug 2021 03:35:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/44] target/arm: Factor out gen_vpst() Date: Wed, 25 Aug 2021 11:35:04 +0100 Message-Id: <20210825103534.6936-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888307378100001 Content-Type: text/plain; charset="utf-8" Factor out the "generate code to update VPR.MASK01/MASK23" part of trans_VPST(); we are going to want to reuse it for the VPT insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index a220521c00b..6d8da361469 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -737,33 +737,24 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vml= aldav *a) return do_long_dual_acc(s, a, fns[a->x]); } =20 -static bool trans_VPST(DisasContext *s, arg_VPST *a) +static void gen_vpst(DisasContext *s, uint32_t mask) { - TCGv_i32 vpr; - - /* mask =3D=3D 0 is a "related encoding" */ - if (!dc_isar_feature(aa32_mve, s) || !a->mask) { - return false; - } - if (!mve_eci_check(s) || !vfp_access_check(s)) { - return true; - } /* * Set the VPR mask fields. We take advantage of MASK01 and MASK23 * being adjacent fields in the register. * - * This insn is not predicated, but it is subject to beat-wise + * Updating the masks is not predicated, but it is subject to beat-wise * execution, and the mask is updated on the odd-numbered beats. * So if PSR.ECI says we should skip beat 1, we mustn't update the * 01 mask field. */ - vpr =3D load_cpu_field(v7m.vpr); + TCGv_i32 vpr =3D load_cpu_field(v7m.vpr); switch (s->eci) { case ECI_NONE: case ECI_A0: /* Update both 01 and 23 fields */ tcg_gen_deposit_i32(vpr, vpr, - tcg_constant_i32(a->mask | (a->mask << 4)), + tcg_constant_i32(mask | (mask << 4)), R_V7M_VPR_MASK01_SHIFT, R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LEN= GTH); break; @@ -772,13 +763,25 @@ static bool trans_VPST(DisasContext *s, arg_VPST *a) case ECI_A0A1A2B0: /* Update only the 23 mask field */ tcg_gen_deposit_i32(vpr, vpr, - tcg_constant_i32(a->mask), + tcg_constant_i32(mask), R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGT= H); break; default: g_assert_not_reached(); } store_cpu_field(vpr, v7m.vpr); +} + +static bool trans_VPST(DisasContext *s, arg_VPST *a) +{ + /* mask =3D=3D 0 is a "related encoding" */ + if (!dc_isar_feature(aa32_mve, s) || !a->mask) { + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + gen_vpst(s, a->mask); mve_update_and_store_eci(s); return true; } --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888469; cv=none; d=zohomail.com; s=zohoarc; b=mAb4FtLAXi+7nx0CGO4iHXVk3KKRmuPB6yP3TAtqJWY3UzLgXi2eY8WYcMw1/O3QGlvM48kIo4x1Vuc6BF3kEkRwBSGMMvRDp6UEaLlIlQlf9202aO4QzMWpbgbkO+NpxH8mqRqYT9koreIfp6g0kRTH3gtDvd8Z2gp/t4vMt/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888469; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ByVPvCjeaXnuNCmNSTqYK/dafUjEZDazMD4qmT4NIMQ=; b=eI4t1X4/ZnhvhbcxyL41pVR1pq7imR9PwcCoOoJwwBxY1nNZIkrK9MRXEYRSkdSKrTSX1TQbhxnKQ/zu9LeqZMX1rfu58Dvzj7ntqrqCUJO/gk6hz20VHnZ+yMkpKvhmxxYzMjtMJn1fAo7ZnZRu5fcfGcc197kxEeQyCbriNo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888469815232.5334061224247; Wed, 25 Aug 2021 03:47:49 -0700 (PDT) Received: from localhost ([::1]:56590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqRf-0002Ud-15 for importer@patchew.org; Wed, 25 Aug 2021 06:47:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqG9-0003Nf-5I for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:53 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36368) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqG6-0005Nc-3m for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:52 -0400 Received: by mail-wm1-x331.google.com with SMTP id 79-20020a1c0452000000b002e6cf79e572so3936553wme.1 for ; Wed, 25 Aug 2021 03:35:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ByVPvCjeaXnuNCmNSTqYK/dafUjEZDazMD4qmT4NIMQ=; b=CIMGSWwoMZViRx0riKi8S677WRw+NJgjvCt5NiRwEo1x1fwgDouVvCY1Gb2d+2/b3S QfKUvJF/hJEmkz1R7c+2RKvBIQxRZPnvQnAGYF8qAiWADYDail8nS9I2bIlqM/Vg0XCw tQmwbrrBNg8lThGfdrZg9YWV/ujMFZdTaI7Zp8MDJODCq5vj9J+GwMCoctZwGFlgV42L +yMATJPKqy6W4wUY+Dofr3KxSdm7lKg5xaF1oabB9mpxGZdf5hYBMR1dcU6tjngoiXS1 oeSkHqzIG2QPzGr15d5602IKBYzO4qiBsiomXOfursh5b+hNzDcKjbfKoe2HX4Irf44O tJ5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ByVPvCjeaXnuNCmNSTqYK/dafUjEZDazMD4qmT4NIMQ=; b=Tl4LgbxwPo/P49jRIWENMWvSh8gY1v9bVyfwoBzodBKKCjmblyq52ye+bGc9dDXU9n iWQh8mV+aC7qLJU5JR5VhgPro0P/39AdZ+AEeicyNt/jsxvwfrjSCoQBcxhaqEI7GJZM 4J7Prgl2DIB0SuQAhh7RLx48ZxFl9afhqEHmqMnHge53GW46cxsW5kH91yUf9n72jiWf Phz975/c5ZUSn5KcIiz8h4oMOYjV1/pU0e9/R3LiiQVhtHPvxOouGCUKwQfME5tRciHD rKGWy3agk19EPxa2B+w/GsWjUIh6yCvHnZrSb85N6EknK0tVldvmS4DLX3FnhO3lRKr+ /PQA== X-Gm-Message-State: AOAM533mlWqufDrT4WbvbJClfZdEKWqwnLUs9fT4K9SIpROEcRBX32fO BDSZeim8n7f0W901fv9x4xQnKYHYDHEkdQ== X-Google-Smtp-Source: ABdhPJzi+79glYI+GRSMGAEefIVVbanbOPmNQDXr6YXTVY/RGmGfFWXWMG51DwhnkJzDJlIULR5iHQ== X-Received: by 2002:a1c:1d1:: with SMTP id 200mr8393553wmb.53.1629887748549; Wed, 25 Aug 2021 03:35:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/44] target/arm: Implement MVE integer vector comparisons Date: Wed, 25 Aug 2021 11:35:05 +0100 Message-Id: <20210825103534.6936-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888471468100002 Content-Type: text/plain; charset="utf-8" Implement the MVE integer vector comparison instructions. These are "VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings T1, T2 and T3. These insns compare corresponding elements in each vector, and update the VPR.P0 predicate bits with the results of the comparison. VPT also sets the VPR.MASK01 and VPR.MASK23 fields -- it is effectively "VCMP then VPST". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 32 ++++++++++++++++++++++ target/arm/mve.decode | 18 +++++++++++- target/arm/mve_helper.c | 56 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 47 ++++++++++++++++++++++++++++++++ 4 files changed, 152 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index b9af03cc03b..ca5a6ab51cc 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -480,3 +480,35 @@ DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, en= v, i32, i32) DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vcmpeqb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpeqh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpeqw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpneb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpneh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpnew, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpcsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpcsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpcsw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmphib, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmphih, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmphiw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpgeb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpgeh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpgew, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpltb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmplth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpltw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpgtb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpgth, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpgtw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpleb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vcmplew, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 88c9c18ebf1..76bbf9a6136 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -37,6 +37,7 @@ &2shift qd qm shift size &vidup qd rn size imm &viwdup qd rn rm size imm +&vcmp qm qn size mask =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -86,6 +87,10 @@ @2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=3D%qd qm=3D%q= m \ size=3D2 shift=3D%rshift_i5 =20 +# Vector comparison; 4-bit Qm but 3-bit Qn +%mask_22_13 22:1 13:3 +@vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=3D%qm mas= k=3D%mask_22_13 + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -345,7 +350,6 @@ VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 11= 0 .... @2scalar } =20 # Predicate operations -%mask_22_13 22:1 13:3 VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask_= 22_13 =20 # Logical immediate operations (1 reg and modified-immediate) @@ -458,3 +462,15 @@ VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 = 1 . 0 ... 0 @2_shr_b VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h =20 VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=3D%qd + +# Comparisons. We expand out the conditions which are split across +# encodings T1, T2, T3 and the fc bits. These include VPT, which is +# effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero. +VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp +VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp +VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp +VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp +VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp +VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp +VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp +VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 38b4181db2a..b0b380b94b0 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1758,3 +1758,59 @@ static uint32_t do_sub_wrap(uint32_t offset, uint32_= t wrap, uint32_t imm) DO_VIDUP_ALL(vidup, DO_ADD) DO_VIWDUP_ALL(viwdup, do_add_wrap) DO_VIWDUP_ALL(vdwdup, do_sub_wrap) + +/* + * Vector comparison. + * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. + * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. + * P0 bits otherwise are updated with the results of the comparisons. + * We must also keep unchanged the MASK fields at the top of v7m.vpr. + */ +#define DO_VCMP(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ + { \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++) { \ + bool r =3D FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + emask <<=3D ESIZE; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } + +#define DO_VCMP_S(OP, FN) \ + DO_VCMP(OP##b, 1, int8_t, FN) \ + DO_VCMP(OP##h, 2, int16_t, FN) \ + DO_VCMP(OP##w, 4, int32_t, FN) + +#define DO_VCMP_U(OP, FN) \ + DO_VCMP(OP##b, 1, uint8_t, FN) \ + DO_VCMP(OP##h, 2, uint16_t, FN) \ + DO_VCMP(OP##w, 4, uint32_t, FN) + +#define DO_EQ(N, M) ((N) =3D=3D (M)) +#define DO_NE(N, M) ((N) !=3D (M)) +#define DO_EQ(N, M) ((N) =3D=3D (M)) +#define DO_EQ(N, M) ((N) =3D=3D (M)) +#define DO_GE(N, M) ((N) >=3D (M)) +#define DO_LT(N, M) ((N) < (M)) +#define DO_GT(N, M) ((N) > (M)) +#define DO_LE(N, M) ((N) <=3D (M)) + +DO_VCMP_U(vcmpeq, DO_EQ) +DO_VCMP_U(vcmpne, DO_NE) +DO_VCMP_U(vcmpcs, DO_GE) +DO_VCMP_U(vcmphi, DO_GT) +DO_VCMP_S(vcmpge, DO_GE) +DO_VCMP_S(vcmplt, DO_LT) +DO_VCMP_S(vcmpgt, DO_GT) +DO_VCMP_S(vcmple, DO_LE) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6d8da361469..2d7211b5271 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -43,6 +43,7 @@ typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, = TCGv_i32); typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i3= 2); typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i= 32, TCGv_i32); +typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -1182,3 +1183,49 @@ static bool trans_VDWDUP(DisasContext *s, arg_viwdup= *a) }; return do_viwdup(s, a, fns[a->size]); } + +static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) +{ + TCGv_ptr qn, qm; + + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || + !fn) { + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qn, qm); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + if (a->mask) { + /* VPT */ + gen_vpst(s, a->mask); + } + mve_update_eci(s); + return true; +} + +#define DO_VCMP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ + { \ + static MVEGenCmpFn * const fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_vcmp(s, a, fns[a->size]); \ + } + +DO_VCMP(VCMPEQ, vcmpeq) +DO_VCMP(VCMPNE, vcmpne) +DO_VCMP(VCMPCS, vcmpcs) +DO_VCMP(VCMPHI, vcmphi) +DO_VCMP(VCMPGE, vcmpge) +DO_VCMP(VCMPLT, vcmplt) +DO_VCMP(VCMPGT, vcmpgt) +DO_VCMP(VCMPLE, vcmple) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888052; cv=none; d=zohomail.com; s=zohoarc; b=mpN31qUkaLqiulrjWmXUP9nqxulKXA6AjH39uVHPyVwjDEbWsNtiTSu4WcoMK9pv8PJntP7hb86xSMKuNRyN3MqY3IjFttpghuH8MbUv9kVOnUxZR3K6Y3KZmmVN9SZqGEPiBnJJ17h54KE2ztcakS5mixY8BW7GG9avu8ZuSTc= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iZpgClRSEyhYOR+Os3hp/BipliKUZ2Q4cpKVQjciGAc=; b=k+x3Nnk4CieKGpphmj+uWOiHGGa6DcYCyZif2P1alU0rJa2YczgMOi+LBvtTQmKy1b Yrtrl2WZRYysqS3v2cKcxLId9y9+ZW2Z7BgIMfuiq87TFcwzZ8syC1I2z0DnMjvXNb/A ZQ0ew9Kjiz56ZuxLOdZG4zYj8g9QlUOGIg8Iu5WzTYlnK6TMocVcatrFMrEHtZsXSHbY VvbiGmQgUcH+gAfE//4IAcdLtiEnpNqAsmXo+QnSiLklRSBdnrUArOTIIdc6Rm34X8AI nz1ohC0o50ETh1q4AwW72T3/CL3ySD7aP6dKrAojylBJtN14zoSfMXOCG97ggktIg5Km HUuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iZpgClRSEyhYOR+Os3hp/BipliKUZ2Q4cpKVQjciGAc=; b=AZeGI33N9zc3tawXg4XGi2PUPEsIUL+ZiFd1Vbd3pvJ/0QeCLJU1YgS4W5+fcasHhv 5qxibbbsQlKVAwsx/C+yYgkqOzf2IYIafnvQWxJKjxd1rRa3P2zUjPWKwVglDr/Ftf6O ShMTyrXxREmtaTFc1dSbA1X75o0+UVjh5NYACG38hTxiaF9Nr8jQ0SAo7TgpWi2qP8fo REhx1bZRbQiliT1eXb2Iah8YwymFbEUsZ69aKZEo2dtNGXIg4MEdddUF8WTyAtXswde+ /5gC0JO+e0lHEjRkwHKFQG2K2gGzNVf9GoZrgyfolWJrYhNpWmCHaa0qCAAc1pd2undp W4JQ== X-Gm-Message-State: AOAM532nJLpbAOS8fkzjxh+cNeHrc9PRlvXn9KZTtCPnOozhTZj6y3+2 EK1AszXwrHx/EGWVFWRoY6TPZ9CBamJ+Uw== X-Google-Smtp-Source: ABdhPJzMYTtO6ipkUkZZZErw7H4B736KlwRSZYx6TjQLiTQOrDDTM2LyB9gHea3q+T6NW2Gi+zfWQw== X-Received: by 2002:a7b:c847:: with SMTP id c7mr8671202wml.1.1629887749490; Wed, 25 Aug 2021 03:35:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons Date: Wed, 25 Aug 2021 11:35:06 +0100 Message-Id: <20210825103534.6936-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888053100100001 Content-Type: text/plain; charset="utf-8" Implement the MVE integer vector comparison instructions that compare each element against a scalar from a general purpose register. These are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)" encodings T4, T5 and T6. We have to move the decodetree pattern for VPST, because it overlaps with VCMP T4 with size =3D 0b11. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 32 +++++++++++++++++++++++++++ target/arm/mve.decode | 18 +++++++++++++--- target/arm/mve_helper.c | 44 +++++++++++++++++++++++++++++++------- target/arm/translate-mve.c | 43 +++++++++++++++++++++++++++++++++++++ 4 files changed, 126 insertions(+), 11 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index ca5a6ab51cc..4f9903e66ef 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -512,3 +512,35 @@ DEF_HELPER_FLAGS_3(mve_vcmpgtw, TCG_CALL_NO_WG, void, = env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vcmpleb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vcmplew, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmpne_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpne_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmphi_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmphi_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmphi_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmpge_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpge_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmplt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmplt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 76bbf9a6136..ef708ba80ff 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -38,6 +38,7 @@ &vidup qd rn size imm &viwdup qd rn rm size imm &vcmp qm qn size mask +&vcmp_scalar qn rm size mask =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -90,6 +91,8 @@ # Vector comparison; 4-bit Qm but 3-bit Qn %mask_22_13 22:1 13:3 @vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=3D%qm mas= k=3D%mask_22_13 +@vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \ + mask=3D%mask_22_13 =20 # Vector loads and stores =20 @@ -349,9 +352,6 @@ VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 11= 0 .... @2scalar rdahi=3D%rdahi rdalo=3D%rdalo } =20 -# Predicate operations -VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask_= 22_13 - # Logical immediate operations (1 reg and modified-immediate) =20 # The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but @@ -474,3 +474,15 @@ VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 = 0 . 0 ... 0 @vcmp VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp + +{ + VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask= _22_13 + VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_sca= lar +} +VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_sca= lar +VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_sca= lar +VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_sca= lar +VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_sca= lar +VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_sca= lar +VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_sca= lar +VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_sca= lar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b0b380b94b0..1a021a9a817 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1787,15 +1787,43 @@ DO_VIWDUP_ALL(vdwdup, do_sub_wrap) mve_advance_vpt(env); \ } =20 -#define DO_VCMP_S(OP, FN) \ - DO_VCMP(OP##b, 1, int8_t, FN) \ - DO_VCMP(OP##h, 2, int16_t, FN) \ - DO_VCMP(OP##w, 4, int32_t, FN) +#define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + uint32_t rm) \ + { \ + TYPE *n =3D vn; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + uint16_t beatpred =3D 0; \ + uint16_t emask =3D MAKE_64BIT_MASK(0, ESIZE); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++) { \ + bool r =3D FN(n[H##ESIZE(e)], (TYPE)rm); \ + /* Comparison sets 0/1 bits for each byte in the element */ \ + beatpred |=3D r * emask; \ + emask <<=3D ESIZE; \ + } \ + beatpred &=3D mask; \ + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | \ + (beatpred & eci_mask); \ + mve_advance_vpt(env); \ + } =20 -#define DO_VCMP_U(OP, FN) \ - DO_VCMP(OP##b, 1, uint8_t, FN) \ - DO_VCMP(OP##h, 2, uint16_t, FN) \ - DO_VCMP(OP##w, 4, uint32_t, FN) +#define DO_VCMP_S(OP, FN) \ + DO_VCMP(OP##b, 1, int8_t, FN) \ + DO_VCMP(OP##h, 2, int16_t, FN) \ + DO_VCMP(OP##w, 4, int32_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) + +#define DO_VCMP_U(OP, FN) \ + DO_VCMP(OP##b, 1, uint8_t, FN) \ + DO_VCMP(OP##h, 2, uint16_t, FN) \ + DO_VCMP(OP##w, 4, uint32_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ + DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) =20 #define DO_EQ(N, M) ((N) =3D=3D (M)) #define DO_NE(N, M) ((N) !=3D (M)) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2d7211b5271..6c6f159aa3e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -44,6 +44,7 @@ typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i6= 4); typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i3= 2); typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i= 32, TCGv_i32); typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -1209,6 +1210,37 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MV= EGenCmpFn *fn) return true; } =20 +static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, + MVEGenScalarCmpFn *fn) +{ + TCGv_ptr qn; + TCGv_i32 rm; + + if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm =3D=3D 13) { + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qn =3D mve_qreg_ptr(a->qn); + if (a->rm =3D=3D 15) { + /* Encoding Rm=3D0b1111 means "constant zero" */ + rm =3D tcg_constant_i32(0); + } else { + rm =3D load_reg(s, a->rm); + } + fn(cpu_env, qn, rm); + tcg_temp_free_ptr(qn); + tcg_temp_free_i32(rm); + if (a->mask) { + /* VPT */ + gen_vpst(s, a->mask); + } + mve_update_eci(s); + return true; +} + #define DO_VCMP(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ { \ @@ -1219,6 +1251,17 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MV= EGenCmpFn *fn) NULL, \ }; \ return do_vcmp(s, a, fns[a->size]); \ + } \ + static bool trans_##INSN##_scalar(DisasContext *s, \ + arg_vcmp_scalar *a) \ + { \ + static MVEGenScalarCmpFn * const fns[] =3D { \ + gen_helper_mve_##FN##_scalarb, \ + gen_helper_mve_##FN##_scalarh, \ + gen_helper_mve_##FN##_scalarw, \ + NULL, \ + }; \ + return do_vcmp_scalar(s, a, fns[a->size]); \ } =20 DO_VCMP(VCMPEQ, vcmpeq) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=H9TZmaWqhZmwH6AhFQ01QX7XQokaEmxCohWlyYnItss=; b=ebfs9qU6dDeEsaoVEGx9gzbie/CWqLJ3cpH9QNl9mncPBVKRqniNF+JRNoPpAcOyAt sI95YGImI56ZS5UXCLlwCVf3BY/9WK6muEMSGjyBUooagcMkKQ/zXkpzeNsP4yS7QWTQ JQNSUY/l6WvVMF0Fzh781OImEusRKAoS9ndE+zw5Kl6NP6uS2Jm2z3ZyHjMCM5WTLZln Z+Pio+yGT+/Jiou5nAKFPH0cFowWE/iCWdL3mwVsdN2SAkkt03BeGN/a6vDQnKl25Id1 HJdsciEKVBuiLzmqNAFzYLeam2eMZG6jZjyjzhRZKHJguV6G082XFU/6rzd60O+U6tUN ZKhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H9TZmaWqhZmwH6AhFQ01QX7XQokaEmxCohWlyYnItss=; b=n9cEPayV3OVGYubpbL9lljG5BQSK2GQukiZKeIpnBdwpds2vDo4uzcTLzIypWcJM+d QG/uRvH5PqyqvGKhg8fpxzD4xEKyA4oAQ3At2/4+umAfJms6vl2p+vMIJziZmxTO7KCw NKApDTRwQ/M/wEvirpu4ywzglQbBX81dkyOAi46I7oZjMuhUjEZzUGS+LW9oA3x4zUp3 X21FyAwYZaZzDFXPG4QaiZO6kb8WRM7wJCjboxw2g60xnbFmrkxRSUCzSrG85gH1822Y t0jc2kCNuTJ6rbXWN1O7fkB46/zrUnVL7jVDLxJwQz07PpjLNPmCug5nuwyIVefC/W30 LkJw== X-Gm-Message-State: AOAM53120n2QMzKHUvRwQqqLfl/tyFmAd2Xnvm/Wg1G/M1mGqY+RAICW Js8J5Y7a/jU+8nf7sTDGOZXzuryyx8I4BA== X-Google-Smtp-Source: ABdhPJzytiaRF7cXY2kuAZRFauI6MktpX0GNpPceYekLyK0AqU+gzBlaHx6LacvpkqkPgTf+oGRzHA== X-Received: by 2002:a05:600c:2f90:: with SMTP id t16mr8807066wmn.136.1629887750289; Wed, 25 Aug 2021 03:35:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/44] target/arm: Implement MVE VPSEL Date: Wed, 25 Aug 2021 11:35:07 +0100 Message-Id: <20210825103534.6936-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888274184100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VPSEL insn, which sets each byte of the destination vector Qd to the byte from either Qn or Qm depending on the value of the corresponding bit in VPR.P0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 2 ++ target/arm/mve.decode | 7 +++++-- target/arm/mve_helper.c | 19 +++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 4f9903e66ef..16c4c3b8f61 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -82,6 +82,8 @@ DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, p= tr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index ef708ba80ff..4bd20a9a319 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -468,8 +468,11 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 11= 00 rdm:4 qd=3D%qd # effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero. VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp -VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp -VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp +{ + VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz + VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp + VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp +} VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1a021a9a817..03171766b57 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1842,3 +1842,22 @@ DO_VCMP_S(vcmpge, DO_GE) DO_VCMP_S(vcmplt, DO_LT) DO_VCMP_S(vcmpgt, DO_GT) DO_VCMP_S(vcmple, DO_LE) + +void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) +{ + /* + * Qd[n] =3D VPR.P0[n] ? Qn[n] : Qm[n] + * but note that whether bytes are written to Qd is still subject + * to (all forms of) predication in the usual way. + */ + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint16_t mask =3D mve_element_mask(env); + uint16_t p0 =3D FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); + unsigned e; + for (e =3D 0; e < 16 / 8; e++, mask >>=3D 8, p0 >>=3D 8) { + uint64_t r =3D m[H8(e)]; + mergemask(&r, n[H8(e)], p0); + mergemask(&d[H8(e)], r, mask); + } + mve_advance_vpt(env); +} diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6c6f159aa3e..aa38218e08f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -376,6 +376,8 @@ DO_LOGIC(VORR, gen_helper_mve_vorr) DO_LOGIC(VORN, gen_helper_mve_vorn) DO_LOGIC(VEOR, gen_helper_mve_veor) =20 +DO_LOGIC(VPSEL, gen_helper_mve_vpsel) + #define DO_2OP(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ { \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888577; cv=none; d=zohomail.com; s=zohoarc; b=iKAKF60Q2Yf7vyoLOBL9uwi0ufULNU4dLwhzcSPXM030ci9RqkIpfJDX2/i5y9+AUsRV+D45oJjJcRsDhw2oluZpRjVW693VJGB+yL8nZrgwK6aNWtWBopwD4bJl/aFfWvUffUOhHyWGVeLmbOlwWLRCLOFINNLxv9KH+k5ySAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888577; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WJjWm9FDJCY1N24UtIPKV2StMedL6VIApBeIOCLcWD0=; b=KYd+i6H+7vNjS4OYUV+8uL8DdjfTl/GjhEHWCoGcPn9aejFgpCfS2kmACmpY1sZDnhRd0PWnG8swYiQm5e50rlieJEfTLCpTpy+adPCSud9w8FLiKJV0wH6ewGlKzhbgRvXEy+CVns+OCj6lHbtpLliShsE4GPY1dvTIFQ9t4Ig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888577388744.8796587836396; Wed, 25 Aug 2021 03:49:37 -0700 (PDT) Received: from localhost ([::1]:36602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqTQ-00086n-9V for importer@patchew.org; Wed, 25 Aug 2021 06:49:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGC-0003cB-KZ for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:56 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:43681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGA-0005Rq-VF for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:56 -0400 Received: by mail-wr1-x42f.google.com with SMTP id b6so210165wrh.10 for ; Wed, 25 Aug 2021 03:35:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WJjWm9FDJCY1N24UtIPKV2StMedL6VIApBeIOCLcWD0=; b=iBdMToZbh83LbR92ngbvj5jlxYloZV1WchphqYdjAfePZAINJAB7ZJEUdQyg/NWud3 zQEzlHD7NDRxFypeu/i52Cbo+tWfTOVbJtoj3USxrH/huIiyQjZZ6wgOt1ao+B8uzZeY TQFGE//EKaoVAHmT29NZKJzB7r9bhRgLs02Db1DSdSOaRgv3T1/wLx6fTv7GLNH9Lm+p JTH3oXLoDDeBpVFjC+Qv2EToyl1EkqYad/1C9bZJbW5JDBIke0u+uWFbHG6RtRJPzGvf fEgLZbFww0OdyQzh822kdXURthBCJmRUc8yJ64GV3RsqkWSdipdD7uwOMpVwK9fR6/3a FXBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WJjWm9FDJCY1N24UtIPKV2StMedL6VIApBeIOCLcWD0=; b=Wstk/Osu6rF6HedjpVxvxdRlZhzhVefi1B5VIj2H1xg19FCe3B3xn7l8kicdG7wxqE pqVK90ynk+R6shxhHFSR1i3m9WJv2071moGEqTkRiDSzRUDsi0YOB/UGUuDvwEpPLxR9 kQ6RkTpn/kKDmaeyKroYXvv4EGL8SBK5ZOF2iIEOvVsO2EeazhRA4lQu3iS6sX6gTpbs 8zqUiRD7bY4g+a4Cvne9MlXGPhAYuwlMSldzKGTaebAhrAvppWD5yZf1Utxe2yHEzVyK Nk0h0H43gJ6vhISmlWvGzwDIo2kv1TiW+mTM8aAHDLr0zP+bFtPwU5WWjFrCnfqRSYcx LIFw== X-Gm-Message-State: AOAM530EMab7uuhJDXkQ0Nxdvd5Nwxqx45kvo5OFPFYUnSNJGVZH4QEs 054Y/DNLXZzoBIr7B9lSjZP6TAgD3c787g== X-Google-Smtp-Source: ABdhPJz5ylBx6J/eO/PHftuiHDrsqcNUpF/2rR2gREhgo5eRbGGLkh6EHeaCOTpgQweoDuOR/FfCBw== X-Received: by 2002:adf:b347:: with SMTP id k7mr21928330wrd.239.1629887753623; Wed, 25 Aug 2021 03:35:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/44] target/arm: Implement MVE VMLAS Date: Wed, 25 Aug 2021 11:35:08 +0100 Message-Id: <20210825103534.6936-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888579076100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMLAS insn, which multiplies a vector by a vector and adds a scalar. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-mve.c | 1 + 4 files changed, 34 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 16c4c3b8f61..715b1bbd012 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -347,6 +347,10 @@ DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_W= G, void, env, ptr, ptr, i3 DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vmlasb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlash, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlasw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 4bd20a9a319..226b74790b3 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -345,6 +345,9 @@ VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 11= 0 .... @2scalar VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar =20 +# The U bit (28) is don't-care because it does not affect the result +VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar + # Vector add across vector { VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 r= da=3D%rdalo diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 03171766b57..ab02a1e60f4 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -948,6 +948,22 @@ DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdml= sdh_w) mve_advance_vpt(env); \ } =20 +/* "accumulating" version where FN takes d as well as n and m */ +#define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + mergemask(&d[H##ESIZE(e)], \ + FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ + } \ + mve_advance_vpt(env); \ + } + /* provide unsigned 2-op scalar helpers for all sizes */ #define DO_2OP_SCALAR_U(OP, FN) \ DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ @@ -958,6 +974,11 @@ DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdml= sdh_w) DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ DO_2OP_SCALAR(OP##w, 4, int32_t, FN) =20 +#define DO_2OP_ACC_SCALAR_U(OP, FN) \ + DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ + DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ + DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) + DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) @@ -987,6 +1008,11 @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRD= MULH_B) DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) =20 +/* Vector by vector plus scalar */ +#define DO_VMLAS(D, N, M) ((N) * (D) + (M)) + +DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) + /* * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index aa38218e08f..b56c91db2ab 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -596,6 +596,7 @@ DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) +DO_2OP_SCALAR(VMLAS, vmlas) =20 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888521; cv=none; d=zohomail.com; s=zohoarc; b=MlrQqlqcjWfqPpXujYBBSeofMO2Pd0tQs6wYZ/uGSep+ehSS1LcstrZ3TzGH+U2XfunWa3OzoodvGDNP2x7C4d4VNI/B/zBEpbPWGjnkTPaGSFbjvJNf+3QFuE0qV94W/Iimyqc53IAKzWrtnkaXML8QXzl1m1xtgpOF0E6ZSUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888521; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TWbXHhQWATq+c4AfBX4ejJAoMYSLeEhYRoWPRhuFdZs=; b=A0qLlOMwCSmDLwpcIrqM2oqfsKl+hupaRHsxsWtJi9BWxjdt/xA9IseG4eOgoi5G6Hw7aE1IiB8sVAjAEyNRsY1SNgZyXJLmdLtwE3C6MwiJOJf7gecnlbm+dmwmZTAVYvlqyCymO/xo2eom87blDtXe9xiBWVJedIVymZ7VKgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888521419224.9769331979087; Wed, 25 Aug 2021 03:48:41 -0700 (PDT) Received: from localhost ([::1]:32974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqSW-0005dj-4P for importer@patchew.org; Wed, 25 Aug 2021 06:48:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGD-0003gz-OG for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:57 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:37473) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGB-0005Rw-RE for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:57 -0400 Received: by mail-wm1-x331.google.com with SMTP id c8-20020a7bc008000000b002e6e462e95fso3921576wmb.2 for ; Wed, 25 Aug 2021 03:35:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TWbXHhQWATq+c4AfBX4ejJAoMYSLeEhYRoWPRhuFdZs=; b=TkK9gA1lnA/u4FL9tjmQLsehq6wpZrdtXDusxQlOyFlSz1ZaH91qxMOeavhJGoEso/ 7jLltQ0J/nAmFUxacUj8A2hmThFiIRpXU4K0zVQp2+Xr8ZJLZmAVE1P/WKya5AEz1T4t b3Z2qI1/xo76RDz7uBO93HD+27Xe3Mf7uKvTZ1NfphdROyI2BTqZdsHCRrEng3dTt8A+ BZsPZv6q/F1eRqpPvOvcfvngwqztaYXZrSwe3Dfwitst2Y18cF2Uh9FfFxJcn0+kR6YD EzzAaPtd7+YJe/QmAv6LGSF3ncURfgSIjsqotTlxKnQu++qAbvuRznv78W4gVp8Ciz2q Z+hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TWbXHhQWATq+c4AfBX4ejJAoMYSLeEhYRoWPRhuFdZs=; b=t1Vq5tU3KDjYIVTH6X7SSrq/hUQCKZZGiyiyAb5XyiwqWx9ALZuHuE08WtfLEx4eFE t0wCo0Smgp4LT/rWXTB/wlNLL4Ftt/OXmiQTg+KABx01jNRfxVTv5YkhHH888PXO9eBu +6PaPKGsIpffgR56S67YkZX+XvdWv0Sj0HazrLhXWFcV6AfT+RS9uCHqQ+XPLZtfqoMI hhpM843aSzCFQYFrpYQsKidKRa3Vzu/VVqXpwXAfzZvkoZUx37dWkw5TWaTXzZL9dnEv tCcYG90i6ZuS8N8/8Wq4mwLAVbcdK4gVZ22+EaM3eH0dQRqCjTcWzn3MpYzQJxKGo2fW z2iA== X-Gm-Message-State: AOAM532M8lraHNEPLrVL2sLRzT5q8WL7n9fZQAYBNYzdM4e4snzoQ1H/ x6r7/uF5sECQ7WaZsVQDvOYYYTLC4qhiYw== X-Google-Smtp-Source: ABdhPJwIdhw7KIuRrWcXa3ZRnRYHLvs55zL2lm8GOk/DyxXTWyNTF4f1vTgRjvmH6aaBvwSESvB1wQ== X-Received: by 2002:a1c:9a91:: with SMTP id c139mr8612082wme.106.1629887754325; Wed, 25 Aug 2021 03:35:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/44] target/arm: Implement MVE shift-by-scalar Date: Wed, 25 Aug 2021 11:35:09 +0100 Message-Id: <20210825103534.6936-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888522667100001 Content-Type: text/plain; charset="utf-8" Implement the MVE instructions which perform shifts by a scalar. These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the shift amount in a general purpose register and shift every element in the vector by that amount. Mostly we can reuse the helper functions for shift-by-immediate; we do need two new helpers for VQRSHL. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 +++++++ target/arm/mve.decode | 23 ++++++++++++++++--- target/arm/mve_helper.c | 2 ++ target/arm/translate-mve.c | 46 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 715b1bbd012..0ee5ea3cabd 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -414,6 +414,14 @@ DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void= , env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vqrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(mve_vqrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 226b74790b3..eb26b103d12 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -39,6 +39,7 @@ &viwdup qd rn rm size imm &vcmp qm qn size mask &vcmp_scalar qn rm size mask +&shl_scalar qda rm size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -88,6 +89,8 @@ @2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=3D%qd qm=3D%q= m \ size=3D2 shift=3D%rshift_i5 =20 +@shl_scalar .... .... .... size:2 .. .... .... .... rm:4 &shl_scalar qda= =3D%qd + # Vector comparison; 4-bit Qm but 3-bit Qn %mask_22_13 22:1 13:3 @vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=3D%qm mas= k=3D%mask_22_13 @@ -320,7 +323,23 @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . = 0 a:1 0 ... 1 @vmlaldav_no =20 VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar -VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar + +{ + VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar + VRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar + VQSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar + VQRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar + VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar +} + +{ + VSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar + VRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar + VQSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar + VQRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar + VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar +} + VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar @@ -340,8 +359,6 @@ VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 10= 0 .... @2scalar size=3D%size_28 } =20 -VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar - VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ab02a1e60f4..ac608fc524b 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1334,6 +1334,8 @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) DO_2SHIFT_U(vrshli_u, DO_VRSHLU) DO_2SHIFT_S(vrshli_s, DO_VRSHLS) +DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) +DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) =20 /* Shift-and-insert; we always work with 64 bits at a time */ #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index b56c91db2ab..44731fc4eb7 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1003,6 +1003,52 @@ DO_2SHIFT(VRSHRI_U, vrshli_u, true) DO_2SHIFT(VSRI, vsri, false) DO_2SHIFT(VSLI, vsli, false) =20 +static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, + MVEGenTwoOpShiftFn *fn) +{ + TCGv_ptr qda; + TCGv_i32 rm; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qda) || + a->rm =3D=3D 13 || a->rm =3D=3D 15 || !fn) { + /* Rm cases are UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qda =3D mve_qreg_ptr(a->qda); + rm =3D load_reg(s, a->rm); + fn(cpu_env, qda, qda, rm); + tcg_temp_free_ptr(qda); + tcg_temp_free_i32(rm); + mve_update_eci(s); + return true; +} + +#define DO_2SHIFT_SCALAR(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a) \ + { \ + static MVEGenTwoOpShiftFn * const fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_2shift_scalar(s, a, fns[a->size]); \ + } + +DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s) +DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u) +DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s) +DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u) +DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s) +DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) +DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) +DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) + #define DO_VSHLL(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ { \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888646; cv=none; d=zohomail.com; s=zohoarc; b=ISEMB+VQIs02DhgmIVYclHksBB0BAfOaNatq6M5Z7lix6Lb48iEZyFpoOnv7R8UDjmliTXFhoj6YFPe/m/bRl2LF8bzeHy8viY+nbfzRC2+h3vJ0aoinFPr5soveFDUgNfLkkVGAuooWVUh+d5JSEQ99TtQssW5WFjUJ8cfq4+Q= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=87OSQfI+t8J/2NRNU5SXGP9uuTxhBzV2bH7+CgjkZBI=; b=Ux3FSliY4jA6iWLCnxeTPf34D0JvEiFs5tLpQnFcLq+dKRaYMhLG0ySqDk/ilZAx3u 7kcWwCg3pka1JqBFE42ifJVQKjtHQZ9kGkMG6YIxT6Sb/zOZeQiBaMV3uSBPYAYyqpiL b501Uvkvygo4nHp6kQBk+bq1cwUcleQmo/VIIatgwoudDhie9+ezPYc1JFgnG1W7I8Xa AYl4l9yM1QAMR2PTttzvn2VdTCy0Ai9NJ90hADfa6gXwHRbFBdkkC/1uvZxPEuJtdZcm hty4lM4MvhSiVFgQt0QkRjjv5Q4S0R2UFvG/ReTvFs8GT9wQZDWXZSSJw+YDoVCgtD0S WbpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=87OSQfI+t8J/2NRNU5SXGP9uuTxhBzV2bH7+CgjkZBI=; b=KA5yaYcTVFkSmJaGfcsXVmd4DSPvUAL8zYy1PYCWd74FYXy6PibHs5pLC7CP6dTNCa KswRGCd6JdHS04nua6NUyjIPTnWgM0BypMxXzQgkGLC+IHknarQOwvfhQJLmEOOxHOSB oBORy6EHJEce2jmnwBrTm5XDh+EQfSeSckrZ3z7aS5TR4tYesm+ikAgbPpwliEqEMkyS 2CYJCUafKgjs+TdUf9tX2tJGHhJ19giDpQ0gMFZRXvtWcrPJYh53sEtBNjntnHFfwjA5 To44ckDhGGoM4cSd3EaR/DMeoVhmYVbm+SlfyqN5YIM8qYdzV2tiLWbiVhItw2w/3JUm WQbg== X-Gm-Message-State: AOAM531aQyt+S+FGIMpa9NmNnzlFYM7fHiXruAo6Xs68iiKsOzanje1U BGmmCTORaegjaK/uiPf/swYV4XUCx/UqPg== X-Google-Smtp-Source: ABdhPJzFRnx0xzF2h3AvILo2O7YyTbjdGgkq0o0IRGZyfVI/nfqc8wW9a2tQ7kQGKlvqsCckRUsa6w== X-Received: by 2002:a1c:f60c:: with SMTP id w12mr8625110wmc.3.1629887754925; Wed, 25 Aug 2021 03:35:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/44] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats Date: Wed, 25 Aug 2021 11:35:10 +0100 Message-Id: <20210825103534.6936-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888647426100001 Content-Type: text/plain; charset="utf-8" All the users of the vmlaldav formats have an 'x bit in bit 12 and an 'a' bit in bit 5; move these to the format rather than specifying them in each insn pattern. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index eb26b103d12..bdcd660aaf4 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -305,19 +305,19 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0= 0 1 0000 @vdup size=3D2 =20 &vmlaldav rdahi rdalo size qn qm x a =20 -@vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ +@vmlaldav .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D%size_16 &v= mlaldav -@vmlaldav_nosz .... .... . ... ... . ... . .... .... qm:3 . \ +@vmlaldav_nosz .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D0 &vmlaldav -VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav -VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav +VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav +VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav =20 -VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav +VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav =20 -VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlal= dav_nosz -VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlal= dav_nosz +VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz +VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz =20 -VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav_nosz +VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_= nosz =20 # Scalar operations =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888770; cv=none; d=zohomail.com; s=zohoarc; b=lD6sYxQRaQDfuSG+t7TJLiwIYxWF5uvTog90xBEdBmG/UnEeOLRq3m88MkcQ/vJU1DXK8avbnlrm3Glivhx/uTWUkrLdOx6R41FzjXF5CQoJQGorhM/QjS0vTx7uYL4ylPyNEiPObfwUQp0mleZfStv5qrbCcH2cjehGF/CFzak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888770; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NJAhFClF5w6TY6HD/a0cefoc3l/jviVuLtp+/3Lj16A=; b=oJPahzcmFUolPOgca8OisR5YX9syc6dJXYwfp8nFM+a2UBVzZ2QfBIEhXB49oR0fcfqiAmYGv+PeccZ1fwxJmFXC2zBmSzd3Iy0q6lk69lAsqUAKTtdH+kQZ08VXc+CijicsZoc2dwGiyUmAaDvySA/9zknaBFtPgVpFfvR+XV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162988877009426.946998855302922; Wed, 25 Aug 2021 03:52:50 -0700 (PDT) Received: from localhost ([::1]:49826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqWW-0000CX-W2 for importer@patchew.org; Wed, 25 Aug 2021 06:52:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGF-0003oe-HP for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:59 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46869) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGD-0005TF-6A for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:35:59 -0400 Received: by mail-wr1-x432.google.com with SMTP id f5so35619203wrm.13 for ; Wed, 25 Aug 2021 03:35:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NJAhFClF5w6TY6HD/a0cefoc3l/jviVuLtp+/3Lj16A=; b=ctktNCqpWieFyvtMM6te9e54fp+ovAOWGS2B9OY1LRTVSP5NNzmNLGo6PpEbld0TTx 4eSItM+/U+XkVmLCrUkislhyuzT9xwQkKz/bq+xqaMWt64TWBYESgdLhRXFNh/ySgCcs ep+ZLSQ6OZQRMc/jQBuXvlgdYP3hnMqVHtv8oRltZym1FU+00zsU2/3CPjBGi3Gy55TL MplpeamRht5yOYZErCiAOaNXc8vzr7wk2vd6BUgJfydkN7UFGhVFap+evRY0QAKMZKpq GT2nrPY/OpFJtjzDcNcKDFh1531dEupaxZPGOK/tIIAiAZ/jivSiCslh4p6v7gA3DO6F zPCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NJAhFClF5w6TY6HD/a0cefoc3l/jviVuLtp+/3Lj16A=; b=bNIjbfAw98bQDlxvPRkCpnQW9DI/Uu+8uZjTgpV55E9nkS6+oq2U+iXckYgQ7ZsfA9 A7+tksQOdF6WcVB2qLQWdGmesyFBKDtqec4uF8wHB4TvAdF2S5H9kg0jyE1+Kk0enmpP ZrOKqJ/ovMtKqfDSbFMjGIBVOQYXKd63Jzm5jOPdwWCW8YgpWRclgElFV+pt+ovwXdrO ZI9QR4uj1jBrd1gOlsZu0b7bj6WcUwV7yRRpe5mBL/tkuqSYr+ms/aMM1uZyEcuNp7R0 4apheRgYPsqqMa3JJxxb6UCWQac9bvV6oYM0gJb4JKqoq6CVWz3B2vX+VPQymT6xGa2K 1kTA== X-Gm-Message-State: AOAM5313OXsOTIPwPnLH6v+LUm2d9fiJBcM4/nzdavn3I0HM9uB7Fumq 0kbxwqwZkaEekm5F6Pg6ynZW/Z0L79QLpg== X-Google-Smtp-Source: ABdhPJz1wNUTOis443zGOAcc2GvnLsFlrwSCdshDCVIfoaeOrw4aFPC1N7sHbHjgljted2P4WvTsPA== X-Received: by 2002:adf:f645:: with SMTP id x5mr19252119wrp.353.1629887755663; Wed, 25 Aug 2021 03:35:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/44] target/arm: Implement MVE integer min/max across vector Date: Wed, 25 Aug 2021 11:35:11 +0100 Message-Id: <20210825103534.6936-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888771735100001 Content-Type: text/plain; charset="utf-8" Implement the MVE integer min/max across vector insns VMAXV, VMINV, VMAXAV and VMINAV, which find the maximum from the vector elements and a general purpose register, and store the maximum back into the general purpose register. These insns overlap with VRMLALDAVH (they use what would be RdaHi=3D0b110). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 20 ++++++++++++ target/arm/mve.decode | 18 +++++++++-- target/arm/mve_helper.c | 66 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 48 +++++++++++++++++++++++++++ 4 files changed, 150 insertions(+), 2 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 0ee5ea3cabd..2c66fcba792 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -379,6 +379,26 @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, e= nv, ptr, i32) DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vmaxvsb, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxvub, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxavb, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vmaxavw, TCG_CALL_NO_WG, i32, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vminvsb, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminvub, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminavb, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminavh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vminavw, TCG_CALL_NO_WG, i32, env, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) =20 diff --git a/target/arm/mve.decode b/target/arm/mve.decode index bdcd660aaf4..83dc0300d69 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -40,6 +40,7 @@ &vcmp qm qn size mask &vcmp_scalar qn rm size mask &shl_scalar qda rm size +&vmaxv qm rda size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -97,6 +98,8 @@ @vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \ mask=3D%mask_22_13 =20 +@vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=3D%qm + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -314,8 +317,19 @@ VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 = . 0 ... 0 @vmlaldav =20 VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav =20 -VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz -VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz +{ + VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv + VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz +} + +{ + VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv + VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz +} =20 VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_= nosz =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ac608fc524b..924ad7f2bdc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1254,6 +1254,72 @@ DO_VADDV(vaddvub, 1, uint8_t) DO_VADDV(vaddvuh, 2, uint16_t) DO_VADDV(vaddvuw, 4, uint32_t) =20 +/* + * Vector max/min across vector. Unlike VADDV, we must + * read ra as the element size, not its full width. + * We work with int64_t internally for simplicity. + */ +#define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ + uint32_t ra_in) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *m =3D vm; \ + int64_t ra =3D (RATYPE)ra_in; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + if (mask & 1) { \ + ra =3D FN(ra, m[H##ESIZE(e)]); \ + } \ + } \ + mve_advance_vpt(env); \ + return ra; \ + } \ + +#define DO_VMAXMINV_U(INSN, FN) \ + DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ + DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ + DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) +#define DO_VMAXMINV_S(INSN, FN) \ + DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ + DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ + DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) + +/* + * Helpers for max and min of absolute values across vector: + * note that we only take the absolute value of 'm', not 'n' + */ +static int64_t do_maxa(int64_t n, int64_t m) +{ + if (m < 0) { + m =3D -m; + } + return MAX(n, m); +} + +static int64_t do_mina(int64_t n, int64_t m) +{ + if (m < 0) { + m =3D -m; + } + return MIN(n, m); +} + +DO_VMAXMINV_S(vmaxvs, DO_MAX) +DO_VMAXMINV_U(vmaxvu, DO_MAX) +DO_VMAXMINV_S(vminvs, DO_MIN) +DO_VMAXMINV_U(vminvu, DO_MIN) +/* + * VMAXAV, VMINAV treat the general purpose input as unsigned + * and the vector elements as signed. + */ +DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) +DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) +DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) +DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) +DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) +DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) + #define DO_VADDLV(OP, TYPE, LTYPE) \ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ uint64_t ra) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 44731fc4eb7..2fce74f86ab 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1321,3 +1321,51 @@ DO_VCMP(VCMPGE, vcmpge) DO_VCMP(VCMPLT, vcmplt) DO_VCMP(VCMPGT, vcmpgt) DO_VCMP(VCMPLE, vcmple) + +static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) +{ + /* + * MIN/MAX operations across a vector: compute the min or + * max of the initial value in a general purpose register + * and all the elements in the vector, and store it back + * into the general purpose register. + */ + TCGv_ptr qm; + TCGv_i32 rda; + + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || + !fn || a->rda =3D=3D 13 || a->rda =3D=3D 15) { + /* Rda cases are UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qm =3D mve_qreg_ptr(a->qm); + rda =3D load_reg(s, a->rda); + fn(rda, cpu_env, qm, rda); + store_reg(s, a->rda, rda); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +#define DO_VMAXV(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ + { \ + static MVEGenVADDVFn * const fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_vmaxv(s, a, fns[a->size]); \ + } + +DO_VMAXV(VMAXV_S, vmaxvs) +DO_VMAXV(VMAXV_U, vmaxvu) +DO_VMAXV(VMAXAV, vmaxav) +DO_VMAXV(VMINV_S, vminvs) +DO_VMAXV(VMINV_U, vminvu) +DO_VMAXV(VMINAV, vminav) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wLBDTVo8uPxsFMze+DTZAhzyPrmDpywm7k5ga1QcofA=; b=W9dR7tUvyId4kQ5RBG7IOzh6/W9CGnVKFgN2bGGB1lNWGPNTdJ6iGZLXpLZ/YL4XgR w93gqmT12bnwEqI7piqoNF6fz2AMoKTJvMp5AP78zW/U9/+bP0bFpjEidqEAPJzIjzsJ szPCzdjVuPJUjMCF6p5Sus5vzgT9gyHHi5CMfnPbpLRLAN8b5QYLUT9eeqzA810dhz0R VmKljeRhYcVbUC2h+cEFs2DJJ8jAvaDNC8lv80TFngo0TY7kZ3qcKrOlNXsM9XomeI9r xzl15q++RaLzKHYxHbMVnlEp/7Y8PUPD8DnyIynvj3noMF4CYxd6KALznlZQ97qS5rYV VimQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wLBDTVo8uPxsFMze+DTZAhzyPrmDpywm7k5ga1QcofA=; b=JEF4HW/1AMNthH6tKD8AhKji0oGfbpPUcDR3OblysiQ6cWAybTByWDZ6V7QJYnEzvp 21qzETPTDrzz/iL365wVoI8Tju8cUyzJ6/yg/bmVSBfHFlWeuXKC9wd6ccqnXdwsUmDb pwtebI7UVR/kZHH34Cto0zy8JANjtvIrM21f5VR+0RJZ0sUNfKn9mCHqToNXWgW4z0mc lYDj0FNIzmzASSRJJ9WbAs9dZvwo9u7XKh1KJY3Es3r9cCW0hOAeEgPS1REtHYjyTlKk QzdUVY5gMbxLLad+j0aQh9Jxz6uiIfpY5ZxxGRP3fvc+WiR4MTFLicNQEWrCkurNAOlK AB4Q== X-Gm-Message-State: AOAM533sYQwc+m7Sktq+xuGfJPKdJl7gH8yJKFzdEFA0/mEARwd2GHyi BaMVevQZB+WvdXOI72e0OEEnPl5asVCOZA== X-Google-Smtp-Source: ABdhPJyGa6goEKJdRo7jlpBUug7TFceGQXbfzqOgMBpAyPS1hSZTQVWS5reGzTUsExdRPg9sa4NYRg== X-Received: by 2002:a1c:a5c2:: with SMTP id o185mr8615452wme.34.1629887756582; Wed, 25 Aug 2021 03:35:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/44] target/arm: Implement MVE VABAV Date: Wed, 25 Aug 2021 11:35:12 +0100 Message-Id: <20210825103534.6936-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888178711100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VABAV insn, which computes absolute differences between elements of two vectors and accumulates the result into a general purpose register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 7 +++++++ target/arm/mve.decode | 6 ++++++ target/arm/mve_helper.c | 26 +++++++++++++++++++++++ target/arm/translate-mve.c | 43 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 2c66fcba792..c7e7aab2cbb 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -402,6 +402,13 @@ DEF_HELPER_FLAGS_3(mve_vminavw, TCG_CALL_NO_WG, i32, e= nv, ptr, i32) DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) =20 +DEF_HELPER_FLAGS_4(mve_vabavsb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vabavsh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vabavsw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vabavub, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vabavuh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vabavuw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 83dc0300d69..c8a06edca78 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -41,6 +41,7 @@ &vcmp_scalar qn rm size mask &shl_scalar qda rm size &vmaxv qm rda size +&vabav qn qm rda size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -386,6 +387,11 @@ VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 1= 00 .... @2scalar rdahi=3D%rdahi rdalo=3D%rdalo } =20 +@vabav .... .... .. size:2 .... rda:4 .... .... .... &vabav qn= =3D%qn qm=3D%qm + +VABAV_S 111 0 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav +VABAV_U 111 1 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav + # Logical immediate operations (1 reg and modified-immediate) =20 # The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 924ad7f2bdc..fed0f3cd610 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1320,6 +1320,32 @@ DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) =20 +#define DO_VABAV(OP, ESIZE, TYPE) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + void *vm, uint32_t ra) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *m =3D vm, *n =3D vn; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + if (mask & 1) { \ + int64_t n0 =3D n[H##ESIZE(e)]; \ + int64_t m0 =3D m[H##ESIZE(e)]; \ + uint32_t r =3D n0 >=3D m0 ? (n0 - m0) : (m0 - n0); \ + ra +=3D r; \ + } \ + } \ + mve_advance_vpt(env); \ + return ra; \ + } + +DO_VABAV(vabavsb, 1, int8_t) +DO_VABAV(vabavsh, 2, int16_t) +DO_VABAV(vabavsw, 4, int32_t) +DO_VABAV(vabavub, 1, uint8_t) +DO_VABAV(vabavuh, 2, uint16_t) +DO_VABAV(vabavuw, 4, uint32_t) + #define DO_VADDLV(OP, TYPE, LTYPE) \ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ uint64_t ra) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2fce74f86ab..247f6719e6f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -45,6 +45,7 @@ typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, = TCGv_i32, TCGv_i32); typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i= 32, TCGv_i32); typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i3= 2); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -1369,3 +1370,45 @@ DO_VMAXV(VMAXAV, vmaxav) DO_VMAXV(VMINV_S, vminvs) DO_VMAXV(VMINV_U, vminvu) DO_VMAXV(VMINAV, vminav) + +static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) +{ + /* Absolute difference accumulated across vector */ + TCGv_ptr qn, qm; + TCGv_i32 rda; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qm | a->qn) || + !fn || a->rda =3D=3D 13 || a->rda =3D=3D 15) { + /* Rda cases are UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qm =3D mve_qreg_ptr(a->qm); + qn =3D mve_qreg_ptr(a->qn); + rda =3D load_reg(s, a->rda); + fn(rda, cpu_env, qn, qm, rda); + store_reg(s, a->rda, rda); + tcg_temp_free_ptr(qm); + tcg_temp_free_ptr(qn); + mve_update_eci(s); + return true; +} + +#define DO_VABAV(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vabav *a) \ + { \ + static MVEGenVABAVFn * const fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_vabav(s, a, fns[a->size]); \ + } + +DO_VABAV(VABAV_S, vabavs) +DO_VABAV(VABAV_U, vabavu) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888696; cv=none; d=zohomail.com; s=zohoarc; b=DeqR2vWcOGjZYc/BGC+GjG0n4fti8Uzz/g6UdeFqHWDZdDNLFbRhs4BL5zsQDYGIuxoun3Yy8QyN5OroNOMd9qXUO5v+Yh97rMttW0Br4breZz3dE7MlBccjhUQsbKe0zUiOmpgxE1SZ0qN1ZZLC79fltJzHTIZz4rc02CkruhY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888696; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rmaXRFhzA84467Map0exaJ0g7V5QOi2vgBWwnWDrh20=; b=KgszVDzxi3OKH/LPAaLqLXB0fhJUd0QvLw9ebC0mW8fg/W2R8SvsFY1YFyf5QZf42kUBvV6BQzkQsWPbvumJFR9kp4bm/7lpNQRKlDd3+6fP8OdcW1HtI4KlS0WdosUXhyS33dOvmVqfaiGXwrGxtvEr5ONYUP16uwqtzXTAHK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888696139327.45358247374827; Wed, 25 Aug 2021 03:51:36 -0700 (PDT) Received: from localhost ([::1]:45066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqVK-0005TH-Vp for importer@patchew.org; Wed, 25 Aug 2021 06:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGH-0003wI-BG for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:01 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:39853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGE-0005UF-NE for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:01 -0400 Received: by mail-wr1-x432.google.com with SMTP id z4so20022044wrr.6 for ; Wed, 25 Aug 2021 03:35:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rmaXRFhzA84467Map0exaJ0g7V5QOi2vgBWwnWDrh20=; b=Ya8nvbsIITLHEbGo9C9gVRj3tDDMfQg04E553+jvgGa1uaRGSHWLeQD/ZglyD9vHLg 8dglgKX1xQJaRpmA+Mb4cJXmHah8HgHmNLhVaBNK+VTCL89WR4Scg3HfQd/HVfenp5Pk JB/SoapdrFcm7+Sazg/UYFQFoM1HlfZogZtSyNft0iwUr+lgecQ5NJTWKpMpJ9nqrd58 7fHp7J4d42tdp9vHsGKpws5yNQjwXPQvaaMuRE7M3PM3Zt/Eml9ixyRAqy2LOi6qDxvA SLF+ceqPyViWtSJUxFX1e07qMfJ6wD5cwA856WC38hHoCGI65R3nFf9Esj3KOofOG2at lT+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rmaXRFhzA84467Map0exaJ0g7V5QOi2vgBWwnWDrh20=; b=ahjkq18N3tEO2r7o3eeZlYjSugsQ3j2KNlUtfPEAsSyVTCd6M7MERmNHCHSJ4cO/Bd u62rjwtjAdY3loWXYnpRqdrjI3q6Dd6Sg/ijTm7GFXzzMpNeCkdQNT98iVB0pTcVTDTm VsmximnMSLSKXmJxITSpCx4Nagir/LjiS0qXc6DJBTAdENN1YMZ8L6ZhTI6eDExShA5P 8T988j4W22f9Um8xdtpUhUv55W9nY5bUzY5GTZ31YkWdO3NNqWLO4duDcXzAy0OQF7Do /tFor6StRav3D0XQFTnGLvs66M7/AtUvaMsTpedJHChjLFF/GONf674Bk5MHUDJWXyue MXGQ== X-Gm-Message-State: AOAM532vyVt1rBjfG3eyI7svhWduhkdDHWc1Izk8ukqZZ8vOJJKGUhSR 354Uwnde+zizox/OAg6RMzQo/7NKnZG6DA== X-Google-Smtp-Source: ABdhPJxfc9qjP5W9XrTxrQfWuqMJCuowGgo2naZ3Ikpv7RAzlfRuqkRbynlgDHsvFt1JkpAG3aYJ7A== X-Received: by 2002:a5d:460a:: with SMTP id t10mr19527622wrq.147.1629887757342; Wed, 25 Aug 2021 03:35:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/44] target/arm: Implement MVE narrowing moves Date: Wed, 25 Aug 2021 11:35:13 +0100 Message-Id: <20210825103534.6936-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888697822100001 Content-Type: text/plain; charset="utf-8" Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN. These take a double-width input, narrow it (possibly saturating) and store the result to either the top or bottom half of the output element. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 20 ++++++++++ target/arm/mve.decode | 12 ++++++ target/arm/mve_helper.c | 78 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 22 +++++++++++ 4 files changed, 132 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index c7e7aab2cbb..17484f74323 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -76,6 +76,26 @@ DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env,= ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vmovnth, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vqmovunbb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovunbh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovuntb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovunth, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vqmovnbsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovnbsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovntsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovntsh, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vqmovnbub, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovnbuh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovntub, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqmovntuh, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vand, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c8a06edca78..d295a693b18 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -153,6 +153,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 + VQMOVUNB 111 0 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op + VQMOVN_BS 111 0 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op } =20 @@ -160,6 +163,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 + VMOVNB 111 1 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op + VQMOVN_BU 111 1 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op } =20 @@ -167,6 +173,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 + VQMOVUNT 111 0 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op + VQMOVN_TS 111 0 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op } =20 @@ -174,6 +183,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_b VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_= esize_h =20 + VMOVNT 111 1 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op + VQMOVN_TU 111 1 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op } =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index fed0f3cd610..72c30f360ac 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1650,6 +1650,84 @@ DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_U= H) DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) =20 +#define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ + { \ + LTYPE *m =3D vm; \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned le; \ + mask >>=3D ESIZE * TOP; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + mergemask(&d[H##ESIZE(le * 2 + TOP)], \ + m[H##LESIZE(le)], mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) +DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) +DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) +DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) + +#define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ + { \ + LTYPE *m =3D vm; \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + bool qc =3D false; \ + unsigned le; \ + mask >>=3D ESIZE * TOP; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + bool sat =3D false; \ + TYPE r =3D FN(m[H##LESIZE(le)], &sat); \ + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ + qc |=3D sat & mask & 1; \ + } \ + if (qc) { \ + env->vfp.qc[0] =3D qc; \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ + DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ + DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) + +#define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ + DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ + DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) + +#define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ + DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ + DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) + +#define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ + DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ + DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) + +#define DO_VQMOVN_SB(N, SATP) \ + do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) +#define DO_VQMOVN_UB(N, SATP) \ + do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) +#define DO_VQMOVUN_B(N, SATP) \ + do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) + +#define DO_VQMOVN_SH(N, SATP) \ + do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) +#define DO_VQMOVN_UH(N, SATP) \ + do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) +#define DO_VQMOVUN_H(N, SATP) \ + do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) + +DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) +DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) +DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) +DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) +DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) +DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) + uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, uint32_t shift) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 247f6719e6f..5c3655efc3c 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -275,6 +275,28 @@ DO_1OP(VCLS, vcls) DO_1OP(VABS, vabs) DO_1OP(VNEG, vneg) =20 +/* Narrowing moves: only size 0 and 1 are valid */ +#define DO_VMOVN(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + NULL, \ + NULL, \ + }; \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VMOVN(VMOVNB, vmovnb) +DO_VMOVN(VMOVNT, vmovnt) +DO_VMOVN(VQMOVUNB, vqmovunb) +DO_VMOVN(VQMOVUNT, vqmovunt) +DO_VMOVN(VQMOVN_BS, vqmovnbs) +DO_VMOVN(VQMOVN_TS, vqmovnts) +DO_VMOVN(VQMOVN_BU, vqmovnbu) +DO_VMOVN(VQMOVN_TU, vqmovntu) + static bool trans_VREV16(DisasContext *s, arg_1op *a) { static MVEGenOneOpFn * const fns[] =3D { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888821; cv=none; d=zohomail.com; s=zohoarc; b=C3yle9YtCuYgCpPqyS/o+8iDvIfam22oEMX7I/b53gzDoYe/DGUuR8PCKPi5WjAmqEdwxt9VzbPPqcoRzzyh8C4P+YHQf8wqPOTxh7z1ntHIJILi0kyVor7j3EiBkrx56njuPlT8W7MylFFsdXVjvnPQyP3FLTN2oUF4UPP+syU= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bjNMiUKUCYi1YMIhagOS3VyZtwvdg9vDgXthAdg4/AU=; b=iIxVYzcAC2yXRfxEtnMRwUDxJG122KdpLFt9Kovgtt+ZJehFhgPsRpCQive1T8G7Lz /Nu1bO9VRmZgh6++aNn+kJBCfsWQv2UaFlFmxp3RMBECYVfAjCPhjX7eFAiNALP/4jMk Yn/s7bHbR8qBk4panMk6Q47mRyQZpMyhcfpBA0j62/0vd8TA2etnD2+gwKgAzW02IKir jfQCA9IQjwcOat6CpoFBEdq/o49ubYfbufD75FWufRyNV5QhdWDBgKVAhqvuXfS+IL3T Fp3pTyA8heBGQDjQRDfdDj0oRa7RrbLun82XIxRQQCkN/H2hPMnIrDn4bZ2u4z4kDPtH LK0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bjNMiUKUCYi1YMIhagOS3VyZtwvdg9vDgXthAdg4/AU=; b=gzf/J+R+MVXfBaArjf70qOTo/Lfv9RSiQuLb/DJFPP1lr6wyP15amidMZ35Af1Az/4 QZRRjP4tW0uZul892BrOdpqlafmVhBPw/Phkm4PzWLyAQA+m9SJkzwufaAC1GZhNMcjq F4iNybmS8kTzwjDGl3j2WQGoAh16MAR88yc6aGemHSsrlbfwi9UrWFzH/t+NAnef682p Ynf9/iKY0kpM3MlVXWOvEgONOn4glU8R0roZodhjdTQtJd9EH+nXfGJyxD9sbmjpmh3q DQGhLomAUoZSECr325mqVci4U7odrhiBztGjxM4yHJC0lCyyn/On8bKYttiFHXuXgtrv L1YQ== X-Gm-Message-State: AOAM533XT3pt+suQf0+farsNQN7wINmyhQc4mVquaLvQ+NoDxcsgVeGX 6e4CxN0yhkhVi3TFxmQOsFkt1vtNF8WfdA== X-Google-Smtp-Source: ABdhPJzMnGqATNgjE8Y4YX6fU+DapxhULgKMxRK4y0pPp519MfesqFtCOO9FLWxnZjfNuRnDrsderQ== X-Received: by 2002:a5d:51c6:: with SMTP id n6mr24451606wrv.370.1629887757958; Wed, 25 Aug 2021 03:35:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/44] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn Date: Wed, 25 Aug 2021 11:35:14 +0100 Message-Id: <20210825103534.6936-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888823147100001 Content-Type: text/plain; charset="utf-8" The MVEGenDualAccOpFn is a bit misnamed, since it is used for the "long dual accumulate" operations that use a 64-bit accumulator. Rename it to MVEGenLongDualAccOpFn so we can use the former name for the 32-bit accumulator insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 5c3655efc3c..676411e05cb 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -38,7 +38,7 @@ typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); -typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); +typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr,= TCGv_i64); typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i3= 2); @@ -652,7 +652,7 @@ static bool trans_VQDMULLT_scalar(DisasContext *s, arg_= 2scalar *a) } =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, - MVEGenDualAccOpFn *fn) + MVEGenLongDualAccOpFn *fn) { TCGv_ptr qn, qm; TCGv_i64 rda; @@ -710,7 +710,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlal= dav *a, =20 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[4][2] =3D { + static MVEGenLongDualAccOpFn * const fns[4][2] =3D { { NULL, NULL }, { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, @@ -721,7 +721,7 @@ static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlal= dav *a) =20 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[4][2] =3D { + static MVEGenLongDualAccOpFn * const fns[4][2] =3D { { NULL, NULL }, { gen_helper_mve_vmlaldavuh, NULL }, { gen_helper_mve_vmlaldavuw, NULL }, @@ -732,7 +732,7 @@ static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlal= dav *a) =20 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[4][2] =3D { + static MVEGenLongDualAccOpFn * const fns[4][2] =3D { { NULL, NULL }, { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, @@ -743,7 +743,7 @@ static bool trans_VMLSLDAV(DisasContext *s, arg_vmlalda= v *a) =20 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[] =3D { + static MVEGenLongDualAccOpFn * const fns[] =3D { gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, }; return do_long_dual_acc(s, a, fns[a->x]); @@ -751,7 +751,7 @@ static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vml= aldav *a) =20 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[] =3D { + static MVEGenLongDualAccOpFn * const fns[] =3D { gen_helper_mve_vrmlaldavhuw, NULL, }; return do_long_dual_acc(s, a, fns[a->x]); @@ -759,7 +759,7 @@ static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vml= aldav *a) =20 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) { - static MVEGenDualAccOpFn * const fns[] =3D { + static MVEGenLongDualAccOpFn * const fns[] =3D { gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, }; return do_long_dual_acc(s, a, fns[a->x]); --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OIN56S8ygwPfGNHYDNt+mnV7Jb27Ma6YNdL6z4Tr/Uk=; b=oCzQ19ZAycPhINS0JPqAnf0NYScVxSGpwdoB2/RNShyToXsQ3jEgtJlpNJK0YmxiHW GWYDR2bMtHPtRSPU5asmZVfflh+gMB49/g3UN8TMFM6X01qtWeqTcQcmv6YbUPPRAbdI k1tY+nFOqAdezViDvwwXNYiYAyTfa/CkoRmaC+iBUhWGlVT2Sd6ZyASc5WytMsHiCJGa WPYu25dLF1wGx9BQgync2NMog9agl9X9sSTnX8aTB707TBSQS7AlC9xQZeVyeIsqq1jC 7G5O1yXqtCsQX0qCp0kFNGMcu6WnODY5P19Q/X9NBhrRTYbDLrhFOwQKv3vrIrRUyCgE d+kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OIN56S8ygwPfGNHYDNt+mnV7Jb27Ma6YNdL6z4Tr/Uk=; b=T2aFttw0S3KQE9aqHUjE0pq6VJDLRkxbXsbSojpDzS2M9A7oua8YiF/LxeplIKaC7i oU+0oPnEb/NY3+NH4UZ5Nui4LBDEtqcYN56nxqU5IvgigGEbpKgZu5v5hT8CjgM3CsJF CgKRrteTWrkq6xhbeBIa5oDcO7hF8K0wf6NnkAnZttSmZXDpbFd6KvL+7UmNFoyN83yU xXBD7lWLlOqNocjWk9Sly7h0Gptx6m1FCtAQJuXnhSRS5OggsBKv/gezl1I1xYD9ROMQ rFspOEqob/3OuwL6SyQnog5gWeoHjK19kUvIEfvFw4D0hj1bmwHX5gscOiI8wYrDKnL5 hMfg== X-Gm-Message-State: AOAM530d806R+ZA/ziUqvEygaKXdH6DsgGQkr3mzc05uH8vyDSv0JGG8 f0AZ5RXFsUYohbqqjTzHo4Sz4TR1LNEURQ== X-Google-Smtp-Source: ABdhPJxqLO0VRkyklksPfLUA1BiIPMqQVhMIiyq8knTbKrS3r/W5/R//DSPA8xgcivKoHuXlK8oyrg== X-Received: by 2002:adf:fcc5:: with SMTP id f5mr25046974wrs.114.1629887758750; Wed, 25 Aug 2021 03:35:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/44] target/arm: Implement MVE VMLADAV and VMLSLDAV Date: Wed, 25 Aug 2021 11:35:15 +0100 Message-Id: <20210825103534.6936-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888891974100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMLADAV and VMLSLDAV insns. Like the VMLALDAV and VMLSLDAV insns already implemented, these accumulate multiplied vector elements; but they accumulate a 32-bit result rather than a 64-bit one. Note that these encodings overlap with what would be RdaHi=3D0b111 for VMLALDAV, VMLSLDAV, VRMLALDAVH and VRMLSLDAVH. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 17 ++++++++++ target/arm/mve.decode | 33 +++++++++++++++++--- target/arm/mve_helper.c | 41 ++++++++++++++++++++++++ target/arm/translate-mve.c | 64 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 150 insertions(+), 5 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 17484f74323..34d644a519c 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -392,6 +392,23 @@ DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i= 64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i= 64) DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, = i64) =20 +DEF_HELPER_FLAGS_4(mve_vmladavsb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavsh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavsw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavub, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavuh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavuw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vmladavsxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavsxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmladavsxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlsdavxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vaddvsb, TCG_CALL_NO_WG, i32, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vaddvub, TCG_CALL_NO_WG, i32, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d295a693b18..cec5a51b0ee 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -320,32 +320,55 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0= 0 1 0000 @vdup size=3D2 %size_16 16:1 !function=3Dplus_1 =20 &vmlaldav rdahi rdalo size qn qm x a +&vmladav rda size qn qm x a =20 @vmlaldav .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D%size_16 &v= mlaldav @vmlaldav_nosz .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \ qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D0 &vmlaldav -VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav -VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav +@vmladav .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \ + qn=3D%qn rda=3D%rdalo size=3D%size_16 &vmladav +@vmladav_nosz .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \ + qn=3D%qn rda=3D%rdalo size=3D0 &vmladav =20 -VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav +{ + VMLADAV_S 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav + VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav +} +{ + VMLADAV_U 1111 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav + VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav +} + +{ + VMLSDAV 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 1 @vmladav + VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav +} + +{ + VMLSDAV 1111 1110 1111 ... 0 ... . 1110 . 0 . 0 ... 1 @vmladav_n= osz + VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_= nosz +} + +VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_n= osz +VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_n= osz =20 { VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv + VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_n= osz VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz } =20 { VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv + VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_n= osz VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_= nosz } =20 -VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_= nosz - # Scalar operations =20 VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 72c30f360ac..ea206c932bc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1189,6 +1189,47 @@ DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=3D, -=3D) DO_LDAV(vmlsldavsw, 4, int32_t, false, +=3D, -=3D) DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=3D, -=3D) =20 +/* + * Multiply add dual accumulate ops + */ +#define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + void *vm, uint32_t a) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *n =3D vn, *m =3D vm; = \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if (mask & 1) { \ + if (e & 1) { \ + a ODDACC \ + n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ + } else { \ + a EVENACC \ + n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ + } \ + } \ + } \ + mve_advance_vpt(env); \ + return a; \ + } + +#define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) + +#define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ + DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) + +DO_DAV_S(vmladavs, false, +=3D, +=3D) +DO_DAV_U(vmladavu, false, +=3D, +=3D) +DO_DAV_S(vmlsdav, false, +=3D, -=3D) +DO_DAV_S(vmladavsx, true, +=3D, +=3D) +DO_DAV_S(vmlsdavx, true, +=3D, -=3D) + /* * Rounding multiply add long dual accumulate high. In the pseudocode * this is implemented with a 72-bit internal accumulator value of which diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 676411e05cb..92ed1be83e7 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -46,6 +46,7 @@ typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr,= TCGv_i32, TCGv_i32, TC typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i3= 2); +typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -765,6 +766,69 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmla= ldav *a) return do_long_dual_acc(s, a, fns[a->x]); } =20 +static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn= *fn) +{ + TCGv_ptr qn, qm; + TCGv_i32 rda; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qn) || + !fn) { + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + + /* + * This insn is subject to beat-wise execution. Partial execution + * of an A=3D0 (no-accumulate) insn which does not execute the first + * beat must start with the current rda value, not 0. + */ + if (a->a || mve_skip_first_beat(s)) { + rda =3D load_reg(s, a->rda); + } else { + rda =3D tcg_const_i32(0); + } + + fn(rda, cpu_env, qn, qm, rda); + store_reg(s, a->rda, rda); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + + mve_update_eci(s); + return true; +} + +#define DO_DUAL_ACC(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_vmladav *a) \ + { \ + static MVEGenDualAccOpFn * const fns[4][2] =3D { \ + { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb }, \ + { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh }, \ + { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw }, \ + { NULL, NULL }, \ + }; \ + return do_dual_acc(s, a, fns[a->size][a->x]); \ + } + +DO_DUAL_ACC(VMLADAV_S, vmladavs) +DO_DUAL_ACC(VMLSDAV, vmlsdav) + +static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a) +{ + static MVEGenDualAccOpFn * const fns[4][2] =3D { + { gen_helper_mve_vmladavub, NULL }, + { gen_helper_mve_vmladavuh, NULL }, + { gen_helper_mve_vmladavuw, NULL }, + { NULL, NULL }, + }; + return do_dual_acc(s, a, fns[a->size][a->x]); +} + static void gen_vpst(DisasContext *s, uint32_t mask) { /* --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889003; cv=none; d=zohomail.com; s=zohoarc; b=cR/mGiegQCLmtOh1EuLrc8Nr3U8Hz6OR00rI5HaCvOGMiXTd9laKq6M/tm7fnRNIm6zysk/cPIxKB5PVpZ0nJp6ljs8Ccn5QfhmZr8SAZos7zj7KqS1HpIqQeRf7ukOKbkKXP6+H5oTcsP2iGjUnpppYTK7Zeu86qavrfHpZJcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889003; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NJusvALsxx1wfuPxnrHFhdTt2/bgniw0YypUZm+dSAo=; b=KeQRh9ME4cOBrbC0K9ZuxW9tIi+VV4wcCobYPOUzjPqsX+l4VgUsBlaF9p/hlI7jPh1Ekub31t2kTzZOdly8IFKAx1PDe2IK+YEMg/FEYwIYTbwtUIXxskv9UD6RlAiXApgv5mHKOwi5oBn/UFmX42KC3E6XNnLnqSFHKaEmvgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629889003764885.5534347090152; Wed, 25 Aug 2021 03:56:43 -0700 (PDT) Received: from localhost ([::1]:38864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqaI-0003Ft-KT for importer@patchew.org; Wed, 25 Aug 2021 06:56:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGI-00040y-NX for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:02 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52895) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGG-0005Vt-KU for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:02 -0400 Received: by mail-wm1-x32c.google.com with SMTP id f10so14671535wml.2 for ; Wed, 25 Aug 2021 03:36:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NJusvALsxx1wfuPxnrHFhdTt2/bgniw0YypUZm+dSAo=; b=Pw1AJWwYGUNji5T9gB9E8YQyfZyTvckcd4SVR4xw7E5xwGiUDh4IaosrpeP+htU2TQ V5bFemN1NJ73jsL45Qk4HSEPw6SPY70VGpyF+VpJnllC/24QBcywjNqJcO9//HjLz7Jm K4/BbNdXFAwZ4ZfwzKi3JWW/2jJQtAu5/+CaySC1fJq2f9gsLvX57D+08igyPQfJUl0W YAc0zEiR+H5EXY58miKQdngFN8ntiMc2ZOs6iXT4vAqFBga0fzshwtRq4jUNsVt2gz/b YTousboD29g8lEGaxtOZBIcSoLRtHw8wua/KjUctwEG80fQgt6aUCwMmGrWJE7OnLoxY 2SDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NJusvALsxx1wfuPxnrHFhdTt2/bgniw0YypUZm+dSAo=; b=kN3VnVOiQb8SFZwJD+Pb9ZXgFCz2OOZTqECBu2x4rBpSqRU7TgAH2aq5KpOQbR1p62 ET1y9O3TsupPeVg9PoM0glZwgPhonm9ADvBQLq3m9C4aBC6FH5AtrIRoH5jngW1AW9km zHhm+b2auDTSEuDfXgvHptURcH4eeIlXgloEg48xVtqjgBwvGtPI/GpOik75W7dMOtdx pvf2vbams7SMeG5tY1acfSkT5HzRtj2A4sH9c3SsMUcqIgI19wH0bsRHprOIbz/lV0jC 6dNfaA0nOWM+7RzXO6yvcToIcjJ02aaI6g0kjhjjEfVEn+yVKAQkzB4p8Aagje5Oy6zL mJ6g== X-Gm-Message-State: AOAM533gK8id50I5yZa8OS123FBIi6q/iSAcNP7hmbez9m4JB5fmqGjJ U1j2ubbGO5jM8sZk6P+SqbfzZxzSk2arSw== X-Google-Smtp-Source: ABdhPJwKpRKTXgngdhNVx9N+UYMzsme4/OAkhAMS/FR5/UsfiWmgYoMYeF0QdqOvvC7evsUvKObjLA== X-Received: by 2002:a7b:c387:: with SMTP id s7mr8369424wmj.26.1629887759392; Wed, 25 Aug 2021 03:35:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/44] target/arm: Implement MVE VMLA Date: Wed, 25 Aug 2021 11:35:16 +0100 Message-Id: <20210825103534.6936-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889004249100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMLA insn, which multiplies a vector by a scalar and accumulates into another vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 1 + target/arm/mve_helper.c | 5 +++++ target/arm/translate-mve.c | 1 + 4 files changed, 11 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 34d644a519c..328e31e2665 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -367,6 +367,10 @@ DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_W= G, void, env, ptr, ptr, i3 DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vmlab, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlah, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmlaw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vmlasb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vmlash, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vmlasw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index cec5a51b0ee..cd9c806a11c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -413,6 +413,7 @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 11= 0 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar =20 # The U bit (28) is don't-care because it does not affect the result +VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar =20 # Vector add across vector diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ea206c932bc..8004b9bb728 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1008,6 +1008,11 @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QR= DMULH_B) DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) =20 +/* Vector by scalar plus vector */ +#define DO_VMLA(D, N, M) ((N) * (M) + (D)) + +DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) + /* Vector by vector plus scalar */ #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) =20 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 92ed1be83e7..f8899af352d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -620,6 +620,7 @@ DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) +DO_2OP_SCALAR(VMLA, vmla) DO_2OP_SCALAR(VMLAS, vmlas) =20 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.35.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TU5VLZPJYGx6Qh3NO9t/DQaQygrYYqxLMGPPbmN9qvY=; b=tyFWMeFSNvFxmzL1iABRAIxdVaFGR74+Gc+uXk94zWibC656gjHi0rufrlMImjvRDc +5WEckwKDA+sTUSo/JpNRJomsQXxrxwrO93bZeSs6iFB+xIk3yjqXJpErRqGwfNtbeRJ pc7gqc8DvgyK7ipubKEC7pIa1gXMiGla2GzqMRsnF/YszukIwIGG4gLC+dTOdxb+03Il o2nd3w9IqXCsWaZbGqhGeM1Owbjm7CZrC+xO0RjakZlub00bfpMIpueHsT7rG4KMvnl+ XqrgHhBYmwqHIdpM1DNjuahEgGKX9YhMs6E+RzllD2tw9b6XhostlLemqNKehoYf7tl+ 2pRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TU5VLZPJYGx6Qh3NO9t/DQaQygrYYqxLMGPPbmN9qvY=; b=QJckL0E8j+6UF07O7ujKNpBj5hc4LNrNrC9MMqAfg4bL1CEVJ1KfZtqjVISYX4JpQs AY+Pk/0mjUZmL11mFa/wJOz0fS3leI6zGGGqAjR9FjNSIzFUjfF1VC2HhxRtfsjBhsXK V4CB26vIHpmzoOSs9URvR9zGJJrjiHR71l3Is9sJxQc3wzEYM0W89tqIzNrNFrydYNTj bvuZ8reUUzBS5IamXjTDuNS+bZLmO/3ZTDWhyvGJG4OtuypigePlg6MPnS8LkwfWdk7+ s/bu+ea+eo3/5WAyLoLtRy+Vy5THSkOA92NzBiZ0FPycNpi6O7sPmLer1dMXqX0UV5lo 0Xpw== X-Gm-Message-State: AOAM5321UDSzeRdGgAWnv/+Nc+KeMg5Ot7y4qLbNPAjm1sZGCCauwPve Xwp1DWzYxx0uKn426zRmXhZXcpt97lFHNA== X-Google-Smtp-Source: ABdhPJz/zXfd5yAfOEpCuNfBc/nmw2ArAPY3LKprYOHlmRawC+ZBXKn0BuxesZyQXXX30SKcrOtr6w== X-Received: by 2002:a5d:64e6:: with SMTP id g6mr13427683wri.288.1629887760120; Wed, 25 Aug 2021 03:36:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/44] target/arm: Implement MVE saturating doubling multiply accumulates Date: Wed, 25 Aug 2021 11:35:17 +0100 Message-Id: <20210825103534.6936-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888055248100002 Content-Type: text/plain; charset="utf-8" Implement the MVE saturating doubling multiply accumulate insns VQDMLAH, VQRDMLAH, VQDMLASH and VQRDMLASH. These perform a multiply, double, add the accumulator shifted by the element size, possibly round, saturate to twice the element size, then take the high half of the result. The *MLAH insns do vector * scalar + vector, and the *MLASH insns do vector * vector + scalar. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 +++++++ target/arm/mve.decode | 5 ++ target/arm/mve_helper.c | 95 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 ++ 4 files changed, 120 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 328e31e2665..2f54396b2df 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -375,6 +375,22 @@ DEF_HELPER_FLAGS_4(mve_vmlasb, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vmlash, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vmlasw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vqdmlahb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmlahh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmlahw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vqrdmlahb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqrdmlahh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqrdmlahw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vqdmlashb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmlashh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmlashw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vqrdmlashb, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrdmlashh, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(mve_vqrdmlashw, TCG_CALL_NO_WG, void, env, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index cd9c806a11c..7a6de3991b6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -416,6 +416,11 @@ VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 1= 10 .... @2scalar VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar =20 +VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar +VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar +VQDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 110 .... @2scalar +VQDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 110 .... @2scalar + # Vector add across vector { VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 r= da=3D%rdalo diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 8004b9bb728..a69fcd2243c 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -964,6 +964,28 @@ DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdml= sdh_w) mve_advance_vpt(env); \ } =20 +#define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + bool qc =3D false; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + bool sat =3D false; \ + mergemask(&d[H##ESIZE(e)], \ + FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ + mask); \ + qc |=3D sat & mask & 1; \ + } \ + if (qc) { \ + env->vfp.qc[0] =3D qc; \ + } \ + mve_advance_vpt(env); \ + } + /* provide unsigned 2-op scalar helpers for all sizes */ #define DO_2OP_SCALAR_U(OP, FN) \ DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ @@ -1008,6 +1030,79 @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QR= DMULH_B) DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) =20 +static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *= sat) +{ + int64_t r =3D (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); + return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; +} + +static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, + int round, bool *sat) +{ + int64_t r =3D (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; +} + +static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, + int round, bool *sat) +{ + /* + * Architecturally we should do the entire add, double, round + * and then check for saturation. We do three saturating adds, + * but we need to be careful about the order. If the first + * m1 + m2 saturates then it's impossible for the *2+rc to + * bring it back into the non-saturated range. However, if + * m1 + m2 is negative then it's possible that doing the doubling + * would take the intermediate result below INT64_MAX and the + * addition of the rounding constant then brings it back in range. + * So we add half the rounding constant and half the "c << esize" + * before doubling rather than adding the rounding constant after + * the doubling. + */ + int64_t m1 =3D (int64_t)a * b; + int64_t m2 =3D (int64_t)c << 31; + int64_t r; + if (sadd64_overflow(m1, m2, &r) || + sadd64_overflow(r, (round << 30), &r) || + sadd64_overflow(r, r, &r)) { + *sat =3D true; + return r < 0 ? INT32_MAX : INT32_MIN; + } + return r >> 32; +} + +/* + * The *MLAH insns are vector * scalar + vector; + * the *MLASH insns are vector * vector + scalar + */ +#define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) +#define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) +#define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) +#define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) +#define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) +#define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) + +#define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) +#define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) +#define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) +#define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) +#define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) +#define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) + +DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) +DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) +DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) +DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) +DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) +DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) + +DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) +DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) +DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) +DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) +DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) +DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) + /* Vector by scalar plus vector */ #define DO_VMLA(D, N, M) ((N) * (M) + (D)) =20 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index f8899af352d..e3e115c1aa9 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -622,6 +622,10 @@ DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) DO_2OP_SCALAR(VMLA, vmla) DO_2OP_SCALAR(VMLAS, vmlas) +DO_2OP_SCALAR(VQDMLAH, vqdmlah) +DO_2OP_SCALAR(VQRDMLAH, vqrdmlah) +DO_2OP_SCALAR(VQDMLASH, vqdmlash) +DO_2OP_SCALAR(VQRDMLASH, vqrdmlash) =20 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889090; cv=none; d=zohomail.com; s=zohoarc; b=j4HMktyu02TznCCFu3+6fWGwY6EHPGFVOoDE/GKTPn3+QQp5+RcsLCSJsEB9DicH2WdfoVlNwFCqyRKJcGTIVRKlpWCubWfpyobKx8/WDXA3JcTBcBxjuDlqI7oy9ICjTrUs/MNjqV+BgZVXlQ+sC0Rfjwk5RHXxX4L981ob6pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889090; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2WneyhHKqIU7XDRl0YOpayRXl21coDrx+TpbKifug4Y=; b=lBNacgj8c5NhGLktJXEJn6ZE8k0MUjMvMH3HSWpcJ6NOv5PJx8pE8ySrmdgMpKeXW1axfvMN/yivxljIUOVZ+SYu2gaThjHmRZ5QyUsuUBxVV/FOuFqvrD9BaPflkc29T7fuNl1MEID8j/yCv6is8tR3ZtyoWU+N8++YlqeZJ6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629889090164554.8207147630776; Wed, 25 Aug 2021 03:58:10 -0700 (PDT) Received: from localhost ([::1]:47446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqbh-0000WJ-35 for importer@patchew.org; Wed, 25 Aug 2021 06:58:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGK-00046z-9i for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:04 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:55842) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGI-0005Wo-B8 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:03 -0400 Received: by mail-wm1-x336.google.com with SMTP id g135so5369287wme.5 for ; Wed, 25 Aug 2021 03:36:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2WneyhHKqIU7XDRl0YOpayRXl21coDrx+TpbKifug4Y=; b=DsTzT33ZOE1ztNhTKAWKwUiTomASiAOI/o3q30zeL8zzDI0m9pbbz5PRxD8clsjZ3i 9EvJUw8WLX9mOposq8K94LXbclyztUwKzYjxCygUqEpUgvKnCzjo1fH0ukGcUhqk2cFk UDnIBe6SOp6iHrrEJGP2+cng6yRq3y0NorQ0OFNT9yyCQGVv9GBaDps7ZDNDTJ+KqzaC Rmy0mvQujUMPKhZEn1InsbeIiV2yO356wsUhzyo87q9voHiOQkGnP505PDd/yULKWo/v UG3GH/pPrS2pORYvN2w4DfLqBW601mNgepfIW8glUYXs8qOw8BypWG88rqUBtxnSiYKO osBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2WneyhHKqIU7XDRl0YOpayRXl21coDrx+TpbKifug4Y=; b=YW4KFCGKYU4trMUCwM+oSwsVyR52jt7G5RxjDjgbishaBuyfyttO9gs7m+Q5rQtkxp Ax3TMzdrLlNvz/p8kzCYyQCwgrd3HdgtsFeX4pl+6/OB2h7U/YqIqwTxEA0p6fA3GWbn n4Ald02runi7wRjZra0SYillxJpD+MLi+oNG2FnJeLrEViSP+FjiyUdRhUmxvgkMajrn igL7kSKtLKcSJcgRhs+BBq+9U9MmsmjWTdbVL5zq2o1HnULklgj/3ZOOvU1pCeBLVHbz t0O2YYza1YRR05ygGjr0YS3caHZPDnlriOWJB5dWIep2nvFhpzVnLUpNR0Gu2AFsshuw 6mUQ== X-Gm-Message-State: AOAM533ERJR9muVXXaYTo3WMyN9B8myeOLgEpPA5WKDS9W5lkX0klW80 ePoGEWzDH8vxS1P2EphL3wZx9EdSTUgJfQ== X-Google-Smtp-Source: ABdhPJyWUW9O80nwGrjLX/tpdQAJrn8qeyULm3O53LRVqTtTzf9Prb7qKYMDODK4AgdcGWUJfWB1EQ== X-Received: by 2002:a1c:1d1:: with SMTP id 200mr8394382wmb.53.1629887760800; Wed, 25 Aug 2021 03:36:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/44] target/arm: Implement MVE VQABS, VQNEG Date: Wed, 25 Aug 2021 11:35:18 +0100 Message-Id: <20210825103534.6936-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889092333100001 Content-Type: text/plain; charset="utf-8" Implement the MVE 1-operand saturating operations VQABS and VQNEG. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 50 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 2f54396b2df..f9345bfafc7 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -76,6 +76,14 @@ DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env,= ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vqabsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqabsw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vqnegb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vqnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 7a6de3991b6..a05b882f9d9 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -279,6 +279,9 @@ VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 .= 0 ... 0 @1op VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op =20 +VQABS 1111 1111 1 . 11 .. 00 ... 0 0111 01 . 0 ... 0 @1op +VQNEG 1111 1111 1 . 11 .. 00 ... 0 0111 11 . 0 ... 0 @1op + &vdup qd rt size # Qd is in the fields usually named Qn @vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=3D%qn &v= dup diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a69fcd2243c..6539012ddd8 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2200,3 +2200,40 @@ void HELPER(mve_vpsel)(CPUARMState *env, void *vd, v= oid *vn, void *vm) } mve_advance_vpt(env); } + +#define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + bool qc =3D false; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + bool sat =3D false; \ + mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ + qc |=3D sat & mask & 1; \ + } \ + if (qc) { \ + env->vfp.qc[0] =3D qc; \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VQABS_B(N, SATP) \ + do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) +#define DO_VQABS_H(N, SATP) \ + do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) +#define DO_VQABS_W(N, SATP) \ + do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) + +#define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SA= TP) +#define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, = SATP) +#define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, = SATP) + +DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) +DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) +DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) + +DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) +DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) +DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e3e115c1aa9..f2213ec8cde 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -275,6 +275,8 @@ DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) DO_1OP(VABS, vabs) DO_1OP(VNEG, vneg) +DO_1OP(VQABS, vqabs) +DO_1OP(VQNEG, vqneg) =20 /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NHW+bio5vpc+hqjWMB9d8Ta5DNoBT2v+EDTK/IAK+GE=; b=uBRpAo6YsqjOe/+ZSotZNVKIRm1ciUoy/niKIsv8N2Kd/A9v8M9adevaVFGCZEyZOD c1wHRhVr+lH1+hPzhy2tXQtS0OyTc9YpmZur8PUqSLS9vxQCofKhojaYeW3ixUSA4VDN hSJvuB2bNNwSH7dEopZ7z11G809lDBg9X3Rknd/RMpBp0br8lcyPJsBh0ncp7r9HT3K0 6pGMwPuQZExrX1/NxRIej5GhXqBSAWDIHwLE17dMCHXrTgIzG09NDd68+4DOinAg3tnn 4G1MbqS8KLQ+f1+Y5oxo2sIfEs7KpThVwqBBSYgmeBzw6RUQN/e5faxjyQExFWtXaxL4 QSQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NHW+bio5vpc+hqjWMB9d8Ta5DNoBT2v+EDTK/IAK+GE=; b=O+ikr8pnruFEZzXRDxhLizeIq35iLJtt+Lo3XrlKYURBmbEWV9LU12+0SdYVvemJk+ C1u7zYZw2fp3306OelvsgU1xcKhZbkLDiJqpcwQSU5X7UM5YC581f/wLMACOWRRDf264 uLsejA4Sdg6GGreL2UhVyhMRLGY89816I1lVolPHIyT6GbYYpquIbTM3ivJUpkckoIUr VOl38/MsfEiMyEsE2whVw3k8cCyxhxy6bqSRluL4039C8+5BpNveEbtm5hn8N+gA8MRq +rrEIP0n4oaqkUbPGSb2Qe+5aJhSVzyRAZqSiBvpQSezSctstbILwLJKx81JeLF3WigH 4eoQ== X-Gm-Message-State: AOAM530+WNyMto+r5C3QCTPlysHdydu1JDgsFTvwsx/Vif3oixvHvnTI VTn4hEEavJrYdz1mPQW1QrbFC320sX15ZQ== X-Google-Smtp-Source: ABdhPJzzmnHOp6+7SZdYF7cRD8+D/L7qDHDANQ4rslx9GnJ5uzMrQzoyfc6wmeYtja9TBld57v02Lw== X-Received: by 2002:adf:82b0:: with SMTP id 45mr2758456wrc.161.1629887761412; Wed, 25 Aug 2021 03:36:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/44] target/arm: Implement MVE VMAXA, VMINA Date: Wed, 25 Aug 2021 11:35:19 +0100 Message-Id: <20210825103534.6936-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888931468100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VMAXA and VMINA insns, which take the absolute value of the signed elements in the input vector and then accumulate the unsigned max or min into the destination vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 4 ++++ target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f9345bfafc7..651020aaad8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -84,6 +84,14 @@ DEF_HELPER_FLAGS_3(mve_vqnegb, TCG_CALL_NO_WG, void, env= , ptr, ptr) DEF_HELPER_FLAGS_3(mve_vqnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vqnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 +DEF_HELPER_FLAGS_3(mve_vmaxab, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vmaxah, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vmaxaw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vminab, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vminah, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vminaw, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index a05b882f9d9..0955ed0cc22 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -156,6 +156,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VQMOVUNB 111 0 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op VQMOVN_BS 111 0 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op =20 + VMAXA 111 0 1110 0 . 11 .. 11 ... 0 1110 1 0 . 0 ... 1 @1op + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op } =20 @@ -176,6 +178,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 = . 1 ... 0 @2op VQMOVUNT 111 0 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op VQMOVN_TS 111 0 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op =20 + VMINA 111 0 1110 0 . 11 .. 11 ... 1 1110 1 0 . 0 ... 1 @1op + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op } =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 6539012ddd8..d326205cbf0 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2237,3 +2237,29 @@ DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) + +/* + * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its + * absolute value; we then do an unsigned comparison. + */ +#define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ + { \ + UTYPE *d =3D vd; \ + STYPE *m =3D vm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + UTYPE r =3D DO_ABS(m[H##ESIZE(e)]); \ + r =3D FN(d[H##ESIZE(e)], r); \ + mergemask(&d[H##ESIZE(e)], r, mask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) +DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) +DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) +DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) +DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) +DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index f2213ec8cde..02c26987a2d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -277,6 +277,8 @@ DO_1OP(VABS, vabs) DO_1OP(VNEG, vneg) DO_1OP(VQABS, vqabs) DO_1OP(VQNEG, vqneg) +DO_1OP(VMAXA, vmaxa) +DO_1OP(VMINA, vmina) =20 /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Qp88lepzk56QVkhZRSGO2VDv/JbZJtAi4P83EneyDdw=; b=A44bHS3ZwSAXAjBPRxcgBd6VirTPvZtoql3YQr1BVgA2scJ/JTqdfqT3kke21sWDU3 VpPiy8v/xyZujqjztAV1nVipb1jUke0ruWFO4sPBs8gF7+en45At6ygD3qvLFORu0HsH VBXuXXhC92fqhNoQpPJJvxSGeh4RbvQWeFYG2ij1TpxF6KTxuRvhEMH4Tmo9JmD9x1H+ 2d1RQ7x3Ch12n2/gzzXOJk+QfHCm3PXmLk2IPckJVFx3gXoTO2TjhpEaNyHpiYkgZ5/d 9z6sWC0G+qUewdds9ianjnrGCF/wYDBr/oj9CR+TB3qIAtPKJiBgWiO0U2Apab7wMbC2 g12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qp88lepzk56QVkhZRSGO2VDv/JbZJtAi4P83EneyDdw=; b=B+Ys2i8uuRl2C0e3s0kdav190N/VGDiTA3Z0ZAR+qWJT8T5rob/gBIrnI5UnmSSsls TtWwR5X7UvJGmPCTULKorFuQpLv/rWokkza4COCpK9ARAo2dGMCdoHB+HFDpFb1g5I/V tVSOZ8LN9QRBgkm1GvT+XeLnzQkoJUFBX8ahttXADMKa1/+SkeBTla1mBIfONfJsaVSr YGmE1jgSVQnIE9L3R6T0S0IfkH1vE9NedxZAnvscDB4orMBHsgSIVLKZ75PYIjBvVL8r DTUmjCRLsNkrUfJSWPMtclztjy5tPvO45NXHkBtuKFgShAEOjBy4Y2RBTXdZELLWWSJo d76g== X-Gm-Message-State: AOAM532hD98nDFGE9cumFiHBHmoxVF17PlvDoro433XFd73SEe+bkkKu n8xIsDaO0TWXSKnojdphMu1sX1d04VZ4KA== X-Google-Smtp-Source: ABdhPJxFYME5caNsWY3WFlD5HBHhmYFfRqRMEYTRWNMubK/dnCaw5l8rp/uNE+8JfhTCJuUijhVpkA== X-Received: by 2002:a5d:490d:: with SMTP id x13mr22972171wrq.412.1629887762075; Wed, 25 Aug 2021 03:36:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/44] target/arm: Implement MVE VMOV to/from 2 general-purpose registers Date: Wed, 25 Aug 2021 11:35:20 +0100 Message-Id: <20210825103534.6936-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888178732100002 Content-Type: text/plain; charset="utf-8" Implement the MVE VMOV forms that move data between 2 general-purpose registers and 2 32-bit lanes in a vector register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 1 + target/arm/mve.decode | 4 ++ target/arm/translate-mve.c | 85 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-vfp.c | 2 +- 4 files changed, 91 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 6dfcafe1796..6f4d65ddb00 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -49,6 +49,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var); void clear_eci_state(DisasContext *s); bool mve_eci_check(DisasContext *s); void mve_update_and_store_eci(DisasContext *s); +bool mve_skip_vmov(DisasContext *s, int vn, int index, int size); =20 static inline TCGv_i32 load_cpu_offset(int offset) { diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 0955ed0cc22..774ee2a1a5b 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -136,6 +136,10 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101= ....... @vldr_vstr \ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vst= r \ size=3D2 p=3D1 =20 +# Moves between 2 32-bit vector lanes and 2 general purpose registers +VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd +VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd + # Vector 2-op VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 02c26987a2d..93707fdd681 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1507,3 +1507,88 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, = MVEGenVABAVFn *fn) =20 DO_VABAV(VABAV_S, vabavs) DO_VABAV(VABAV_U, vabavu) + +static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a) +{ + /* + * VMOV two 32-bit vector lanes to two general-purpose registers. + * This insn is not predicated but it is subject to beat-wise + * execution if it is not in an IT block. For us this means + * only that if PSR.ECI says we should not be executing the beat + * corresponding to the lane of the vector register being accessed + * then we should skip perfoming the move, and that we need to do + * the usual check for bad ECI state and advance of ECI state. + * (If PSR.ECI is non-zero then we cannot be in an IT block.) + */ + TCGv_i32 tmp; + int vd; + + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || + a->rt =3D=3D 13 || a->rt =3D=3D 15 || a->rt2 =3D=3D 13 || a->rt2 = =3D=3D 15 || + a->rt =3D=3D a->rt2) { + /* Rt/Rt2 cases are UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + /* Convert Qreg index to Dreg for read_neon_element32() etc */ + vd =3D a->qd * 2; + + if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, vd, a->idx, MO_32); + store_reg(s, a->rt, tmp); + } + if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, vd + 1, a->idx, MO_32); + store_reg(s, a->rt2, tmp); + } + + mve_update_and_store_eci(s); + return true; +} + +static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a) +{ + /* + * VMOV two general-purpose registers to two 32-bit vector lanes. + * This insn is not predicated but it is subject to beat-wise + * execution if it is not in an IT block. For us this means + * only that if PSR.ECI says we should not be executing the beat + * corresponding to the lane of the vector register being accessed + * then we should skip perfoming the move, and that we need to do + * the usual check for bad ECI state and advance of ECI state. + * (If PSR.ECI is non-zero then we cannot be in an IT block.) + */ + TCGv_i32 tmp; + int vd; + + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || + a->rt =3D=3D 13 || a->rt =3D=3D 15 || a->rt2 =3D=3D 13 || a->rt2 = =3D=3D 15) { + /* Rt/Rt2 cases are UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + /* Convert Qreg idx to Dreg for read_neon_element32() etc */ + vd =3D a->qd * 2; + + if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { + tmp =3D load_reg(s, a->rt); + write_neon_element32(tmp, vd, a->idx, MO_32); + tcg_temp_free_i32(tmp); + } + if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { + tmp =3D load_reg(s, a->rt2); + write_neon_element32(tmp, vd + 1, a->idx, MO_32); + tcg_temp_free_i32(tmp); + } + + mve_update_and_store_eci(s); + return true; +} diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index b2991e21ec7..e2eb797c829 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -581,7 +581,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return true; } =20 -static bool mve_skip_vmov(DisasContext *s, int vn, int index, int size) +bool mve_skip_vmov(DisasContext *s, int vn, int index, int size) { /* * In a CPU with MVE, the VMOV (vector lane to general-purpose registe= r) --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888275; cv=none; d=zohomail.com; s=zohoarc; b=PGOtmG/X9F3JQD7Kiue16gy5HccIK8gUy6N/rxxolAkM9IOfBZpZaI/3ll+BlygA+mlyxn2BzV3Rm2Yim6rdQ2VRi2xTBvNOaUG1ArjMSkrovX4jt4Wi+Df9CnANmUXYS0QyQh1O2OhobtKYJbPuTNu79H1Om6S1XZkDtG//GEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888275; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZsgiYwh7qNLAcSkC7LxnVfqa/pmBeTfF8iAebdcRKSo=; b=WVVR55jKmb2GQCHQmbOIG0m8fvUb3Rs1UQHVSx5aGy3g5UpdpjVmQNA6lrmWStES/Bbmgor8RnrEZbXV8v8lGsn4EkaEswMWHAxuxYdyfmbUvywgcStYhS6xpP/d2v0DX7Uwemaco7jUmjjOlluDXhxcOIfNfOLHdkRbkUJH9GY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888275054628.3716287011779; Wed, 25 Aug 2021 03:44:35 -0700 (PDT) Received: from localhost ([::1]:45326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqOY-0003Ah-0q for importer@patchew.org; Wed, 25 Aug 2021 06:44:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGM-0004EZ-3O for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:06 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34422) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGK-0005ZE-8r for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id h13so35716721wrp.1 for ; Wed, 25 Aug 2021 03:36:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZsgiYwh7qNLAcSkC7LxnVfqa/pmBeTfF8iAebdcRKSo=; b=X/kaiGm0HIH+XywoUk4rRcgQ3f0n3n0ER56IIaC0O+Yw30RmquKCAYCfKDISwUJ1Fp bAYfU6hkQji+zy94D47cqBTpKnQDWZ7dL5uzyQy7JbyrZJnNLWCIPFwLSD0PzHkTRs4M APvfNz+8+XxuKQT8wMCAayax1VKQsCSVCRwhlera5pUN7iQKbWo+nPtTYw1uFhRez+DC 0Fg3oyOVybCLEA8j+f2PjJ5Uw2Zidj7LiEviNDIO91fvptsQbHbabiC8fH9JwIVqJP9C EiiuUN3yBtt4somaatkbzWKgI0LeF3CL8JA+36pJIrjWfSnmxTtmeMRvg1+sM2t1uCCr qbBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZsgiYwh7qNLAcSkC7LxnVfqa/pmBeTfF8iAebdcRKSo=; b=TSn1l7W5UGN1UDkK1sDIsQc/g7IvpiUmmABmyaEHLLaZ+Mjp4k1aKZ5H7njewMcQR/ ww01Ngd9jf3utypYWqVCe6L8iJ5NMxyw79k6ZrlucoSIhZfDubkL9/iJhUPfeT5JWKEh WY9xJL0gQoPFOMQweO3guy23KRtkkuZ5ac+NRKJ7MItiYFDU14G/0igw4QBycg5be1iT TVXGDf7YS78/xYHgyE6IWK9zWkHP5N/9Vvp3r83TRzr3h5aoRFRKWYQGspfID3Vp1lvN UPaZYFfD/2YmpFAhoRviY5ijVzxkp1xILUBJZcXSFNwtpQ2mULFOxg4ezkuOsd3eJ4Pa 8ttA== X-Gm-Message-State: AOAM532bRuAinonId+Lwnh4wUQtls1jf63jVaWWBovLD4OowFkOvWJCO dZ2byOH5QiXhHgRjh74xwL7IlbzzxcKYbw== X-Google-Smtp-Source: ABdhPJxe735Un+W1YKjw7reM5tvea3HvvLPvjHU4z3/I9+GZCdOFBSzHv9u4wK7XLm+rjgyhO4n7jQ== X-Received: by 2002:a5d:4c4e:: with SMTP id n14mr23771444wrt.226.1629887762758; Wed, 25 Aug 2021 03:36:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/44] target/arm: Implement MVE VPNOT Date: Wed, 25 Aug 2021 11:35:21 +0100 Message-Id: <20210825103534.6936-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888276443100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VPNOT insn, which inverts the bits in VPR.P0 (subject to both predication and to beatwise execution). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 1 + target/arm/mve.decode | 1 + target/arm/mve_helper.c | 17 +++++++++++++++++ target/arm/translate-mve.c | 19 +++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 651020aaad8..8cb941912fc 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -119,6 +119,7 @@ DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env,= ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env) =20 DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 774ee2a1a5b..40bd0c04b59 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -571,6 +571,7 @@ VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0= . 0 ... 1 @vcmp VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp =20 { + VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101 VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask= _22_13 VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_sca= lar } diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d326205cbf0..c22a00c5ed6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2201,6 +2201,23 @@ void HELPER(mve_vpsel)(CPUARMState *env, void *vd, v= oid *vn, void *vm) mve_advance_vpt(env); } =20 +void HELPER(mve_vpnot)(CPUARMState *env) +{ + /* + * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. + * P0 bits for predicated lanes in executed bits (where mask is 0) are= 0. + * P0 bits otherwise are inverted. + * (This is the same logic as VCMP.) + * This insn is itself subject to predication and to beat-wise executi= on, + * and after it executes VPT state advances in the usual way. + */ + uint16_t mask =3D mve_element_mask(env); + uint16_t eci_mask =3D mve_eci_mask(env); + uint16_t beatpred =3D ~env->v7m.vpr & mask; + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & ec= i_mask); + mve_advance_vpt(env); +} + #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 93707fdd681..cc2e58cfe2f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -887,6 +887,25 @@ static bool trans_VPST(DisasContext *s, arg_VPST *a) return true; } =20 +static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) +{ + /* + * Invert the predicate in VPR.P0. We have call out to + * a helper because this insn itself is beatwise and can + * be predicated. + */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + gen_helper_mve_vpnot(cpu_env); + mve_update_eci(s); + return true; +} + static bool trans_VADDV(DisasContext *s, arg_VADDV *a) { /* VADDV: vector add across vector */ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889045; cv=none; d=zohomail.com; s=zohoarc; b=iRBPxVZZoSBM+Y5x6M3hsEnDeqQ7dsDu267gyrIdi5l8gOVWXZh4bSZVGN45UwKhMMwXOsZkhHajLAuCn40S9NsGnvLNNf+RSPdD263NR5IngmB+p2fq9jXNl3XmvsA5GI6eNj+SsDcrk7H245AH3btvqGFsgVuq06sz8HhQX+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889045; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m3w3Ow7urHFvFZW+mQsIR7ooKiNtRVZse42MclMGtaw=; b=IGQcIBbAvmM4BuWJtrw82fTEeqGNuTFD3h5UNsxY4+rbFQYBVAJYTMNlfa5d5a+p7RcamkYcaB2n1EmGgcD2f7W+F+PoBaouq4qarMicaboWHu97KxJJQrNR7Z+cJsHUnvNuAun6wG/46sRlYBUUOYbqZ7x42t+KIqKpvuWh/wg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629889045495125.17819724818628; Wed, 25 Aug 2021 03:57:25 -0700 (PDT) Received: from localhost ([::1]:42752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqay-0005qo-9W for importer@patchew.org; Wed, 25 Aug 2021 06:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGM-0004Ib-Sm for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:06 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:33446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGL-0005aI-3D for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:06 -0400 Received: by mail-wm1-x334.google.com with SMTP id j14-20020a1c230e000000b002e748b9a48bso3401553wmj.0 for ; Wed, 25 Aug 2021 03:36:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=m3w3Ow7urHFvFZW+mQsIR7ooKiNtRVZse42MclMGtaw=; b=OPTbOkKjy/FtPtH+7fAGyk6XJWKtXz4CthArruwOdNfzDVbL3B2UzFcYVgj02UaSMy xFoWpm57tTGQvF7pCoxrbEow2Ge2ndUB0tuDlJrMUmL23n/itwsKJakRbLvFZSfQISjy 6ZmOLwBmmFkQDsVJsuLFfy7dgcf41NU9qQDmsv3VmUnnxBDjNLuxlsMlohrHydIozm+z fnbHJNTfAHvO98wWKddRL62gtNYmwN6MbW5sPWH6fEUdWck57ffyuC26mGlONx8mLRiV XAitN+PDrTWltDjq/+ntkqXDiWBNN2X4kZId/d2hFsapUozbPAgK1E6vLRylfImVoySu D7rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m3w3Ow7urHFvFZW+mQsIR7ooKiNtRVZse42MclMGtaw=; b=eAsSDkWlNHtUCuH+3/BcwhXsIkbRC+175gPLDK5RqKTLfSa8UCfPNsyOAOkmm6hyfF uUEm2nwxKuyOte20dZDSjQKcYwFuCLbwftuxyRuWcbT0fBK2u/EK6rRP9X7731E4UqA/ vovCxqVYR2LcuyU2b/Neqp1C+KRQ8cWrIufJuGcclcKwbAqtj7S4dEY7ZTV51pbqyplZ SIM1ixcxmHDboc/XKbjI/r1IPIH0MSbNHlWIUUQIU19M9YL4rb5eflo15SABSRWG9IIE s4TTQ0KjPukc5GPvQ8LavhkX0m0l53TbHqkxBvI1qUNJugdxBT0j1vshbatoY3wVEN3u f6FA== X-Gm-Message-State: AOAM533xUvi4sdFHOnI3C9fdAb70XYhLn6W7zUex21LBP7lOqgoPXy5W P5M2l6Kl/AH4hxlQrf57TEq2pLW1dzPUbw== X-Google-Smtp-Source: ABdhPJyyD7EVZ0t/gN/S2tFibtnUBchqZjmM2knErCWiYhCdtDdYb6JyQbcrK0Ui8/8JUrkzwijXlQ== X-Received: by 2002:a7b:c956:: with SMTP id i22mr2812357wml.82.1629887763739; Wed, 25 Aug 2021 03:36:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/44] target/arm: Implement MVE VCTP Date: Wed, 25 Aug 2021 11:35:22 +0100 Message-Id: <20210825103534.6936-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889047116100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so as to predicate any element at index Rn or greater is predicated. As with VPNOT, this insn itself is predicable and subject to beatwise execution. The calculation of the mask is the same as is used to determine ltpmask in mve_element_mask(), but we precalculate masklen in generated code to avoid having to have 4 helpers specialized by size. We put the decode line in with the low-overhead-loop insns in t32.decode because it's logically part of that collection of insn patterns, even though it is an MVE only insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 2 ++ target/arm/translate-a32.h | 1 + target/arm/t32.decode | 1 + target/arm/mve_helper.c | 20 ++++++++++++++++++++ target/arm/translate-mve.c | 2 +- target/arm/translate.c | 33 +++++++++++++++++++++++++++++++++ 6 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 8cb941912fc..b6cf3f0c94d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env,= ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env) =20 +DEF_HELPER_FLAGS_2(mve_vctp, TCG_CALL_NO_WG, void, env, i32) + DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 6f4d65ddb00..88f15df60e8 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -48,6 +48,7 @@ long neon_element_offset(int reg, int element, MemOp memo= p); void gen_rev16(TCGv_i32 dest, TCGv_i32 var); void clear_eci_state(DisasContext *s); bool mve_eci_check(DisasContext *s); +void mve_update_eci(DisasContext *s); void mve_update_and_store_eci(DisasContext *s); bool mve_skip_vmov(DisasContext *s, int vn, int index, int size); =20 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 2d47f31f143..78fadef9d62 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -748,5 +748,6 @@ BL 1111 0. .......... 11.1 ............ = @branch24 # This is DLSTP DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001 } + VCTP 1111 0 0000 0 size:2 rn:4 1110 1000 0000 0001 ] } diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c22a00c5ed6..1752555a218 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -2218,6 +2218,26 @@ void HELPER(mve_vpnot)(CPUARMState *env) mve_advance_vpt(env); } =20 +/* + * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, + * otherwise set according to value of Rn. The calculation of + * newmask here works in the same way as the calculation of the + * ltpmask in mve_element_mask(), but we have pre-calculated + * the masklen in the generated code. + */ +void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) +{ + uint16_t mask =3D mve_element_mask(env); + uint16_t eci_mask =3D mve_eci_mask(env); + uint16_t newmask; + + assert(masklen <=3D 16); + newmask =3D masklen ? MAKE_64BIT_MASK(0, masklen) : 0; + newmask &=3D mask; + env->v7m.vpr =3D (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci= _mask); + mve_advance_vpt(env); +} + #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index cc2e58cfe2f..865d5acbe76 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -93,7 +93,7 @@ bool mve_eci_check(DisasContext *s) } } =20 -static void mve_update_eci(DisasContext *s) +void mve_update_eci(DisasContext *s) { /* * The helper function will always update the CPUState field, diff --git a/target/arm/translate.c b/target/arm/translate.c index 80c282669f0..804a53279bd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8669,6 +8669,39 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a) return true; } =20 +static bool trans_VCTP(DisasContext *s, arg_VCTP *a) +{ + /* + * M-profile Create Vector Tail Predicate. This insn is itself + * predicated and is subject to beatwise execution. + */ + TCGv_i32 rn_shifted, masklen; + + if (!dc_isar_feature(aa32_mve, s) || a->rn =3D=3D 13 || a->rn =3D=3D 1= 5) { + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + /* + * We pre-calculate the mask length here to avoid having + * to have multiple helpers specialized for size. + * We pass the helper "rn <=3D (1 << (4 - size)) ? (rn << size) : 16". + */ + rn_shifted =3D tcg_temp_new_i32(); + masklen =3D load_reg(s, a->rn); + tcg_gen_shli_i32(rn_shifted, masklen, a->size); + tcg_gen_movcond_i32(TCG_COND_LEU, masklen, + masklen, tcg_constant_i32(1 << (4 - a->size)), + rn_shifted, tcg_constant_i32(16)); + gen_helper_mve_vctp(cpu_env, masklen); + tcg_temp_free_i32(masklen); + tcg_temp_free_i32(rn_shifted); + mve_update_eci(s); + return true; +} =20 static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888469; cv=none; d=zohomail.com; s=zohoarc; b=RAzWdYH/Q/xruUHi2G45jd0uU/gEoQVJGzVNnPxdmw0ZJYs38K21fl8hg+h/d9bKOYGjmRdB48vg+N4izPwNgTc5rx4TztSe1eGZmcUxazyc9YjkSY3qQOIhPh5YDlksrvB8+YJdSWvR37qlcqc/5ZQVwMfZShUP+hFG+BLgYN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888469; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e3QsIw8l+no/AQshGiOw4moU36KoAvG6XaI7zJyoNM0=; b=J8gHPlvy7bmUVbHv00TxQ6xRkM/3KnlGBJdDFMu5Jd9438Nn6fgrKwqqP+6KtQltDgfYu1pnW1lWSFhpjw1tQr//Fih7ph32QAlmiyhS/KTG4G8qsVWkzms5F4Gb0W5WRjRN4DDyvNQjz84vnV2O510JEl5uVdgBY9aIUiujXEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888469162112.64650067530067; Wed, 25 Aug 2021 03:47:49 -0700 (PDT) Received: from localhost ([::1]:56572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqRf-0002Th-Ur for importer@patchew.org; Wed, 25 Aug 2021 06:47:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGO-0004QQ-Qm for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:08 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGM-0005bK-AT for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:08 -0400 Received: by mail-wr1-x42a.google.com with SMTP id u16so35670403wrn.5 for ; Wed, 25 Aug 2021 03:36:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=e3QsIw8l+no/AQshGiOw4moU36KoAvG6XaI7zJyoNM0=; b=oz812UtiWlsKQiRLXUQpDrLkFOC87djzGjH+eeJuiqp1tZezDTsjpP4GCe3BfZqEtI a4Hp2KA0AGv9hLo0x8nhM7mR8DlK+ONzUBllJgMGHQIuJSFvDQYeyUEsZUQKhNoJvHUs YnY1rfUFn6mu1vPZ+OYxeBerJ7vhIYLu+aueL/1A7Rdx39nIys2cRvDJbYez84rx+3Tx sAL2Sm70GI1cjkMP3ATIysJOhVMV1G0ni9sdO7QCM5WnVmd+vc+FYcAW/0B+vjefuTgC +C/B6pNEaaO33xjn2cwzizqZM4L4OZKxy5/6i8l9szBZuc8m2VujegLSCwC3vxC5er6o FUgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e3QsIw8l+no/AQshGiOw4moU36KoAvG6XaI7zJyoNM0=; b=cNhPM2Y8oMSNz+XZ0YqRqmm1+n7jg1KKaXLQC4U97OGyRKfonkhhC0N1rqF7wtufdI soJ2qXdb9RWQoyA67nN3lKRUpWI4xx2Pi76dRX7jlF5UbinFc/rRekOB27Q0YOoWIo70 O/vJ7VGZmNCSW7EKnPH7VphEfqDDDpA3nSh23b2ft2VmlGDesD+MPT6N858ui60wTDGl kdiMMG1znE/xv7Du71+pPvJE1Ouv6nFMulXdIBKGWKHMPXUATD+aaXfF/WAZCFZgaRcT 2uCZ1oSME1WT8o+Lqqa942WQlFBz2rc4ZVjLXsZJnb1V0fqIdmZqqxpmPuQUo7qL3i4b 1KQw== X-Gm-Message-State: AOAM531GvvZLk8kGA2zBZExNy5JTLEOqMEYxXj205/uvHBBE8Wjh/bxO IkLpDggEMqPYu9SbtmwPnE/a24BJ1rxu4w== X-Google-Smtp-Source: ABdhPJzOEtTml0aTqOB5WLs/2sbUnyYXH496qzhNC0Eyv/h6igTqBxPJjS8PnMcwkUr4fhLzds25DQ== X-Received: by 2002:adf:fa82:: with SMTP id h2mr23659551wrr.129.1629887764648; Wed, 25 Aug 2021 03:36:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/44] target/arm: Implement MVE scatter-gather insns Date: Wed, 25 Aug 2021 11:35:23 +0100 Message-Id: <20210825103534.6936-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888471285100001 Content-Type: text/plain; charset="utf-8" Implement the MVE gather-loads and scatter-stores which form the address by adding a base value from a scalar register to an offset in each element of a vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 32 +++++++++ target/arm/mve.decode | 12 ++++ target/arm/mve_helper.c | 129 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 97 ++++++++++++++++++++++++++++ 4 files changed, 270 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index b6cf3f0c94d..ba842b97c17 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -33,6 +33,38 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, en= v, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vldrb_sg_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrb_sg_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrh_sg_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(mve_vldrb_sg_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrb_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrb_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrh_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrh_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrw_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vldrd_sg_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(mve_vstrb_sg_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrb_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrb_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrh_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrh_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrw_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(mve_vstrd_sg_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_sw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_uh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vldrw_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vldrd_sg_os_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vstrh_sg_os_uh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vstrh_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vstrw_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vstrd_sg_os_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vidupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 40bd0c04b59..6c3f45c7195 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -42,11 +42,18 @@ &shl_scalar qda rm size &vmaxv qm rda size &vabav qn qm rda size +&vldst_sg qd qm rn size msize os + +# scatter-gather memory size is in bits 6:4 +%sg_msize 6:1 4:1 =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr =20 +@vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \ + qd=3D%qd qm=3D%qm msize=3D%sg_msize + @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @@ -136,6 +143,11 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101= ....... @vldr_vstr \ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vst= r \ size=3D2 p=3D1 =20 +# gather loads/scatter stores +VLDR_S_sg 111 0 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg +VLDR_U_sg 111 1 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg +VSTR_sg 111 0 1100 1 . 00 .... ... 0 111 . .... .... @vldst_sg + # Moves between 2 32-bit vector lanes and 2 general purpose registers VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1752555a218..2b882db1c3d 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -206,6 +206,135 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) #undef DO_VLDR #undef DO_VSTR =20 +/* + * Gather loads/scatter stores. Here each element of Qm specifies + * an offset to use from the base register Rm. In the _os_ versions + * that offset is scaled by the element size. + * For loads, predicated lanes are zeroed instead of retaining + * their previous values. + */ +#define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ + uint32_t base) \ + { \ + TYPE *d =3D vd; \ + OFFTYPE *m =3D vm; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + unsigned e; \ + uint32_t addr; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ + if (!(eci_mask & 1)) { \ + continue; \ + } \ + addr =3D ADDRFN(base, m[H##ESIZE(e)]); \ + d[H##ESIZE(e)] =3D (mask & 1) ? \ + cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ + } \ + mve_advance_vpt(env); \ + } + +/* We know here TYPE is unsigned so always the same as the offset type */ +#define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ + uint32_t base) \ + { \ + TYPE *d =3D vd; \ + TYPE *m =3D vm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + uint32_t addr; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + addr =3D ADDRFN(base, m[H##ESIZE(e)]); \ + if (mask & 1) { \ + cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC())= ; \ + } \ + } \ + mve_advance_vpt(env); \ + } + +/* + * 64-bit accesses are slightly different: they are done as two 32-bit + * accesses, controlled by the predicate mask for the relevant beat, + * and with a single 32-bit offset in the first of the two Qm elements. + * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). + */ +#define DO_VLDR64_SG(OP, ADDRFN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ + uint32_t base) \ + { \ + uint32_t *d =3D vd; \ + uint32_t *m =3D vm; \ + uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ + unsigned e; \ + uint32_t addr; \ + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ + if (!(eci_mask & 1)) { \ + continue; \ + } \ + addr =3D ADDRFN(base, m[H4(e & ~1)]); \ + addr +=3D 4 * (e & 1); \ + d[H4(e)] =3D (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) = : 0; \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VSTR64_SG(OP, ADDRFN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ + uint32_t base) \ + { \ + uint32_t *d =3D vd; \ + uint32_t *m =3D vm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + uint32_t addr; \ + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { = \ + addr =3D ADDRFN(base, m[H4(e & ~1)]); \ + addr +=3D 4 * (e & 1); \ + if (mask & 1) { \ + cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ + } \ + } \ + mve_advance_vpt(env); \ + } + +#define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) +#define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) +#define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) +#define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) + +DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD) +DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD) +DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD) + +DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD) +DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD) +DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD) +DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD) +DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD) +DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD) +DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD) + +DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH) +DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH) +DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH) +DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW) +DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD) + +DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD) +DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD) +DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD) +DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD) +DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD) +DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD) +DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD) + +DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH) +DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH) +DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW) +DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD) + /* * The mergemask(D, R, M) macro performs the operation "*D =3D R" but * storing only the bytes which correspond to 1 bits in M, diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 865d5acbe76..24d4e57ead4 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -34,6 +34,7 @@ static inline int vidup_imm(DisasContext *s, int x) #include "decode-mve.c.inc" =20 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); @@ -209,6 +210,102 @@ DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vs= trb_h, MO_8) DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) =20 +static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn) +{ + TCGv_i32 addr; + TCGv_ptr qd, qm; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qd | a->qm) || + !fn || a->rn =3D=3D 15) { + /* Rn case is UNPREDICTABLE */ + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + addr =3D load_reg(s, a->rn); + + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm, addr); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + tcg_temp_free_i32(addr); + mve_update_eci(s); + return true; +} + +/* + * The naming scheme here is "vldrb_sg_sh =3D=3D in-memory byte loads + * signextended to halfword elements in register". _os_ indicates that + * the offsets in Qm should be scaled by the element size. + */ +/* This macro is just to make the arrays more compact in these functions */ +#define F(N) gen_helper_mve_##N + +/* VLDRB/VSTRB (ie msize 1) with OS=3D1 is UNPREDICTABLE; we UNDEF */ +static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a) +{ + static MVEGenLdStSGFn * const fns[2][4][4] =3D { { + { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL }, + { NULL, NULL, F(vldrh_sg_sw), NULL }, + { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL } + }, { + { NULL, NULL, NULL, NULL }, + { NULL, NULL, F(vldrh_sg_os_sw), NULL }, + { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL } + } + }; + if (a->qd =3D=3D a->qm) { + return false; /* UNPREDICTABLE */ + } + return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); +} + +static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a) +{ + static MVEGenLdStSGFn * const fns[2][4][4] =3D { { + { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL }, + { NULL, F(vldrh_sg_uh), F(vldrh_sg_uw), NULL }, + { NULL, NULL, F(vldrw_sg_uw), NULL }, + { NULL, NULL, NULL, F(vldrd_sg_u= d) } + }, { + { NULL, NULL, NULL, NULL }, + { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL }, + { NULL, NULL, F(vldrw_sg_os_uw), NULL }, + { NULL, NULL, NULL, F(vldrd_sg_os_ud= ) } + } + }; + if (a->qd =3D=3D a->qm) { + return false; /* UNPREDICTABLE */ + } + return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); +} + +static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a) +{ + static MVEGenLdStSGFn * const fns[2][4][4] =3D { { + { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL }, + { NULL, F(vstrh_sg_uh), F(vstrh_sg_uw), NULL }, + { NULL, NULL, F(vstrw_sg_uw), NULL }, + { NULL, NULL, NULL, F(vstrd_sg_u= d) } + }, { + { NULL, NULL, NULL, NULL }, + { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL }, + { NULL, NULL, F(vstrw_sg_os_uw), NULL }, + { NULL, NULL, NULL, F(vstrd_sg_os_ud= ) } + } + }; + return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); +} + +#undef F + static bool trans_VDUP(DisasContext *s, arg_VDUP *a) { TCGv_ptr qd; --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889126; cv=none; d=zohomail.com; s=zohoarc; b=l+3nAkCKyvAKnQvW2n3tQ78lrRzwk2KlmlqQw7c1+jfAyEALrlV3BtGYG4wAs9gCFk/IBWqoxOJmAiPl/7ED2LnS+OsaVlBAPU+ENYZebiDGfuj0qhojI599nAP4MEFE0G6Ti9TM4UAeWxjYBIZfeKLemYRqKxwvL1F5YyGPPBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889126; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XPDSRt79Sljs50ZsUdlm+FK/S4O1jr6J7KCkR7e6jsg=; b=WE6WUt1AQVQCUn9W/jRWhfflQwl771N+osC5Ih7fROoigKpA2QCWdeEMmqGTACNMQo MrA2TfEB26kMgnf4Z7cXr3sYDQyz6es6IacO73yd+a0CTIkLYZvECCbbPA4EsUCBHn+3 42nxvsZUSxCfeX3sKNn3nfCAKBc+72U5BX5Tu9cF9AhQmOEXeTi/aDxYYUw0BS1qGeQf C5sPVkNwduYV0uXxUhRkAhOo98boNoCMO1QByEC5qzoFj2Yg01mlkklA6x9WLdznbWLD Zjm8yJL9XallrUEMY7jaAiIQHh+uHTB0FUyHLnc5CR072b6ff97v35WMUwYJhvW9ljz4 5J5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XPDSRt79Sljs50ZsUdlm+FK/S4O1jr6J7KCkR7e6jsg=; b=Fp+s485h+nHt0RMj3AZexyVYm2VKCIyJxnj+Gdg6azeIhg7GntuDEY1Ly3kGPSiWf8 +Q/nc9ofdfF0Cly6rPj5GkW9/96ZQMWhojdllRVWkK2eWiJMJm1avfXhxGnDtyYBRq+u qCcwi3VUJeximmjjECuRu92oy6NUNx1EW1zAzh0+/cPqPfoobz96SdbAMP4ZI86ELKPv xMUdaetlkC3/M6HEDyZfWdNUdZmD5UHhQTYeXmnQnvvF3rd9RiycTSoO3+IVNIlkG2Np R8vDbwi5swRhQr5U1kepctkO3XOulQY3R3MDhZgvtHGdGWtKNirLH7vwD4nAPs9C5pkh rExw== X-Gm-Message-State: AOAM5324M408kp7KiaGowCIf8a8QZelR1wYvDDcczScv/ewtDDqdv+7T 2ZIkV7anyFHNh8p46HdscCdhZe+r9E5uSg== X-Google-Smtp-Source: ABdhPJzDCH5fGopDCFZlQDi3H9CsbK1vrQD5+TvAl8wpKtoCoWKAW1UYj9IqjlLliXDf0i6TA4n5QA== X-Received: by 2002:a1c:20d7:: with SMTP id g206mr8828965wmg.153.1629887765481; Wed, 25 Aug 2021 03:36:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/44] target/arm: Implement MVE scatter-gather immediate forms Date: Wed, 25 Aug 2021 11:35:24 +0100 Message-Id: <20210825103534.6936-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889127256100001 Content-Type: text/plain; charset="utf-8" Implement the MVE VLDR/VSTR insns which do scatter-gather using base addresses from Qm plus or minus an immediate offset (possibly with writeback). Note that writeback is not predicated but it does have to honour ECI state, so we have to add an eci_mask check to the VSTR_SG macros (the VLDR_SG macros already needed this to be able to distinguish "skip beat" from "set predicated element to 0"). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++ target/arm/mve.decode | 10 +++++ target/arm/mve_helper.c | 91 ++++++++++++++++++++++++-------------- target/arm/translate-mve.c | 72 ++++++++++++++++++++++++++++++ 4 files changed, 146 insertions(+), 32 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index ba842b97c17..a85a7e1b75d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -65,6 +65,11 @@ DEF_HELPER_FLAGS_4(mve_vstrh_sg_os_uw, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vstrw_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) DEF_HELPER_FLAGS_4(mve_vstrd_sg_os_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) =20 +DEF_HELPER_FLAGS_4(mve_vldrw_sg_wb_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vldrd_sg_wb_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vstrw_sg_wb_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vstrd_sg_wb_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vidupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 6c3f45c7195..48882dd7f38 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -43,6 +43,7 @@ &vmaxv qm rda size &vabav qn qm rda size &vldst_sg qd qm rn size msize os +&vldst_sg_imm qd qm a w imm =20 # scatter-gather memory size is in bits 6:4 %sg_msize 6:1 4:1 @@ -54,6 +55,10 @@ @vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \ qd=3D%qd qm=3D%qm msize=3D%sg_msize =20 +# Qm is in the fields usually labeled Qn +@vldst_sg_imm .... .... a:1 . w:1 . .... .... .... . imm:7 &vldst_sg_imm \ + qd=3D%qd qm=3D%qn + @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @@ -148,6 +153,11 @@ VLDR_S_sg 111 0 1100 1 . 01 .... ... 0 111 . ..= .. .... @vldst_sg VLDR_U_sg 111 1 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg VSTR_sg 111 0 1100 1 . 00 .... ... 0 111 . .... .... @vldst_sg =20 +VLDRW_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1110 .... .... @vldst_sg_imm +VLDRD_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1111 .... .... @vldst_sg_imm +VSTRW_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1110 .... .... @vldst_sg_imm +VSTRD_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1111 .... .... @vldst_sg_imm + # Moves between 2 32-bit vector lanes and 2 general purpose registers VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2b882db1c3d..bbbaa538074 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -213,7 +213,7 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) * For loads, predicated lanes are zeroed instead of retaining * their previous values. */ -#define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN) \ +#define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ uint32_t base) \ { \ @@ -230,25 +230,35 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) addr =3D ADDRFN(base, m[H##ESIZE(e)]); \ d[H##ESIZE(e)] =3D (mask & 1) ? \ cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ + if (WB) { \ + m[H##ESIZE(e)] =3D addr; \ + } \ } \ mve_advance_vpt(env); \ } =20 /* We know here TYPE is unsigned so always the same as the offset type */ -#define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN) \ +#define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ uint32_t base) \ { \ TYPE *d =3D vd; \ TYPE *m =3D vm; \ uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ unsigned e; \ uint32_t addr; \ - for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ + if (!(eci_mask & 1)) { \ + continue; \ + } \ addr =3D ADDRFN(base, m[H##ESIZE(e)]); \ if (mask & 1) { \ cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC())= ; \ } \ + if (WB) { \ + m[H##ESIZE(e)] =3D addr; \ + } \ } \ mve_advance_vpt(env); \ } @@ -258,8 +268,10 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) * accesses, controlled by the predicate mask for the relevant beat, * and with a single 32-bit offset in the first of the two Qm elements. * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). + * Address writeback happens on the odd beats and updates the address + * stored in the even-beat element. */ -#define DO_VLDR64_SG(OP, ADDRFN) \ +#define DO_VLDR64_SG(OP, ADDRFN, WB) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ uint32_t base) \ { \ @@ -276,25 +288,35 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) addr =3D ADDRFN(base, m[H4(e & ~1)]); \ addr +=3D 4 * (e & 1); \ d[H4(e)] =3D (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) = : 0; \ + if (WB && (e & 1)) { \ + m[H4(e & ~1)] =3D addr - 4; \ + } \ } \ mve_advance_vpt(env); \ } =20 -#define DO_VSTR64_SG(OP, ADDRFN) \ +#define DO_VSTR64_SG(OP, ADDRFN, WB) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ uint32_t base) \ { \ uint32_t *d =3D vd; \ uint32_t *m =3D vm; \ uint16_t mask =3D mve_element_mask(env); \ + uint16_t eci_mask =3D mve_eci_mask(env); \ unsigned e; \ uint32_t addr; \ - for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { = \ + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ + if (!(eci_mask & 1)) { \ + continue; \ + } \ addr =3D ADDRFN(base, m[H4(e & ~1)]); \ addr +=3D 4 * (e & 1); \ if (mask & 1) { \ cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ } \ + if (WB && (e & 1)) { \ + m[H4(e & ~1)] =3D addr - 4; \ + } \ } \ mve_advance_vpt(env); \ } @@ -304,36 +326,41 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) =20 -DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD) -DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD) -DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD) +DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD) -DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD) -DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD) -DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD) -DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD) -DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD) -DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD) +DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD, false) +DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH) -DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH) -DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH) -DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW) -DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD) +DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) +DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, fals= e) +DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, fals= e) +DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) +DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) =20 -DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD) -DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD) -DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD) -DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD) -DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD) -DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD) -DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD) +DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false) +DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false) +DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) =20 -DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH) -DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH) -DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW) -DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD) +DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false) +DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false) +DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false) +DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) + +DO_VLDR_SG(vldrw_sg_wb_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) +DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) +DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) +DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 /* * The mergemask(D, R, M) macro performs the operation "*D =3D R" but diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 24d4e57ead4..d3cb3396863 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -306,6 +306,78 @@ static bool trans_VSTR_sg(DisasContext *s, arg_vldst_s= g *a) =20 #undef F =20 +static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a, + MVEGenLdStSGFn *fn, unsigned msize) +{ + uint32_t offset; + TCGv_ptr qd, qm; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qd | a->qm) || + !fn) { + return false; + } + + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + offset =3D a->imm << msize; + if (!a->a) { + offset =3D -offset; + } + + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm, tcg_constant_i32(offset)); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) +{ + static MVEGenLdStSGFn * const fns[] =3D { + gen_helper_mve_vldrw_sg_uw, + gen_helper_mve_vldrw_sg_wb_uw, + }; + if (a->qd =3D=3D a->qm) { + return false; /* UNPREDICTABLE */ + } + return do_ldst_sg_imm(s, a, fns[a->w], MO_32); +} + +static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) +{ + static MVEGenLdStSGFn * const fns[] =3D { + gen_helper_mve_vldrd_sg_ud, + gen_helper_mve_vldrd_sg_wb_ud, + }; + if (a->qd =3D=3D a->qm) { + return false; /* UNPREDICTABLE */ + } + return do_ldst_sg_imm(s, a, fns[a->w], MO_64); +} + +static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) +{ + static MVEGenLdStSGFn * const fns[] =3D { + gen_helper_mve_vstrw_sg_uw, + gen_helper_mve_vstrw_sg_wb_uw, + }; + return do_ldst_sg_imm(s, a, fns[a->w], MO_32); +} + +static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) +{ + static MVEGenLdStSGFn * const fns[] =3D { + gen_helper_mve_vstrd_sg_ud, + gen_helper_mve_vstrd_sg_wb_ud, + }; + return do_ldst_sg_imm(s, a, fns[a->w], MO_64); +} + static bool trans_VDUP(DisasContext *s, arg_VDUP *a) { TCGv_ptr qd; --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=w53XSDCLQrd8GgegDr6lPzwZ3ubUcyF/EnxMkrOo9Ss=; b=EdH3fVWlm7+fLKYOxCRykwQr2XNe4vsQ6aB3OWf99LVQtMnBBoENGiXh3L16ks+CGS B8ZfgDZi+UIrdPmV+PsDUZQNYwx6yU7kFSNG3UWWz2wR5m0j2fooY+b2K9H3Y+6nmFqu Q3Ad6dlzf/xMf8tstPKDp3q88aYGo7NIpHdSLXf90bxndhQqCHRWmO2fVgSv19Ow6M/J YPOuJ3vE/mhJ9CO9jLkmQlXURoZQz+CJVFHozG1NOwJymJRB4U6JMFJStlOKEJoCfkul +BRBhsHH/rAo5IZJ2BCzoWckCvGmKFutqjkJ5sKqOs83VwlBn2ciuscrE1MJyMtkmJJc fLLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w53XSDCLQrd8GgegDr6lPzwZ3ubUcyF/EnxMkrOo9Ss=; b=lzTAL/Kk8df73wWMHJFJflAPvReb/zFEuBi+OTaAPawv+yQ655jOpJL45ZQGLbkkbU cwUuDYzFS927aV0UeaL32243PdX6uC/hyQHRNS2OqThwAfEPk14ccroZe1c/qN1B7+5f KAez4uWO6rbNjmN6W4bmX4vMbRa7TTsYUGGA2m9ZHLKVCknDNMqGIMuPCEhuAumLvLkQ umNnncGgaElMsyVIXvz1ZcYjUZIBuxnJJo2KSqFNL0KIP7bI3188EOhCp1AJOI0hj92o mkT4k0CoHKu07M+q521M4xtvFkEA7UFlia3H3Ig5eIBjIm5xOIi80sCv8NaPdaibC6AS OhKg== X-Gm-Message-State: AOAM531EByb0fDVkPWtm/cQAU+RYKvn+XxFSTzNPDDcRbeY2ShP4ErXJ P34cV5nh6bLRitMf0jhzoiiRUUA+2/6WeA== X-Google-Smtp-Source: ABdhPJzPTUv8jmHU/JMgU3Cc/gVn1fdkxqmGaFDE76vqvUxALDuimbF2M5wLCjCBuWr6C9Z2Z7P3SQ== X-Received: by 2002:adf:b347:: with SMTP id k7mr21929332wrd.239.1629887766574; Wed, 25 Aug 2021 03:36:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/44] target/arm: Implement MVE interleaving loads/stores Date: Wed, 25 Aug 2021 11:35:25 +0100 Message-Id: <20210825103534.6936-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889270434100001 Content-Type: text/plain; charset="utf-8" Implement the MVE interleaving load/store functions VLD2, VLD4, VST2 and VST4. VLD2 loads 16 bytes of data from memory and writes to 2 consecutive Qregs; VLD4 loads 16 bytes of data from memory and writes to 4 consecutive Qregs. The 'pattern' field in the encoding determines the offset into memory which is accessed and also which elements in the Qregs are written to. (The intention is that a sequence of four consecutive VLD4 with different pattern values performs a complete de-interleaving load of 64 bytes into all elements of the 4 Qregs.) VST2 and VST4 do the same, but for stores. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 48 ++++++ target/arm/mve.decode | 11 ++ target/arm/mve_helper.c | 342 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 94 ++++++++++ 4 files changed, 495 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index a85a7e1b75d..3db9b15f121 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -70,6 +70,54 @@ DEF_HELPER_FLAGS_4(mve_vldrd_sg_wb_ud, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vstrw_sg_wb_uw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) DEF_HELPER_FLAGS_4(mve_vstrd_sg_wb_ud, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) =20 +DEF_HELPER_FLAGS_3(mve_vld20b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld20h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld20w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vld21b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld21h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld21w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vld40b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld40h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld40w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vld41b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld41h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld41w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vld42b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld42h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld42w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vld43b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld43h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vld43w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst20b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst20h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst20w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst21b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst21h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst21w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst40b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst40h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst40w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst41b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst41h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst41w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst42b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst42h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst42w, TCG_CALL_NO_WG, void, env, i32, i32) + +DEF_HELPER_FLAGS_3(mve_vst43b, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst43h, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mve_vst43w, TCG_CALL_NO_WG, void, env, i32, i32) + DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32) =20 DEF_HELPER_FLAGS_4(mve_vidupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 48882dd7f38..87446816293 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -44,6 +44,7 @@ &vabav qn qm rda size &vldst_sg qd qm rn size msize os &vldst_sg_imm qd qm a w imm +&vldst_il qd rn size pat w =20 # scatter-gather memory size is in bits 6:4 %sg_msize 6:1 4:1 @@ -59,6 +60,10 @@ @vldst_sg_imm .... .... a:1 . w:1 . .... .... .... . imm:7 &vldst_sg_imm \ qd=3D%qd qm=3D%qn =20 +# Deinterleaving load/interleaving store +@vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \ + qd=3D%qd + @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @@ -158,6 +163,12 @@ VLDRD_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1111 ...= . .... @vldst_sg_imm VSTRW_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1110 .... .... @vldst_sg_imm VSTRD_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1111 .... .... @vldst_sg_imm =20 +# deinterleaving loads/interleaving stores +VLD2 1111 1100 1 .. 1 .... ... 1 111 .. .. 00000 @vldst_il +VLD4 1111 1100 1 .. 1 .... ... 1 111 .. .. 00001 @vldst_il +VST2 1111 1100 1 .. 0 .... ... 1 111 .. .. 00000 @vldst_il +VST4 1111 1100 1 .. 0 .... ... 1 111 .. .. 00001 @vldst_il + # Moves between 2 32-bit vector lanes and 2 general purpose registers VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=3D%qd diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index bbbaa538074..c2826eb5f9f 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -362,6 +362,348 @@ DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 +/* + * Deinterleaving loads/interleaving stores. + * + * For these helpers we are passed the index of the first Qreg + * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) + * and the value of the base address register Rn. + * The helpers are specialized for pattern and element size, so + * for instance vld42h is VLD4 with pattern 2, element size MO_16. + * + * These insns are beatwise but not predicated, so we must honour ECI, + * but need not look at mve_element_mask(). + * + * The pseudocode implements these insns with multiple memory accesses + * of the element size, but rules R_VVVG and R_FXDM permit us to make + * one 32-bit memory access per beat. + */ +#define DO_VLD4B(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat, e; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + for (e =3D 0; e < 4; e++, data >>=3D 8) { = \ + uint8_t *qd =3D (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ + qd[H1(off[beat])] =3D data; \ + } \ + } \ + } + +#define DO_VLD4H(OP, O1, O2) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O1, O2, O2 }; \ + uint32_t addr, data; \ + int y; /* y counts 0 2 0 2 */ \ + uint16_t *qd; \ + for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 8 + (beat & 1) * 4; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ + qd[H2(off[beat])] =3D data; \ + data >>=3D 16; \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ + qd[H2(off[beat])] =3D data; \ + } \ + } + +#define DO_VLD4W(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint32_t *qd; \ + int y; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + y =3D (beat + (O1 & 2)) & 3; \ + qd =3D (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ + qd[H4(off[beat] >> 2)] =3D data; \ + } \ + } + +DO_VLD4B(vld40b, 0, 1, 10, 11) +DO_VLD4B(vld41b, 2, 3, 12, 13) +DO_VLD4B(vld42b, 4, 5, 14, 15) +DO_VLD4B(vld43b, 6, 7, 8, 9) + +DO_VLD4H(vld40h, 0, 5) +DO_VLD4H(vld41h, 1, 6) +DO_VLD4H(vld42h, 2, 7) +DO_VLD4H(vld43h, 3, 4) + +DO_VLD4W(vld40w, 0, 1, 10, 11) +DO_VLD4W(vld41w, 2, 3, 12, 13) +DO_VLD4W(vld42w, 4, 5, 14, 15) +DO_VLD4W(vld43w, 6, 7, 8, 9) + +#define DO_VLD2B(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat, e; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint8_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 2; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + for (e =3D 0; e < 4; e++, data >>=3D 8) { = \ + qd =3D (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ + qd[H1(off[beat] + (e >> 1))] =3D data; \ + } \ + } \ + } + +#define DO_VLD2H(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + int e; \ + uint16_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + for (e =3D 0; e < 2; e++, data >>=3D 16) { = \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ + qd[H2(off[beat])] =3D data; \ + } \ + } \ + } + +#define DO_VLD2W(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint32_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat]; \ + data =3D cpu_ldl_le_data_ra(env, addr, GETPC()); \ + qd =3D (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ + qd[H4(off[beat] >> 3)] =3D data; \ + } \ + } + +DO_VLD2B(vld20b, 0, 2, 12, 14) +DO_VLD2B(vld21b, 4, 6, 8, 10) + +DO_VLD2H(vld20h, 0, 1, 6, 7) +DO_VLD2H(vld21h, 2, 3, 4, 5) + +DO_VLD2W(vld20w, 0, 4, 24, 28) +DO_VLD2W(vld21w, 8, 12, 16, 20) + +#define DO_VST4B(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat, e; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + data =3D 0; \ + for (e =3D 3; e >=3D 0; e--) { = \ + uint8_t *qd =3D (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ + data =3D (data << 8) | qd[H1(off[beat])]; \ + } \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +#define DO_VST4H(OP, O1, O2) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O1, O2, O2 }; \ + uint32_t addr, data; \ + int y; /* y counts 0 2 0 2 */ \ + uint16_t *qd; \ + for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 8 + (beat & 1) * 4; \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ + data =3D qd[H2(off[beat])]; \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ + data |=3D qd[H2(off[beat])] << 16; \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +#define DO_VST4W(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint32_t *qd; \ + int y; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + y =3D (beat + (O1 & 2)) & 3; \ + qd =3D (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ + data =3D qd[H4(off[beat] >> 2)]; \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +DO_VST4B(vst40b, 0, 1, 10, 11) +DO_VST4B(vst41b, 2, 3, 12, 13) +DO_VST4B(vst42b, 4, 5, 14, 15) +DO_VST4B(vst43b, 6, 7, 8, 9) + +DO_VST4H(vst40h, 0, 5) +DO_VST4H(vst41h, 1, 6) +DO_VST4H(vst42h, 2, 7) +DO_VST4H(vst43h, 3, 4) + +DO_VST4W(vst40w, 0, 1, 10, 11) +DO_VST4W(vst41w, 2, 3, 12, 13) +DO_VST4W(vst42w, 4, 5, 14, 15) +DO_VST4W(vst43w, 6, 7, 8, 9) + +#define DO_VST2B(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat, e; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint8_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 2; \ + data =3D 0; \ + for (e =3D 3; e >=3D 0; e--) { = \ + qd =3D (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ + data =3D (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ + } \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +#define DO_VST2H(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + int e; \ + uint16_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat] * 4; \ + data =3D 0; \ + for (e =3D 1; e >=3D 0; e--) { = \ + qd =3D (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ + data =3D (data << 16) | qd[H2(off[beat])]; \ + } \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +#define DO_VST2W(OP, O1, O2, O3, O4) \ + void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ + uint32_t base) \ + { \ + int beat; \ + uint16_t mask =3D mve_eci_mask(env); \ + static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ + uint32_t addr, data; \ + uint32_t *qd; \ + for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ + if ((mask & 1) =3D=3D 0) { = \ + /* ECI says skip this beat */ \ + continue; \ + } \ + addr =3D base + off[beat]; \ + qd =3D (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ + data =3D qd[H4(off[beat] >> 3)]; \ + cpu_stl_le_data_ra(env, addr, data, GETPC()); \ + } \ + } + +DO_VST2B(vst20b, 0, 2, 12, 14) +DO_VST2B(vst21b, 4, 6, 8, 10) + +DO_VST2H(vst20h, 0, 1, 6, 7) +DO_VST2H(vst21h, 2, 3, 4, 5) + +DO_VST2W(vst20w, 0, 4, 24, 28) +DO_VST2W(vst21w, 8, 12, 16, 20) + /* * The mergemask(D, R, M) macro performs the operation "*D =3D R" but * storing only the bytes which correspond to 1 bits in M, diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d3cb3396863..78229c44c68 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -35,6 +35,7 @@ static inline int vidup_imm(DisasContext *s, int x) =20 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); @@ -378,6 +379,99 @@ static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vl= dst_sg_imm *a) return do_ldst_sg_imm(s, a, fns[a->w], MO_64); } =20 +static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *= fn, + int addrinc) +{ + TCGv_i32 rn; + + if (!dc_isar_feature(aa32_mve, s) || + !mve_check_qreg_bank(s, a->qd) || + !fn || (a->rn =3D=3D 13 && a->w) || a->rn =3D=3D 15) { + /* Variously UNPREDICTABLE or UNDEF or related-encoding */ + return false; + } + if (!mve_eci_check(s) || !vfp_access_check(s)) { + return true; + } + + rn =3D load_reg(s, a->rn); + /* + * We pass the index of Qd, not a pointer, because the helper must + * access multiple Q registers starting at Qd and working up. + */ + fn(cpu_env, tcg_constant_i32(a->qd), rn); + + if (a->w) { + tcg_gen_addi_i32(rn, rn, addrinc); + store_reg(s, a->rn, rn); + } else { + tcg_temp_free_i32(rn); + } + mve_update_and_store_eci(s); + return true; +} + +/* This macro is just to make the arrays more compact in these functions */ +#define F(N) gen_helper_mve_##N + +static bool trans_VLD2(DisasContext *s, arg_vldst_il *a) +{ + static MVEGenLdStIlFn * const fns[4][4] =3D { + { F(vld20b), F(vld20h), F(vld20w), NULL, }, + { F(vld21b), F(vld21h), F(vld21w), NULL, }, + { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL }, + }; + if (a->qd > 6) { + return false; + } + return do_vldst_il(s, a, fns[a->pat][a->size], 32); +} + +static bool trans_VLD4(DisasContext *s, arg_vldst_il *a) +{ + static MVEGenLdStIlFn * const fns[4][4] =3D { + { F(vld40b), F(vld40h), F(vld40w), NULL, }, + { F(vld41b), F(vld41h), F(vld41w), NULL, }, + { F(vld42b), F(vld42h), F(vld42w), NULL, }, + { F(vld43b), F(vld43h), F(vld43w), NULL, }, + }; + if (a->qd > 4) { + return false; + } + return do_vldst_il(s, a, fns[a->pat][a->size], 64); +} + +static bool trans_VST2(DisasContext *s, arg_vldst_il *a) +{ + static MVEGenLdStIlFn * const fns[4][4] =3D { + { F(vst20b), F(vst20h), F(vst20w), NULL, }, + { F(vst21b), F(vst21h), F(vst21w), NULL, }, + { NULL, NULL, NULL, NULL }, + { NULL, NULL, NULL, NULL }, + }; + if (a->qd > 6) { + return false; + } + return do_vldst_il(s, a, fns[a->pat][a->size], 32); +} + +static bool trans_VST4(DisasContext *s, arg_vldst_il *a) +{ + static MVEGenLdStIlFn * const fns[4][4] =3D { + { F(vst40b), F(vst40h), F(vst40w), NULL, }, + { F(vst41b), F(vst41h), F(vst41w), NULL, }, + { F(vst42b), F(vst42h), F(vst42w), NULL, }, + { F(vst43b), F(vst43h), F(vst43w), NULL, }, + }; + if (a->qd > 4) { + return false; + } + return do_vldst_il(s, a, fns[a->pat][a->size], 64); +} + +#undef F + static bool trans_VDUP(DisasContext *s, arg_VDUP *a) { TCGv_ptr qd; --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uBxA9lRn32o8jxzCzodlCKjwyFhbRGHrLqfALZs17cU=; b=S+DbVzvvrqECqKhypbhmuUypvGgRE3lzIRGHnD+P/vT/OE1bm3jDBVgk1bdjPlxCrt PGLvyyAmUufPMHI50tG0NnMgJr45rCYWid7BSWiIABef1LUaYhxArwEKiE8MXlbG7fcO KZuUJ9lMsNTm4xZt+xEGcN2ogFBEAVmX9ap2/WX8sXoHteRMGapaKyrNM4H/Vrb2jFxQ XXfW8WtF1/DakC93sm9QM1lcBJYShbDiHobNXBBsbN5991f1bS8MqSOdm9l9oehG//ww MvvrL66Y6J/hwl1nVR6hNEVe2c+NnEVwY+tnEaOhgQg3KApm6bY7qiT3ttZRE5YKlwwL jvEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uBxA9lRn32o8jxzCzodlCKjwyFhbRGHrLqfALZs17cU=; b=jOlWpU+qQxSmTEu1rJICb605pb/8uoOjYrxEf68Nf/PBdGJlA+yok+53XBY8WD+9Td 5ywdss8OJTMiqVOdevXJJGLycTTCe2mrO7vXQUQSR1G5izQO9xrm4LoOIFFSIGx8JWoJ luHiIEes8Unb/mjMfswyoH7rw7X2EROh4zunjOx3WnLvFw0a5CEyQdGBvMkauRihQ8Ff u+bGbyvi1O/sl0qcNXLNoZmz/5hIKvxVXojBUmiSJlkluTX5ww77H+74G1kVCz2KX8UX jLjvjJi/6KAa/0aw4R5Tr65KBA0T19eJIHcV3AlUnETd0X5MIkzeMoXhmMX57WyWbgLf 2Hng== X-Gm-Message-State: AOAM531kZOWaqG9hbcqTgLEm3pdub7LlfJbfeQlIOlNjnw9RVFu4q16v IMgWiu8gg+j8HNx/zPE8dsIvezoE6fRP+w== X-Google-Smtp-Source: ABdhPJzT2ypQv06Eo1Jbidr6I7vYT+fmApnMszF32xE2B0KPnfZULB+YKqvJHc3e99ML03CG7rJFAQ== X-Received: by 2002:adf:ba08:: with SMTP id o8mr21031211wrg.234.1629887767159; Wed, 25 Aug 2021 03:36:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/44] target/arm: Re-indent sdiv and udiv helpers Date: Wed, 25 Aug 2021 11:35:26 +0100 Message-Id: <20210825103534.6936-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888579225100003 Content-Type: text/plain; charset="utf-8" We're about to make a code change to the sdiv and udiv helper functions, so first fix their indentation and coding style. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210730151636.17254-2-peter.maydell@linaro.org --- target/arm/helper.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 155d8bf2399..8e9c2a2cf8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9355,17 +9355,20 @@ uint32_t HELPER(uxtb16)(uint32_t x) =20 int32_t HELPER(sdiv)(int32_t num, int32_t den) { - if (den =3D=3D 0) - return 0; - if (num =3D=3D INT_MIN && den =3D=3D -1) - return INT_MIN; + if (den =3D=3D 0) { + return 0; + } + if (num =3D=3D INT_MIN && den =3D=3D -1) { + return INT_MIN; + } return num / den; } =20 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) { - if (den =3D=3D 0) - return 0; + if (den =3D=3D 0) { + return 0; + } return num / den; } =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889199; cv=none; d=zohomail.com; s=zohoarc; b=U7+NIkLRaTSm4eArGWzRFO51+VCQZDL30/tS4iLgAUjq0jLSLRA9JG1OHYIAhb7pzIj/9TaJIHMclehEewzXHjdqGA+gOGvvm/UgzIl/qz4sdBQXpqHRErLV60IQwpD5yspPgWi37/TSju2eJLSX6W22beOYaSxHAZV4IbGb05A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889199; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DkSKucbRVfZaukjnVODkmhOBvmBFYtKFjtgssow2x4M=; b=Fy8h2bkFJ/5kc07iLGCI/z4A80dUjuC2TfAC6yx/pmJljITCLcKn+LF5S46juCosB+/CMwiZ0SQOm/41NeWIHlGz6nym+G3qYSf4SCYmbdjZFvg+O05I4bv0ug1DrQdiJckfmr5wGBGgA+qF++mZrN4ndtHucTOzythTIVhsA5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162988919832649.53875193225622; Wed, 25 Aug 2021 03:59:58 -0700 (PDT) Received: from localhost ([::1]:54258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqdQ-00055W-Ae for importer@patchew.org; Wed, 25 Aug 2021 06:59:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGU-0004mK-2q for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:14 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGP-0005dk-6B for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:13 -0400 Received: by mail-wr1-x42a.google.com with SMTP id f5so35619930wrm.13 for ; Wed, 25 Aug 2021 03:36:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DkSKucbRVfZaukjnVODkmhOBvmBFYtKFjtgssow2x4M=; b=grIijKxBBCp71b61W9eHjT+WKK6suKIsXOcswYxPn9CTAaujW9N1uOmnrKMUv+MQHe Gp7M1YpylbN8GNBZjibR3IqxdBZjfAgflMGkA5i5nJaU5v5h6UiM6a4mCXkCqhqXx2sB x3D8p4SYBf+Q5Inyr4HcEyeXGlBPWg6in1kbr3VMsLOaj/J+npZjSgiOa1UCNhhcMvYI WKuWW9dZsdTsANeXmcsOJzf+t/Ob1GTblZXvQaknv8q0K0FV6ir4BMLtyECGO+COEJBa 0DrBpc2wmYdWxonaz/8Z72psQTvXYPEj9jkilT088Colvuqka99u4pcvm/5DGH4dehNV nOKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DkSKucbRVfZaukjnVODkmhOBvmBFYtKFjtgssow2x4M=; b=K+vtiIheuU8IbVe1UkswjXad452geLeDI7EJjwkMF+n52/k+0+LuS5ac3+yyg/r7Og g8UcxaOzBlNxSMERO5uGgH1Tdq2NV/N5EDydtN8JGGI6zUZPZ1/0p22AYfyOu4/GqbAb FQTvnVlNu/q/ciOSmNVCD1KQU+8AxW0O1K3rvr34CtOw5BMslv3B77CT060GJ/QSh3J9 A+umTN/T9UhKv9azHrmdlCPPog7lcHHebTbMBbVAuNtPC3t6yN0u2LW28DjtqlXeTqpi PpsXkTSvh0Id5CFpNN/FB7uTTfVqsZnnpHLTCROfjxxOzAxnE+it1r0uyTs5HZTSLvmd puiw== X-Gm-Message-State: AOAM530ZV7RTRo7l2ZWX9SnNEInTPVND7wcWroK6QbXV+HBNFfq44KUF Q7gThpRrm539lQ20W8hkO4RrgxAEmrkk6w== X-Google-Smtp-Source: ABdhPJzOX0yzdGRJ8EWPvC2CsvXDQW0S+RtiBLQgmR86YD9zvaeFVfclXMtxcWT/2EUVHLwDSKViBA== X-Received: by 2002:a5d:5983:: with SMTP id n3mr14866454wri.227.1629887767922; Wed, 25 Aug 2021 03:36:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/44] target/arm: Implement M-profile trapping on division by zero Date: Wed, 25 Aug 2021 11:35:27 +0100 Message-Id: <20210825103534.6936-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889203190100003 Content-Type: text/plain; charset="utf-8" Unlike A-profile, for M-profile the UDIV and SDIV insns can be configured to raise an exception on division by zero, using the CCR DIV_0_TRP bit. Implement support for setting this bit by making the helper functions raise the appropriate exception. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210730151636.17254-3-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/helper.h | 4 ++-- target/arm/helper.c | 19 +++++++++++++++++-- target/arm/m_helper.c | 4 ++++ target/arm/translate.c | 4 ++-- 5 files changed, 26 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d50..5cf8996ae3c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -54,6 +54,7 @@ #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ +#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 248569b0cd8..aee8f0019b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -6,8 +6,8 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32) DEF_HELPER_3(sub_saturate, i32, env, i32, i32) DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32) -DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) =20 #define PAS_OP(pfx) \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e9c2a2cf8c..56c520cf8e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9345,6 +9345,18 @@ uint32_t HELPER(sxtb16)(uint32_t x) return res; } =20 +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + uint32_t HELPER(uxtb16)(uint32_t x) { uint32_t res; @@ -9353,9 +9365,10 @@ uint32_t HELPER(uxtb16)(uint32_t x) return res; } =20 -int32_t HELPER(sdiv)(int32_t num, int32_t den) +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) { if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } if (num =3D=3D INT_MIN && den =3D=3D -1) { @@ -9364,9 +9377,10 @@ int32_t HELPER(sdiv)(int32_t num, int32_t den) return num / den; } =20 -uint32_t HELPER(udiv)(uint32_t num, uint32_t den) +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) { if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } return num / den; @@ -9567,6 +9581,7 @@ void arm_log_exception(int idx) [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 20761c94877..47903b3dc35 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2252,6 +2252,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNALIGNED_MASK; break; + case EXCP_DIVBYZERO: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_DIVBYZERO_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secur= e); diff --git a/target/arm/translate.c b/target/arm/translate.c index 804a53279bd..115aa768b6a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7992,9 +7992,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); if (u) { - gen_helper_udiv(t1, t1, t2); + gen_helper_udiv(t1, cpu_env, t1, t2); } else { - gen_helper_sdiv(t1, t1, t2); + gen_helper_sdiv(t1, cpu_env, t1, t2); } tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888434; cv=none; d=zohomail.com; s=zohoarc; b=bgEKtaxQg8NZzl9Mp/NcZ+IgFzaGyjjY3hQZ9347hgAeg4PXxGAgOxbBOQ38FaktzHnGRrBBiKB0Bi5o1AJPX0C115UKVazrVAyNSeR4v9pOhXleJy8v23sRNWz4Ldhjm7wRxZ2Ktp6FixdYW0E/yLmyYoK6w0QFd6LD/7Wuq3k= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vm7ius1nKHLmi0kFWlYTD0HSlr7YYDUTqZ7gyOscQOk=; b=ZsEVRlqs2KcS1k0wTZaYctdn/3M8udY4e3ZOwNUccS/Vc/e534OfXAOjGAHKkPtmwF z+HB6yIZ+ZITiA9zNpxkhQnGgT/b/UbYIxfomkwZgf3VBKv3WP2yGfpTOrz2DfRqRRo2 zvYkBXX4y9uljZcW/zg9/7gsBI1n+dd3Uc9nl0uws9vLgulVaxra1AA1vcqyXnRremH6 BGktSpsoQd5fnNpai55evXz/iTlexjZVBPpG1q2zpEsAw4T4Fde3eL2NOhJacHOurRmb VzecHE/p4q/1DynFgkDLNnT7yjP00WJidhlcvYftVptBZWqHO7mrg7amKisLW7uIyV5W 6oOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vm7ius1nKHLmi0kFWlYTD0HSlr7YYDUTqZ7gyOscQOk=; b=BQJnVPVaucd3NMMPPyZGJYTeBr85/2bV9usgTmJ3ZBoWMghUQ5xC4jDlzH2RYXOr0J W6E9qVXuvkY4UUJB8yrwGok4nG7rxzx4vKcNMFqGuVg1uWa3/aYxjZUqTslFGPO83bZh xMOTQAxMxH6Os0Bpv3CWWL5ZECttICs3UytdDnLGMAieUJH0cJgxJbijBDNmm971PzM2 i8LWqFa9cLiyqek8zOlG2Dbuii0qThO3LoMu+cwnGkmZ9MCPT+qZOoU2LDlf7e4TiYUO jBm55n6Mjjm1ATfqBnSVcV7seerb85mfa9MKnsjbTT6Q3J7eXyQPVXyWv6p0GvALCqom 6NOw== X-Gm-Message-State: AOAM533VfU9FlF/5tAV7WcmSQv3hL1xTsoUATgP+bDoBO9PXWpn8wWbm l8+qMfjPs2201IjwSgvONNmpl8KE5X9gjw== X-Google-Smtp-Source: ABdhPJw9sBVYep71TYkxNo0f+1kPLTl3xIV4Z1vsAWchT+XuhI0t5prmZuS4eU08HsEfPqpdfdTO0g== X-Received: by 2002:a1c:2285:: with SMTP id i127mr2894662wmi.64.1629887768649; Wed, 25 Aug 2021 03:36:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/44] target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() Date: Wed, 25 Aug 2021 11:35:28 +0100 Message-Id: <20210825103534.6936-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888436490100001 Content-Type: text/plain; charset="utf-8" From: Hamza Mahfooz As per commit 5626f8c6d468 ("rcu: Add automatically released rcu_read_lock variants"), RCU_READ_LOCK_GUARD() should be used instead of rcu_read_{un}lock(). Signed-off-by: Hamza Mahfooz Reviewed-by: Paolo Bonzini Message-id: 20210727235201.11491-1-someguy@effective-light.com Signed-off-by: Peter Maydell --- target/arm/kvm.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d8381ba2245..5d55de1a493 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -998,7 +998,6 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_ent= ry *route, hwaddr xlat, len, doorbell_gpa; MemoryRegionSection mrs; MemoryRegion *mr; - int ret =3D 1; =20 if (as =3D=3D &address_space_memory) { return 0; @@ -1006,15 +1005,19 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing= _entry *route, =20 /* MSI doorbell address is translated by an IOMMU */ =20 - rcu_read_lock(); + RCU_READ_LOCK_GUARD(); + mr =3D address_space_translate(as, address, &xlat, &len, true, MEMTXATTRS_UNSPECIFIED); + if (!mr) { - goto unlock; + return 1; } + mrs =3D memory_region_find(mr, xlat, 1); + if (!mrs.mr) { - goto unlock; + return 1; } =20 doorbell_gpa =3D mrs.offset_within_address_space; @@ -1025,11 +1028,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_= entry *route, =20 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); =20 - ret =3D 0; - -unlock: - rcu_read_unlock(); - return ret; + return 0; } =20 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888528; cv=none; d=zohomail.com; s=zohoarc; b=T6iafXRFE/FvLvofBtfaPlgzietsl9mNDFnDWjYTp1jla/wr/vLbFxtgH55S/p7aXCPNEzGlExYyd78ca7Kqxerz7yAYpH0JdguI1iFWZrWEQBG0Vd9MDYLCJhZw6sk9JQdsNSfaCxmKvx1+/VIRRogVwl5I86Rc/6vnKa73TCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888528; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HOJv+mxMWwAU2cVeZjJ47Jn4+NXPcnKdS6AaQhDJDoU=; b=OlPqj1hFtkaz9J6cq9xo5NFTSa2voNoE3SZuFqh0O8p7PVZwYgqpP+qzyHsP69MEpkD4dD1Il67UuzDFXSVVk2nnuthcXeOzJmNRyRlBwzVFzLSlBXnCHRhbIMfNCo3GTXHFMrvVz43syH6VgDe4JCUkMufx5SFi7A4d/xten74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629888528392612.4839772724498; Wed, 25 Aug 2021 03:48:48 -0700 (PDT) Received: from localhost ([::1]:33698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqSd-00067X-AU for importer@patchew.org; Wed, 25 Aug 2021 06:48:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGS-0004fE-C1 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:12 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:46961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGQ-0005eH-OZ for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:12 -0400 Received: by mail-wm1-x32b.google.com with SMTP id m25-20020a7bcb99000000b002e751bcb5dbso4223462wmi.5 for ; Wed, 25 Aug 2021 03:36:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HOJv+mxMWwAU2cVeZjJ47Jn4+NXPcnKdS6AaQhDJDoU=; b=Z9MAWHBsa09I0F3KjZmkTFarCBrRsyzIvAxnA9ZAlk2LS/QColahuBpsm8/VLiL5wo k+KxU3/WrNWgUQ06f0WxInGJGFxfblScHiA7DRQRoTSk9L+5Uff/BSfnkuUei/Xq3fOU /7M2/7g6kYajKINvAgSTB8s7vCr9kzwp7hcOCFTGeHWbT58fwk82D66qyXYfytITKLSM gPeemp0L2pNraTRLiwzQtb2a3mbhVGW83UM8Phfg/3Z9APO9l9IOXyJm8QAMUFp4jCEs 8S9qAzYglBBjTLHXI84irhsucGd6/TicSVIMJGXuxAh/Ew+g8K7kFKIeCCTguax3yiab OAVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HOJv+mxMWwAU2cVeZjJ47Jn4+NXPcnKdS6AaQhDJDoU=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888529422100001 Content-Type: text/plain; charset="utf-8" From: Jan Luebbe Break events are currently only handled by chardev/char-serial.c, so we just ignore errors, which results in no behaviour change for other chardevs. Signed-off-by: Jan Luebbe Message-id: 20210806144700.3751979-1-jlu@pengutronix.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/char/pl011.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index dc85527a5f9..6e2d7f75095 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties-system.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" +#include "chardev/char-serial.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" @@ -231,6 +232,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->read_count =3D 0; s->read_pos =3D 0; } + if ((s->lcr ^ value) & 0x1) { + int break_enable =3D value & 0x1; + qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, + &break_enable); + } s->lcr =3D value; pl011_set_read_trigger(s); break; --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889450; cv=none; d=zohomail.com; s=zohoarc; b=R2LKYbjMjwC5AEfLjjl9iye4vVnPZS8fwvG4PTZjUy/9gMH1uOj+SLmuUnL3sC0pLyUdrys5sV0hqX+tp9J/LEOA4yVT2LYa4W3C+RaEQ8Z58xcJc6X0z6TghMOuWUb92oik7AOUsbzwvBvYaOBc7cqR37LG5PH1A5K2uYrbJ3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889450; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=n63vJxGRMpP5Eh4GilygWZg8oc7U1262scL0OrU0E08=; b=ydX2AQy1ExyjeX1w7zPJw7JDdSZR8mnV2QkdHUu0zxJa/tlQWhWqEnKZE01P9Hj/kH 6gifO6B/EscR4481JTciQw8a5XBIPymrHFaXHRDatYzVOfs5SbCgtpiHwwBVs+XD2Y3n 9VhhsOM9iA25y/ligOJ1H4jktldHPBCdbvWxs0nlOYB5YZ/PXW6u3ARg6fA+y41Lfp2S TvMPy5219/ErRMW2qq2M/GT5wt4OE6uF4tyPpG4nmxfdZccA4ph4oJVabYn8mtGaFX2t jMY8rEPfDg6j2jeUVQpNMYVHGX2kPsBpo/M4Nyz+aGf04BpP2N5KMkFFnGIQ8IPjVUeB B/BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n63vJxGRMpP5Eh4GilygWZg8oc7U1262scL0OrU0E08=; b=gPcSCBi6qThCAJQBahhcMPyh+dExDzfky6caaPTnUFa+AQ7QAoBwzdxYnUmFXAp6r9 KaWQS4xf63vUczqu5orGMvYsE3MinkfmTnzXVYIftnnuKVKFZRHsvuHhkLPnNwUs8VtR H1irNz/NoPQhYF22vwpCz05GKw9l2m7TxvfUNqoqByjd70fnSPuX5O9leza7iJjBn0rO fDKaiMsF/dyj9wXnhgnk4WW8UTsmQXgCFj8EYDV14RjEy4MvH5v4x9ppzL7LzJe0WDyx Se2FuVFYDkubSP/qrH3K498mQRY/+4qHVYku4vv5cYTQSA22/SiLRz5hNEvRe7dQsYec BfwA== X-Gm-Message-State: AOAM530wQshePNs63iQ/yUTTGEtzcSEfhbqwI16T4GZe3QViW0T65lpz SxOMWv3f4bfbZKcyzR3wfvxqv7vv4oB/fg== X-Google-Smtp-Source: ABdhPJwKO854cagAOLpMkm47BaDGqhPm9POTHLgNKZHagSkfpnYJerikyD7FTLWka4AeKg/Igjiabg== X-Received: by 2002:a05:600c:1d0d:: with SMTP id l13mr8467494wms.76.1629887770188; Wed, 25 Aug 2021 03:36:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/44] fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices Date: Wed, 25 Aug 2021 11:35:30 +0100 Message-Id: <20210825103534.6936-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889451519100001 From: Guenter Roeck Instantiate SAI1/2/3 and ASRC as unimplemented devices to avoid random Linux kernel crashes, such as Unhandled fault: external abort on non-linefetch (0x808) at 0xd1580010 pgd =3D (ptrval) [d1580010] *pgd=3D8231b811, *pte=3D02034653, *ppte=3D02034453 Internal error: : 808 [#1] SMP ARM ... [] (regmap_mmio_write32le) from [] (regmap_mmio_write+0= x3c/0x54) [] (regmap_mmio_write) from [] (_regmap_write+0x4c/0x1f= 0) [] (_regmap_write) from [] (_regmap_update_bits+0xe4/0x= ec) [] (_regmap_update_bits) from [] (regmap_update_bits_ba= se+0x50/0x74) [] (regmap_update_bits_base) from [] (fsl_asrc_runtime_= resume+0x1e4/0x21c) [] (fsl_asrc_runtime_resume) from [] (__rpm_callback+0x= 3c/0x108) [] (__rpm_callback) from [] (rpm_callback+0x60/0x64) [] (rpm_callback) from [] (rpm_resume+0x5cc/0x808) [] (rpm_resume) from [] (__pm_runtime_resume+0x60/0xa0) [] (__pm_runtime_resume) from [] (fsl_asrc_probe+0x2a8/= 0x708) [] (fsl_asrc_probe) from [] (platform_probe+0x58/0xb8) [] (platform_probe) from [] (really_probe.part.0+0x9c/0= x334) [] (really_probe.part.0) from [] (__driver_probe_device= +0xa0/0x138) [] (__driver_probe_device) from [] (driver_probe_device= +0x30/0xc8) [] (driver_probe_device) from [] (__driver_attach+0x90/= 0x130) [] (__driver_attach) from [] (bus_for_each_dev+0x78/0xb= 8) [] (bus_for_each_dev) from [] (bus_add_driver+0xf0/0x1d= 8) [] (bus_add_driver) from [] (driver_register+0x88/0x118) [] (driver_register) from [] (do_one_initcall+0x7c/0x3a= 4) [] (do_one_initcall) from [] (kernel_init_freeable+0x19= 8/0x22c) [] (kernel_init_freeable) from [] (kernel_init+0x10/0x1= 28) [] (kernel_init) from [] (ret_from_fork+0x14/0x38) or Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000 pgd =3D (ptrval) [d19b0000] *pgd=3D82711811, *pte=3D308a0653, *ppte=3D308a0453 Internal error: : 808 [#1] SMP ARM ... [] (regmap_mmio_write32le) from [] (regmap_mmio_write+0= x3c/0x54) [] (regmap_mmio_write) from [] (_regmap_write+0x4c/0x1f= 0) [] (_regmap_write) from [] (regmap_write+0x3c/0x60) [] (regmap_write) from [] (fsl_sai_runtime_resume+0x9c/= 0x1ec) [] (fsl_sai_runtime_resume) from [] (__rpm_callback+0x3= c/0x108) [] (__rpm_callback) from [] (rpm_callback+0x60/0x64) [] (rpm_callback) from [] (rpm_resume+0x5cc/0x808) [] (rpm_resume) from [] (__pm_runtime_resume+0x60/0xa0) [] (__pm_runtime_resume) from [] (fsl_sai_probe+0x2b8/0= x65c) [] (fsl_sai_probe) from [] (platform_probe+0x58/0xb8) [] (platform_probe) from [] (really_probe.part.0+0x9c/0= x334) [] (really_probe.part.0) from [] (__driver_probe_device= +0xa0/0x138) [] (__driver_probe_device) from [] (driver_probe_device= +0x30/0xc8) [] (driver_probe_device) from [] (__driver_attach+0x90/= 0x130) [] (__driver_attach) from [] (bus_for_each_dev+0x78/0xb= 8) [] (bus_for_each_dev) from [] (bus_add_driver+0xf0/0x1d= 8) [] (bus_add_driver) from [] (driver_register+0x88/0x118) [] (driver_register) from [] (do_one_initcall+0x7c/0x3a= 4) [] (do_one_initcall) from [] (kernel_init_freeable+0x19= 8/0x22c) [] (kernel_init_freeable) from [] (kernel_init+0x10/0x1= 28) [] (kernel_init) from [] (ret_from_fork+0x14/0x38) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Guenter Roeck Message-id: 20210810160318.87376-1-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6ul.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index e0128d73161..1d1a708dd97 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -534,6 +534,13 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) */ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); =20 + /* + * SAI (Audio SSI (Synchronous Serial Interface)) + */ + create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); + create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); + create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); + /* * PWM */ @@ -542,6 +549,11 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); =20 + /* + * Audio ASRC (asynchronous sample rate converter) + */ + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); + /* * CAN */ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889781; cv=none; d=zohomail.com; s=zohoarc; b=Xy6V9J7onvLbk00mtajy0cQLsDbqRr/14JU5mPNZDQK5o/Xcz3zCjPOcq/dvaH7aXCatRwfyC0QI1AG+sTX8tujIbwDHTeIPDfHrTUAEBIKab4P04gXzeOZ3vyCKBAWv421RG+5ZO4ldS73huTWTYS/L2QL7xI8JAHQS1rN39ts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889781; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=us54UYZLQN0nQhY4FPVzcNyu00zb835SaV13XZLLvmk=; b=A0EjK+KW95BR+VGuISMA72vUosHaiOv1lNGYH6WcT9Yghj25/5pphrR6TRlO1bC6eMQWhWe5xYlfxaJian20u4ybIZjWHJFJHU3koGc+mOu8z1MMbWDKgt3hU7eUZQ/Pny2aihNxe4liSOvjDuBBqJnKLwNKW7N+nqY/TTvoFHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629889781348371.2014571610308; Wed, 25 Aug 2021 04:09:41 -0700 (PDT) Received: from localhost ([::1]:51194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqmq-0006FV-9P for importer@patchew.org; Wed, 25 Aug 2021 07:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGW-0004xR-Vu for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:17 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:38851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGS-0005fl-6c for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:16 -0400 Received: by mail-wr1-x434.google.com with SMTP id u16so35670739wrn.5 for ; Wed, 25 Aug 2021 03:36:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=us54UYZLQN0nQhY4FPVzcNyu00zb835SaV13XZLLvmk=; b=K5ZwMOSURXmIFiSqaz4L0uqQUKyj9m1qtPzVcdp/hGyIsQgv9G1ygf9fBM8SIUJSEX 5h8K02eVmO/J2ub/VTM5MQ7llI1sV2dBY17U/VRXdaNDFHL0tqn4TMtAUcBMHpL0v/E1 5iUImVpyNn1Bf/0J7In1fSF28ajxe9Icva6KkLY02/m08h1jY1d3DE7WMzJF47ecEpn9 8wFLmhW2D/kc4/1b8BzJATSqJw8fsjlU9L4IlHZmodCirReu7YP4MFBEwO8dhfspMj4R yH7u8zF2VvbIYCc/pIJwK6plJZaNe730t5afFL3MFfWL8+bup4ObWzNXU4bIh6i+L3/P lWbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=us54UYZLQN0nQhY4FPVzcNyu00zb835SaV13XZLLvmk=; b=fywTKbOMtMhI1/qYBdBE9P4OxHcJP0mZyYVYG+4NFS7HCVfnEX5ROVaFIj0GDrlEsA +o/G0Nk91wmZ8uilNxuLHgyLejF4KtVnyNMkMvJ9Ws6X7hxGNqKkKzpoOjRKWsBp1W6p dJF/9xX7fkAttJm9iBi8o6F07OvvyFCuu5X7/zP9EyC7BHDGBzoJLg6QP0n04JBHwJEA 9WYUqRMwuMGppEyI8+5Tnc0Mjx2EJQuSUOaCtNFAoNwtC13s1xatNenRdRsh7DuXvgnI kWXSWnxnr+Bon4g2/083UPS6/63RJ/BbZNWN4tjMu3jB5sqfoQNVTm7JBy7nJ7cD31rM Ho8g== X-Gm-Message-State: AOAM533lUtzgqPhFn/gJXDZeKkoMBuJKqajwdhAjMZKdx6CgGX+F402c dF6vWRIX/6dFA/FNP0PcAMNCp0jjdUbk9Q== X-Google-Smtp-Source: ABdhPJzDz9jfxS7suraODR3eTRaYkOrTDw013khmC8uJbKx4Eww8CxKbWttcnpi0XJ/xpbvXuE6ghA== X-Received: by 2002:a5d:51c6:: with SMTP id n6mr24452687wrv.370.1629887770929; Wed, 25 Aug 2021 03:36:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/44] hw/dma/pl330: Add memory region to replace default Date: Wed, 25 Aug 2021 11:35:31 +0100 Message-Id: <20210825103534.6936-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889782850100001 From: "Wen, Jianxian" Add property memory region which can connect with IOMMU region to support S= MMU translate. Signed-off-by: Jianxian Wen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 4C23C17B8E87E74E906A25A3254A03F4FA1FEC31@SHASXM03.verisilicon.c= om Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 3 +++ hw/arm/xilinx_zynq.c | 3 +++ hw/dma/pl330.c | 26 ++++++++++++++++++++++---- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 5c7a51bbad7..0299e81f853 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -173,6 +173,9 @@ static DeviceState *pl330_create(uint32_t base, qemu_or= _irq *orgate, int i; =20 dev =3D qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(get_system_memory()), + &error_fatal); qdev_prop_set_uint8(dev, "num_events", nevents); qdev_prop_set_uint8(dev, "num_chnls", 8); qdev_prop_set_uint8(dev, "num_periph_req", nreq); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 245af81bbb7..69c333e91b1 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -312,6 +312,9 @@ static void zynq_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); =20 dev =3D qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(address_space_mem), + &error_fatal); qdev_prop_set_uint8(dev, "num_chnls", 8); qdev_prop_set_uint8(dev, "num_periph_req", 4); qdev_prop_set_uint8(dev, "num_events", 16); diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 944ba296b08..0cb46191c19 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -269,6 +269,9 @@ struct PL330State { uint8_t num_faulting; uint8_t periph_busy[PL330_PERIPH_NUM]; =20 + /* Memory region that DMA operation access */ + MemoryRegion *mem_mr; + AddressSpace *mem_as; }; =20 #define TYPE_PL330 "pl330" @@ -1108,7 +1111,7 @@ static inline const PL330InsnDesc *pl330_fetch_insn(P= L330Chan *ch) uint8_t opcode; int i; =20 - dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); + dma_memory_read(ch->parent->mem_as, ch->pc, &opcode, 1); for (i =3D 0; insn_desc[i].size; i++) { if ((opcode & insn_desc[i].opmask) =3D=3D insn_desc[i].opcode) { return &insn_desc[i]; @@ -1122,7 +1125,7 @@ static inline void pl330_exec_insn(PL330Chan *ch, con= st PL330InsnDesc *insn) uint8_t buf[PL330_INSN_MAXSIZE]; =20 assert(insn->size <=3D PL330_INSN_MAXSIZE); - dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); + dma_memory_read(ch->parent->mem_as, ch->pc, buf, insn->size); insn->exec(ch, buf[0], &buf[1], insn->size - 1); } =20 @@ -1186,7 +1189,7 @@ static int pl330_exec_cycle(PL330Chan *channel) if (q !=3D NULL && q->len <=3D pl330_fifo_num_free(&s->fifo)) { int len =3D q->len - (q->addr & (q->len - 1)); =20 - dma_memory_read(&address_space_memory, q->addr, buf, len); + dma_memory_read(s->mem_as, q->addr, buf, len); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); @@ -1217,7 +1220,7 @@ static int pl330_exec_cycle(PL330Chan *channel) fifo_res =3D pl330_fifo_get(&s->fifo, buf, len, q->tag); } if (fifo_res =3D=3D PL330_FIFO_OK || q->z) { - dma_memory_write(&address_space_memory, q->addr, buf, len); + dma_memory_write(s->mem_as, q->addr, buf, len); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); @@ -1562,6 +1565,18 @@ static void pl330_realize(DeviceState *dev, Error **= errp) "dma", PL330_IOMEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); =20 + if (!s->mem_mr) { + error_setg(errp, "'memory' link is not set"); + return; + } else if (s->mem_mr =3D=3D get_system_memory()) { + /* Avoid creating new AS for system memory. */ + s->mem_as =3D &address_space_memory; + } else { + s->mem_as =3D g_new0(AddressSpace, 1); + address_space_init(s->mem_as, s->mem_mr, + memory_region_name(s->mem_mr)); + } + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, = s); =20 s->cfg[0] =3D (s->mgr_ns_at_rst ? 0x4 : 0) | @@ -1656,6 +1671,9 @@ static Property pl330_properties[] =3D { DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256= ), =20 + DEFINE_PROP_LINK("memory", PL330State, mem_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889394; cv=none; d=zohomail.com; s=zohoarc; b=dKhqwwA7r5NYOQ3AyCUvisZMIXu4K/iNraQl8TD5HzacuzswbI+jccs8dZzSePAz9vY2hnx25ScRoTpFH8zgupqO/Knp0CWJTH2av0t3xo73ZHKW5X3VWUpRrkFIHPK7wkl1NEp5ysN0IlGuZtXegBpKpz52IdIDSi33viGsiqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629889394; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7aydmPw1AXLOUQd24DIqYVnzOLGoGypnBxuU2CTMgJo=; b=WIDTTAw9hqJ8ZDp1uuB2mQ9rDqOegcxT56Y/v528U+rhfoh8X1I2m9vpOyau8tlugH+gyNTv4lVcrXEvusHLBB+uu2Vybff9s7NVlp30vb87uykqYCzRpUENRVbEmmHafX6KxSIN/g/ImCsv+X57eAwIF1MSOcD2Jxl1X2Jw6cE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629889394634557.1005083784298; Wed, 25 Aug 2021 04:03:14 -0700 (PDT) Received: from localhost ([::1]:60594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqgb-00017S-Jw for importer@patchew.org; Wed, 25 Aug 2021 07:03:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGZ-00058i-Q5 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:19 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:36680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGS-0005g3-Ul for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:19 -0400 Received: by mail-wr1-x42d.google.com with SMTP id q14so1525898wrp.3 for ; Wed, 25 Aug 2021 03:36:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7aydmPw1AXLOUQd24DIqYVnzOLGoGypnBxuU2CTMgJo=; b=hXnomgKW+XHDOdCDQsugbPK1G0YCzi7LfoP1FxGUCumKWMcECQikxJ5N0oJ3k0MCnL rEuwxs9mWKnjoWUxKPbbv1/7e/E8rOzXKRKoNsDicDyCF05XEjkejIjd1YARwzQBn991 ZYMQM6AnEpe2J1NXq1lQNP9aNNreglM2KTho+9v2hHyt0Mrjb4xdoexRMy7Y4Cqrd4Cg IpEEl3Ps3jrALbYKzU/6wNZeMma3CbbOwJ8eGfvqa8xq6vajJ5qGgbeONialnYiv7082 bCIiCh5OwMVVCrRMLTf+GJ1iuXvriwGDVPr/pysEGlyZIlPC+KzAgs8qAvB2jENHycbZ gh3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7aydmPw1AXLOUQd24DIqYVnzOLGoGypnBxuU2CTMgJo=; b=kIc51EsQdiDm0HIyzD/CIzUenqtbh4qRv4tVf8i7fAopQHio8mTApg8NwwR1ATcvvK +2NBKGKxR4tMzXzf851rY2Soj+QX/WfQHVDdjkv/EdWk2udZ0XC5qhnoqdUpk8IobdMd SRBuMW6Lz/TWWe16I6tcVU8pkQ2SWkO5W+zZ/8jArMZSO3GXiYxvMAxcnKMhNw5c1apK +8O/BhHdT8NZ8Loadh5RhpfTAN8XHbXngW4fr3+KYReIiiMDKRFJJxVkTBfn5kGWHwAY GKWeuTSumVBDfEF2WjVUbKATinc0oYimakvPXa9f1s5v+MXnirsLwOU1fbKEt0v/jlK+ Czzg== X-Gm-Message-State: AOAM531TpeR+88hD+c/E401D0bzZNbhPjGhiXHpB8i141XMqHACWEmkN 8IBfZY9tvQTq/LrFrzNXiLAQKGOjNO7g5A== X-Google-Smtp-Source: ABdhPJy5z2u9KOQtR6FCA4uAWFhhhcMM+Nfu2vmWldkymsXSqcXlftiOZkD8RxQO17L2LPG7aKRBiA== X-Received: by 2002:adf:fcc5:: with SMTP id f5mr25048052wrs.114.1629887771514; Wed, 25 Aug 2021 03:36:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/44] sbsa-ref: Rename SBSA_GWDT enum value Date: Wed, 25 Aug 2021 11:35:32 +0100 Message-Id: <20210825103534.6936-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889396004100003 Content-Type: text/plain; charset="utf-8" From: Eduardo Habkost The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type checking helper, preventing us from using a OBJECT_DEFINE* or DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper. If I understand the SBSA 6.0 specification correctly, the signal being connected to IRQ 16 is the WS0 output signal from the Generic Watchdog. Rename the enum value to SBSA_GWDT_WS0 to be more explicit and avoid the name conflict. Signed-off-by: Eduardo Habkost Message-id: 20210806023119.431680-1-ehabkost@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index c1629df6031..509c5f09b4e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -65,7 +65,7 @@ enum { SBSA_GIC_DIST, SBSA_GIC_REDIST, SBSA_SECURE_EC, - SBSA_GWDT, + SBSA_GWDT_WS0, SBSA_GWDT_REFRESH, SBSA_GWDT_CONTROL, SBSA_SMMU, @@ -140,7 +140,7 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_AHCI] =3D 10, [SBSA_EHCI] =3D 11, [SBSA_SMMU] =3D 12, /* ... to 15 */ - [SBSA_GWDT] =3D 16, + [SBSA_GWDT_WS0] =3D 16, }; =20 static const char * const valid_cpus[] =3D { @@ -481,7 +481,7 @@ static void create_wdt(const SBSAMachineState *sms) hwaddr cbase =3D sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; DeviceState *dev =3D qdev_new(TYPE_WDT_SBSA); SysBusDevice *s =3D SYS_BUS_DEVICE(dev); - int irq =3D sbsa_ref_irqmap[SBSA_GWDT]; + int irq =3D sbsa_ref_irqmap[SBSA_GWDT_WS0]; =20 sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, rbase); --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629888704; cv=none; d=zohomail.com; s=zohoarc; b=EfyORkAQyas4H0+LXKH4EfItw3sv11Se//LNG5UmNoH6syipAxpyZaTsLMrt4sf1e06sSpdiKktvtPLLiOaVe1QGbGOvgM4KK/CD7D6gx18WRY7RU9aly3wLc4BAeBsNCKyqr74h+vKPOKGPWQ5vRxTNYgWdFZTLCNOhd/ydq7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629888704; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wbPly+qqd4AS1dpoI091FozMPYkS2uEC5VGsCj8EC38=; b=AffdONSS1fDoMQ0HYLBDqH6i1qiWkRE939DJnOwwndX/XviwvGZ5TSWFp5AWkuUnPoTx67NNZXutAg4uVPMMppKCFHQLHUrglyuxgPJszl8vAeEuSup1OAJEERIeRzt1HBt6VT7zqnA15zbtUkEKN/Xf9zzrco4aeGqmTnsmcMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162988870485583.95210714468249; Wed, 25 Aug 2021 03:51:44 -0700 (PDT) Received: from localhost ([::1]:45202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIqVS-0005YL-00 for importer@patchew.org; Wed, 25 Aug 2021 06:51:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIqGV-0004rC-E3 for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:15 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:55235) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIqGT-0005go-Mx for qemu-devel@nongnu.org; Wed, 25 Aug 2021 06:36:15 -0400 Received: by mail-wm1-x336.google.com with SMTP id g138so14655290wmg.4 for ; Wed, 25 Aug 2021 03:36:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wbPly+qqd4AS1dpoI091FozMPYkS2uEC5VGsCj8EC38=; b=hxOTx4mMhVUOr4s9P28PARTyJI8X6E6QOrjx7O1KexsQ1foxLeD6oy8vA2YmtSFf3W JAXdvGfZwh3tDOb/luwdTlLM9z++9GKgEAXK/Cadv3lPtWZU8Wz+uVnPEaudaZB2N/BT kGJgEodBqQ7ZyesnHi0h6Lc9wMKpkm/6t5EmfFhOZxSh8u8JgmU46nImllhc2zH6Sywb 3t8L81eAfZRbUN58ASbsrMdAZTug82kjaRN8l8hF7HdGEJM5Z3vH0+r9LuMSUNSyMP1Z 4scMLBXe2XWRVcNA4CiYNlBGOIQ385xTve5XcsHO0lo1o8mNolSyYSuDRElPHCCn85l4 AJgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wbPly+qqd4AS1dpoI091FozMPYkS2uEC5VGsCj8EC38=; b=gxCx0SGFB54X+MnJ7J/L+BJby8o0IG7N/KMcY2qQ6ti/hJs7gU+6H9H3DRo0wfliPY yCTtdiGWrVi4lviCV7dvKTJB4Z1Q5+fu7mvRaWNrCU3RH4DrOyCsFa/Tbwsis0yFwEtJ NgunqPyAKRVrgohuBH5/ApaKeymQ/+H1oEVKT2yAQ+Lau1ecR79kkFnYfda2SgQt0ZLL rwrGLxN0jkpw3uh3h/FOMO86Y/X2r0kK8ql/8ATjZjd+Y7LMDV3Urh3yUfyK/1ID+E7j pDAWmxkH9flLJFlpsh4AbCwbvFY6MVxTRKv4P/Hkqp8T9g3P8JiJUm7YUSvStYfku8ct hMnQ== X-Gm-Message-State: AOAM530WcYCjJHcpVfwkRIPa3ZMl9wtf0yJLVtIB09l+ZKk3j8We50gh F8pi2kYN/SUEa5S6HDZTwDnnSNMGJaOycQ== X-Google-Smtp-Source: ABdhPJwi0KORd4Ey84ANdsPxuBJVUjLUeLT/mt1C3NPuVt+OriKzeHeczKqHcExxGx3AkumVjYWcDQ== X-Received: by 2002:a1c:1d1:: with SMTP id 200mr8395232wmb.53.1629887772318; Wed, 25 Aug 2021 03:36:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/44] fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices Date: Wed, 25 Aug 2021 11:35:33 +0100 Message-Id: <20210825103534.6936-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629888706478100001 Content-Type: text/plain; charset="utf-8" From: Guenter Roeck Instantiate SAI1/2/3 as unimplemented devices to avoid Linux kernel crashes such as the following. Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000 pgd =3D (ptrval) [d19b0000] *pgd=3D82711811, *pte=3D308a0653, *ppte=3D308a0453 Internal error: : 808 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc5 #1 ... [] (regmap_mmio_write32le) from [] (regmap_mmio_write+0= x3c/0x54) [] (regmap_mmio_write) from [] (_regmap_write+0x4c/0x1f= 0) [] (_regmap_write) from [] (regmap_write+0x3c/0x60) [] (regmap_write) from [] (fsl_sai_runtime_resume+0x9c/= 0x1ec) [] (fsl_sai_runtime_resume) from [] (__rpm_callback+0x3= c/0x108) [] (__rpm_callback) from [] (rpm_callback+0x60/0x64) [] (rpm_callback) from [] (rpm_resume+0x5cc/0x808) [] (rpm_resume) from [] (__pm_runtime_resume+0x60/0xa0) [] (__pm_runtime_resume) from [] (fsl_sai_probe+0x2b8/0= x65c) [] (fsl_sai_probe) from [] (platform_probe+0x58/0xb8) [] (platform_probe) from [] (really_probe.part.0+0x9c/0= x334) [] (really_probe.part.0) from [] (__driver_probe_device= +0xa0/0x138) [] (__driver_probe_device) from [] (driver_probe_device= +0x30/0xc8) [] (driver_probe_device) from [] (__driver_attach+0x90/= 0x130) [] (__driver_attach) from [] (bus_for_each_dev+0x78/0xb= 8) [] (bus_for_each_dev) from [] (bus_add_driver+0xf0/0x1d= 8) [] (bus_add_driver) from [] (driver_register+0x88/0x118) [] (driver_register) from [] (do_one_initcall+0x7c/0x3a= 4) [] (do_one_initcall) from [] (kernel_init_freeable+0x19= 8/0x22c) [] (kernel_init_freeable) from [] (kernel_init+0x10/0x1= 28) [] (kernel_init) from [] (ret_from_fork+0x14/0x38) Signed-off-by: Guenter Roeck Message-id: 20210810175607.538090-1-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 5 +++++ hw/arm/fsl-imx7.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index f5d527a4906..1c5fa6fd676 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -174,6 +174,11 @@ enum FslIMX7MemoryMap { FSL_IMX7_UART6_ADDR =3D 0x30A80000, FSL_IMX7_UART7_ADDR =3D 0x30A90000, =20 + FSL_IMX7_SAI1_ADDR =3D 0x308A0000, + FSL_IMX7_SAI2_ADDR =3D 0x308B0000, + FSL_IMX7_SAI3_ADDR =3D 0x308C0000, + FSL_IMX7_SAIn_SIZE =3D 0x10000, + FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, =20 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 2ff2cab9246..149885f2b80 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -467,6 +467,13 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_= SIZE); create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_= SIZE); =20 + /* + * SAI (Audio SSI (Synchronous Serial Interface)) + */ + create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_= SIZE); + create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_= SIZE); + create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_= SIZE); + /* * OCOTP */ --=20 2.20.1 From nobody Tue May 7 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629889573; cv=none; d=zohomail.com; s=zohoarc; b=D+YKJE73CddI8GvCYbPdBmrtvdARba+MGar6r2FN68KEaz+Z/jdIPoMtKTgCMmA/wtnAZrmdJodC4kmBhxqcfWM0ppoZLgFLTFC2ReEpbFoSWwluKo64djBYye7XgaPXrm2bSKFcXzYRfxWRWJaI3mGn45QXUF6ehxHgIRn3tGw= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m4sm5075931wml.28.2021.08.25.03.36.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 03:36:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LLWtgW+9AQrEcf5IWz/pAYLJCA/RqHavinTg7t+HK3g=; b=CDAE0DSZLxTWYF0fcXXVfxgns8ixZaDZGbXfBJgf/AlagPwnVFnuNwyd+58Ro59xCZ 1woQmZ8pH6tZASRCdpXdFo0MHNB23toAnyICKkrSaXq8b2qezFVevCJiBez0ghbncq0d pzLHsFkErQlT3CQ0hs5pcdX9pegl8ZhcYKbzZRkPQBNrx8fOcT6Auvu7bSWS4Cjs9PfP xlyWXtCYzyB1pDuKxWW8JBUEFbpQTSbfFlhMqiK2PlEO5hVqfFzRv/leq0Ff37qTN6eq fKdEhHZE7/Cung1s2b+WLtljm4q8LTlDkAaRR1C86NcQuDnp+C35UulyEhFW2XHEkygx wAsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LLWtgW+9AQrEcf5IWz/pAYLJCA/RqHavinTg7t+HK3g=; b=kIQ0L8N4RTanFvYfEdBfYRPXBakn8Qnrf1F8Hw6yO6oO8Kf30LcZlL+RtebpWUHpob g4pAxYgApEJUWOs9DLhQ7m2zFqs6xruN2TQ1fw3yUvFZciJIk8ART+W1/M9ldqTc9PbU CfLeBmmtPt+LdMYfzw3PlPiHVGQUf84iMmJpn8zQ3eBO4ZJlNl7cDW8FQiys9PC+Cqy9 SvLsmPki0gz+IKleUw7XQPBlxSQZkYNGGiw+SON0QNG5PbInxRaYzI+Zg/hhSYJDjnvB KCrzDjAeNgoKdC3tQYabXSIxTagq2erxB418VsWNBhcGtaP+oQRa26/D4CQimua8/hPt WDkQ== X-Gm-Message-State: AOAM530UPxk0T7IcIDht5PN66SJDw0q7C/ZcfdzWS5SIyA4tHkcMcvRl 2JPdVj0wjHPazFGGulmVnFH5LmLd0h+iuw== X-Google-Smtp-Source: ABdhPJyCLSWTx/rf2G9qvnUaCgIrP6+MMvVA0HCazE/CQdSYtkkNzVtkgR9SWMr6tJic9eY/+H58+w== X-Received: by 2002:a1c:6a04:: with SMTP id f4mr8575581wmc.54.1629887772927; Wed, 25 Aug 2021 03:36:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/44] docs: Document how to use gdb with unix sockets Date: Wed, 25 Aug 2021 11:35:34 +0100 Message-Id: <20210825103534.6936-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210825103534.6936-1-peter.maydell@linaro.org> References: <20210825103534.6936-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629889574703100001 From: Sebastian Meyer With gdb 9.0 and better it is possible to connect to a gdbstub over unix sockets, which is better than a TCP socket connection in some situations. The QEMU command line to set this up is non-obvious; document it. Signed-off-by: Sebastian Meyer Message-id: 162867284829.27377.4784930719350564918-0@git.sr.ht [PMM: Tweaked commit message; adjusted wording in a couple of places; fixed rST formatting issue; moved section up out of the 'advanced debugging options' subsection] Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- docs/system/gdb.rst | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst index 144d083df31..bdb42dae2fe 100644 --- a/docs/system/gdb.rst +++ b/docs/system/gdb.rst @@ -15,7 +15,8 @@ The ``-s`` option will make QEMU listen for an incoming c= onnection from gdb on TCP port 1234, and ``-S`` will make QEMU not start the guest until you tell it to from gdb. (If you want to specify which TCP port to use or to use something other than TCP for the gdbstub -connection, use the ``-gdb dev`` option instead of ``-s``.) +connection, use the ``-gdb dev`` option instead of ``-s``. See +`Using unix sockets`_ for an example.) =20 .. parsed-literal:: =20 @@ -100,6 +101,29 @@ not just those in the cluster you are currently workin= g on:: =20 (gdb) set schedule-multiple on =20 +Using unix sockets +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +An alternate method for connecting gdb to the QEMU gdbstub is to use +a unix socket (if supported by your operating system). This is useful when +running several tests in parallel, or if you do not have a known free TCP +port (e.g. when running automated tests). + +First create a chardev with the appropriate options, then +instruct the gdbserver to use that device: + +.. parsed-literal:: + + |qemu_system| -chardev socket,path=3D/tmp/gdb-socket,server=3Don,wait= =3Doff,id=3Dgdb0 -gdb chardev:gdb0 -S ... + +Start gdb as before, but this time connect using the path to +the socket:: + + (gdb) target remote /tmp/gdb-socket + +Note that to use a unix socket for the connection you will need +gdb version 9.0 or newer. + Advanced debugging options =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 --=20 2.20.1