From nobody Sat Sep 27 11:42:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629749188512339.871937390216; Mon, 23 Aug 2021 13:06:28 -0700 (PDT) Received: from localhost ([::1]:50654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIGDD-0004k1-1O for importer@patchew.org; Mon, 23 Aug 2021 16:06:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIG36-0006ts-5v for qemu-devel@nongnu.org; Mon, 23 Aug 2021 15:56:00 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:41630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIG2w-0003Dg-8M for qemu-devel@nongnu.org; Mon, 23 Aug 2021 15:55:59 -0400 Received: by mail-pj1-x1033.google.com with SMTP id z24-20020a17090acb1800b0018e87a24300so751617pjt.0 for ; Mon, 23 Aug 2021 12:55:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id v15sm16685078pff.105.2021.08.23.12.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 12:55:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Nkzm7eBwwK6YNx3T/orn7JiGzqUz9K0xgscSXV8LIM=; b=U4Ql+KlWA/EJMh7If9/daSNgsY84E6Ra+6XEQxTXRVCtdxCnUyPMVX9CqEX1KaURo1 uzCSvWqnCqEfYhvx3Ze8Xjyyrnm51wxtkUd0Xbx9nIyFUZM5KahsJDxBAKSbhK5raN9P +4gq3M13qHjuDvp9QyuZUyUBKxVh/wzTfk1/4qfCZguwkkv+MFirAdMNoyzSfHP+FNUi 4+we4xgoOC5Kdu1RZ87ZaLkfEBM6Pu0DPLnf+69Rp1SdUfZcvjZN2rzXAOXKXecWRhLE C4ElpM9FU9xajgFt0eBa4yJLFassQgZmhgSzkXx468yKRdxl2JP41wqyuJztqahAfZUP WCFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Nkzm7eBwwK6YNx3T/orn7JiGzqUz9K0xgscSXV8LIM=; b=dzcc0hiA5rvzQob1vSTnlhAcShO/7CCGIt9SAHK75PTNsXwn7RXEDzwNAo4jn1Uo5A SY74A5e/DY7hAp55LpRWbEWt0IKt2h52Bkw2lJCOrbM6Nwai82H55ppKWLDqeHh2MEx9 umtEu8yaf8catXNQQITLbbCu8g/gPZjK07nZLq7CrJ4hgYcS95w7lUuJpulJISOZYE7m GWto7uIlmjmevJYUJMFLxaIQUdDt026/2DoNa8BmkM/FmDi/cLFIqUPe6Bx7ed3PZ63V lCRqsLgh3tZ9buK9Gd4xr9fwHFN6iskf1vIfU069lgxAYTmUwKKIzGANPotm1iMmP73d YVyQ== X-Gm-Message-State: AOAM532IiXW6Pc0IQU5Ad9NWNusSs4fCyBqYI5n4Ya2z+DEKYlzpxl8f WyuXo+jl8I0ePH7UW2Qa7Cv6eCfAZ4G2Ww== X-Google-Smtp-Source: ABdhPJw7+FrXi+G8T/fjc0sA3Ck/UFd5hG6Etq1Ym/dwoWcG2uQlm0E9+xmetMLaDYfpiRLbdvtbRw== X-Received: by 2002:a17:90b:3b92:: with SMTP id pc18mr218012pjb.149.1629748545608; Mon, 23 Aug 2021 12:55:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF Date: Mon, 23 Aug 2021 12:55:26 -0700 Message-Id: <20210823195529.560295-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823195529.560295-1-richard.henderson@linaro.org> References: <20210823195529.560295-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629749190984100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Bin Meng Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.c.inc | 146 ++++++++++++------------ 1 file changed, 70 insertions(+), 76 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index fb9f7f9c00..bddbd418d9 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -25,32 +25,43 @@ =20 static bool trans_flw(DisasContext *ctx, arg_flw *a) { + TCGv_i64 dest; + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + dest =3D cpu_fpr[a->rd]; + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); + gen_nanbox_s(dest, dest); =20 - tcg_temp_free(t0); mark_fs_dirty(ctx); return true; } =20 static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); =20 - tcg_gen_addi_tl(t0, t0, a->imm); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D tcg_temp_new(); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); =20 - tcg_temp_free(t0); return true; } =20 @@ -271,12 +282,11 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcv= t_w_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -285,12 +295,11 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fc= vt_wu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -300,17 +309,15 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 #if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); + tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); #else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); #endif =20 - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); - + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -318,10 +325,11 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -329,10 +337,11 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -340,10 +349,11 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s = *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -352,13 +362,10 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fcl= ass_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - - gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); - - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_fclass_s(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -367,15 +374,12 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcv= t_s_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -384,15 +388,12 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fc= vt_s_wu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -402,15 +403,12 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_= w_x *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 - tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -420,11 +418,11 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcv= t_l_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -434,11 +432,11 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fc= vt_lu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -448,14 +446,12 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcv= t_s_l *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } =20 @@ -465,13 +461,11 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fc= vt_s_lu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } --=20 2.25.1