From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737391451244.25646585619802; Mon, 23 Aug 2021 09:49:51 -0700 (PDT) Received: from localhost ([::1]:47736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID8w-0006kW-Bk for importer@patchew.org; Mon, 23 Aug 2021 12:49:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0F-0006EU-9I for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:51 -0400 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]:33519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0A-0006HK-IM for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:50 -0400 Received: by mail-lj1-x233.google.com with SMTP id s12so7407226ljg.0 for ; Mon, 23 Aug 2021 09:40:44 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id z5sm1491671lfs.126.2021.08.23.09.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VEoCDINFgPbEp42QED+f3EBPY61v48BREXQWFSwsRt8=; b=T83w1rbtuCWQ61X22N5E55bPRwwwGLaY0XXUQ4G047NW4UtluEA0ZmLbAPq6d8Ug6o h3DZAHfWxPQ5vqzwXmp871wGKCLckBJLXtbeOY+JF7Lxi4o6/I5R3nQXQu2fZ/zPZ1eK hrpogdYOOLbo5T3b414pSCb4BMZ0QrAxdZ4sJxVz/7o4b9Ay6W1Lt7BxvqVXB6x1fRPS 6uekTUN1cd/R0ZAcGmpTApDvWBJfO5OB0Y2zxNWBEaI7MPkE9iLmvWgj63MUP+F4Y7yz St2J/hbz4fOR1v2Ne/yI3v0oQIfhSvl5wPs72oC4FRjyExu/wd1nb/NRUd7n9fZVD55K 1T5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VEoCDINFgPbEp42QED+f3EBPY61v48BREXQWFSwsRt8=; b=HhjySgC8jYcvhtrj1RjwBD06eaAtqwY5ekgIc+wISvIXj08w3RzP48iqzWfLVKFHtZ Lx3P4LD57XwaAgFykkpiolFYqJD3Ewdp592m4Dd+4iQHQI6yid2e+Zy/KoqqVJS6xWxz +w9zH1NRVQMvk6EF+ziSpQVf6n939uNYBizthwCKJH2zn5+jwi9HmpPDwGJsTN5u8rMK VH9+Zm8h+xm3N+4abXEXOUy4tx1Pw6aCtneOMoQEjbh1nceH9W7qE7ZS/38U1tiMPZBf Ch8sCCaK4VzDU045gp4A36SR76Ba1K/TcpypeAplvobErEFwe1ygonYAfA82ViL2hbJg 6Z2g== X-Gm-Message-State: AOAM530KwaFVXTgLrKAlSQMt/t6HgOCLgszotp7aEPS5vHM7Gb05MIZO IXo+k78UrPfDtkkEdT6eTLh9ZOXtqvxmVS8C X-Google-Smtp-Source: ABdhPJxg5gy9q9aUpm0hBHaVNx0uKN+sq1EhpJTslmIwrkVC1t9jNXkuGcZVTNPmJNtNm/HoWS35Kg== X-Received: by 2002:a2e:9e53:: with SMTP id g19mr29095544ljk.58.1629736842692; Mon, 23 Aug 2021 09:40:42 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Date: Mon, 23 Aug 2021 18:40:24 +0200 Message-Id: <20210823164038.2195113-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737391949100001 Content-Type: text/plain; charset="utf-8" The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Split off removal of 'x-b' property and 'ext_b' field into a separate patch to ensure bisectability. target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..c7bc1f9f44 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -585,6 +585,10 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), + DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), + DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), + DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), + DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..7c4cd8ea89 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,6 +293,10 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; bool ext_counters; bool ext_ifencei; bool ext_icsr; --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16297369750131009.7261197172994; Mon, 23 Aug 2021 09:42:55 -0700 (PDT) Received: from localhost ([::1]:54364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID2D-0000Vo-Is for importer@patchew.org; Mon, 23 Aug 2021 12:42:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0D-0006Di-Av for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629736977076100002 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - The changes to the Zba instructions (i.e. the REQUIRE_ZBA macro and its use for qualifying the Zba instructions) are moved into a separate commit. target/riscv/insn32.decode | 20 ++++++++++++-------- target/riscv/insn_trans/trans_rvb.c.inc | 17 ++++++++++++----- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f09f8d5faf..68b163b72d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -659,6 +659,18 @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 010111= 1 @r_wdvm vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm =20 +# *** RV32 Zba Standard Extension *** +sh1add 0010000 .......... 010 ..... 0110011 @r +sh2add 0010000 .......... 100 ..... 0110011 @r +sh3add 0010000 .......... 110 ..... 0110011 @r + +# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** +add_uw 0000100 .......... 000 ..... 0111011 @r +sh1add_uw 0010000 .......... 010 ..... 0111011 @r +sh2add_uw 0010000 .......... 100 ..... 0111011 @r +sh3add_uw 0010000 .......... 110 ..... 0111011 @r +slli_uw 00001 ............ 001 ..... 0011011 @sh + # *** RV32B Standard Extension *** clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 @@ -686,9 +698,6 @@ ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r -sh1add 0010000 .......... 010 ..... 0110011 @r -sh2add 0010000 .......... 100 ..... 0110011 @r -sh3add 0010000 .......... 110 ..... 0110011 @r =20 bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -717,10 +726,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sh1add_uw 0010000 .......... 010 ..... 0111011 @r -sh2add_uw 0010000 .......... 100 ..... 0111011 @r -sh3add_uw 0010000 .......... 110 ..... 0111011 @r -add_uw 0000100 .......... 000 ..... 0111011 @r =20 bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -731,4 +736,3 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 -slli_uw 00001. ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 9e81f6e3de..3cdd70a2b9 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,8 +1,9 @@ /* - * RISC-V translation routines for the RVB Standard Extension. + * RISC-V translation routines for the RVB draft and Zba Standard Extensio= n. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,6 +18,12 @@ * this program. If not, see . */ =20 +#define REQUIRE_ZBA(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \ + return false; \ + } \ +} while (0) + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); @@ -229,7 +236,7 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a) #define GEN_TRANS_SHADD(SHAMT) = \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ - REQUIRE_EXT(ctx, RVB); = \ + REQUIRE_ZBA(ctx); = \ return gen_arith(ctx, a, gen_sh##SHAMT##add); = \ } =20 @@ -403,7 +410,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, = \ arg_sh##SHAMT##add_uw *a) \ { \ REQUIRE_64BIT(ctx); \ - REQUIRE_EXT(ctx, RVB); \ + REQUIRE_ZBA(ctx); \ return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \ } =20 @@ -414,14 +421,14 @@ GEN_TRANS_SHADD_UW(3) static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); return gen_arith(ctx, a, gen_add_uw); } =20 static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); =20 TCGv source1 =3D tcg_temp_new(); gen_get_gpr(source1, a->rs1); --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629736976959946.1280147194392; Mon, 23 Aug 2021 09:42:56 -0700 (PDT) Received: from localhost ([::1]:54554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID2F-0000ec-Uk for importer@patchew.org; Mon, 23 Aug 2021 12:42:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0E-0006Dv-OS for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:50 -0400 Received: from mail-lf1-x12b.google.com ([2a00:1450:4864:20::12b]:45618) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0A-0006Im-Mo for qemu-devel@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+COX/Fn+nzsEGsVRznatLTqCCICkma7A3L/FrfzefDA=; b=GH0ueYc7RYyrTHRUFracv0jfVVUVH8tJ/1nC3lyhGEkBqzRkso8IXn6ZYDHzWbPrJW t1bAhMtXfIi5baEyq9lkQ8FVRa50dpvOToNG6yBsoykmvGvK+Z0EimS8Mj9f2t6W52hQ mqlGor5p/HoqnnP1xgnePnWmmwV/utenOglCkIsnGySjBU/mksO+I8DVkyQklAnpgHx3 MYwdErar/f7H6foH4uLYsepGWBI2wRZaWoibDyMlVfzriZBM6BH0mR9wbCriZIjR8dPS 0BE/kfeBg9UWoeHqb7wLvWV3/vm2ka6KOOM/lebPWYnZtLLqwFksHLtD/5G68aPiUyuU 8KFw== X-Gm-Message-State: AOAM532Na8EcIUWHwkpYfwyGZK8G40K5ys8d/EajB0d/e8NSZCOAwdBu 0zXZrNsumqcqDfgjVeXWhNP9H2/AOuM40fdl X-Google-Smtp-Source: ABdhPJzvhZUjQ0VLp7g7Hdhbtq0fD3Hq3Ivl0mWTxjqnpfl4117pV4ev2QY+Qa6WXCZUX7+gUCgazg== X-Received: by 2002:a05:6512:ba8:: with SMTP id b40mr17846946lfv.50.1629736844249; Mon, 23 Aug 2021 09:40:44 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Date: Mon, 23 Aug 2021 18:40:26 +0200 Message-Id: <20210823164038.2195113-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12b.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629736978794100005 Content-Type: text/plain; charset="utf-8" For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding space currently reserves a wider shamt-field (for use is a future RV128 ISA), setting the additional bit to 1 will not map to slli.uw for RV64 and needs to be treated as an illegal instruction. Note that this encoding being reserved for a future RV128 does not imply that no other instructions for RV64-only could be added in this encoding space in the future. As the implementation is separate from the gen_shifti helpers, we keep it that way and add the check for the shamt-width here. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Instead of defining a new decoding format, we treat slli.uw as if it had a 7bit-wide field for shamt (the 7th bit is reserved for RV128) and check for validity of the encoding in C code. target/riscv/insn_trans/trans_rvb.c.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 3cdd70a2b9..dcc7b6893d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -430,6 +430,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_= uw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBA(ctx); =20 + /* + * The shamt field is only 6 bits for RV64 (with the 7th bit + * remaining reserved for RV128). If the reserved bit is set + * on RV64, the encoding is illegal. + */ + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + TCGv source1 =3D tcg_temp_new(); gen_get_gpr(source1, a->rs1); =20 --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737177344677.3838773557195; Mon, 23 Aug 2021 09:46:17 -0700 (PDT) Received: from localhost ([::1]:34740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID5U-0006GM-BT for importer@patchew.org; Mon, 23 Aug 2021 12:46:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0F-0006EM-6x for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:51 -0400 Received: from mail-lj1-x22b.google.com ([2a00:1450:4864:20::22b]:37538) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0A-0006Jv-Ps for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:50 -0400 Received: by mail-lj1-x22b.google.com with SMTP id d16so32594021ljq.4 for ; Mon, 23 Aug 2021 09:40:46 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id z5sm1491671lfs.126.2021.08.23.09.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=44LsKWJBbQ5K9Od4Jq0DZvCIdFE+s8My6nfN58Xwxrc=; b=o847uwZG8SeLkHazg0r5rSwCZAAkY8Y4qiuUtFjaoJs1k7Ih49jvXr70U3gl1WxlcU Rw+uIa+zA4DaBn04ROxacLVzZxrZ/5iGjRQIV5WWzkt9L7A6glWtsaEtkggsUH4wftL1 2w8HfcG3lpJJ7p0ZHQGPlBGfiGMoKJcAyHIywe6buNh6LgHQh5ed2A+fpYQgEWrJFrtS 78ItUhYpJf5mm6ArPkGwmNvA9cLf258i5sX5VwkWYyUd3Bu42IL6sEC6tpHEwcibFYQ5 nywkPTxBQITNhoESHuRpz2nzyBhBM+dO2xwUK6Eu8GUytBU95pJzwkdAUkEhBOtCHceS w8Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=44LsKWJBbQ5K9Od4Jq0DZvCIdFE+s8My6nfN58Xwxrc=; b=NQo8gej8GhwQL0R0C3j/PfIeS3KbG2B5j57JF0pEbyg5B5wD3Zksveoh+P8CE3aO92 GXbfbNQtN+/LehY7fwVoFt8TxJpHVVXrU+DJ788wKlapJf+p0cCPK/alcBb0uKQSbQsj S/Um07aKsFgnRSKHQTj2hvW+qKSxI5X9bn93LrzCgq4PGvgBgVdco+JfX5XlQbNb5VXU dmfEmU76IMyopdC4YhheXeHGJJantSZWHD9O9y79AsLZaNGINOlgg4LfrmouUxtZSTqE mOPHPzsuZIO/RYKpIQIKrfdPf3vLkwrGDKdW4KeakGEDIHmPzqMfYk5D//ZJWZNEbZDM rvPA== X-Gm-Message-State: AOAM530+B5GFgNRpieEsYdYgZerue1UmYjsATvgIyrqRERSj7W686T52 ry+PjAqguFnYhxoQecQv7ap01UiFONgIfyv7 X-Google-Smtp-Source: ABdhPJyZ5NZzXnYdvTaHqpDsX2hKNhd/Xebhx7lDDiNAedwTmTvKQygq87Vhw/wMaBjS+XWy2qhfzA== X-Received: by 2002:a05:651c:481:: with SMTP id s1mr26848609ljc.446.1629736844996; Mon, 23 Aug 2021 09:40:44 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs Date: Mon, 23 Aug 2021 18:40:27 +0200 Message-Id: <20210823164038.2195113-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737178381100003 Content-Type: text/plain; charset="utf-8" Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extenstion and have not been present in the binutils patches circulating in January 2021. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Remove the W-form instructions from Zbs in a separate commit. target/riscv/insn32.decode | 7 ---- target/riscv/insn_trans/trans_rvb.c.inc | 49 ------------------------- 2 files changed, 56 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 68b163b72d..9abdbcb799 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -716,10 +716,6 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 =20 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -bsetw 0010100 .......... 001 ..... 0111011 @r -bclrw 0100100 .......... 001 ..... 0111011 @r -binvw 0110100 .......... 001 ..... 0111011 @r -bextw 0100100 .......... 101 ..... 0111011 @r slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r @@ -727,9 +723,6 @@ rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -bsetiw 0010100 .......... 001 ..... 0011011 @sh5 -bclriw 0100100 .......... 001 ..... 0011011 @sh5 -binviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index dcc7b6893d..975492d45c 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -279,55 +279,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw= *a) return gen_arith(ctx, a, gen_packuw); } =20 -static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bset); -} - -static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_bset); -} - -static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bclr); -} - -static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_bclr); -} - -static bool trans_binvw(DisasContext *ctx, arg_binvw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_binv); -} - -static bool trans_binviw(DisasContext *ctx, arg_binviw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_binv); -} - -static bool trans_bextw(DisasContext *ctx, arg_bextw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_bext); -} - static bool trans_slow(DisasContext *ctx, arg_slow *a) { REQUIRE_64BIT(ctx); --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737279733743.7248505948422; Mon, 23 Aug 2021 09:47:59 -0700 (PDT) Received: from localhost ([::1]:41270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID78-0002Jg-NZ for importer@patchew.org; Mon, 23 Aug 2021 12:47:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0F-0006EN-6W for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:51 -0400 Received: from mail-lj1-x230.google.com ([2a00:1450:4864:20::230]:38490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0B-0006KY-C4 for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:50 -0400 Received: by mail-lj1-x230.google.com with SMTP id c12so32617060ljr.5 for ; Mon, 23 Aug 2021 09:40:46 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id z5sm1491671lfs.126.2021.08.23.09.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gPhKrJMCI+/hHEYZKIRNImGP0IHRP8SO8bk5wT7Weu4=; b=oDa+b0aHsNNAUGrqWUnB+GBQ3EmWqrRkRQJV4Y7wX1eE7jGE2Z8D2XCeK3qP3ahV2W tPGWIRap3xq7TBQ2qdlJUO9gOYId9KrKnreHVe12TNJa/wLgsEW/GP7M0G7ho+7/2VgK 1iUVT5ctTWpGlR9oy9+EljxCom22EYPWsqXsTtcdAIUg3Cc4zU2CGlZnMJ8g/8h5vrps uDtrmPfnevZk6Dpgkj6clMbxsPqoY3z1mbLfI0cr4c6a+6KnJmilvShQtBgX3vH9Xr2H tY9Vv0zsFLLxcRO515cojTNlMdAbUybF/prAYYHpY1kdys6aRjU9tNO3AHw/zKwI9wvh rekw== X-Google-DKIM-Signature: v=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x230.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737280458100001 Content-Type: text/plain; charset="utf-8" The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Remove shift-one instructions in a separate commit. target/riscv/insn32.decode | 8 ---- target/riscv/insn_trans/trans_rvb.c.inc | 52 ------------------------- target/riscv/translate.c | 14 ------- 3 files changed, 74 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9abdbcb799..7e38477553 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -692,8 +692,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -703,8 +701,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -716,15 +712,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 =20 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 975492d45c..ac706349f5 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -162,30 +162,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *= a) return gen_shifti(ctx, a, gen_bext); } =20 -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_slo); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -279,34 +255,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw= *a) return gen_arith(ctx, a, gen_packuw); } =20 -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_sro); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6983be5723..fc22ae82d0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -595,20 +595,6 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } =20 -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - static bool gen_grevi(DisasContext *ctx, arg_grevi *a) { TCGv source1 =3D tcg_temp_new(); --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737052795689.0194292499609; Mon, 23 Aug 2021 09:44:12 -0700 (PDT) Received: from localhost ([::1]:57724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID3T-0002mG-Rk for importer@patchew.org; Mon, 23 Aug 2021 12:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0K-0006Js-F9 for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:56 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]:34624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0C-0006Ky-2D for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x133.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737054910100001 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and its use for qualifying the Zba instructions) are moved into a separate commit. target/riscv/insn32.decode | 17 +++++++++-------- target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++--------- 2 files changed, 24 insertions(+), 17 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7e38477553..1166e7f648 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -688,19 +688,11 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r -bset 0010100 .......... 001 ..... 0110011 @r -bclr 0100100 .......... 001 ..... 0110011 @r -binv 0110100 .......... 001 ..... 0110011 @r -bext 0100100 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r =20 -bseti 00101. ........... 001 ..... 0010011 @sh -bclri 01001. ........... 001 ..... 0010011 @sh -binvi 01101. ........... 001 ..... 0010011 @sh -bexti 01001. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -721,3 +713,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 +# *** RV32 Zbs Standard Extension *** +bclr 0100100 .......... 001 ..... 0110011 @r +bclri 01001. ........... 001 ..... 0010011 @sh +bext 0100100 .......... 101 ..... 0110011 @r +bexti 01001. ........... 101 ..... 0010011 @sh +binv 0110100 .......... 001 ..... 0110011 @r +binvi 01101. ........... 001 ..... 0010011 @sh +bset 0010100 .......... 001 ..... 0110011 @r +bseti 00101. ........... 001 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index ac706349f5..21d713df27 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the RVB draft and Zba Standard Extensio= n. + * RISC-V translation routines for the RVB draft Zb[as] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) =20 +#define REQUIRE_ZBS(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ + return false; \ + } \ +} while (0) + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); @@ -116,49 +122,49 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_= h *a) =20 static bool trans_bset(DisasContext *ctx, arg_bset *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, gen_bset); } =20 static bool trans_bseti(DisasContext *ctx, arg_bseti *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shifti(ctx, a, gen_bset); } =20 static bool trans_bclr(DisasContext *ctx, arg_bclr *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, gen_bclr); } =20 static bool trans_bclri(DisasContext *ctx, arg_bclri *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shifti(ctx, a, gen_bclr); } =20 static bool trans_binv(DisasContext *ctx, arg_binv *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, gen_binv); } =20 static bool trans_binvi(DisasContext *ctx, arg_binvi *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shifti(ctx, a, gen_binv); } =20 static bool trans_bext(DisasContext *ctx, arg_bext *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shift(ctx, a, gen_bext); } =20 static bool trans_bexti(DisasContext *ctx, arg_bexti *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBS(ctx); return gen_shifti(ctx, a, gen_bext); } =20 --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737176812346.4585787684025; Mon, 23 Aug 2021 09:46:16 -0700 (PDT) Received: from localhost ([::1]:34676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID5T-0006DI-Ip for importer@patchew.org; Mon, 23 Aug 2021 12:46:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0K-0006Jk-DD for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737178312100001 Content-Type: text/plain; charset="utf-8" The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich --- Changes in v3: - This adds the Zbc instructions as a spearate commit. - Uses a helper for clmul/clmulr instead of inlining the calculation of the result (addressing a comment from Richard Henderson). target/riscv/bitmanip_helper.c | 27 ++++++++++++++++++ target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 5 ++++ target/riscv/insn_trans/trans_rvb.c.inc | 37 ++++++++++++++++++++++++- 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 5b2f795d03..73be5a81c7 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -3,6 +3,7 @@ * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulon= g rs2) { return do_gorc(rs1, rs2, 32); } + +target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) +{ + target_ulong result =3D 0; + + for (int i =3D 0; i < TARGET_LONG_BITS; i++) { + if ((rs2 >> i) & 1) { + result ^=3D (rs1 << i); + } + } + + return result; +} + +target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) +{ + target_ulong result =3D 0; + + for (int i =3D 0; i < TARGET_LONG_BITS; i++) { + if ((rs2 >> i) & 1) { + result ^=3D (rs1 >> (TARGET_LONG_BITS - i - 1)); + } + } + + return result; +} diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 415e37bc37..c559c860a7 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Special functions */ DEF_HELPER_3(csrrw, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1166e7f648..04711111c8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -713,6 +713,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 +# *** RV32 Zbc Standard Extension *** +clmul 0000101 .......... 001 ..... 0110011 @r +clmulh 0000101 .......... 011 ..... 0110011 @r +clmulr 0000101 .......... 010 ..... 0110011 @r + # *** RV32 Zbs Standard Extension *** bclr 0100100 .......... 001 ..... 0110011 @r bclri 01001. ........... 001 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 21d713df27..92c31ea1e6 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the RVB draft Zb[as] Standard Extension. + * RISC-V translation routines for the Zb[acs] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) =20 +#define REQUIRE_ZBC(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZBS(ctx) do { \ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ return false; \ @@ -357,3 +363,32 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_= uw *a) tcg_temp_free(source1); return true; } + +static bool trans_clmul(DisasContext *ctx, arg_clmul *a) +{ + REQUIRE_ZBC(ctx); + return gen_arith(ctx, a, gen_helper_clmul); +} + +static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a) +{ + REQUIRE_ZBC(ctx); + + /* Perform a clmulr ... */ + gen_arith(ctx, a, gen_helper_clmulr); + + /* ... then shift the result 1 bit to the right. */ + TCGv dst =3D tcg_temp_new(); + gen_get_gpr(dst, a->rd); + tcg_gen_shri_tl(dst, dst, 1); + gen_set_gpr(a->rd, dst); + tcg_temp_free(dst); + + return true; +} + +static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a) +{ + REQUIRE_ZBC(ctx); + return gen_arith(ctx, a, gen_helper_clmulr); +} --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x131.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737282587100001 Content-Type: text/plain; charset="utf-8" This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - The changes to the Zbb instructions (i.e. use the REQUIRE_ZBB macro) are now in a separate commit. target/riscv/insn32.decode | 40 ++++++++++---------- target/riscv/insn_trans/trans_rvb.c.inc | 50 ++++++++++++++----------- 2 files changed, 49 insertions(+), 41 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 04711111c8..faa56836d8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -671,45 +671,47 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r sh3add_uw 0010000 .......... 110 ..... 0111011 @r slli_uw 00001 ............ 001 ..... 0011011 @sh =20 -# *** RV32B Standard Extension *** +# *** RV32 Zbb Standard Extension *** +andn 0100000 .......... 111 ..... 0110011 @r clz 011000 000000 ..... 001 ..... 0010011 @r2 -ctz 011000 000001 ..... 001 ..... 0010011 @r2 cpop 011000 000010 ..... 001 ..... 0010011 @r2 +ctz 011000 000001 ..... 001 ..... 0010011 @r2 +max 0000101 .......... 110 ..... 0110011 @r +maxu 0000101 .......... 111 ..... 0110011 @r +min 0000101 .......... 100 ..... 0110011 @r +minu 0000101 .......... 101 ..... 0110011 @r +orn 0100000 .......... 110 ..... 0110011 @r +rol 0110000 .......... 001 ..... 0110011 @r +ror 0110000 .......... 101 ..... 0110011 @r +rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 - -andn 0100000 .......... 111 ..... 0110011 @r -orn 0100000 .......... 110 ..... 0110011 @r xnor 0100000 .......... 100 ..... 0110011 @r + +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 +rolw 0110000 .......... 001 ..... 0111011 @r +roriw 0110000 .......... 101 ..... 0011011 @sh5 +rorw 0110000 .......... 101 ..... 0111011 @r + +# *** RV32B Standard Extension *** pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r -min 0000101 .......... 100 ..... 0110011 @r -minu 0000101 .......... 101 ..... 0110011 @r -max 0000101 .......... 110 ..... 0110011 @r -maxu 0000101 .......... 111 ..... 0110011 @r -ror 0110000 .......... 101 ..... 0110011 @r -rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r =20 -rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** -clzw 0110000 00000 ..... 001 ..... 0011011 @r2 -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 - packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -rorw 0110000 .......... 101 ..... 0111011 @r -rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r =20 -roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 92c31ea1e6..0aa7e9abf7 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zb[acs] Standard Extension. + * RISC-V translation routines for the Zb[abcs] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) =20 +#define REQUIRE_ZBB(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZBC(ctx) do { \ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ return false; \ @@ -38,37 +44,37 @@ =20 static bool trans_clz(DisasContext *ctx, arg_clz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_clz); } =20 static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_ctz); } =20 static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ctpop_tl); } =20 static bool trans_andn(DisasContext *ctx, arg_andn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_andc_tl); } =20 static bool trans_orn(DisasContext *ctx, arg_orn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_orc_tl); } =20 static bool trans_xnor(DisasContext *ctx, arg_xnor *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_eqv_tl); } =20 @@ -92,37 +98,37 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a) =20 static bool trans_min(DisasContext *ctx, arg_min *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_smin_tl); } =20 static bool trans_max(DisasContext *ctx, arg_max *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_smax_tl); } =20 static bool trans_minu(DisasContext *ctx, arg_minu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_umin_tl); } =20 static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_umax_tl); } =20 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ext8s_tl); } =20 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ext16s_tl); } =20 @@ -176,19 +182,19 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti = *a) =20 static bool trans_ror(DisasContext *ctx, arg_ror *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, tcg_gen_rotr_tl); } =20 static bool trans_rori(DisasContext *ctx, arg_rori *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shifti(ctx, a, tcg_gen_rotr_tl); } =20 static bool trans_rol(DisasContext *ctx, arg_rol *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, tcg_gen_rotl_tl); } =20 @@ -235,21 +241,21 @@ GEN_TRANS_SHADD(3) static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_clzw); } =20 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_ctzw); } =20 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_cpopw); } =20 @@ -270,21 +276,21 @@ static bool trans_packuw(DisasContext *ctx, arg_packu= w *a) static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftw(ctx, a, gen_rorw); } =20 static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftiw(ctx, a, gen_rorw); } =20 static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftw(ctx, a, gen_rolw); } =20 --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162973755108656.52933425749666; Mon, 23 Aug 2021 09:52:31 -0700 (PDT) Received: from localhost ([::1]:54430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIDBW-0002sX-1j for importer@patchew.org; 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Mon, 23 Aug 2021 09:40:48 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Date: Mon, 23 Aug 2021 18:40:32 +0200 Message-Id: <20210823164038.2195113-10-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737553279100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich Change orc.b to implementation suggested by Richard Henderson Reviewed-by: Richard Henderson --- Changes in v3: - Moved orc.b and gorc/gorci changes into separate commit. - Using the simpler orc.b implementation suggested by Richard Henderson target/riscv/bitmanip_helper.c | 26 ------------------ target/riscv/helper.h | 2 -- target/riscv/insn32.decode | 6 +---- target/riscv/insn_trans/trans_rvb.c.inc | 35 +++++++++++-------------- target/riscv/translate.c | 6 ----- 5 files changed, 16 insertions(+), 59 deletions(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 73be5a81c7..bb48388fcd 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -64,32 +64,6 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulon= g rs2) return do_grev(rs1, rs2, 32); } =20 -static target_ulong do_gorc(target_ulong rs1, - target_ulong rs2, - int bits) -{ - target_ulong x =3D rs1; - int i, shift; - - for (i =3D 0, shift =3D 1; shift < bits; i++, shift <<=3D 1) { - if (rs2 & shift) { - x |=3D do_swap(x, adjacent_masks[i], shift); - } - } - - return x; -} - -target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2) -{ - return do_gorc(rs1, rs2, TARGET_LONG_BITS); -} - -target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2) -{ - return do_gorc(rs1, rs2, 32); -} - target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) { target_ulong result =3D 0; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c559c860a7..80561e8866 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -61,8 +61,6 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) /* Bitmanip */ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index faa56836d8..8bcb602455 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -680,6 +680,7 @@ max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r +orc_b 001010 000111 ..... 101 ..... 0010011 @r2 orn 0100000 .......... 110 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r @@ -701,19 +702,14 @@ pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r -gorc 0010100 .......... 101 ..... 0110011 @r - grevi 01101. ........... 101 ..... 0010011 @sh -gorci 00101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r -gorcw 0010100 .......... 101 ..... 0111011 @r =20 greviw 0110100 .......... 101 ..... 0011011 @sh5 -gorciw 0010100 .......... 101 ..... 0011011 @sh5 =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 0aa7e9abf7..4271dc4f2f 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -215,18 +215,27 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi = *a) return gen_grevi(ctx, a); } =20 -static bool trans_gorc(DisasContext *ctx, arg_gorc *a) +static void gen_orc_b(TCGv ret, TCGv source1) { - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_helper_gorc); + TCGv tmp =3D tcg_temp_new(); + + /* Set msb in each byte if the byte was zero. */ + tcg_gen_subi_tl(tmp, source1, dup_const(MO_8, 0x01)); + tcg_gen_andc_tl(tmp, tmp, source1); + tcg_gen_andi_tl(tmp, tmp, dup_const(MO_8, 0x80)); + + /* Replicate the msb of each byte across the byte. */ + tcg_gen_shri_tl(tmp, tmp, 7); + tcg_gen_muli_tl(ret, tmp, 0xff); } =20 -static bool trans_gorci(DisasContext *ctx, arg_gorci *a) +static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a) { - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_helper_gorc); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &gen_orc_b); } =20 + #define GEN_TRANS_SHADD(SHAMT) = \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ { = \ @@ -308,20 +317,6 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw= *a) return gen_shiftiw(ctx, a, gen_grevw); } =20 -static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_gorcw); -} - -static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_gorcw); -} - #define GEN_TRANS_SHADD_UW(SHAMT) \ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ arg_sh##SHAMT##add_uw *a) \ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fc22ae82d0..5c099ff007 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -710,12 +710,6 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) gen_helper_grev(ret, arg1, arg2); } =20 -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_gorcw(ret, arg1, arg2); -} - #define GEN_SHADD_UW(SHAMT) \ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ { \ --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x130.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737227452100001 Content-Type: text/plain; charset="utf-8" With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Moved the REQUIRE_32BIT macro into a separate commit. target/riscv/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5c099ff007..aabdd44663 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -417,6 +417,12 @@ EX_SH(12) } \ } while (0) =20 +#define REQUIRE_32BIT(ctx) do { \ + if (!is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_64BIT(ctx) do { \ if (is_32bit(ctx)) { \ return false; \ --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737393511733.452065838201; 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Mon, 23 Aug 2021 09:40:50 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi Date: Mon, 23 Aug 2021 18:40:34 +0200 Message-Id: <20210823164038.2195113-12-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x135.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737394111100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - rev8-addition & grevi*-removal moved to a separate commit target/riscv/bitmanip_helper.c | 40 ------------------------- target/riscv/helper.h | 2 -- target/riscv/insn32.decode | 10 +++---- target/riscv/insn_trans/trans_rvb.c.inc | 31 +++++-------------- target/riscv/translate.c | 28 ----------------- 5 files changed, 12 insertions(+), 99 deletions(-) diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index bb48388fcd..f1b5e5549f 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -24,46 +24,6 @@ #include "exec/helper-proto.h" #include "tcg/tcg.h" =20 -static const uint64_t adjacent_masks[] =3D { - dup_const(MO_8, 0x55), - dup_const(MO_8, 0x33), - dup_const(MO_8, 0x0f), - dup_const(MO_16, 0xff), - dup_const(MO_32, 0xffff), - UINT32_MAX -}; - -static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shif= t) -{ - return ((x & mask) << shift) | ((x & ~mask) >> shift); -} - -static target_ulong do_grev(target_ulong rs1, - target_ulong rs2, - int bits) -{ - target_ulong x =3D rs1; - int i, shift; - - for (i =3D 0, shift =3D 1; shift < bits; i++, shift <<=3D 1) { - if (rs2 & shift) { - x =3D do_swap(x, adjacent_masks[i], shift); - } - } - - return x; -} - -target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2) -{ - return do_grev(rs1, rs2, TARGET_LONG_BITS); -} - -target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2) -{ - return do_grev(rs1, rs2, 32); -} - target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) { target_ulong result =3D 0; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 80561e8866..ae2e94542c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -59,8 +59,6 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, = tl) DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) =20 /* Bitmanip */ -DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8bcb602455..72b73c6df2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -682,6 +682,7 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r orc_b 001010 000111 ..... 101 ..... 0010011 @r2 orn 0100000 .......... 110 ..... 0110011 @r +rev8 011010 011000 ..... 101 ..... 0010011 @r2 rol 0110000 .......... 001 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rori 01100 ............ 101 ..... 0010011 @sh @@ -693,6 +694,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 +# The encoding for rev8 differs between RV32 and RV64. +# When executing on RV64, the encoding used in RV32 is an illegal +# instruction, so we use different handler functions to differentiate. +rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 rolw 0110000 .......... 001 ..... 0111011 @r roriw 0110000 .......... 101 ..... 0011011 @sh5 rorw 0110000 .......... 101 ..... 0111011 @r @@ -701,15 +706,10 @@ rorw 0110000 .......... 101 ..... 0111011 @r pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r -grev 0110100 .......... 101 ..... 0110011 @r -grevi 01101. ........... 101 ..... 0010011 @sh =20 # *** RV64B Standard Extension (in addition to RV32B) *** packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -grevw 0110100 .......... 101 ..... 0111011 @r - -greviw 0110100 .......... 101 ..... 0011011 @sh5 =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 4271dc4f2f..9f567cd69e 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -198,21 +198,11 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, tcg_gen_rotl_tl); } =20 -static bool trans_grev(DisasContext *ctx, arg_grev *a) +static bool trans_rev8(DisasContext *ctx, arg_rev8 *a) { - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_helper_grev); -} - -static bool trans_grevi(DisasContext *ctx, arg_grevi *a) -{ - REQUIRE_EXT(ctx, RVB); - - if (a->shamt >=3D TARGET_LONG_BITS) { - return false; - } - - return gen_grevi(ctx, a); + REQUIRE_32BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_bswap_tl); } =20 static void gen_orc_b(TCGv ret, TCGv source1) @@ -303,18 +293,11 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) return gen_shiftw(ctx, a, gen_rolw); } =20 -static bool trans_grevw(DisasContext *ctx, arg_grevw *a) +static bool trans_rev8_64(DisasContext *ctx, arg_rev8 *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_grevw); -} - -static bool trans_greviw(DisasContext *ctx, arg_greviw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_grevw); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_bswap_tl); } =20 #define GEN_TRANS_SHADD_UW(SHAMT) \ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index aabdd44663..f16ac8bb1a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -601,28 +601,6 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } =20 -static bool gen_grevi(DisasContext *ctx, arg_grevi *a) -{ - TCGv source1 =3D tcg_temp_new(); - TCGv source2; - - gen_get_gpr(source1, a->rs1); - - if (a->shamt =3D=3D (TARGET_LONG_BITS - 8)) { - /* rev8, byte swaps */ - tcg_gen_bswap_tl(source1, source1); - } else { - source2 =3D tcg_temp_new(); - tcg_gen_movi_tl(source2, a->shamt); - gen_helper_grev(source1, source1, source2); - tcg_temp_free(source2); - } - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - return true; -} - #define GEN_SHADD(SHAMT) \ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ { \ @@ -710,12 +688,6 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free_i32(t2); } =20 -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_ext32u_tl(arg1, arg1); - gen_helper_grev(ret, arg1, arg2); -} - #define GEN_SHADD_UW(SHAMT) \ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ { \ --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737327873211.59430697642745; Mon, 23 Aug 2021 09:48:47 -0700 (PDT) Received: from localhost ([::1]:43834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID7u-000451-QO for importer@patchew.org; Mon, 23 Aug 2021 12:48:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0N-0006U8-5m for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737329673100001 Content-Type: text/plain; charset="utf-8" The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Moved zext.h-addition & pack*-removal to a separate commit. target/riscv/insn32.decode | 10 +++--- target/riscv/insn_trans/trans_rvb.c.inc | 45 +++++++------------------ target/riscv/translate.c | 40 ---------------------- 3 files changed, 18 insertions(+), 77 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 72b73c6df2..0fd5afc289 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -689,6 +689,7 @@ rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 xnor 0100000 .......... 100 ..... 0110011 @r +zext_h 0000100 00000 ..... 100 ..... 0110011 @r2 =20 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -701,15 +702,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 rolw 0110000 .......... 001 ..... 0111011 @r roriw 0110000 .......... 101 ..... 0011011 @sh5 rorw 0110000 .......... 101 ..... 0111011 @r +# The encoding for zext.h differs between RV32 and RV64. +# When executing on RV64, the encoding used in RV32 is an illegal +# instruction, so we use different handler functions to differentiate. +zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 =20 # *** RV32B Standard Extension *** -pack 0000100 .......... 100 ..... 0110011 @r -packu 0100100 .......... 100 ..... 0110011 @r -packh 0000100 .......... 111 ..... 0110011 @r =20 # *** RV64B Standard Extension (in addition to RV32B) *** -packw 0000100 .......... 100 ..... 0111011 @r -packuw 0100100 .......... 100 ..... 0111011 @r =20 # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 9f567cd69e..b134abd263 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -78,24 +78,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) return gen_arith(ctx, a, tcg_gen_eqv_tl); } =20 -static bool trans_pack(DisasContext *ctx, arg_pack *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); -} - -static bool trans_packu(DisasContext *ctx, arg_packu *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); -} - -static bool trans_packh(DisasContext *ctx, arg_packh *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); -} - static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_ZBB(ctx); @@ -225,6 +207,12 @@ static bool trans_orc_b(DisasContext *ctx, arg_orc_b *= a) return gen_unary(ctx, a, &gen_orc_b); } =20 +static bool trans_zext_h(DisasContext *ctx, arg_sext_h *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_ext16u_tl); +} =20 #define GEN_TRANS_SHADD(SHAMT) = \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a)= \ @@ -258,20 +246,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *= a) return gen_unary(ctx, a, gen_cpopw); } =20 -static bool trans_packw(DisasContext *ctx, arg_packw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packw); -} - -static bool trans_packuw(DisasContext *ctx, arg_packuw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packuw); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -348,6 +322,13 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_= uw *a) return true; } =20 +static bool trans_zext_h_64(DisasContext *ctx, arg_sext_h *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_ext16u_tl); +} + static bool trans_clmul(DisasContext *ctx, arg_clmul *a) { REQUIRE_ZBC(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f16ac8bb1a..639f34b8f6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -536,29 +536,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r = *a, return true; } =20 -static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_deposit_tl(ret, arg1, arg2, - TARGET_LONG_BITS / 2, - TARGET_LONG_BITS / 2); -} - -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); - tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); - tcg_temp_free(t); -} - -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext8u_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); - tcg_temp_free(t); -} - static void gen_sbop_mask(TCGv ret, TCGv shamt) { tcg_gen_movi_tl(ret, 1); @@ -635,23 +612,6 @@ static void gen_cpopw(TCGv ret, TCGv arg1) tcg_gen_ctpop_tl(ret, arg1); } =20 -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_ext16s_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 16, 48); - tcg_temp_free(t); -} - -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t =3D tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, 16); - tcg_gen_deposit_tl(ret, arg2, t, 0, 16); - tcg_gen_ext32s_tl(ret, ret); - tcg_temp_free(t); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 =3D tcg_temp_new_i32(); --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737589620400.1877731470703; Mon, 23 Aug 2021 09:53:09 -0700 (PDT) Received: from localhost ([::1]:56916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIDC7-0004Xh-Rt for importer@patchew.org; Mon, 23 Aug 2021 12:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0O-0006b1-TI for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:41:00 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]:36511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0K-0006Om-7N for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x132.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737591175100001 Content-Type: text/plain; charset="utf-8" With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/message/532 Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Removing RVB moved into a separate commit at the tail-end of the series. target/riscv/cpu.c | 27 --------------------------- target/riscv/cpu.h | 3 --- target/riscv/insn32.decode | 4 ---- 3 files changed, 34 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c7bc1f9f44..93bd8f7802 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_bext_version(CPURISCVState *env, int bext_ver) -{ - env->bext_ver =3D bext_ver; -} - static void set_vext_version(CPURISCVState *env, int vext_ver) { env->vext_ver =3D vext_ver; @@ -393,7 +388,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); int priv_version =3D PRIV_VERSION_1_11_0; - int bext_version =3D BEXT_VERSION_0_93_0; int vext_version =3D VEXT_VERSION_0_07_1; target_ulong target_misa =3D env->misa; Error *local_err =3D NULL; @@ -418,7 +412,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 set_priv_version(env, priv_version); - set_bext_version(env, bext_version); set_vext_version(env, vext_version); =20 if (cpu->cfg.mmu) { @@ -496,24 +489,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_h) { target_misa |=3D RVH; } - if (cpu->cfg.ext_b) { - target_misa |=3D RVB; - - if (cpu->cfg.bext_spec) { - if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) { - bext_version =3D BEXT_VERSION_0_93_0; - } else { - error_setg(errp, - "Unsupported bitmanip spec version '%s'", - cpu->cfg.bext_spec); - return; - } - } else { - qemu_log("bitmanip version is not specified, " - "use the default value v0.93\n"); - } - set_bext_version(env, bext_version); - } if (cpu->cfg.ext_v) { target_misa |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -584,7 +559,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), @@ -595,7 +569,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4cd8ea89..77e8b06106 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,7 +67,6 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVB RV('B') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -83,7 +82,6 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 -#define BEXT_VERSION_0_93_0 0x00009300 #define VEXT_VERSION_0_07_1 0x00000701 =20 enum { @@ -288,7 +286,6 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; - bool ext_b; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0fd5afc289..7f29b779b6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -707,10 +707,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r # instruction, so we use different handler functions to differentiate. zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 =20 -# *** RV32B Standard Extension *** - -# *** RV64B Standard Extension (in addition to RV32B) *** - # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r clmulh 0000101 .......... 011 ..... 0110011 @r --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629737546202611.2083251976677; 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Mon, 23 Aug 2021 09:40:52 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec Date: Mon, 23 Aug 2021 18:40:37 +0200 Message-Id: <20210823164038.2195113-15-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737546723100001 Content-Type: text/plain; charset="utf-8" The slli.uw instruction is defined as X(rd) =3D (EXTZ(X(rs)[31..0]) << shamt); This rewrites its implementation to directly match this, allowing for the small optimisation of not emitting the zero-extension if the immediate shift is greater than 32. Signed-off-by: Philipp Tomsich --- (no changes since v1) target/riscv/insn_trans/trans_rvb.c.inc | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index b134abd263..3419dcf1bb 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -308,17 +308,14 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli= _uw *a) return false; } =20 - TCGv source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - + TCGv source =3D tcg_temp_new(); + gen_get_gpr(source, a->rs1); if (a->shamt < 32) { - tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); - } else { - tcg_gen_shli_tl(source1, source1, a->shamt); + tcg_gen_ext32u_tl(source, source); } - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); + tcg_gen_shli_tl(source, source, a->shamt); + gen_set_gpr(a->rd, source); + tcg_temp_free(source); return true; } =20 --=20 2.25.1 From nobody Mon Apr 29 03:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=6gA6AgzFN/LynHfv17xwUKOcMNg7N+0ObrNPFIAHP2Q=; b=tJEWOO1Sm4aXE9i7U+rjblNwcoq5dhnJgmiRGG1zk53+rjV/czpcp4xYl38lpPOGI4 WaWAZib6YL9+fXejF6mWYc/h/09kI1ibjOCyEJd4i40ox5viWTh489ADF0IgKIy5CCUZ 3OGKbKze7LV6i7oKCsR1FHoGX898oCkJolUz83slp7xjt+1eYnQz6Qz8MCRe3E3b8NDO 9ToRu73wrLCQbUAb08ekbe90h/i3WtXAaDVdXShKBRuvTwDacqQgE/uCBtNgyw1T8tSS BVrg3lim1i/5JAsdmYUbREvDwQdaQVqTpARjbtSEi8Le4wnZH98Y5GFtfJEQNis/H3v0 934g== X-Gm-Message-State: AOAM530xeF+yXoM7X678gPzzyfspmHzgAiBICFJC6P72sE+LA2yQu+1/ PBLtQz0cmfxyYd4BoopJ8GS4db/fLbNa6w87 X-Google-Smtp-Source: ABdhPJx/OfAZLEr+FAoAyFd/s4tow4F4vMgSILQOFS1btvX2kTfZnxXpxkpRPCUNe/mPh90Rumzl2Q== X-Received: by 2002:a05:651c:94:: with SMTP id 20mr29132777ljq.164.1629736853035; Mon, 23 Aug 2021 09:40:53 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 15/15] disas/riscv: Add Zb[abcs] instructions Date: Mon, 23 Aug 2021 18:40:38 +0200 Message-Id: <20210823164038.2195113-16-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x235.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629737444886100001 Content-Type: text/plain; charset="utf-8" With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich --- (no changes since v2) Changes in v2: - Fix missing ';' from last-minute whitespace cleanups. disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 278d9be924..793ad14c27 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -478,6 +478,49 @@ typedef enum { rv_op_fsflags =3D 316, rv_op_fsrmi =3D 317, rv_op_fsflagsi =3D 318, + rv_op_bseti =3D 319, + rv_op_bclri =3D 320, + rv_op_binvi =3D 321, + rv_op_bexti =3D 322, + rv_op_rori =3D 323, + rv_op_clz =3D 324, + rv_op_ctz =3D 325, + rv_op_cpop =3D 326, + rv_op_sext_h =3D 327, + rv_op_sext_b =3D 328, + rv_op_xnor =3D 329, + rv_op_orn =3D 330, + rv_op_andn =3D 331, + rv_op_rol =3D 332, + rv_op_ror =3D 333, + rv_op_sh1add =3D 334, + rv_op_sh2add =3D 335, + rv_op_sh3add =3D 336, + rv_op_sh1add_uw =3D 337, + rv_op_sh2add_uw =3D 338, + rv_op_sh3add_uw =3D 339, + rv_op_clmul =3D 340, + rv_op_clmulr =3D 341, + rv_op_clmulh =3D 342, + rv_op_min =3D 343, + rv_op_minu =3D 344, + rv_op_max =3D 345, + rv_op_maxu =3D 346, + rv_op_clzw =3D 347, + rv_op_ctzw =3D 348, + rv_op_cpopw =3D 349, + rv_op_slli_uw =3D 350, + rv_op_add_uw =3D 351, + rv_op_rolw =3D 352, + rv_op_rorw =3D 353, + rv_op_rev8 =3D 354, + rv_op_zext_h =3D 355, + rv_op_roriw =3D 356, + rv_op_orc_b =3D 357, + rv_op_bset =3D 358, + rv_op_bclr =3D 359, + rv_op_binv =3D 360, + rv_op_bext =3D 361, } rv_op; =20 /* structures */ @@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] =3D { { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, + { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 0: op =3D rv_op_addi; break; case 1: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_slli; break; + case 0b00000: op =3D rv_op_slli; break; + case 0b00101: op =3D rv_op_bseti; break; + case 0b01001: op =3D rv_op_bclri; break; + case 0b01101: op =3D rv_op_binvi; break; + case 0b01100: + switch (((inst >> 20) & 0b1111111)) { + case 0b0000000: op =3D rv_op_clz; break; + case 0b0000001: op =3D rv_op_ctz; break; + case 0b0000010: op =3D rv_op_cpop; break; + /* 0b0000011 */ + case 0b0000100: op =3D rv_op_sext_b; break; + case 0b0000101: op =3D rv_op_sext_h; break; + } + break; } break; case 2: op =3D rv_op_slti; break; @@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 4: op =3D rv_op_xori; break; case 5: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_srli; break; - case 8: op =3D rv_op_srai; break; + case 0b00000: op =3D rv_op_srli; break; + case 0b00101: op =3D rv_op_orc_b; break; + case 0b01000: op =3D rv_op_srai; break; + case 0b01001: op =3D rv_op_bexti; break; + case 0b01100: op =3D rv_op_rori; break; + case 0b01101: + switch ((inst >> 20) & 0b1111111) { + case 0b0111000: op =3D rv_op_rev8; break; + } + break; } break; case 6: op =3D rv_op_ori; break; @@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) case 1: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_slliw; break; + case 4: op =3D rv_op_slli_uw; break; + case 48: + switch ((inst >> 20) & 0b11111) { + case 0b00000: op =3D rv_op_clzw; break; + case 0b00001: op =3D rv_op_ctzw; break; + case 0b00010: op =3D rv_op_cpopw; break; + } + break; } break; case 5: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_srliw; break; case 32: op =3D rv_op_sraiw; break; + case 48: op =3D rv_op_roriw; break; } break; } @@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divu; break; case 14: op =3D rv_op_rem; break; case 15: op =3D rv_op_remu; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 41: op =3D rv_op_clmul; break; + case 42: op =3D rv_op_clmulr; break; + case 43: op =3D rv_op_clmulh; break; + case 44: op =3D rv_op_min; break; + case 45: op =3D rv_op_minu; break; + case 46: op =3D rv_op_max; break; + case 47: op =3D rv_op_maxu; break; + case 130: op =3D rv_op_sh1add; break; + case 132: op =3D rv_op_sh2add; break; + case 134: op =3D rv_op_sh3add; break; + case 161: op =3D rv_op_bset; break; case 256: op =3D rv_op_sub; break; + case 260: op =3D rv_op_xnor; break; case 261: op =3D rv_op_sra; break; + case 262: op =3D rv_op_orn; break; + case 263: op =3D rv_op_andn; break; + case 289: op =3D rv_op_bclr; break; + case 293: op =3D rv_op_bext; break; + case 385: op =3D rv_op_rol; break; + case 386: op =3D rv_op_ror; break; + case 417: op =3D rv_op_binv; break; } break; case 13: op =3D rv_op_lui; break; @@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divuw; break; case 14: op =3D rv_op_remw; break; case 15: op =3D rv_op_remuw; break; + case 32: op =3D rv_op_add_uw; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 130: op =3D rv_op_sh1add_uw; break; + case 132: op =3D rv_op_sh2add_uw; break; + case 134: op =3D rv_op_sh3add_uw; break; case 256: op =3D rv_op_subw; break; case 261: op =3D rv_op_sraw; break; + case 385: op =3D rv_op_rolw; break; + case 389: op =3D rv_op_rorw; break; } break; case 16: --=20 2.25.1