From nobody Wed Feb 11 01:00:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629481724390547.8975406561632; Fri, 20 Aug 2021 10:48:44 -0700 (PDT) Received: from localhost ([::1]:36778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mH8dH-00062Z-9q for importer@patchew.org; Fri, 20 Aug 2021 13:48:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mH8Y7-0005TK-FW for qemu-devel@nongnu.org; Fri, 20 Aug 2021 13:43:23 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:45880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mH8Xv-0003pE-Uq for qemu-devel@nongnu.org; Fri, 20 Aug 2021 13:43:23 -0400 Received: by mail-pg1-x535.google.com with SMTP id n18so9888639pgm.12 for ; Fri, 20 Aug 2021 10:43:09 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id l2sm7304142pfc.157.2021.08.20.10.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Aug 2021 10:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Pf4TdST1CnK+75+r+uXrqPGEkixRdiO4H07DkQ8XIEM=; b=cVAxia9MOnw2Arqko85iR+SdqqLAZDDTHUX2kWbwzqQNi3MUcTRp1goN2JfyrAAJxZ Qx1lwH4FDD/DtbCPz5FhlqdHxeejdMli+kVGavx29/f9aYCUYTqlPXCicl50nykk71A9 Y3iWiB31qelYjt1D9tK7BlYOF5oGuwgfbFWuLfFP+p+DjqUBKpHZ5nhnCaz5b+4/lEZC TvBn+ZhkFKGppICnG74JjXmNOEh4WSlpmirGBCHNHVVxBVEz7tISxNDGaAsSh0aCGFdx +g9odk4wIKWwPv6w6O8NGSOlSk2Om+mHac3T2KLul5BiNPj/7L6a/w7MGD7bcC/otddD 3g+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pf4TdST1CnK+75+r+uXrqPGEkixRdiO4H07DkQ8XIEM=; b=QHgGERTK5CQAMT8gG9KDNrK1lA4ETjJgAkkettxl8n6Qj0rXzyx92Xkd52i04J0GWY fhm/ydovLdZRNouC8H53zK0jxDcjytsUX2gq4Kx/8tuY7JLw/gLMXFXIu5Amg5pcs+0s XGm4sS6yDyycjt/u4pAoh8SoEA7aVYIycD/BKKN35ZIhnqCHv+qHd7Wa2io9hvP2gR+D yJ1UeqqJgcHKWl3vJWq5nXvS4Or/1Y+mENDy8PTYthhywlJoh1Ssdo9T7K37SNByf00h 45zg21DrFwSO02he6t/9sZGm464UJ69HEjunItM6KSE+Rv8DbXino9YI4VpWBx9gHINL eBZw== X-Gm-Message-State: AOAM533Tx9kITzWbzgJqhpHTGR7TFssc+VxF7/XvdduCgK3n9NI3sD9X zfLZnarb9EU6O5Bc6kHCJEV9VmuIiTrtJg== X-Google-Smtp-Source: ABdhPJyhs6VXSlvcuZGRk3zxNXyva/PXIZlqm0AEdrZu8Ex1tQVbokPYX9zlgvSTzmr3xT7ELbiH1A== X-Received: by 2002:a63:1b45:: with SMTP id b5mr19833126pgm.302.1629481389012; Fri, 20 Aug 2021 10:43:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers Date: Fri, 20 Aug 2021 07:42:41 -1000 Message-Id: <20210820174257.548286-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210820174257.548286-1-richard.henderson@linaro.org> References: <20210820174257.548286-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629481726160100001 Content-Type: text/plain; charset="utf-8" Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 101 ++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 18 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce4c56c179..d7552dc377 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -39,15 +39,25 @@ static TCGv load_val; =20 #include "exec/gen-icount.h" =20 +/* + * If an operation is being performed on less than TARGET_LONG_BITS, + * it may require the inputs to be sign- or zero-extended; which will + * depend on the exact operation being performed. + */ +typedef enum { + EXT_NONE, + EXT_SIGN, + EXT_ZERO, +} DisasExtend; + typedef struct DisasContext { DisasContextBase base; /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - bool virt_enabled; + target_ulong misa; uint32_t opcode; uint32_t mstatus_fs; - target_ulong misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -55,6 +65,8 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + bool w; + bool virt_enabled; bool ext_ifencei; bool hlsx; /* vector extension */ @@ -64,7 +76,11 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + uint8_t ntemp; CPUState *cs; + TCGv zero; + /* Space for 3 operands plus 1 extra for address computation. */ + TCGv temp[4]; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -172,27 +188,64 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) } } =20 -/* Wrapper for getting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated +/* + * Wrappers for getting reg values. + * + * The $zero register does not have cpu_gpr[0] allocated -- we supply the + * constant zero as a source, and an uninitialized sink as destination. + * + * Further, we may provide an extension for word operations. */ -static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) +static TCGv temp_new(DisasContext *ctx) { - if (reg_num =3D=3D 0) { - tcg_gen_movi_tl(t, 0); - } else { - tcg_gen_mov_tl(t, cpu_gpr[reg_num]); - } + assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); + return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); } =20 -/* Wrapper for setting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated. this is more for safety purposes, - * since we usually avoid calling the OP_TYPE_gen function if we see a wri= te to - * $zero - */ -static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t) +static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) { - if (reg_num_dst !=3D 0) { - tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); + TCGv t; + + if (reg_num =3D=3D 0) { + return ctx->zero; + } + + switch (ctx->w ? ext : EXT_NONE) { + case EXT_NONE: + return cpu_gpr[reg_num]; + case EXT_SIGN: + t =3D temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t =3D temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + } + g_assert_not_reached(); +} + +static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) +{ + tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE)); +} + +static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_nu= m) +{ + if (reg_num =3D=3D 0 || ctx->w) { + return temp_new(ctx); + } + return cpu_gpr[reg_num]; +} + +static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) +{ + if (reg_num !=3D 0) { + if (ctx->w) { + tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); + } else { + tcg_gen_mov_tl(cpu_gpr[reg_num], t); + } } } =20 @@ -940,6 +993,11 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs =3D cs; + ctx->w =3D false; + ctx->ntemp =3D 0; + memset(ctx->temp, 0, sizeof(ctx->temp)); + + ctx->zero =3D tcg_constant_tl(0); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -961,6 +1019,13 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; + ctx->w =3D false; + + for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) { + tcg_temp_free(ctx->temp[i]); + ctx->temp[i] =3D NULL; + } + ctx->ntemp =3D 0; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { target_ulong page_start; --=20 2.25.1