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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629482733257100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Bin Meng Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 125 ++++++++++++------------ 1 file changed, 60 insertions(+), 65 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 11b9b3f90b..db9ae15755 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -20,30 +20,40 @@ =20 static bool trans_fld(DisasContext *ctx, arg_fld *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } =20 static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { + TCGv addr; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); + addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp =3D temp_new(ctx); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); =20 - tcg_temp_free(t0); return true; } =20 @@ -252,11 +262,10 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -265,11 +274,10 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -278,11 +286,10 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d = *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -291,10 +298,10 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fcl= ass_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); + + gen_helper_fclass_d(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -303,12 +310,11 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcv= t_w_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -317,12 +323,11 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fc= vt_wu_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + TCGv dest =3D dest_gpr(ctx, a->rd); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -331,12 +336,10 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcv= t_d_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); return true; @@ -347,12 +350,10 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fc= vt_d_wu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src); =20 mark_fs_dirty(ctx); return true; @@ -364,11 +365,11 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcv= t_l_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -378,11 +379,11 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D dest_gpr(ctx, a->rd); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(ctx, a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); return true; } =20 @@ -406,12 +407,11 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcv= t_d_l *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src); + mark_fs_dirty(ctx); return true; } @@ -422,12 +422,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fc= vt_d_lu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); + TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src); + mark_fs_dirty(ctx); return true; } @@ -439,11 +438,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d= _x *a) REQUIRE_EXT(ctx, RVD); =20 #ifdef TARGET_RISCV64 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(ctx, t0, a->rs1); - - tcg_gen_mov_tl(cpu_fpr[a->rd], t0); - tcg_temp_free(t0); + tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE)); mark_fs_dirty(ctx); return true; #else --=20 2.25.1