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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322852403100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b20c313615..2f55b94ada 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -563,7 +563,7 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t offs= et) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int = rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | @@ -596,14 +596,14 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond= , TCGReg rn) } } =20 -static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } =20 -static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -630,8 +630,8 @@ static void tcg_out_memop_8(TCGContext *s, ARMCond cond= , ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); } =20 -static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCG= Reg rt, - TCGReg rn, int imm12, bool p, bool w) +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rt, TCGReg rn, int imm12, bool p, bool= w) { bool u =3D 1; if (imm12 < 0) { @@ -866,7 +866,7 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond,= int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg ds= t, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGAr= g dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -880,8 +880,8 @@ static void tcg_out_dat_rI(TCGContext *s, ARMCond cond,= int opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opin= v, - TCGReg dst, TCGReg lhs, TCGArg rhs, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg = rhs, bool rhs_is_const) { if (rhs_is_const) { @@ -896,8 +896,8 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond= , int opc, int opinv, } } =20 -static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opne= g, - TCGArg dst, TCGArg lhs, TCGArg rhs, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg = rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn. --=20 2.25.1