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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322269420100001 Content-Type: text/plain; charset="utf-8" GCC since 4.8 provides the definition and we now require 7.5. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index d113b7f8db..18bb16c784 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -26,25 +26,6 @@ #ifndef ARM_TCG_TARGET_H #define ARM_TCG_TARGET_H =20 -/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. = */ -#ifndef __ARM_ARCH -# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH 7 -# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) -# define __ARM_ARCH 6 -# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \ - || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH 5 -# else -# define __ARM_ARCH 4 -# endif -#endif - extern int arm_arch; =20 #if defined(__ARM_ARCH_5T__) \ --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322822406100001 Content-Type: text/plain; charset="utf-8" Some of the functions specified _reg, some _imm, and some left it blank. Make it clearer to which we are referring. Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when we do not actually require BX semantics. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index cbe3057a9d..0578f9749b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -525,19 +525,19 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_blx(TCGContext *s, int cond, int rn) +static inline void tcg_out_blx_reg(TCGContext *s, int cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -568,13 +568,19 @@ static inline void tcg_out_mov_reg(TCGContext *s, int= cond, int rd, int rm) } } =20 -static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_bx_reg(TCGContext *s, int cond, TCGReg rn) { - /* Unless the C portion of QEMU is compiled as thumb, we don't - actually need true BX semantics; merely a branch to an address - held in a register. */ + tcg_out32(s, (cond << 28) | 0x012fff10 | rn); +} + +static void tcg_out_b_reg(TCGContext *s, int cond, TCGReg rn) +{ + /* + * Unless the C portion of QEMU is compiled as thumb, we don't need + * true BX semantics; merely a branch to an address held in a register. + */ if (use_armv5t_instructions) { - tcg_out32(s, (cond << 28) | 0x012fff10 | rn); + tcg_out_bx_reg(s, cond, rn); } else { tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); } @@ -1215,7 +1221,7 @@ static void tcg_out_goto(TCGContext *s, int cond, con= st tcg_insn_unit *addr) ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); =20 if ((addri & 1) =3D=3D 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01f= ffffd) { - tcg_out_b(s, cond, disp); + tcg_out_b_imm(s, cond, disp); return; } tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); @@ -1236,11 +1242,11 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *addr) } tcg_out_blx_imm(s, disp); } else { - tcg_out_bl(s, COND_AL, disp); + tcg_out_bl_imm(s, COND_AL, disp); } } else if (use_armv7_instructions) { tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_blx(s, COND_AL, TCG_REG_TMP); + tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); } else { /* ??? Know that movi_pool emits exactly 1 insn. */ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); @@ -1254,7 +1260,7 @@ static inline void tcg_out_goto_label(TCGContext *s, = int cond, TCGLabel *l) tcg_out_goto(s, cond, l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); - tcg_out_b(s, cond, 0); + tcg_out_b_imm(s, cond, 0); } } =20 @@ -1823,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) /* This a conditional BL only to load a pointer within this opcode int= o LR for the slow path. We will not be using the value for a tail call.= */ label_ptr =3D s->code_ptr; - tcg_out_bl(s, COND_NE, 0); + tcg_out_bl_imm(s, COND_NE, 0); =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); =20 @@ -1929,7 +1935,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) =20 /* The conditional call must come last, as we're going to return here.= */ label_ptr =3D s->code_ptr; - tcg_out_bl(s, COND_NE, 0); + tcg_out_bl_imm(s, COND_NE, 0); =20 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); @@ -1982,7 +1988,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); + tcg_out_b_reg(s, COND_AL, args[0]); break; case INDEX_op_br: tcg_out_goto_label(s, COND_AL, arg_label(args[0])); @@ -3065,7 +3071,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 - tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]); + tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); =20 /* * Return path for goto_ptr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322273785100001 Content-Type: text/plain; charset="utf-8" According to the Arm ARM DDI 0406C, section A1.3, the valid variants are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. Therefore simplify the test from preprocessor ifdefs to base architecture revision. Retain the "t" in the name to minimize churn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 18bb16c784..f41b809554 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,13 +28,7 @@ =20 extern int arm_arch; =20 -#if defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) -# define use_armv5t_instructions 1 -#else -# define use_armv5t_instructions use_armv6_instructions -#endif - +#define use_armv5t_instructions (__ARM_ARCH >=3D 5 || arm_arch >=3D 5) #define use_armv6_instructions (__ARM_ARCH >=3D 6 || arm_arch >=3D 6) #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 14:29:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/14] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call Date: Wed, 18 Aug 2021 11:29:02 -1000 Message-Id: <20210818212912.396794-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322712189100001 Content-Type: text/plain; charset="utf-8" ARMv4T has BX as its only interworking instruction. In order to support testing of different architecture revisions with a qemu binary that may have been built for, say ARMv6T2, fill in the blank required to make calls to helpers in thumb mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 49 ++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0578f9749b..87df812bb5 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1211,7 +1211,8 @@ static inline void tcg_out_st8(TCGContext *s, int con= d, tcg_out_st8_12(s, cond, rd, rn, offset); } =20 -/* The _goto case is normally between TBs within the same code buffer, and +/* + * The _goto case is normally between TBs within the same code buffer, and * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which d= oes. */ @@ -1219,38 +1220,56 @@ static void tcg_out_goto(TCGContext *s, int cond, c= onst tcg_insn_unit *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); + bool arm_mode =3D !(addri & 1); =20 - if ((addri & 1) =3D=3D 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01f= ffffd) { + if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { tcg_out_b_imm(s, cond, disp); return; } - tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); + + /* LDR is interworking from v5t. */ + if (arm_mode || use_armv5t_instructions) { + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); + return; + } + + /* else v4t */ + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); } =20 -/* The call case is mostly used for helpers - so it's not unreasonable - * for them to be beyond branch range */ +/* + * The call case is mostly used for helpers - so it's not unreasonable + * for them to be beyond branch range. + */ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); + bool arm_mode =3D !(addri & 1); =20 if (disp - 8 < 0x02000000 && disp - 8 >=3D -0x02000000) { - if (addri & 1) { - /* Use BLX if the target is in Thumb mode */ - if (!use_armv5t_instructions) { - tcg_abort(); - } - tcg_out_blx_imm(s, disp); - } else { + if (arm_mode) { tcg_out_bl_imm(s, COND_AL, disp); + return; } - } else if (use_armv7_instructions) { + if (use_armv5t_instructions) { + tcg_out_blx_imm(s, disp); + return; + } + } + + if (use_armv5t_instructions) { tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); - } else { + } else if (arm_mode) { /* ??? Know that movi_pool emits exactly 1 insn. */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); + tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC); + tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP); } } =20 --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629322941; cv=none; d=zohomail.com; s=zohoarc; b=AE7Z2obfnNKoTYQ7cp+yr3PWYSxA8NMxC80RqmZTnl+ZH/QmNE05j/xFGjs/YcvfExpvbG4QtWDfH2p9oww2G1ShuKWpyRVc3xyWhNvvoIF/+CXjvx+jT3xhsuYKa7pNzySraJ0j8Iq4XWrqk0Z3UPsjHIoB7jTwR6CKb+r+HGQ= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 14:29:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/14] tcg/arm: Examine QEMU_TCG_DEBUG environment variable Date: Wed, 18 Aug 2021 11:29:03 -1000 Message-Id: <20210818212912.396794-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322942973100001 Content-Type: text/plain; charset="utf-8" Use the environment variable to test an older ISA from the one supported by the host. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 8 +++++++- tcg/arm/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index f41b809554..e47720a85b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -28,9 +28,15 @@ =20 extern int arm_arch; =20 +#ifdef CONFIG_DEBUG_TCG +#define use_armv5t_instructions (arm_arch >=3D 5) +#define use_armv6_instructions (arm_arch >=3D 6) +#define use_armv7_instructions (arm_arch >=3D 7) +#else #define use_armv5t_instructions (__ARM_ARCH >=3D 5 || arm_arch >=3D 5) #define use_armv6_instructions (__ARM_ARCH >=3D 6 || arm_arch >=3D 6) #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) +#endif =20 #undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 @@ -83,7 +89,7 @@ typedef enum { #else extern bool use_idiv_instructions; #endif -#ifdef __ARM_NEON__ +#if defined(__ARM_NEON__) && !defined(CONFIG_DEBUG_TCG) #define use_neon_instructions 1 #else extern bool use_neon_instructions; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 87df812bb5..0c7e4f8411 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2455,6 +2455,38 @@ static void tcg_target_init(TCGContext *s) } } =20 + /* + * For debugging/testing purposes, allow the ISA to be reduced + * (but not extended) from the set detected above. + */ +#ifdef CONFIG_DEBUG_TCG + { + char *opt =3D g_strdup(getenv("QEMU_TCG_DEBUG")); + if (opt) { + for (char *o =3D strtok(opt, ","); o ; o =3D strtok(NULL, ",")= ) { + if (o[0] =3D=3D 'v' && + o[1] >=3D '4' && + o[1] <=3D '0' + arm_arch && + o[2] =3D=3D 0) { + arm_arch =3D o[1] - '0'; + continue; + } + if (strcmp(o, "!neon") =3D=3D 0) { + use_neon_instructions =3D false; + continue; + } + if (strcmp(o, "help") =3D=3D 0) { + printf("QEMU_TCG_DEBUG=3D{,} where is\= n" + " v select ARMv\n" + " !neon disable ARM NEON\n"); + exit(0); + } + } + g_free(opt); + } + } +#endif + tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; =20 tcg_target_call_clobber_regs =3D 0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322303057100001 Content-Type: text/plain; charset="utf-8" From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read and not use LDRD/STRD when the access is not aligned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 69 ++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 31 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0c7e4f8411..c55167cc84 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -34,13 +34,6 @@ bool use_idiv_instructions; bool use_neon_instructions; #endif =20 -/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ -#ifdef CONFIG_SOFTMMU -# define USING_SOFTMMU 1 -#else -# define USING_SOFTMMU 0 -#endif - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", @@ -1526,15 +1519,20 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + unsigned a_mask =3D (1 << get_alignment_bits(opc)) - 1; + TCGReg t_addr; =20 /* - * We don't support inline unaligned acceses, but we can easily - * support overalignment checks. + * For v7, support for unaligned accesses is mandatory. + * For v6, support for unaligned accesses is enabled by SCTLR.U, + * which is enabled by (at least) Linux and FreeBSD. + * For v4 and v5, unaligned accesses are... complicated, and + * unhelped by Linux having a global not per-process flag + * for unaligned handling. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; + if (!use_armv6_instructions && a_mask < s_mask) { + a_mask =3D s_mask; } =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ @@ -1578,27 +1576,32 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, =20 /* * Check alignment, check comparators. - * Do this in no more than 3 insns. Use MOVW for v7, if possible, + * Do this in 2-4 insns. Use MOVW for v7, if possible, * to reduce the number of sequential conditional instructions. * Almost all guests have at least 4k pages, which means that we need * to clear at least 9 bits even for an 8-byte memory, which means it * isn't worth checking for an immediate operand for BIC. */ + /* For unaligned accesses, test the page of the last byte. */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); - - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); + t_addr, TCG_REG_TMP, 0); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); } else { - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, - (1 << a_bits) - 1); + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } @@ -1763,8 +1766,9 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, MemOp opc, tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); break; case MO_Q: - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + /* LDRD requires alignment; double-check that. */ + if (use_armv6_instructions + && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); } else if (datalo !=3D addend) { @@ -1806,8 +1810,9 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, MemOp opc, tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_Q: - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + /* LDRD requires alignment; double-check that. */ + if (use_armv6_instructions + && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); } else if (datalo =3D=3D addrlo) { @@ -1882,8 +1887,9 @@ static inline void tcg_out_qemu_st_index(TCGContext *= s, int cond, MemOp opc, tcg_out_st32_r(s, cond, datalo, addrlo, addend); break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + /* STRD requires alignment; double-check that. */ + if (use_armv6_instructions + && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { @@ -1914,8 +1920,9 @@ static inline void tcg_out_qemu_st_direct(TCGContext = *s, MemOp opc, tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions + /* STRD requires alignment; double-check that. */ + if (use_armv6_instructions + && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322524504100001 Content-Type: text/plain; charset="utf-8" Expand these hard-coded instructions symbolically. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c55167cc84..63b786a3e5 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -134,6 +134,9 @@ typedef enum { INSN_CLZ =3D 0x016f0f10, INSN_RBIT =3D 0x06ff0f30, =20 + INSN_LDMIA =3D 0x08b00000, + INSN_STMDB =3D 0x09200000, + INSN_LDR_IMM =3D 0x04100000, INSN_LDR_REG =3D 0x06100000, INSN_STR_IMM =3D 0x04000000, @@ -586,6 +589,12 @@ static inline void tcg_out_dat_imm(TCGContext *s, (rn << 16) | (rd << 12) | im); } =20 +static void tcg_out_ldstm(TCGContext *s, int cond, int opc, + TCGReg rn, uint16_t mask) +{ + tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); +} + /* Note that this routine is used for both LDR and LDRH formats, so we do not wish to include an immediate shift at this point. */ static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, @@ -3119,7 +3128,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) { /* Calling convention requires us to save r4-r11 and lr. */ /* stmdb sp!, { r4 - r11, lr } */ - tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); + tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK, + (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | + (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | + (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= R14)); =20 /* Reserve callee argument and tcg temp space. */ tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, @@ -3147,7 +3159,10 @@ static void tcg_out_epilogue(TCGContext *s) TCG_REG_CALL_STACK, STACK_ADDEND, 1); =20 /* ldmia sp!, { r4 - r11, pc } */ - tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); + tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK, + (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6= ) | + (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9= ) | + (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_= PC)); } =20 typedef struct { --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 14:29:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/14] tcg/arm: Simplify usage of encode_imm Date: Wed, 18 Aug 2021 11:29:06 -1000 Message-Id: <20210818212912.396794-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322716436100001 Content-Type: text/plain; charset="utf-8" We have already computed the rotated value of the imm8 portion of the complete imm12 encoding. No sense leaving the combination of rot + rotation to the caller. Create an encode_imm12_nofail helper that performs an assert. This removes the final use of the local "rotl" function, which duplicated our generic "rol32" function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.c.inc | 141 +++++++++++++++++++++------------------ 1 file changed, 77 insertions(+), 64 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 63b786a3e5..265370b2ee 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -305,10 +305,10 @@ static bool reloc_pc8(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) { const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); ptrdiff_t offset =3D tcg_ptr_byte_diff(target, src_rx) - 8; - int rot =3D encode_imm(offset); + int imm12 =3D encode_imm(offset); =20 - if (rot >=3D 0) { - *src_rw =3D deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot <<= 7)); + if (imm12 >=3D 0) { + *src_rw =3D deposit32(*src_rw, 0, 12, imm12); return true; } return false; @@ -362,33 +362,52 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) #endif =20 -static inline uint32_t rotl(uint32_t val, int n) -{ - return (val << n) | (val >> (32 - n)); -} - -/* ARM immediates for ALU instructions are made of an unsigned 8-bit - right-rotated by an even amount between 0 and 30. */ +/* + * ARM immediates for ALU instructions are made of an unsigned 8-bit + * right-rotated by an even amount between 0 and 30. + * + * Return < 0 if @imm cannot be encoded, else the entire imm12 field. + */ static int encode_imm(uint32_t imm) { - int shift; + uint32_t rot, imm8; =20 - /* simple case, only lower bits */ - if ((imm & ~0xff) =3D=3D 0) - return 0; - /* then try a simple even shift */ - shift =3D ctz32(imm) & ~1; - if (((imm >> shift) & ~0xff) =3D=3D 0) - return 32 - shift; - /* now try harder with rotations */ - if ((rotl(imm, 2) & ~0xff) =3D=3D 0) - return 2; - if ((rotl(imm, 4) & ~0xff) =3D=3D 0) - return 4; - if ((rotl(imm, 6) & ~0xff) =3D=3D 0) - return 6; - /* imm can't be encoded */ + /* Simple case, no rotation required. */ + if ((imm & ~0xff) =3D=3D 0) { + return imm; + } + + /* Next, try a simple even shift. */ + rot =3D ctz32(imm) & ~1; + imm8 =3D imm >> rot; + rot =3D 32 - rot; + if ((imm8 & ~0xff) =3D=3D 0) { + goto found; + } + + /* + * Finally, try harder with rotations. + * The ctz test above will have taken care of rotates >=3D 8. + */ + for (rot =3D 2; rot < 8; rot +=3D 2) { + imm8 =3D rol32(imm, rot); + if ((imm8 & ~0xff) =3D=3D 0) { + goto found; + } + } + /* Fail: imm cannot be encoded. */ return -1; + + found: + /* Note that rot is even, and we discard bit 0 by shifting by 7. */ + return rot << 7 | imm8; +} + +static int encode_imm_nofail(uint32_t imm) +{ + int ret =3D encode_imm(imm); + tcg_debug_assert(ret >=3D 0); + return ret; } =20 static inline int check_fit_imm(uint32_t imm) @@ -775,20 +794,18 @@ static void tcg_out_movi_pool(TCGContext *s, int cond= , int rd, uint32_t arg) =20 static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) { - int rot, diff, opc, sh1, sh2; + int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; =20 /* Check a single MOV/MVN before anything else. */ - rot =3D encode_imm(arg); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, - rotl(arg, rot) | (rot << 7)); + imm12 =3D encode_imm(arg); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12); return; } - rot =3D encode_imm(~arg); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, - rotl(~arg, rot) | (rot << 7)); + imm12 =3D encode_imm(~arg); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12); return; } =20 @@ -796,17 +813,15 @@ static void tcg_out_movi32(TCGContext *s, int cond, i= nt rd, uint32_t arg) or within the TB, which is immediately before the code block. */ diff =3D tcg_pcrel_diff(s, (void *)arg) - 8; if (diff >=3D 0) { - rot =3D encode_imm(diff); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, - rotl(diff, rot) | (rot << 7)); + imm12 =3D encode_imm(diff); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12); return; } } else { - rot =3D encode_imm(-diff); - if (rot >=3D 0) { - tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, - rotl(-diff, rot) | (rot << 7)); + imm12 =3D encode_imm(-diff); + if (imm12 >=3D 0) { + tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12); return; } } @@ -838,6 +853,8 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) sh2 =3D ctz32(tt1) & ~1; tt2 =3D tt1 & ~(0xff << sh2); if (tt2 =3D=3D 0) { + int rot; + rot =3D ((32 - sh1) << 7) & 0xf00; tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); rot =3D ((32 - sh2) << 7) & 0xf00; @@ -850,37 +867,35 @@ static void tcg_out_movi32(TCGContext *s, int cond, i= nt rd, uint32_t arg) tcg_out_movi_pool(s, cond, rd, arg); } =20 +/* + * Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rI" constraint. + */ static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg= dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rI" constraint. - */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } } =20 +/* + * Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIK" constraint. + */ static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, bool rhs_is_const) { - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIK" constraint. - */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - if (rot < 0) { - rhs =3D ~rhs; - rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); + int imm12 =3D encode_imm(rhs); + if (imm12 < 0) { + imm12 =3D encode_imm_nofail(~rhs); opc =3D opinv; } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } @@ -894,14 +909,12 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, = int opc, int opneg, * rhs must satisfy the "rIN" constraint. */ if (rhs_is_const) { - int rot =3D encode_imm(rhs); - if (rot < 0) { - rhs =3D -rhs; - rot =3D encode_imm(rhs); - tcg_debug_assert(rot >=3D 0); + int imm12 =3D encode_imm(rhs); + if (imm12 < 0) { + imm12 =3D encode_imm_nofail(-rhs); opc =3D opneg; } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7= )); + tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12); } else { tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); } --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 18 Aug 2021 14:29:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/14] tcg/arm: Drop inline markers Date: Wed, 18 Aug 2021 11:29:07 -1000 Message-Id: <20210818212912.396794-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322533353100001 Content-Type: text/plain; charset="utf-8" Let the compiler decide about inlining. Remove tcg_out_nop as unused. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 234 +++++++++++++++++++-------------------- 1 file changed, 114 insertions(+), 120 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 265370b2ee..327032f0df 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -410,7 +410,7 @@ static int encode_imm_nofail(uint32_t imm) return ret; } =20 -static inline int check_fit_imm(uint32_t imm) +static bool check_fit_imm(uint32_t imm) { return encode_imm(imm) >=3D 0; } @@ -540,42 +540,37 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static inline void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_blx_reg(TCGContext *s, int cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, int cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } =20 -static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) +static void tcg_out_blx_imm(TCGContext *s, int32_t offset) { tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static inline void tcg_out_dat_reg(TCGContext *s, +static void tcg_out_dat_reg(TCGContext *s, int cond, int opc, int rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, INSN_NOP); -} - -static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -601,8 +596,8 @@ static void tcg_out_b_reg(TCGContext *s, int cond, TCGR= eg rn) } } =20 -static inline void tcg_out_dat_imm(TCGContext *s, - int cond, int opc, int rd, int rn, int im) +static void tcg_out_dat_imm(TCGContext *s, int cond, int opc, + int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); @@ -647,141 +642,141 @@ static void tcg_out_memop_12(TCGContext *s, int con= d, ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | imm12); } =20 -static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void __attribute__((unused)) +tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); } =20 /* Register pre-increment with base writeback. */ -static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); } =20 -static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) +static void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) +static void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) +static void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } @@ -871,8 +866,8 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg= dst, - TCGArg lhs, TCGArg rhs, int rhs_is_const) +static void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, + TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); @@ -920,8 +915,8 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, in= t opc, int opneg, } } =20 -static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, - TCGReg rn, TCGReg rm) +static void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, + TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && d =3D=3D n then UNPREDICTABLE; */ if (!use_armv6_instructions && rd =3D=3D rn) { @@ -938,8 +933,8 @@ static inline void tcg_out_mul32(TCGContext *s, int con= d, TCGReg rd, tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); } =20 -static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) +static void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { @@ -957,8 +952,8 @@ static inline void tcg_out_umull32(TCGContext *s, int c= ond, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) +static void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ if (!use_armv6_instructions && (rd0 =3D=3D rn || rd1 =3D=3D rn)) { @@ -976,18 +971,17 @@ static inline void tcg_out_smull32(TCGContext *s, int= cond, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, i= nt rm) +static void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, i= nt rm) +static void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static inline void tcg_out_ext8s(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* sxtb */ @@ -1000,14 +994,13 @@ static inline void tcg_out_ext8s(TCGContext *s, int = cond, } } =20 -static inline void tcg_out_ext8u(TCGContext *s, int cond, - int rd, int rn) +static void __attribute__((unused)) +tcg_out_ext8u(TCGContext *s, int cond, int rd, int rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static inline void tcg_out_ext16s(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* sxth */ @@ -1020,8 +1013,7 @@ static inline void tcg_out_ext16s(TCGContext *s, int = cond, } } =20 -static inline void tcg_out_ext16u(TCGContext *s, int cond, - int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* uxth */ @@ -1101,7 +1093,7 @@ static void tcg_out_bswap16(TCGContext *s, int cond, = int rd, int rn, int flags) ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { /* rev */ @@ -1118,8 +1110,8 @@ static inline void tcg_out_bswap32(TCGContext *s, int= cond, int rd, int rn) } } =20 -static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len, bool const= _a1) +static void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) { if (const_a1) { /* bfi becomes bfc with rn =3D=3D 15. */ @@ -1130,24 +1122,24 @@ static inline void tcg_out_deposit(TCGContext *s, i= nt cond, TCGReg rd, | (ofs << 7) | ((ofs + len - 1) << 16)); } =20 -static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) +static void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) { /* ubfx */ tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 | (ofs << 7) | ((len - 1) << 16)); } =20 -static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) +static void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) { /* sbfx */ tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 | (ofs << 7) | ((len - 1) << 16)); } =20 -static inline void tcg_out_ld32u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld32u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1156,8 +1148,8 @@ static inline void tcg_out_ld32u(TCGContext *s, int c= ond, tcg_out_ld32_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st32(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st32(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1166,8 +1158,8 @@ static inline void tcg_out_st32(TCGContext *s, int co= nd, tcg_out_st32_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld16u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld16u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1176,8 +1168,8 @@ static inline void tcg_out_ld16u(TCGContext *s, int c= ond, tcg_out_ld16u_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld16s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld16s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1186,8 +1178,8 @@ static inline void tcg_out_ld16s(TCGContext *s, int c= ond, tcg_out_ld16s_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st16(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st16(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1196,8 +1188,8 @@ static inline void tcg_out_st16(TCGContext *s, int co= nd, tcg_out_st16_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld8u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld8u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1206,8 +1198,8 @@ static inline void tcg_out_ld8u(TCGContext *s, int co= nd, tcg_out_ld8_12(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_ld8s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_ld8s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1216,8 +1208,8 @@ static inline void tcg_out_ld8s(TCGContext *s, int co= nd, tcg_out_ld8s_8(s, cond, rd, rn, offset); } =20 -static inline void tcg_out_st8(TCGContext *s, int cond, - int rd, int rn, int32_t offset) +static void tcg_out_st8(TCGContext *s, int cond, + int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1288,7 +1280,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *addr) } } =20 -static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) +static void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) { if (l->has_value) { tcg_out_goto(s, cond, l->u.value_ptr); @@ -1298,7 +1290,7 @@ static inline void tcg_out_goto_label(TCGContext *s, = int cond, TCGLabel *l) } } =20 -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, TCGArg a0) { if (use_armv7_instructions) { tcg_out32(s, INSN_DMB_ISH); @@ -1764,9 +1756,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } #endif /* SOFTMMU */ =20 -static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) +static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1808,9 +1800,9 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, MemOp opc, } } =20 -static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) +#ifndef CONFIG_SOFTMMU +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, TCGReg addrlo) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1849,6 +1841,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, MemOp opc, g_assert_not_reached(); } } +#endif =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { @@ -1891,9 +1884,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif } =20 -static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp op= c, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) +static void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1924,9 +1917,9 @@ static inline void tcg_out_qemu_st_index(TCGContext *= s, int cond, MemOp opc, } } =20 -static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) +#ifndef CONFIG_SOFTMMU +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, TCGReg addrlo) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1956,6 +1949,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext = *s, MemOp opc, g_assert_not_reached(); } } +#endif =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { @@ -2000,9 +1994,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) =20 static void tcg_out_epilogue(TCGContext *s); =20 -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2, a3, a4, a5; int c; @@ -2591,8 +2585,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, } } =20 -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { return false; } --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629322721; cv=none; d=zohomail.com; s=zohoarc; b=Yf07EV7U14v34zEKwc+0bAKJA0+ndKTBpeiqd8eczuaB0ybKpqfnbws+wi4Z5M1J8qyDgKof1/0XbX5eIRMu7p2MtFrGugSQOHZ6opPcWHEAsY17yBW5H/qI/8Xu0fBmiaOigu08vHMcCGJL/guqIzbvlkh96+uqThEQdsvjT6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Wed, 18 Aug 2021 14:29:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/14] tcg/arm: Give enum arm_cond_code_e a typedef and use it Date: Wed, 18 Aug 2021 11:29:08 -1000 Message-Id: <20210818212912.396794-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322723088100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 136 +++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 327032f0df..b20c313615 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -85,7 +85,7 @@ static const int tcg_target_call_oarg_regs[2] =3D { #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 =20 -enum arm_cond_code_e { +typedef enum { COND_EQ =3D 0x0, COND_NE =3D 0x1, COND_CS =3D 0x2, /* Unsigned greater or equal */ @@ -101,7 +101,7 @@ enum arm_cond_code_e { COND_GT =3D 0xc, COND_LE =3D 0xd, COND_AL =3D 0xe, -}; +} ARMCond; =20 #define TO_CPSR (1 << 20) =20 @@ -540,19 +540,19 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) return 0; } =20 -static void tcg_out_b_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_bl_imm(TCGContext *s, int cond, int32_t offset) +static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0b000000 | (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_blx_reg(TCGContext *s, int cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, int rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -563,14 +563,14 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t of= fset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, - int cond, int opc, int rd, int rn, int rm, int shift) +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, + int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, int rd, int rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -578,12 +578,12 @@ static void tcg_out_mov_reg(TCGContext *s, int cond, = int rd, int rm) } } =20 -static void tcg_out_bx_reg(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn) { tcg_out32(s, (cond << 28) | 0x012fff10 | rn); } =20 -static void tcg_out_b_reg(TCGContext *s, int cond, TCGReg rn) +static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) { /* * Unless the C portion of QEMU is compiled as thumb, we don't need @@ -596,14 +596,14 @@ static void tcg_out_b_reg(TCGContext *s, int cond, TC= GReg rn) } } =20 -static void tcg_out_dat_imm(TCGContext *s, int cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } =20 -static void tcg_out_ldstm(TCGContext *s, int cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -611,14 +611,14 @@ static void tcg_out_ldstm(TCGContext *s, int cond, in= t opc, =20 /* Note that this routine is used for both LDR and LDRH formats, so we do not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, +static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, TCGReg rn, TCGReg rm, bool u, bool p, bool w) { tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | (rn << 16) | (rt << 12) | rm); } =20 -static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, +static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGR= eg rt, TCGReg rn, int imm8, bool p, bool w) { bool u =3D 1; @@ -630,7 +630,7 @@ static void tcg_out_memop_8(TCGContext *s, int cond, AR= MInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); } =20 -static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg = rt, +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCG= Reg rt, TCGReg rn, int imm12, bool p, bool w) { bool u =3D 1; @@ -642,152 +642,152 @@ static void tcg_out_memop_12(TCGContext *s, int con= d, ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | imm12); } =20 -static void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); } =20 static void __attribute__((unused)) -tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, TCGReg rn, TCGReg rm) +tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg= rm) { tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); } =20 /* Register pre-increment with base writeback. */ -static void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm12) { tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); } =20 -static void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); } =20 -static void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, +static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm) { tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t ar= g) +static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, int rd, uint32_= t arg) { new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); } =20 -static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) +static void tcg_out_movi32(TCGContext *s, ARMCond cond, int rd, uint32_t a= rg) { int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; @@ -866,7 +866,7 @@ static void tcg_out_movi32(TCGContext *s, int cond, int= rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg ds= t, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -880,7 +880,7 @@ static void tcg_out_dat_rI(TCGContext *s, int cond, int= opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opin= v, TCGReg dst, TCGReg lhs, TCGArg rhs, bool rhs_is_const) { @@ -896,7 +896,7 @@ static void tcg_out_dat_rIK(TCGContext *s, int cond, in= t opc, int opinv, } } =20 -static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opne= g, TCGArg dst, TCGArg lhs, TCGArg rhs, bool rhs_is_const) { @@ -915,7 +915,7 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, in= t opc, int opneg, } } =20 -static void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && d =3D=3D n then UNPREDICTABLE; */ @@ -933,7 +933,7 @@ static void tcg_out_mul32(TCGContext *s, int cond, TCGR= eg rd, tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); } =20 -static void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, +static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ @@ -952,7 +952,7 @@ static void tcg_out_umull32(TCGContext *s, int cond, TC= GReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, +static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0, TCGReg rd1, TCGReg rn, TCGReg rm) { /* if ArchVersion() < 6 && (dHi =3D=3D n || dLo =3D=3D n) then UNPREDI= CTABLE; */ @@ -971,17 +971,17 @@ static void tcg_out_smull32(TCGContext *s, int cond, = TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) +static void tcg_out_sdiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) +static void tcg_out_udiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* sxtb */ @@ -995,12 +995,12 @@ static void tcg_out_ext8s(TCGContext *s, int cond, in= t rd, int rn) } =20 static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, int cond, int rd, int rn) +tcg_out_ext8u(TCGContext *s, ARMCond cond, int rd, int rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static void tcg_out_ext16s(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* sxth */ @@ -1013,7 +1013,7 @@ static void tcg_out_ext16s(TCGContext *s, int cond, i= nt rd, int rn) } } =20 -static void tcg_out_ext16u(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* uxth */ @@ -1026,7 +1026,7 @@ static void tcg_out_ext16u(TCGContext *s, int cond, i= nt rd, int rn) } } =20 -static void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn, int f= lags) +static void tcg_out_bswap16(TCGContext *s, ARMCond cond, int rd, int rn, i= nt flags) { if (use_armv6_instructions) { if (flags & TCG_BSWAP_OS) { @@ -1093,7 +1093,7 @@ static void tcg_out_bswap16(TCGContext *s, int cond, = int rd, int rn, int flags) ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, ARMCond cond, int rd, int rn) { if (use_armv6_instructions) { /* rev */ @@ -1110,7 +1110,7 @@ static void tcg_out_bswap32(TCGContext *s, int cond, = int rd, int rn) } } =20 -static void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len, bool const_a1) { if (const_a1) { @@ -1122,7 +1122,7 @@ static void tcg_out_deposit(TCGContext *s, int cond, = TCGReg rd, | (ofs << 7) | ((ofs + len - 1) << 16)); } =20 -static void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len) { /* ubfx */ @@ -1130,7 +1130,7 @@ static void tcg_out_extract(TCGContext *s, int cond, = TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } =20 -static void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, +static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, TCGArg a1, int ofs, int len) { /* sbfx */ @@ -1138,7 +1138,7 @@ static void tcg_out_sextract(TCGContext *s, int cond,= TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } =20 -static void tcg_out_ld32u(TCGContext *s, int cond, +static void tcg_out_ld32u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1148,7 +1148,7 @@ static void tcg_out_ld32u(TCGContext *s, int cond, tcg_out_ld32_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_st32(TCGContext *s, int cond, +static void tcg_out_st32(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1158,7 +1158,7 @@ static void tcg_out_st32(TCGContext *s, int cond, tcg_out_st32_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld16u(TCGContext *s, int cond, +static void tcg_out_ld16u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1168,7 +1168,7 @@ static void tcg_out_ld16u(TCGContext *s, int cond, tcg_out_ld16u_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld16s(TCGContext *s, int cond, +static void tcg_out_ld16s(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1178,7 +1178,7 @@ static void tcg_out_ld16s(TCGContext *s, int cond, tcg_out_ld16s_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_st16(TCGContext *s, int cond, +static void tcg_out_st16(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1188,7 +1188,7 @@ static void tcg_out_st16(TCGContext *s, int cond, tcg_out_st16_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld8u(TCGContext *s, int cond, +static void tcg_out_ld8u(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1198,7 +1198,7 @@ static void tcg_out_ld8u(TCGContext *s, int cond, tcg_out_ld8_12(s, cond, rd, rn, offset); } =20 -static void tcg_out_ld8s(TCGContext *s, int cond, +static void tcg_out_ld8s(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { @@ -1208,7 +1208,7 @@ static void tcg_out_ld8s(TCGContext *s, int cond, tcg_out_ld8s_8(s, cond, rd, rn, offset); } =20 -static void tcg_out_st8(TCGContext *s, int cond, +static void tcg_out_st8(TCGContext *s, ARMCond cond, int rd, int rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { @@ -1223,7 +1223,7 @@ static void tcg_out_st8(TCGContext *s, int cond, * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which d= oes. */ -static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *add= r) +static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit = *addr) { intptr_t addri =3D (intptr_t)addr; ptrdiff_t disp =3D tcg_pcrel_diff(s, addr); @@ -1280,7 +1280,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *addr) } } =20 -static void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) +static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) { if (l->has_value) { tcg_out_goto(s, cond, l->u.value_ptr); @@ -1884,7 +1884,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif } =20 -static void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, +static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 18 Aug 2021 14:29:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/14] tcg/arm: More use of the ARMInsn enum Date: Wed, 18 Aug 2021 11:29:09 -1000 Message-Id: <20210818212912.396794-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818212912.396794-1-richard.henderson@linaro.org> References: <20210818212912.396794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322852403100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b20c313615..2f55b94ada 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -563,7 +563,7 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t offs= et) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int = rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | @@ -596,14 +596,14 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond= , TCGReg rn) } } =20 -static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } =20 -static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -630,8 +630,8 @@ static void tcg_out_memop_8(TCGContext *s, ARMCond cond= , ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); } =20 -static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCG= Reg rt, - TCGReg rn, int imm12, bool p, bool w) +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rt, TCGReg rn, int imm12, bool p, bool= w) { bool u =3D 1; if (imm12 < 0) { @@ -866,7 +866,7 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond,= int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg ds= t, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGAr= g dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -880,8 +880,8 @@ static void tcg_out_dat_rI(TCGContext *s, ARMCond cond,= int opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opin= v, - TCGReg dst, TCGReg lhs, TCGArg rhs, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg = rhs, bool rhs_is_const) { if (rhs_is_const) { @@ -896,8 +896,8 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond= , int opc, int opinv, } } =20 -static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opne= g, - TCGArg dst, TCGArg lhs, TCGArg rhs, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg = rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn. --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629323074142100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/arm/tcg-target.c.inc | 65 +++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 30 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2f55b94ada..35bd4c68d6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -552,7 +552,7 @@ static void tcg_out_bl_imm(TCGContext *s, ARMCond cond,= int32_t offset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, int rn) +static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn) { tcg_out32(s, (cond << 28) | 0x012fff30 | rn); } @@ -563,14 +563,14 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t of= fset) (((offset - 8) >> 2) & 0x00ffffff)); } =20 -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int = rd, - int rn, int rm, int shift) +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rd, TCGReg rn, TCGReg rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | (rn << 16) | (rd << 12) | shift | rm); } =20 -static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, int rd, int rm) +static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rm) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (rd !=3D rm) { @@ -597,7 +597,7 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond, = TCGReg rn) } =20 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, - int rd, int rn, int im) + TCGReg rd, TCGReg rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); @@ -781,13 +781,15 @@ static void tcg_out_ld8s_r(TCGContext *s, ARMCond con= d, TCGReg rt, tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 -static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, int rd, uint32_= t arg) +static void tcg_out_movi_pool(TCGContext *s, ARMCond cond, + TCGReg rd, uint32_t arg) { new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); } =20 -static void tcg_out_movi32(TCGContext *s, ARMCond cond, int rd, uint32_t a= rg) +static void tcg_out_movi32(TCGContext *s, ARMCond cond, + TCGReg rd, uint32_t arg) { int imm12, diff, opc, sh1, sh2; uint32_t tt0, tt1, tt2; @@ -866,8 +868,8 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond,= int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGAr= g dst, - TCGArg lhs, TCGArg rhs, int rhs_is_const) +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_= const) { if (rhs_is_const) { tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs)); @@ -897,7 +899,7 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond= , ARMInsn opc, } =20 static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, - ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg = rhs, + ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg = rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn. @@ -971,17 +973,19 @@ static void tcg_out_smull32(TCGContext *s, ARMCond co= nd, TCGReg rd0, (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); } =20 -static void tcg_out_sdiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) +static void tcg_out_sdiv(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, TCGReg rm) { tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_udiv(TCGContext *s, ARMCond cond, int rd, int rn, int = rm) +static void tcg_out_udiv(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, TCGReg rm) { tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_ext8s(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg r= n) { if (use_armv6_instructions) { /* sxtb */ @@ -995,12 +999,12 @@ static void tcg_out_ext8s(TCGContext *s, ARMCond cond= , int rd, int rn) } =20 static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, ARMCond cond, int rd, int rn) +tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static void tcg_out_ext16s(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { if (use_armv6_instructions) { /* sxth */ @@ -1013,7 +1017,7 @@ static void tcg_out_ext16s(TCGContext *s, ARMCond con= d, int rd, int rn) } } =20 -static void tcg_out_ext16u(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) { if (use_armv6_instructions) { /* uxth */ @@ -1026,7 +1030,8 @@ static void tcg_out_ext16u(TCGContext *s, ARMCond con= d, int rd, int rn) } } =20 -static void tcg_out_bswap16(TCGContext *s, ARMCond cond, int rd, int rn, i= nt flags) +static void tcg_out_bswap16(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn, int flags) { if (use_armv6_instructions) { if (flags & TCG_BSWAP_OS) { @@ -1093,7 +1098,7 @@ static void tcg_out_bswap16(TCGContext *s, ARMCond co= nd, int rd, int rn, int fla ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8))); } =20 -static void tcg_out_bswap32(TCGContext *s, ARMCond cond, int rd, int rn) +static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg= rn) { if (use_armv6_instructions) { /* rev */ @@ -1123,23 +1128,23 @@ static void tcg_out_deposit(TCGContext *s, ARMCond = cond, TCGReg rd, } =20 static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, - TCGArg a1, int ofs, int len) + TCGReg rn, int ofs, int len) { /* ubfx */ - tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 + tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn | (ofs << 7) | ((len - 1) << 16)); } =20 static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, - TCGArg a1, int ofs, int len) + TCGReg rn, int ofs, int len) { /* sbfx */ - tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 + tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn | (ofs << 7) | ((len - 1) << 16)); } =20 static void tcg_out_ld32u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1149,7 +1154,7 @@ static void tcg_out_ld32u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st32(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1159,7 +1164,7 @@ static void tcg_out_st32(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld16u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1169,7 +1174,7 @@ static void tcg_out_ld16u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld16s(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1179,7 +1184,7 @@ static void tcg_out_ld16s(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st16(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1189,7 +1194,7 @@ static void tcg_out_st16(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld8u(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1199,7 +1204,7 @@ static void tcg_out_ld8u(TCGContext *s, ARMCond cond, } =20 static void tcg_out_ld8s(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xff || offset < -0xff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); @@ -1209,7 +1214,7 @@ static void tcg_out_ld8s(TCGContext *s, ARMCond cond, } =20 static void tcg_out_st8(TCGContext *s, ARMCond cond, - int rd, int rn, int32_t offset) + TCGReg rd, TCGReg rn, int32_t offset) { if (offset > 0xfff || offset < -0xfff) { tcg_out_movi32(s, cond, TCG_REG_TMP, offset); --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322375906100001 Content-Type: text/plain; charset="utf-8" Reserve a register for the guest_base using aarch64 for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 35bd4c68d6..2728035177 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -84,6 +84,9 @@ static const int tcg_target_call_oarg_regs[2] =3D { =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 +#ifndef CONFIG_SOFTMMU +#define TCG_REG_GUEST_BASE TCG_REG_R11 +#endif =20 typedef enum { COND_EQ =3D 0x0, @@ -1763,7 +1766,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) + TCGReg addrlo, TCGReg addend, + bool scratch_addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1790,7 +1794,7 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemO= p opc, && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); - } else if (datalo !=3D addend) { + } else if (scratch_addend) { tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); } else { @@ -1875,14 +1879,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); + tcg_out_qemu_ld_index(s, opc, datalo, datahi, + addrlo, TCG_REG_GUEST_BASE, false); } else { tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); } @@ -1891,7 +1895,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) =20 static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) + TCGReg addrlo, TCGReg addend, + bool scratch_addend) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1912,9 +1917,14 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARM= Cond cond, MemOp opc, && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else { + } else if (scratch_addend) { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); tcg_out_st32_12(s, cond, datahi, addend, 4); + } else { + tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, + addend, addrlo, SHIFT_IMM_LSL(0)); + tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); + tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); } break; default: @@ -1978,7 +1988,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) mem_index =3D get_mmuidx(oi); addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); =20 - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); + tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, + addrlo, addend, true); =20 /* The conditional call must come last, as we're going to return here.= */ label_ptr =3D s->code_ptr; @@ -1988,9 +1999,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, - datahi, addrlo, TCG_REG_TMP); + tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, + addrlo, TCG_REG_GUEST_BASE, false); } else { tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); } @@ -3153,6 +3163,13 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 +#ifndef CONFIG_SOFTMMU + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); + } +#endif + tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); =20 /* --=20 2.25.1 From nobody Fri May 17 11:59:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629322958185100001 Content-Type: text/plain; charset="utf-8" For v6+, use ldm/stm, ldrd/strd for the normal case of alignment matching the access size. Otherwise, emit a test + branch sequence invoking helper_unaligned_{ld,st}. For v4+v5, use piecewise load and stores to implement misalignment. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 - tcg/arm/tcg-target.c.inc | 364 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 340 insertions(+), 26 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index e47720a85b..fa75fd3626 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -159,9 +159,7 @@ extern bool use_neon_instructions; /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2728035177..278639be44 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -23,6 +23,7 @@ */ =20 #include "elf.h" +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 int arm_arch =3D __ARM_ARCH; @@ -86,6 +87,7 @@ static const int tcg_target_call_oarg_regs[2] =3D { #define TCG_VEC_TMP TCG_REG_Q15 #ifndef CONFIG_SOFTMMU #define TCG_REG_GUEST_BASE TCG_REG_R11 +#define TCG_REG_TMP2 TCG_REG_R14 #endif =20 typedef enum { @@ -137,7 +139,9 @@ typedef enum { INSN_CLZ =3D 0x016f0f10, INSN_RBIT =3D 0x06ff0f30, =20 + INSN_LDM =3D 0x08900000, INSN_LDMIA =3D 0x08b00000, + INSN_STM =3D 0x08800000, INSN_STMDB =3D 0x09200000, =20 INSN_LDR_IMM =3D 0x04100000, @@ -1428,8 +1432,6 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn, } =20 #ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1762,6 +1764,74 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, and can easily support 8. = */ + tcg_debug_assert(a_mask <=3D 0xff); + /* tst addr, #mask */ + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + + /* blne slow_path */ + label->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TARGET_LONG_BITS =3D=3D 64) { + /* 64-bit target address is aligned into R2:R3. */ + if (l->addrhi_reg !=3D TCG_REG_R2) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); + } else if (l->addrlo_reg !=3D TCG_REG_R3) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); + } + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); + + /* + * Tail call to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. We have used BLNE to arrive here, so LR is + * already set. + */ + tcg_out_goto(s, COND_AL, (const void *) + (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, @@ -1811,45 +1881,175 @@ static void tcg_out_qemu_ld_index(TCGContext *s, M= emOp opc, =20 #ifndef CONFIG_SOFTMMU static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) + TCGReg datahi, TCGReg addrlo, uint8_t o= fs) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld8_12(s, COND_AL, datalo, addrlo, ofs); break; case MO_SB: - tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, ofs); break; case MO_UW: - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, ofs); break; case MO_SW: - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, ofs); break; case MO_UL: - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, ofs); break; case MO_Q: /* LDRD requires alignment; double-check that. */ if (use_armv6_instructions && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { - tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, ofs); } else if (datalo =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, ofs + 4); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, ofs); } else { - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, ofs); + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, ofs + 4); } break; default: g_assert_not_reached(); } } + +/* + * There are a some interesting special cases for which we can get + * the alignment check for free with the instruction. For MO_16, + * we would need to enlist ARMv8 load-acquire halfword (LDAH). + */ +static bool tcg_out_qemu_ld_align(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, TCGReg addrlo, + unsigned a_bits) +{ + unsigned s_bits =3D opc & MO_SIZE; + + /* LDM enforces 4-byte alignment. */ + if (a_bits =3D=3D MO_32 && s_bits >=3D MO_32) { + TCGReg tmphi, tmplo; + + if (guest_base) { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, addrlo, + TCG_REG_GUEST_BASE, SHIFT_IMM_LSL(0)); + addrlo =3D TCG_REG_TMP; + } + + if (s_bits =3D=3D MO_32) { + /* ldm addrlo, { datalo } */ + tcg_out_ldstm(s, COND_AL, INSN_LDM, addrlo, 1 << datalo); + return true; + } + /* else MO_64... */ + + /* + * LDM loads in mask order, so we want the second part to be loaded + * into a higher register number. Note that both R12 and R14 are + * reserved, so we always have a maximum regno to use. + */ + tmplo =3D datalo; + tmphi =3D datahi; + if (MO_BSWAP =3D=3D MO_LE) { + if (datalo > datahi) { + tmphi =3D TCG_REG_TMP; + } + } else { + if (datalo < datahi) { + tmplo =3D TCG_REG_TMP; + } + } + + /* ldm addrlo, { tmplo, tmphi } */ + tcg_out_ldstm(s, COND_AL, INSN_LDM, addrlo, 1 << tmplo | 1 << tmph= i); + + tcg_out_mov(s, TCG_TYPE_I32, datahi, tmphi); + tcg_out_mov(s, TCG_TYPE_I32, datalo, tmplo); + return true; + } + + /* LDRD enforces 8-byte alignment. */ + if (a_bits =3D=3D MO_64 && s_bits =3D=3D MO_64 + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); + tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, TCG_REG_TMP); + } else { + tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); + } + return true; + } + return false; +} + +static void tcg_out_qemu_ld_unalign(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, unsigned a_bits) +{ + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_size =3D 1 << s_bits; + unsigned a_size =3D 1 << a_bits; + bool init =3D true; + unsigned i; + + if (guest_base) { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP2, addrlo, + TCG_REG_GUEST_BASE, SHIFT_IMM_LSL(0)); + addrlo =3D TCG_REG_TMP2; + } + + /* + * Perform the load in units of a_size. + */ + if (MO_BSWAP =3D=3D MO_LE) { + for (i =3D 0; i < s_size; ) { + if (init) { + tcg_out_qemu_ld_direct(s, a_bits, datalo, 0, addrlo, i); + init =3D false; + } else { + /* + * Note that MO_SIGN will only be set for MO_16, and we + * want the sign bit for the second byte, when !init. + */ + tcg_out_qemu_ld_direct(s, a_bits | (opc & MO_SIZE), + TCG_REG_TMP, 0, addrlo, i); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, + datalo, datalo, TCG_REG_TMP, + SHIFT_IMM_LSL(i * 8)); + } + i +=3D a_size; + if (s_size =3D=3D 8 && i =3D=3D 4) { + datalo =3D datahi; + init =3D true; + } + } + } else { + for (i =3D 0; i < s_size; ) { + if (init) { + /* See above, only reversed for big-endian. */ + tcg_out_qemu_ld_direct(s, a_bits | (opc & MO_SIZE), + datahi, 0, addrlo, i); + init =3D false; + } else { + tcg_out_qemu_ld_direct(s, a_bits, TCG_REG_TMP, 0, addrlo, = i); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, + datahi, TCG_REG_TMP, datahi, + SHIFT_IMM_LSL(a_size * 8)); + } + i +=3D a_size; + if (s_size =3D=3D 8 && i =3D=3D 4) { + datahi =3D datalo; + init =3D true; + } + } + } +} #endif =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) @@ -1861,6 +2061,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) int mem_index; TCGReg addend; tcg_insn_unit *label_ptr; +#else + unsigned a_bits, s_bits; #endif =20 datalo =3D *args++; @@ -1884,11 +2086,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - if (guest_base) { + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; + + if (use_armv6_instructions && + tcg_out_qemu_ld_align(s, datalo, datahi, addrlo, a_bits, s_bits)) { + return; + } + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } + if (!use_armv6_instructions && a_bits < MO_32) { + tcg_out_qemu_ld_unalign(s, opc, datalo, datahi, addrlo, a_bits); + } else if (guest_base) { tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_GUEST_BASE, false); } else { - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo, 0); } #endif } @@ -1934,36 +2148,122 @@ static void tcg_out_qemu_st_index(TCGContext *s, A= RMCond cond, MemOp opc, =20 #ifndef CONFIG_SOFTMMU static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) + TCGReg datahi, TCGReg addrlo, uint8_t o= fs) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_st8_12(s, COND_AL, datalo, addrlo, ofs); break; case MO_16: - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_st16_8(s, COND_AL, datalo, addrlo, ofs); break; case MO_32: - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_st32_12(s, COND_AL, datalo, addrlo, ofs); break; case MO_64: /* STRD requires alignment; double-check that. */ if (use_armv6_instructions && get_alignment_bits(opc) >=3D MO_64 && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_strd_8(s, COND_AL, datalo, addrlo, ofs); } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_st32_12(s, COND_AL, datalo, addrlo, ofs); + tcg_out_st32_12(s, COND_AL, datahi, addrlo, ofs + 4); } break; default: g_assert_not_reached(); } } + +static bool tcg_out_qemu_st_align(TCGContext *s, TCGReg datalo, + TCGReg datahi, TCGReg addrlo, + unsigned a_bits, unsigned s_bits) +{ + /* STM enforces 4-byte alignment. */ + if (a_bits =3D=3D MO_32) { + uint16_t mask =3D 1 << datalo; + + switch (s_bits) { + case MO_64: + /* + * STM stores in mask order, so we want the second part to be + * in a higher register number. Note that both R12 and R14 + * are reserved, so we always have a maximum regno to use. + */ + if (MO_BSWAP =3D=3D MO_LE) { + if (datalo > datahi) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_TMP, datahi); + datahi =3D TCG_REG_TMP; + } + } else { + if (datalo < datahi) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_TMP, datalo); + datalo =3D TCG_REG_TMP; + } + } + mask =3D 1 << datalo | 1 << datahi; + /* fall through */ + + case MO_32: + if (guest_base) { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP2, addrl= o, + TCG_REG_GUEST_BASE, SHIFT_IMM_LSL(0)); + addrlo =3D TCG_REG_TMP2; + } + tcg_out_ldstm(s, COND_AL, INSN_STM, addrlo, mask); + return true; + } + return false; + } + + /* STRD enforces 8-byte alignment. */ + if (a_bits =3D=3D MO_64 && s_bits =3D=3D MO_64 + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + if (guest_base) { + tcg_out_strd_r(s, COND_AL, datalo, addrlo, TCG_REG_GUEST_BASE); + } else { + tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + } + return true; + } + return false; +} + +static void tcg_out_qemu_st_unalign(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, unsigned a_bits) +{ + int s_bits =3D opc & MO_SIZE; + int s_size =3D 1 << s_bits; + int a_size =3D 1 << a_bits; + int i; + + if (guest_base) { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP2, addrlo, + TCG_REG_GUEST_BASE, SHIFT_IMM_LSL(0)); + addrlo =3D TCG_REG_TMP2; + } + + /* + * Perform the store in units of a_size. + */ + for (i =3D 0; i < s_size; i +=3D a_size) { + int shift =3D (MO_BSWAP =3D=3D MO_LE ? i : s_size - a_size - i) * = 8; + TCGReg t =3D (i < 32 ? datalo : datahi); + + shift &=3D 31; + if (shift) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t, + SHIFT_IMM_LSR(shift)); + t =3D TCG_REG_TMP; + } + tcg_out_qemu_st_direct(s, a_bits, t, 0, addrlo, i); + } +} #endif =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) @@ -1975,6 +2275,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) int mem_index; TCGReg addend; tcg_insn_unit *label_ptr; +#else + unsigned a_bits, s_bits; #endif =20 datalo =3D *args++; @@ -1998,11 +2300,22 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is64) add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - if (guest_base) { + a_bits =3D get_alignment_bits(opc); + s_bits =3D opc & MO_SIZE; + + if (tcg_out_qemu_st_align(s, datalo, datahi, addrlo, a_bits, s_bits)) { + return; + } + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } + if (!use_armv6_instructions && a_bits < MO_32) { + tcg_out_qemu_st_unalign(s, opc, datalo, datahi, addrlo, a_bits); + } else if (guest_base) { tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, addrlo, TCG_REG_GUEST_BASE, false); } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); + tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo, 0); } #endif } @@ -2558,6 +2871,9 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); +#ifndef CONFIG_SOFTMMU + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); +#endif } =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, --=20 2.25.1