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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x135.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 18 Aug 2021 16:43:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull-eu.20150623.gappssmtp.com) X-ZM-MESSAGEID: 1629319530030100001 Content-Type: text/plain; charset="utf-8" With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich --- Changes in v2: - Fix missing ';' from last-minute whitespace cleanups. disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 278d9be924..793ad14c27 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -478,6 +478,49 @@ typedef enum { rv_op_fsflags =3D 316, rv_op_fsrmi =3D 317, rv_op_fsflagsi =3D 318, + rv_op_bseti =3D 319, + rv_op_bclri =3D 320, + rv_op_binvi =3D 321, + rv_op_bexti =3D 322, + rv_op_rori =3D 323, + rv_op_clz =3D 324, + rv_op_ctz =3D 325, + rv_op_cpop =3D 326, + rv_op_sext_h =3D 327, + rv_op_sext_b =3D 328, + rv_op_xnor =3D 329, + rv_op_orn =3D 330, + rv_op_andn =3D 331, + rv_op_rol =3D 332, + rv_op_ror =3D 333, + rv_op_sh1add =3D 334, + rv_op_sh2add =3D 335, + rv_op_sh3add =3D 336, + rv_op_sh1add_uw =3D 337, + rv_op_sh2add_uw =3D 338, + rv_op_sh3add_uw =3D 339, + rv_op_clmul =3D 340, + rv_op_clmulr =3D 341, + rv_op_clmulh =3D 342, + rv_op_min =3D 343, + rv_op_minu =3D 344, + rv_op_max =3D 345, + rv_op_maxu =3D 346, + rv_op_clzw =3D 347, + rv_op_ctzw =3D 348, + rv_op_cpopw =3D 349, + rv_op_slli_uw =3D 350, + rv_op_add_uw =3D 351, + rv_op_rolw =3D 352, + rv_op_rorw =3D 353, + rv_op_rev8 =3D 354, + rv_op_zext_h =3D 355, + rv_op_roriw =3D 356, + rv_op_orc_b =3D 357, + rv_op_bset =3D 358, + rv_op_bclr =3D 359, + rv_op_binv =3D 360, + rv_op_bext =3D 361, } rv_op; =20 /* structures */ @@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] =3D { { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, + { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 0: op =3D rv_op_addi; break; case 1: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_slli; break; + case 0b00000: op =3D rv_op_slli; break; + case 0b00101: op =3D rv_op_bseti; break; + case 0b01001: op =3D rv_op_bclri; break; + case 0b01101: op =3D rv_op_binvi; break; + case 0b01100: + switch (((inst >> 20) & 0b1111111)) { + case 0b0000000: op =3D rv_op_clz; break; + case 0b0000001: op =3D rv_op_ctz; break; + case 0b0000010: op =3D rv_op_cpop; break; + /* 0b0000011 */ + case 0b0000100: op =3D rv_op_sext_b; break; + case 0b0000101: op =3D rv_op_sext_h; break; + } + break; } break; case 2: op =3D rv_op_slti; break; @@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 4: op =3D rv_op_xori; break; case 5: switch (((inst >> 27) & 0b11111)) { - case 0: op =3D rv_op_srli; break; - case 8: op =3D rv_op_srai; break; + case 0b00000: op =3D rv_op_srli; break; + case 0b00101: op =3D rv_op_orc_b; break; + case 0b01000: op =3D rv_op_srai; break; + case 0b01001: op =3D rv_op_bexti; break; + case 0b01100: op =3D rv_op_rori; break; + case 0b01101: + switch ((inst >> 20) & 0b1111111) { + case 0b0111000: op =3D rv_op_rev8; break; + } + break; } break; case 6: op =3D rv_op_ori; break; @@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) case 1: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_slliw; break; + case 4: op =3D rv_op_slli_uw; break; + case 48: + switch ((inst >> 20) & 0b11111) { + case 0b00000: op =3D rv_op_clzw; break; + case 0b00001: op =3D rv_op_ctzw; break; + case 0b00010: op =3D rv_op_cpopw; break; + } + break; } break; case 5: switch (((inst >> 25) & 0b1111111)) { case 0: op =3D rv_op_srliw; break; case 32: op =3D rv_op_sraiw; break; + case 48: op =3D rv_op_roriw; break; } break; } @@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divu; break; case 14: op =3D rv_op_rem; break; case 15: op =3D rv_op_remu; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 41: op =3D rv_op_clmul; break; + case 42: op =3D rv_op_clmulr; break; + case 43: op =3D rv_op_clmulh; break; + case 44: op =3D rv_op_min; break; + case 45: op =3D rv_op_minu; break; + case 46: op =3D rv_op_max; break; + case 47: op =3D rv_op_maxu; break; + case 130: op =3D rv_op_sh1add; break; + case 132: op =3D rv_op_sh2add; break; + case 134: op =3D rv_op_sh3add; break; + case 161: op =3D rv_op_bset; break; case 256: op =3D rv_op_sub; break; + case 260: op =3D rv_op_xnor; break; case 261: op =3D rv_op_sra; break; + case 262: op =3D rv_op_orn; break; + case 263: op =3D rv_op_andn; break; + case 289: op =3D rv_op_bclr; break; + case 293: op =3D rv_op_bext; break; + case 385: op =3D rv_op_rol; break; + case 386: op =3D rv_op_ror; break; + case 417: op =3D rv_op_binv; break; } break; case 13: op =3D rv_op_lui; break; @@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 13: op =3D rv_op_divuw; break; case 14: op =3D rv_op_remw; break; case 15: op =3D rv_op_remuw; break; + case 32: op =3D rv_op_add_uw; break; + case 36: + switch ((inst >> 20) & 0b11111) { + case 0: op =3D rv_op_zext_h; break; + } + break; + case 130: op =3D rv_op_sh1add_uw; break; + case 132: op =3D rv_op_sh2add_uw; break; + case 134: op =3D rv_op_sh3add_uw; break; case 256: op =3D rv_op_subw; break; case 261: op =3D rv_op_sraw; break; + case 385: op =3D rv_op_rolw; break; + case 389: op =3D rv_op_rorw; break; } break; case 16: --=20 2.25.1