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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314483462100001 This seems to be either a glibc or gcc bug, but the code appears to be fine with the warning suppressed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- util/qemu-thread-posix.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index fd9d714038..6c5004220d 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -537,9 +537,28 @@ static void *qemu_thread_start(void *args) QEMU_TSAN_ANNOTATE_THREAD_NAME(qemu_thread_args->name); g_free(qemu_thread_args->name); g_free(qemu_thread_args); + + /* + * GCC 11 with glibc 2.17 on PowerPC reports + * + * qemu-thread-posix.c:540:5: error: =E2=80=98__sigsetjmp=E2=80=99 acc= essing 656 bytes + * in a region of size 528 [-Werror=3Dstringop-overflow=3D] + * 540 | pthread_cleanup_push(qemu_thread_atexit_notify, NULL); + * | ^~~~~~~~~~~~~~~~~~~~ + * + * which is clearly nonsense. + */ +#pragma GCC diagnostic push +#ifndef __clang__ +#pragma GCC diagnostic ignored "-Wstringop-overflow" +#endif + pthread_cleanup_push(qemu_thread_atexit_notify, NULL); r =3D start_routine(arg); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314650935100001 While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- include/hw/core/tcg-cpu-ops.h | 3 ++- target/alpha/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/tcg/tcg-internal.h | 4 ++-- target/nios2/cpu.h | 4 ++-- target/ppc/internal.h | 4 ++-- target/riscv/cpu.h | 2 +- target/s390x/s390x-internal.h | 4 ++-- target/sh4/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- target/hppa/cpu.c | 7 ++++--- 12 files changed, 23 insertions(+), 21 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index eab27d0c03..ee0795def4 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -72,10 +72,11 @@ struct TCGCPUOps { MemTxResult response, uintptr_t retaddr); /** * @do_unaligned_access: Callback for unaligned access handling + * The callback must exit via raising an exception. */ void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; =20 /** * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967..6eb3fcc63e 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,8 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a388..8a77929793 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -594,7 +594,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, = ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORE= TURN; =20 /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a755..620c3742e1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -359,7 +359,7 @@ void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219..7ac1e578d1 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,8 +24,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 const char *mips_exception_name(int32_t exception); =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..27227b1e88 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -198,8 +198,8 @@ void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 void do_nios2_semihosting(CPUNios2State *env); =20 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index f1fd3c8d04..d2163bf5a2 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -213,8 +213,8 @@ void helper_compute_fprf_float128(CPUPPCState *env, flo= at128 arg); =20 /* Raise a data fault alignment exception for the specified virtual addres= s */ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 /* translate.c */ =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..a5b0047bfd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -345,7 +345,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch= ); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr); + uintptr_t retaddr) QEMU_NORETURN; bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 5506f185e8..96133ac2b6 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -274,8 +274,8 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 =20 /* fpu_helper.c */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c4344082..a9191951f8 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -211,8 +211,8 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, va= ddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2345cb59c7..aa9c77d719 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -579,8 +579,8 @@ void xtensa_count_regs(const XtensaConfig *config, int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2eace4ee12..c2c56e7635 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -72,9 +72,10 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disass= emble_info *info) } =20 #ifndef CONFIG_USER_ONLY -static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +static void QEMU_NORETURN +hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314651024100003 We shouldn't be ignoring SIGBUS for user-only. Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU. Move the wrapper, cpu_unaligned_access, to cpu-exec-common.c. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 4 ++++ include/hw/core/tcg-cpu-ops.h | 16 ++++++++-------- accel/tcg/cpu-exec-common.c | 12 ++++++++++++ accel/tcg/cputlb.c | 9 --------- 4 files changed, 24 insertions(+), 17 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 881bc1ede0..a5e70cd91d 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -19,4 +19,8 @@ void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintpt= r_t retaddr); void page_init(void); void tb_htable_init(void); =20 +void QEMU_NORETURN cpu_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index ee0795def4..3753af03d8 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -60,6 +60,14 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 + /** + * @do_unaligned_access: Callback for unaligned access handling + * The callback must exit via raising an exception. + */ + void (*do_unaligned_access)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; + #ifdef NEED_CPU_H #ifdef CONFIG_SOFTMMU /** @@ -70,14 +78,6 @@ struct TCGCPUOps { unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); - /** - * @do_unaligned_access: Callback for unaligned access handling - * The callback must exit via raising an exception. - */ - void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) QEMU_NORET= URN; - /** * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM */ diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index be6fe45aa5..eeff20a347 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -21,6 +21,8 @@ #include "sysemu/cpus.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "hw/core/tcg-cpu-ops.h" +#include "internal.h" =20 bool tcg_allowed; =20 @@ -81,3 +83,13 @@ void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc) cpu->exception_index =3D EXCP_ATOMIC; cpu_loop_exit_restore(cpu, pc); } + +void cpu_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + assert(cc->tcg_ops->do_unaligned_access !=3D NULL); + cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, reta= ddr); +} diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b1e5471f94..116b289907 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1306,15 +1306,6 @@ static void tlb_fill(CPUState *cpu, target_ulong add= r, int size, assert(ok); } =20 -static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, reta= ddr); -} - static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629314779353100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 2 +- target/alpha/mem_helper.c | 8 +++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4871ad0c0a..cb7e5261bd 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -220,11 +220,11 @@ static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .tlb_fill =3D alpha_cpu_tlb_fill, + .do_unaligned_access =3D alpha_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, - .do_unaligned_access =3D alpha_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 75e72bc337..e3cf98b270 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -23,30 +23,28 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" =20 -/* Softmmu support */ -#ifndef CONFIG_USER_ONLY void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; - uint64_t pc; uint32_t insn; =20 cpu_restore_state(cs, retaddr, true); =20 - pc =3D env->pc; - insn =3D cpu_ldl_code(env, pc); + insn =3D cpu_ldl_code(env, env->pc); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D insn >> 26; /* opcode */ env->trap_arg2 =3D (insn >> 21) & 31; /* dest regno */ + cs->exception_index =3D EXCP_UNALIGN; env->error_code =3D 0; cpu_loop_exit(cs); } =20 +#ifndef CONFIG_USER_ONLY void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314926832100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 4 ++++ linux-user/arm/cpu_loop.c | 43 +++++++++++++++++++++++++++-------- target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 2 +- 4 files changed, 40 insertions(+), 11 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index ee72a1c20f..998831f87f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -137,6 +137,10 @@ void cpu_loop(CPUARMState *env) case 0x11: /* Synchronous Tag Check Fault */ info.si_code =3D TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + info.si_signo =3D TARGET_SIGBUS; + info.si_code =3D TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 69632d15be..da7da6a0c1 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -23,6 +23,7 @@ #include "elf.h" #include "cpu_loop-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -286,9 +287,8 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); int trapnr; - unsigned int n, insn; + unsigned int n, insn, ec, fsc; target_siginfo_t info; - uint32_t addr; abi_ulong ret; =20 for(;;) { @@ -437,15 +437,40 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - addr =3D env->exception.vaddress; - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D env->exception.vaddress; + /* + * We should only arrive here with EC in {DATAABORT, INSNABORT= }, + * and short-form FSC, which then tells us to look at the FSR. + * ??? arm_cpu_reset never sets TTBCR_EAE, so we always get + * short-form FSC. + */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + fsc =3D extract32(env->exception.syndrome, 0, 6); + assert(fsc =3D=3D 0x3f); + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + info.si_signo =3D TARGET_SIGBUS; + info.si_code =3D TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + info.si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D addr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + default: + g_assert_not_reached(); } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2866dd7658..de0d968d76 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1987,11 +1987,11 @@ static const struct TCGCPUOps arm_tcg_ops =3D { .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, .debug_check_breakpoint =3D arm_debug_check_breakpoint, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ed444bf436..1b91fdc890 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -904,11 +904,11 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, .debug_check_breakpoint =3D arm_debug_check_breakpoint, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314490348100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/hppa/cpu_loop.c | 2 +- target/hppa/cpu.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 82d8183821..5ce30fec8b 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -161,7 +161,7 @@ void cpu_loop(CPUHPPAState *env) case EXCP_UNALIGN: info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; - info.si_code =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; info._sifields._sigfault._addr =3D env->cr[CR_IOR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c2c56e7635..91f149ed77 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -71,7 +71,6 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disasse= mble_info *info) info->print_insn =3D print_insn_hppa; } =20 -#ifndef CONFIG_USER_ONLY static void QEMU_NORETURN hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -81,15 +80,19 @@ hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUHPPAState *env =3D &cpu->env; =20 cs->exception_index =3D EXCP_UNALIGN; +#ifdef CONFIG_USER_ONLY + /* Recall that user-only always uses address space 0. */ + env->cr[CR_IOR] =3D addr; +#else if (env->psw & PSW_Q) { /* ??? Needs tweaking for hppa64. */ env->cr[CR_IOR] =3D addr; env->cr[CR_ISR] =3D addr >> 32; } +#endif =20 cpu_loop_exit_restore(cs, retaddr); } -#endif /* CONFIG_USER_ONLY */ =20 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { @@ -147,10 +150,10 @@ static const struct TCGCPUOps hppa_tcg_ops =3D { .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .tlb_fill =3D hppa_cpu_tlb_fill, + .do_unaligned_access =3D hppa_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D hppa_cpu_do_interrupt, - .do_unaligned_access =3D hppa_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 18 Aug 2021 12:19:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/66] target/microblaze: Do not set MO_ALIGN for user-only Date: Wed, 18 Aug 2021 09:18:21 -1000 Message-Id: <20210818191920.390759-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314831024100001 Content-Type: text/plain; charset="utf-8" The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a14ffed784..ef44bca2fd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int = ra, int rb) } #endif =20 +#ifndef CONFIG_USER_ONLY static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { @@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int = rd, =20 tcg_set_insn_start_param(dc->insn_start, 1, iflags); } +#endif =20 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) @@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv ad= dr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, false); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); =20 @@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv a= ddr, MemOp mop, } } =20 + /* + * For system mode, enforce alignment if the cpu configuration + * requires it. For user-mode, the Linux kernel will have fixed up + * any unaligned access, so emulate that by *not* setting MO_ALIGN. + */ +#ifndef CONFIG_USER_ONLY if (size > MO_8 && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) { record_unaligned_ess(dc, rd, size, true); mop |=3D MO_ALIGN; } +#endif =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629314795; cv=none; d=zohomail.com; s=zohoarc; b=Jdin/qQ7dBbiZx0pXRMXo6VdCFmB5/V9g7+msJXO8T0dFk3AbGRR3ZCiiECOYL3naJq2/noBDkUi4ujaB1OIOfO9pgl2bVoGPeYYQiyaPDBDl3eC4YJe/uOpeHl2BHySelyj9g0gecYgg+l0v4vNwRShAFVrKqL9OtjdNVZqAHI= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 18 Aug 2021 12:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/66] target/mips: Implement do_unaligned_access for user-only Date: Wed, 18 Aug 2021 09:18:22 -1000 Message-Id: <20210818191920.390759-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314797606100002 Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/mips/cpu_loop.c | 20 ++++++++++++++++---- target/mips/cpu.c | 2 +- target/mips/tcg/op_helper.c | 3 +-- target/mips/tcg/user/tlb_helper.c | 23 +++++++++++------------ 4 files changed, 29 insertions(+), 19 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 9d813ece4e..51f4eb65a6 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -158,12 +158,24 @@ done_syscall: break; case EXCP_TLBL: case EXCP_TLBS: - case EXCP_AdEL: - case EXCP_AdES: info.si_signo =3D TARGET_SIGSEGV; info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; + info.si_code =3D (env->error_code & EXCP_TLB_NOMATCH + ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR); + info._sifields._sigfault._addr =3D env->CP0_BadVAddr; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_AdEL: + case EXCP_AdES: + /* + * Note that on real hw AdE is also raised for access to a + * kernel address from user mode instead of a TLB error. + * For simplicity, we do not distinguish this in the user + * version of mips_cpu_tlb_fill so only unaligned comes here. + */ + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; info._sifields._sigfault._addr =3D env->CP0_BadVAddr; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d426918291..a1658af910 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -541,11 +541,11 @@ static const struct TCGCPUOps mips_tcg_ops =3D { .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .tlb_fill =3D mips_cpu_tlb_fill, + .do_unaligned_access =3D mips_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, - .do_unaligned_access =3D mips_cpu_do_unaligned_access, .io_recompile_replay_branch =3D mips_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index fafbf1faca..0b874823e4 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -375,8 +375,6 @@ void helper_pmon(CPUMIPSState *env, int function) } } =20 -#if !defined(CONFIG_USER_ONLY) - void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -402,6 +400,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, do_raise_exception_err(env, excp, error_code, retaddr); } =20 +#if !defined(CONFIG_USER_ONLY) void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index b835144b82..61a99356e9 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -26,24 +26,23 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, MMUAccessType access_type) { CPUState *cs =3D env_cpu(env); + int error_code =3D 0; + int flags; =20 - env->error_code =3D 0; if (access_type =3D=3D MMU_INST_FETCH) { - env->error_code |=3D EXCP_INST_NOTAVAIL; + error_code |=3D EXCP_INST_NOTAVAIL; } =20 - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D EXCP_AdES; - } else { - cs->exception_index =3D EXCP_AdEL; + flags =3D page_get_flags(address); + if (!(flags & PAGE_VALID)) { + error_code |=3D EXCP_TLB_NOMATCH; } =20 - /* Raise exception */ - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr =3D address; - } + cs->exception_index =3D (access_type =3D=3D MMU_DATA_STORE + ? EXCP_TLBS : EXCP_TLBL); + + env->error_code =3D error_code; + env->CP0_BadVAddr =3D address; } =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629314654; cv=none; d=zohomail.com; s=zohoarc; b=Jw7yjpI4PP1ZY1qm8UFlFOtYdXBq/qJlNZkco8BMhmhAXp0lhSfTyKQlHz8/2nPKeHfvr4/WM0jOpM+2D8F8cDODrOsXA1jzXvzHe2LprU5H94iT+AS6Kcc/sLIWA5Dtg9d6aCP/rpPY36V5CnckEiz/MUEnoOPk13eUQGTDd34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629314654; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314655851100001 Content-Type: text/plain; charset="utf-8" By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/ppc/excp_helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a79a0ed465..0df358f93f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -478,13 +478,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ - /* Get rS/rD and rA from faulting opcode */ /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. + * Get rS/rD and rA from faulting opcode. + * Note: We will only invoke ALIGN for atomic operations, + * so all instructions are X-form. */ - env->spr[SPR_DSISR] |=3D (env->error_code & 0x03FF0000) >> 16; + { + uint32_t insn =3D cpu_ldl_code(env, env->nip); + env->spr[SPR_DSISR] |=3D (insn & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ switch (env->error_code & ~0xF) { @@ -1501,14 +1503,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env =3D cs->env_ptr; - uint32_t insn; - - /* Restore state and reload the insn we executed, for filling in DSISR= . */ - cpu_restore_state(cs, retaddr, true); - insn =3D cpu_ldl_code(env, env->nip); =20 cs->exception_index =3D POWERPC_EXCP_ALIGN; - env->error_code =3D insn & 0x03FF0000; - cpu_loop_exit(cs); + env->error_code =3D 0; + cpu_loop_exit_restore(cs, retaddr); } #endif --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315140; cv=none; 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Wed, 18 Aug 2021 12:19:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/66] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Date: Wed, 18 Aug 2021 09:18:24 -1000 Message-Id: <20210818191920.390759-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315142967100001 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/ppc/excp_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0df358f93f..d7743704ac 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1504,6 +1504,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, { CPUPPCState *env =3D cs->env_ptr; =20 + switch (env->mmu_model) { + case POWERPC_MMU_SOFT_4xx: + case POWERPC_MMU_SOFT_4xx_Z: + env->spr[SPR_40x_DEAR] =3D vaddr; + break; + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + env->spr[SPR_BOOKE_DEAR] =3D vaddr; + break; + default: + env->spr[SPR_DAR] =3D vaddr; + break; + } + cs->exception_index =3D POWERPC_EXCP_ALIGN; env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:19:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/66] target/ppc: Implement do_unaligned_access for user-only Date: Wed, 18 Aug 2021 09:18:25 -1000 Message-Id: <20210818191920.390759-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314497094100003 Content-Type: text/plain; charset="utf-8" For simplicity on the linux-user side, always use SPR_DAR. Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/ppc/cpu_loop.c | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index fa91ea0eed..d72d30248b 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -165,7 +165,7 @@ void cpu_loop(CPUPPCState *env) info.si_signo =3D TARGET_SIGBUS; info.si_errno =3D 0; info.si_code =3D TARGET_BUS_ADRALN; - info._sifields._sigfault._addr =3D env->nip; + info._sifields._sigfault._addr =3D env->spr[SPR_DAR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case POWERPC_EXCP_PROGRAM: /* Program exception = */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 505a0ed6ac..84fb6bbb83 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,12 +9014,12 @@ static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, - .do_unaligned_access =3D ppc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index d7743704ac..08cc474340 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1505,6 +1505,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, CPUPPCState *env =3D cs->env_ptr; =20 switch (env->mmu_model) { +#ifndef CONFIG_USER_ONLY case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: env->spr[SPR_40x_DEAR] =3D vaddr; @@ -1513,6 +1514,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, case POWERPC_MMU_BOOKE206: env->spr[SPR_BOOKE_DEAR] =3D vaddr; break; +#endif default: env->spr[SPR_DAR] =3D vaddr; break; --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 18 Aug 2021 12:19:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/66] target/riscv: Implement do_unaligned_access for user-only Date: Wed, 18 Aug 2021 09:18:26 -1000 Message-Id: <20210818191920.390759-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315303757100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 +++++++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 8 +++++++- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 74a9628dc9..0428140d86 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env) sigcode =3D TARGET_SEGV_MAPERR; sigaddr =3D env->badaddr; break; + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_LOAD_ADDR_MIS: + case RISCV_EXCP_STORE_AMO_ADDR_MIS: + signum =3D TARGET_SIGBUS; + sigcode =3D TARGET_BUS_ADRALN; + sigaddr =3D env->badaddr; + break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] =3D do_common_semihosting(cs); env->pc +=3D 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..591d17e62d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, - .do_unaligned_access =3D riscv_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..a440b2834f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); } +#endif /* !CONFIG_USER_ONLY */ =20 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; @@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; + +#ifdef CONFIG_USER_ONLY + cpu_loop_exit_restore(cs, retaddr); +#else env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); +#endif } -#endif /* !CONFIG_USER_ONLY */ =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629314963; cv=none; d=zohomail.com; s=zohoarc; b=l0+usDo37pcmiFy9NkQKzdOWxpGrJfZbjCoWXxpiD4gmQ8AA7lMet72KtIHKDfJJKfHIitKZ/3uaLmNg0bhLh4eKt+dltDRK2BAQN9BHFySCLjrUqlsPtX2tN1bcVP1TTj9VHP7Z3TKSNtuiRfxrxwSSyYEalODOclQ7qSbebuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629314963; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314964817100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 28 +++++++++++++++------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..9d8cfb37cd 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -267,12 +267,12 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, .tlb_fill =3D s390_cpu_tlb_fill, + .do_unaligned_access =3D s390x_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, - .do_unaligned_access =3D s390x_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index a61917d04f..9cbe160f66 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -82,6 +82,21 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t= dxc) tcg_s390_data_exception(env, dxc, GETPC()); } =20 +/* + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, + * this is only for the atomic operations, for which we want to raise a + * specification exception. + */ +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); +} + #if defined(CONFIG_USER_ONLY) =20 void s390_cpu_do_interrupt(CPUState *cs) @@ -602,19 +617,6 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) } } =20 -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - this is only for the atomic operations, for which we want to raise a - specification exception. */ -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - S390CPU *cpu =3D S390_CPU(cs); - CPUS390XState *env =3D &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); -} - static void QEMU_NORETURN monitor_event(CPUS390XState *env, uint64_t monitor_code, uint8_t monitor_class, uintptr_t r= a) --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629314655177304.10298282411395; Wed, 18 Aug 2021 12:24:15 -0700 (PDT) Received: from localhost ([::1]:48130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGRAc-0000hQ-5r for importer@patchew.org; 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Wed, 18 Aug 2021 12:19:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/66] target/sh4: Set fault address in superh_cpu_do_unaligned_access Date: Wed, 18 Aug 2021 09:18:28 -1000 Message-Id: <20210818191920.390759-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629314655904100002 We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index c0cbb95382..d6d70c339f 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { + CPUSH4State *env =3D cs->env_ptr; + + env->tea =3D addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: @@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, case MMU_DATA_STORE: cs->exception_index =3D 0x100; break; + default: + g_assert_not_reached(); } cpu_loop_exit_restore(cs, retaddr); } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:19:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/66] target/sh4: Implement do_unaligned_access for user-only Date: Wed, 18 Aug 2021 09:18:29 -1000 Message-Id: <20210818191920.390759-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314788376100001 Content-Type: text/plain; charset="utf-8" Cc: Yoshinori Sato Signed-off-by: Richard Henderson --- linux-user/sh4/cpu_loop.c | 8 ++++++++ target/sh4/cpu.c | 2 +- target/sh4/op_helper.c | 3 --- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 222ed1c670..21d97250a8 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -71,6 +71,14 @@ void cpu_loop(CPUSH4State *env) info._sifields._sigfault._addr =3D env->tea; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case 0xe0: + case 0x100: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->tea; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); arch_interrupt =3D false; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8326922942..b60234cd31 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -238,10 +238,10 @@ static const struct TCGCPUOps superh_tcg_ops =3D { .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .tlb_fill =3D superh_cpu_tlb_fill, + .do_unaligned_access =3D superh_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D superh_cpu_do_interrupt, - .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index d6d70c339f..b46fc1bf11 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -23,7 +23,6 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" =20 -#ifndef CONFIG_USER_ONLY =20 void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -46,8 +45,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, cpu_loop_exit_restore(cs, retaddr); } =20 -#endif - void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629314935; cv=none; d=zohomail.com; s=zohoarc; b=AFv96hlzo7mchvJFD+S/RnyHtAE6wcbPDfRv9wDA73Ek48llCy9+kp5VNM3lztoQBpPVmbT1tr/qgEgra8G3yC47SkQap+qFSzOhfTy4eT/WEyZliy54yalY0uoZztHGM3+S1QaaHKjbvj6M1vzr69CoiJZUfsQpzGZpfU489WQ= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:19:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/66] target/sparc: Remove DEBUG_UNALIGNED Date: Wed, 18 Aug 2021 09:18:30 -1000 Message-Id: <20210818191920.390759-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629314935887100001 The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 22327d7d72..974afea041 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,6 @@ =20 //#define DEBUG_MMU //#define DEBUG_MXCC -//#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI //#define DEBUG_CACHE_CONTROL @@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_= ulong addr, uint32_t align, uintptr_t ra) { if (addr & align) { -#ifdef DEBUG_UNALIGNED - printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FM= T_lx - "\n", addr, env->pc); -#endif cpu_raise_exception_ra(env, TT_UNALIGNED, ra); } } @@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315452418100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a44473a1c7..5b2fda534a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -526,16 +526,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry = *tlb, return 0; } =20 +static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) +{ + uint64_t sfsr =3D SFSR_VALID_BIT; + + switch (mmu_idx) { + case MMU_PHYS_IDX: + sfsr |=3D SFSR_CT_NOTRANS; + break; + case MMU_USER_IDX: + case MMU_KERNEL_IDX: + sfsr |=3D SFSR_CT_PRIMARY; + break; + case MMU_USER_SECONDARY_IDX: + case MMU_KERNEL_SECONDARY_IDX: + sfsr |=3D SFSR_CT_SECONDARY; + break; + case MMU_NUCLEUS_IDX: + sfsr |=3D SFSR_CT_NUCLEUS; + break; + default: + g_assert_not_reached(); + } + + if (rw =3D=3D 1) { + sfsr |=3D SFSR_WRITE_BIT; + } else if (rw =3D=3D 4) { + sfsr |=3D SFSR_NF_BIT; + } + + if (env->pstate & PS_PRIV) { + sfsr |=3D SFSR_PR_BIT; + } + + if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ + sfsr |=3D SFSR_OW_BIT; /* overflow (not read before another fault)= */ + } + + /* FIXME: ASI field in SFSR must be set */ + + return sfsr; +} + static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); unsigned int i; + uint64_t sfsr; uint64_t context; - uint64_t sfsr =3D 0; bool is_user =3D false; =20 + sfsr =3D build_sfsr(env, mmu_idx, rw); + switch (mmu_idx) { case MMU_PHYS_IDX: g_assert_not_reached(); @@ -544,29 +588,18 @@ static int get_physical_address_data(CPUSPARCState *e= nv, hwaddr *physical, /* fallthru */ case MMU_KERNEL_IDX: context =3D env->dmmu.mmu_primary_context & 0x1fff; - sfsr |=3D SFSR_CT_PRIMARY; break; case MMU_USER_SECONDARY_IDX: is_user =3D true; /* fallthru */ case MMU_KERNEL_SECONDARY_IDX: context =3D env->dmmu.mmu_secondary_context & 0x1fff; - sfsr |=3D SFSR_CT_SECONDARY; break; - case MMU_NUCLEUS_IDX: - sfsr |=3D SFSR_CT_NUCLEUS; - /* FALLTHRU */ default: context =3D 0; break; } =20 - if (rw =3D=3D 1) { - sfsr |=3D SFSR_WRITE_BIT; - } else if (rw =3D=3D 4) { - sfsr |=3D SFSR_NF_BIT; - } - for (i =3D 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { @@ -616,22 +649,9 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, return 0; } =20 - if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status registe= r */ - sfsr |=3D SFSR_OW_BIT; /* overflow (not read before - another fault) */ - } - - if (env->pstate & PS_PRIV) { - sfsr |=3D SFSR_PR_BIT; - } - - /* FIXME: ASI field in SFSR must be set */ - env->dmmu.sfsr =3D sfsr | SFSR_VALID_BIT; - + env->dmmu.sfsr =3D sfsr; env->dmmu.sfar =3D address; /* Fault address register */ - env->dmmu.tag_access =3D (address & ~0x1fffULL) | context; - return 1; } } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315177; cv=none; d=zohomail.com; s=zohoarc; b=m80aLca4snpM2hNlgss9pjxaCY2HLWFc8xApWYrtGgPGPNGqq2n93reTsV0YSoiPOm+CWWaV1fteXL13eGgm3yQlQ76HwvjSXb7PQjzXVX2ii/+1XmeBH388r0P34TRjsJVF/g+6/8PjMOZiyVF6Hdps0uekMictyYTVbLtHeoA= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:19:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/66] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Wed, 18 Aug 2021 09:18:32 -1000 Message-Id: <20210818191920.390759-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315178855100003 Content-Type: text/plain; charset="utf-8" We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 13 ------------- target/sparc/mmu_helper.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 974afea041..ea163200a4 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, is_asi, size, retaddr); } #endif - -#if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - - cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 5b2fda534a..2f260b0085 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -946,4 +946,22 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) } return phys_addr; } + +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + +#ifdef TARGET_SPARC64 + env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); + env->dmmu.sfar =3D addr; +#else + env->mmuregs[4] =3D addr; #endif + + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); +} +#endif /* CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315015; cv=none; d=zohomail.com; s=zohoarc; b=If7IB0Tqeqg/YSR7+nF5fbqAkIxYPNQQ488Q9XgV2XUgd2002p4h5QcP2v+gXGjD2i5H0RKSKmtJ9qfgUMCqByiUkXk9GO0GCFuFWR+gwYt3WfNfeqKt3JqDWD011W0lAJaof1wrHc2jC9i5lxeyraTRHxyj3HlU/mkDlKLe3aA= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:19:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/66] target/sparc: Implement do_unaligned_access for user-only Date: Wed, 18 Aug 2021 09:18:33 -1000 Message-Id: <20210818191920.390759-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315017396100003 Content-Type: text/plain; charset="utf-8" Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 11 +++++++++++ target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 4 +++- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 02532f198d..612e77807e 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -272,6 +272,17 @@ void cpu_loop (CPUSPARCState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; + case TT_UNALIGNED: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; +#ifdef TARGET_SPARC64 + info._sifields._sigfault._addr =3D env->dmmu.sfar; +#else + info._sifields._sigfault._addr =3D env->mmuregs[4]; +#endif + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: info.si_signo =3D TARGET_SIGTRAP; info.si_errno =3D 0; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index da6b30ec74..d33d41e837 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,11 +865,11 @@ static const struct TCGCPUOps sparc_tcg_ops =3D { .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .tlb_fill =3D sparc_cpu_tlb_fill, + .do_unaligned_access =3D sparc_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, - .do_unaligned_access =3D sparc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2f260b0085..6b4aa32181 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -946,6 +946,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phys_addr; } +#endif /* CONFIG_USER_ONLY */ =20 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -956,7 +957,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUSta= te *cs, vaddr addr, CPUSPARCState *env =3D &cpu->env; =20 #ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY env->dmmu.sfsr =3D build_sfsr(env, mmu_idx, access_type); +#endif env->dmmu.sfar =3D addr; #else env->mmuregs[4] =3D addr; @@ -964,4 +967,3 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUSta= te *cs, vaddr addr, =20 cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } -#endif /* CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315580795100001 Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 58ec3a0862..41816d91f6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -195,11 +195,11 @@ static const struct TCGCPUOps xtensa_tcg_ops =3D { .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, + .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, =20 #ifndef CONFIG_USER_ONLY .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, - .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f18ab383fd..a5296399c5 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -242,6 +242,21 @@ void xtensa_cpu_list(void) } } =20 +void xtensa_cpu_do_unaligned_access(CPUState *cs, + vaddr addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + assert(xtensa_option_enabled(env->config, + XTENSA_OPTION_UNALIGNED_EXCEPTION)); + cpu_restore_state(CPU(cpu), retaddr, true); + HELPER(exception_cause_vaddr)(env, + env->pc, LOAD_STORE_ALIGNMENT_CAUSE, + addr); +} + #ifdef CONFIG_USER_ONLY =20 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -263,21 +278,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 #else /* !CONFIG_USER_ONLY */ =20 -void xtensa_cpu_do_unaligned_access(CPUState *cs, - vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); 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Wed, 18 Aug 2021 12:19:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/66] accel/tcg: Report unaligned atomics for user-only Date: Wed, 18 Aug 2021 09:18:35 -1000 Message-Id: <20210818191920.390759-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315204053100001 Use the newly exposed cpu_unaligned_access for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 90d1a2d327..5ad808a25a 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -28,6 +28,7 @@ #include "qemu/atomic128.h" #include "trace/trace-root.h" #include "trace/mem.h" +#include "internal.h" =20 #undef EAX #undef ECX @@ -1230,11 +1231,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, TCGMemOpIdx oi, int size, int prot, uintptr_t retaddr) { + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + MMUAccessType t =3D prot =3D=3D PAGE_READ ? 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Wed, 18 Aug 2021 12:19:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 22/66] accel/tcg: Drop signness in tracing in cputlb.c Date: Wed, 18 Aug 2021 09:18:36 -1000 Message-Id: <20210818191920.390759-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315312808100001 Content-Type: text/plain; charset="utf-8" We are already inconsistent about whether or not MO_SIGN is set in trace_mem_get_info. Dropping it entirely allows some simplification. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 10 +++------- accel/tcg/user-exec.c | 45 ++++++------------------------------------- 2 files changed, 9 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 116b289907..acdd20b1bc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2110,7 +2110,6 @@ static inline uint64_t cpu_load_helper(CPUArchState *= env, abi_ptr addr, meminfo =3D trace_mem_get_info(op, mmu_idx, false); trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); =20 - op &=3D ~MO_SIGN; oi =3D make_memop_idx(op, mmu_idx); ret =3D full_load(env, addr, oi, retaddr); =20 @@ -2128,8 +2127,7 @@ uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_pt= r addr, int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { - return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB, - full_ldub_mmu); + return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); } =20 uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -2141,8 +2139,7 @@ uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi= _ptr addr, int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { - return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW, - full_be_lduw_mmu); + return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); } =20 uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -2166,8 +2163,7 @@ uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi= _ptr addr, int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { - return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW, - full_le_lduw_mmu); + return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); } =20 uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5ad808a25a..e687b9652e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -866,13 +866,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) =20 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) { - int ret; - uint16_t meminfo =3D trace_mem_get_info(MO_SB, MMU_USER_IDX, false); - - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsb_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); - return ret; + return (int8_t)cpu_ldub_data(env, ptr); } =20 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) @@ -888,13 +882,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr p= tr) =20 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) { - int ret; - uint16_t meminfo =3D trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); - - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); - return ret; + return (int16_t)cpu_lduw_be_data(env, ptr); } =20 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) @@ -932,13 +920,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr p= tr) =20 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) { - int ret; - uint16_t meminfo =3D trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); - - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); - ret =3D ldsw_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); - return ret; + return (int16_t)cpu_lduw_le_data(env, ptr); } =20 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) @@ -975,12 +957,7 @@ uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr p= tr, uintptr_t retaddr) =20 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) { - int ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldsb_data(env, ptr); - clear_helper_retaddr(); - return ret; + return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr); } =20 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ret= addr) @@ -995,12 +972,7 @@ uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_pt= r ptr, uintptr_t retaddr) =20 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) { - int ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldsw_be_data(env, ptr); - clear_helper_retaddr(); - return ret; + return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr); } =20 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) @@ -1035,12 +1007,7 @@ uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_= ptr ptr, uintptr_t retaddr) =20 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) { - int ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldsw_le_data(env, ptr); - clear_helper_retaddr(); - return ret; + return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr); } =20 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315769; cv=none; d=zohomail.com; s=zohoarc; b=YXH1zrEcey1j3WBG4Of2/+CBvp3HJKyFFJbMtvySKUO37Qk+UP2LUTeTv7VBctwHTcMzj9tTDgQrXAXqP3jV6yBTVLI6xmkohaYqQSDm0YoQoduMKkdTDA9GUDB8L1JHZ0VqGr+AZj/lOMfFUCQoeczIoggd2kmr07Tw836pHzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629315769; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315770251100001 We have lacked expressive support for memory sizes larger than 64-bits for a while. Fixing that requires adjustment to several points where we used this for array indexing, and two places that develop -Wswitch warnings after the change. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- include/exec/memop.h | 14 +++++++++----- target/arm/translate-a64.c | 2 +- tcg/tcg-op.c | 13 ++++++++----- target/s390x/tcg/translate_vx.c.inc | 2 +- tcg/aarch64/tcg-target.c.inc | 4 ++-- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 4 ++-- tcg/ppc/tcg-target.c.inc | 8 ++++---- tcg/riscv/tcg-target.c.inc | 4 ++-- tcg/s390/tcg-target.c.inc | 4 ++-- tcg/sparc/tcg-target.c.inc | 16 ++++++++-------- 12 files changed, 43 insertions(+), 36 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 529d07b02d..04264ffd6b 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -19,11 +19,15 @@ typedef enum MemOp { MO_16 =3D 1, MO_32 =3D 2, MO_64 =3D 3, - MO_SIZE =3D 3, /* Mask for the above. */ + MO_128 =3D 4, + MO_256 =3D 5, + MO_512 =3D 6, + MO_1024 =3D 7, + MO_SIZE =3D 0x07, /* Mask for the above. */ =20 - MO_SIGN =3D 4, /* Sign-extended, otherwise zero-extended. */ + MO_SIGN =3D 0x08, /* Sign-extended, otherwise zero-extended. */ =20 - MO_BSWAP =3D 8, /* Host reverse endian. */ + MO_BSWAP =3D 0x10, /* Host reverse endian. */ #ifdef HOST_WORDS_BIGENDIAN MO_LE =3D MO_BSWAP, MO_BE =3D 0, @@ -59,8 +63,8 @@ typedef enum MemOp { * - an alignment to a specified size, which may be more or less than * the access size (MO_ALIGN_x where 'x' is a size in bytes); */ - MO_ASHIFT =3D 4, - MO_AMASK =3D 7 << MO_ASHIFT, + MO_ASHIFT =3D 5, + MO_AMASK =3D 0x7 << MO_ASHIFT, #ifdef NEED_CPU_H #ifdef TARGET_ALIGNED_ONLY MO_ALIGN =3D 0, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c9..247c9672be 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1045,7 +1045,7 @@ static void read_vec_element(DisasContext *s, TCGv_i6= 4 tcg_dest, int srcidx, int element, MemOp memop) { int vect_off =3D vec_reg_offset(s, srcidx, element, memop & MO_SIZE); - switch (memop) { + switch ((unsigned)memop) { case MO_8: tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); break; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c754396575..e01f68f44d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2780,10 +2780,13 @@ static inline MemOp tcg_canonicalize_memop(MemOp op= , bool is64, bool st) } break; case MO_64: - if (!is64) { - tcg_abort(); + if (is64) { + op &=3D ~MO_SIGN; + break; } - break; + /* fall through */ + default: + g_assert_not_reached(); } if (st) { op &=3D ~MO_SIGN; @@ -3095,7 +3098,7 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env,= TCGv, # define WITH_ATOMIC64(X) #endif =20 -static void * const table_cmpxchg[16] =3D { +static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_8] =3D gen_helper_atomic_cmpxchgb, [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, @@ -3297,7 +3300,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr,= TCGv_i64 val, } =20 #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \ -static void * const table_##NAME[16] =3D { \ +static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] =3D { \ [MO_8] =3D gen_helper_atomic_##NAME##b, \ [MO_16 | MO_LE] =3D gen_helper_atomic_##NAME##w_le, \ [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index 0afa46e463..28bf5a23b6 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -67,7 +67,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t re= g, uint8_t enr, { const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); =20 - switch (memop) { + switch ((unsigned)memop) { case ES_8: tcg_gen_ld8u_i64(dst, cpu_env, offs); break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5924977b42..6f43c048a5 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1547,7 +1547,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) */ -static void * const qemu_ld_helpers[4] =3D { +static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_ldub_mmu, #ifdef HOST_WORDS_BIGENDIAN [MO_16] =3D helper_be_lduw_mmu, @@ -1564,7 +1564,7 @@ static void * const qemu_ld_helpers[4] =3D { * uintxx_t val, TCGMemOpIdx oi, * uintptr_t ra) */ -static void * const qemu_st_helpers[4] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, #ifdef HOST_WORDS_BIGENDIAN [MO_16] =3D helper_be_stw_mmu, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 007ceee68e..8939b2c2da 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1393,7 +1393,7 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ -static void * const qemu_ld_helpers[8] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, #ifdef HOST_WORDS_BIGENDIAN @@ -1414,7 +1414,7 @@ static void * const qemu_ld_helpers[8] =3D { /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, * uintxx_t val, int mmu_idx, uintptr_= t ra) */ -static void * const qemu_st_helpers[4] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, #ifdef HOST_WORDS_BIGENDIAN [MO_16] =3D helper_be_stw_mmu, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 98d924b91a..5fd4e4392f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1610,7 +1610,7 @@ static void tcg_out_nopn(TCGContext *s, int n) /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ -static void * const qemu_ld_helpers[16] =3D { +static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_LEUW] =3D helper_le_lduw_mmu, [MO_LEUL] =3D helper_le_ldul_mmu, @@ -1623,7 +1623,7 @@ static void * const qemu_ld_helpers[16] =3D { /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, * uintxx_t val, int mmu_idx, uintptr_= t ra) */ -static void * const qemu_st_helpers[16] =3D { +static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bf0eb84e2d..cc279205d6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1037,7 +1037,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *arg) #if defined(CONFIG_SOFTMMU) #include "../tcg-ldst.c.inc" =20 -static void * const qemu_ld_helpers[16] =3D { +static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, [MO_LEUW] =3D helper_le_lduw_mmu, @@ -1054,7 +1054,7 @@ static void * const qemu_ld_helpers[16] =3D { #endif }; =20 -static void * const qemu_st_helpers[16] =3D { +static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0f4665213..3fef2aa6b2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1916,7 +1916,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *target) #endif } =20 -static const uint32_t qemu_ldx_opc[16] =3D { +static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] =3D { [MO_UB] =3D LBZX, [MO_UW] =3D LHZX, [MO_UL] =3D LWZX, @@ -1929,7 +1929,7 @@ static const uint32_t qemu_ldx_opc[16] =3D { [MO_BSWAP | MO_Q] =3D LDBRX, }; =20 -static const uint32_t qemu_stx_opc[16] =3D { +static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] =3D { [MO_UB] =3D STBX, [MO_UW] =3D STHX, [MO_UL] =3D STWX, @@ -1950,7 +1950,7 @@ static const uint32_t qemu_exts_opc[4] =3D { /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ -static void * const qemu_ld_helpers[16] =3D { +static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_LEUW] =3D helper_le_lduw_mmu, [MO_LEUL] =3D helper_le_ldul_mmu, @@ -1963,7 +1963,7 @@ static void * const qemu_ld_helpers[16] =3D { /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, * uintxx_t val, int mmu_idx, uintptr_t ra) */ -static void * const qemu_st_helpers[16] =3D { +static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c16f96b401..6264e58b3a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -852,7 +852,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) */ -static void * const qemu_ld_helpers[8] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, #ifdef HOST_WORDS_BIGENDIAN @@ -878,7 +878,7 @@ static void * const qemu_ld_helpers[8] =3D { * uintxx_t val, TCGMemOpIdx oi, * uintptr_t ra) */ -static void * const qemu_st_helpers[4] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_stb_mmu, #ifdef HOST_WORDS_BIGENDIAN [MO_16] =3D helper_be_stw_mmu, diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index b82cf19f09..67a2ba5ff3 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -350,7 +350,7 @@ static const uint8_t tcg_cond_to_ltr_cond[] =3D { }; =20 #ifdef CONFIG_SOFTMMU -static void * const qemu_ld_helpers[16] =3D { +static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, [MO_LEUW] =3D helper_le_lduw_mmu, @@ -365,7 +365,7 @@ static void * const qemu_ld_helpers[16] =3D { [MO_BEQ] =3D helper_be_ldq_mmu, }; =20 -static void * const qemu_st_helpers[16] =3D { +static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 688827968b..b9bce29282 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -847,8 +847,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } =20 #ifdef CONFIG_SOFTMMU -static const tcg_insn_unit *qemu_ld_trampoline[16]; -static const tcg_insn_unit *qemu_st_trampoline[16]; +static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1]; +static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1]; =20 static void emit_extend(TCGContext *s, TCGReg r, int op) { @@ -875,7 +875,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) =20 static void build_trampolines(TCGContext *s) { - static void * const qemu_ld_helpers[16] =3D { + static void * const qemu_ld_helpers[] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, [MO_LEUW] =3D helper_le_lduw_mmu, @@ -887,7 +887,7 @@ static void build_trampolines(TCGContext *s) [MO_BEUL] =3D helper_be_ldul_mmu, [MO_BEQ] =3D helper_be_ldq_mmu, }; - static void * const qemu_st_helpers[16] =3D { + static void * const qemu_st_helpers[] =3D { [MO_UB] =3D helper_ret_stb_mmu, [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, @@ -900,7 +900,7 @@ static void build_trampolines(TCGContext *s) int i; TCGReg ra; =20 - for (i =3D 0; i < 16; ++i) { + for (i =3D 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) { if (qemu_ld_helpers[i] =3D=3D NULL) { continue; } @@ -928,7 +928,7 @@ static void build_trampolines(TCGContext *s) tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); } =20 - for (i =3D 0; i < 16; ++i) { + for (i =3D 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) { if (qemu_st_helpers[i] =3D=3D NULL) { continue; } @@ -1110,7 +1110,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, } #endif /* CONFIG_SOFTMMU */ =20 -static const int qemu_ld_opc[16] =3D { +static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D LDUB, [MO_SB] =3D LDSB, =20 @@ -1127,7 +1127,7 @@ static const int qemu_ld_opc[16] =3D { [MO_LEQ] =3D LDX_LE, }; =20 -static const int qemu_st_opc[16] =3D { +static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_UB] =3D STB, =20 [MO_BEUW] =3D STH, --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:19:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/66] tcg: Rename TCGMemOpIdx to MemOpIdx Date: Wed, 18 Aug 2021 09:18:38 -1000 Message-Id: <20210818191920.390759-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316111762100002 We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- accel/tcg/atomic_template.h | 24 +++++------ include/tcg/tcg.h | 74 ++++++++++++++++----------------- accel/tcg/cputlb.c | 78 +++++++++++++++++------------------ accel/tcg/user-exec.c | 2 +- target/arm/helper-a64.c | 16 +++---- target/arm/m_helper.c | 2 +- target/i386/tcg/mem_helper.c | 4 +- target/m68k/op_helper.c | 2 +- target/mips/tcg/msa_helper.c | 6 +-- target/s390x/tcg/mem_helper.c | 20 ++++----- target/sparc/ldst_helper.c | 2 +- tcg/optimize.c | 2 +- tcg/tcg-op.c | 12 +++--- tcg/tcg.c | 2 +- tcg/tci.c | 14 +++---- accel/tcg/atomic_common.c.inc | 6 +-- tcg/aarch64/tcg-target.c.inc | 14 +++---- tcg/arm/tcg-target.c.inc | 10 ++--- tcg/i386/tcg-target.c.inc | 10 ++--- tcg/mips/tcg-target.c.inc | 12 +++--- tcg/ppc/tcg-target.c.inc | 10 ++--- tcg/riscv/tcg-target.c.inc | 16 +++---- tcg/s390/tcg-target.c.inc | 10 ++--- tcg/sparc/tcg-target.c.inc | 4 +- tcg/tcg-ldst.c.inc | 2 +- 25 files changed, 177 insertions(+), 177 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 8098a1be31..4230ff2957 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -72,7 +72,7 @@ =20 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE cmpv, ABI_TYPE newv, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); @@ -92,7 +92,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, #if DATA_SIZE >=3D 16 #if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); @@ -106,7 +106,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, } =20 void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); @@ -119,7 +119,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, #endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); @@ -134,7 +134,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, =20 #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ + ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ @@ -167,7 +167,7 @@ GEN_ATOMIC_HELPER(xor_fetch) */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ + ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ @@ -211,7 +211,7 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) =20 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE cmpv, ABI_TYPE newv, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); @@ -231,7 +231,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, #if DATA_SIZE >=3D 16 #if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); @@ -245,7 +245,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, } =20 void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); @@ -259,7 +259,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, #endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); @@ -274,7 +274,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, =20 #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ + ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ @@ -304,7 +304,7 @@ GEN_ATOMIC_HELPER(xor_fetch) */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ + ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 44ccd86f3e..f91ebd0743 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1148,7 +1148,7 @@ static inline size_t tcg_current_code_size(TCGContext= *s) } =20 /* Combine the MemOp and mmu_idx parameters into a single value. */ -typedef uint32_t TCGMemOpIdx; +typedef uint32_t MemOpIdx; =20 /** * make_memop_idx @@ -1157,7 +1157,7 @@ typedef uint32_t TCGMemOpIdx; * * Encode these values into a single parameter. */ -static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx) +static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx) { tcg_debug_assert(idx <=3D 15); return (op << 4) | idx; @@ -1169,7 +1169,7 @@ static inline TCGMemOpIdx make_memop_idx(MemOp op, un= signed idx) * * Extract the memory operation from the combined value. */ -static inline MemOp get_memop(TCGMemOpIdx oi) +static inline MemOp get_memop(MemOpIdx oi) { return oi >> 4; } @@ -1180,7 +1180,7 @@ static inline MemOp get_memop(TCGMemOpIdx oi) * * Extract the mmu index from the combined value. */ -static inline unsigned get_mmuidx(TCGMemOpIdx oi) +static inline unsigned get_mmuidx(MemOpIdx oi) { return oi & 15; } @@ -1278,46 +1278,46 @@ uint64_t dup_const(unsigned vece, uint64_t c); #ifdef CONFIG_SOFTMMU /* Value zero-extended to tcg register size. */ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 /* Value sign-extended to tcg register size. */ tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 /* Temporary aliases until backends are converted. */ #ifdef TARGET_WORDS_BIGENDIAN @@ -1345,30 +1345,30 @@ void helper_be_stq_mmu(CPUArchState *env, target_ul= ong addr, uint64_t val, =20 uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t cmpv, uint64_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t cmpv, uint64_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ (CPUArchState *env, target_ulong addr, TYPE val, \ - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPER_ALL(NAME) \ @@ -1415,19 +1415,19 @@ GEN_ATOMIC_HELPER_ALL(xchg) =20 Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index acdd20b1bc..2dfbc29a0c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1740,7 +1740,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong ad= dr, int mmu_idx, * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, int size, int prot, + MemOpIdx oi, int size, int prot, uintptr_t retaddr) { size_t mmu_idx =3D get_mmuidx(oi); @@ -1841,7 +1841,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, */ =20 typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); + MemOpIdx oi, uintptr_t retaddr); =20 static inline uint64_t QEMU_ALWAYS_INLINE load_memop(const void *haddr, MemOp op) @@ -1867,7 +1867,7 @@ load_memop(const void *haddr, MemOp op) } =20 static inline uint64_t QEMU_ALWAYS_INLINE -load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, +load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load) { @@ -1982,78 +1982,78 @@ load_helper(CPUArchState *env, target_ulong addr, T= CGMemOpIdx oi, */ =20 static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu= ); } =20 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return full_ldub_mmu(env, addr, oi, retaddr); } =20 static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } =20 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return full_le_lduw_mmu(env, addr, oi, retaddr); } =20 static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } =20 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return full_be_lduw_mmu(env, addr, oi, retaddr); } =20 static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } =20 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return full_le_ldul_mmu(env, addr, oi, retaddr); } =20 static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } =20 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return full_be_ldul_mmu(env, addr, oi, retaddr); } =20 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } =20 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); @@ -2066,31 +2066,31 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, targe= t_ulong addr, =20 =20 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); } =20 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); } =20 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); } =20 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr); } =20 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr); } @@ -2104,7 +2104,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *= env, abi_ptr addr, MemOp op, FullLoadHelper *full_load) { uint16_t meminfo; - TCGMemOpIdx oi; + MemOpIdx oi; uint64_t ret; =20 meminfo =3D trace_mem_get_info(op, mmu_idx, false); @@ -2328,7 +2328,7 @@ store_helper_unaligned(CPUArchState *env, target_ulon= g addr, uint64_t val, uintptr_t index, index2; CPUTLBEntry *entry, *entry2; target_ulong page2, tlb_addr, tlb_addr2; - TCGMemOpIdx oi; + MemOpIdx oi; size_t size2; int i; =20 @@ -2395,7 +2395,7 @@ store_helper_unaligned(CPUArchState *env, target_ulon= g addr, uint64_t val, =20 static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) + MemOpIdx oi, uintptr_t retaddr, MemOp op) { uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); @@ -2493,43 +2493,43 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, =20 void __attribute__((noinline)) helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_UB); } =20 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_LEUW); } =20 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_BEUW); } =20 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_LEUL); } =20 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_BEUL); } =20 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_LEQ); } =20 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, MO_BEQ); } @@ -2542,7 +2542,7 @@ static inline void QEMU_ALWAYS_INLINE cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, int mmu_idx, uintptr_t retaddr, MemOp op) { - TCGMemOpIdx oi; + MemOpIdx oi; uint16_t meminfo; =20 meminfo =3D trace_mem_get_info(op, mmu_idx, true); @@ -2708,49 +2708,49 @@ void cpu_stq_le_data(CPUArchState *env, target_ulon= g ptr, uint64_t val) /* Code access functions. */ =20 static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code); } =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); return full_ldub_code(env, addr, oi, 0); } =20 static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_co= de); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { - TCGMemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); return full_lduw_code(env, addr, oi, 0); } =20 static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_cod= e); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { - TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); return full_ldl_code(env, addr, oi, 0); } =20 static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code= ); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ, cpu_mmu_index(env, true)); + MemOpIdx oi =3D make_memop_idx(MO_TEQ, cpu_mmu_index(env, true)); return full_ldq_code(env, addr, oi, 0); } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e687b9652e..eab2b9804d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1195,7 +1195,7 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, int size, int prot, + MemOpIdx oi, int size, int prot, uintptr_t retaddr) { MemOp mop =3D get_memop(oi); diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 26f79f9141..13d1e3f808 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -531,8 +531,8 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, clear_helper_retaddr(); #else int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); + MemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); =20 o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); @@ -555,7 +555,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, uintptr_t ra =3D GETPC(); bool success; int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; =20 assert(HAVE_CMPXCHG128); =20 @@ -601,8 +601,8 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, clear_helper_retaddr(); #else int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); + MemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); =20 o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); @@ -625,7 +625,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, uintptr_t ra =3D GETPC(); bool success; int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; =20 assert(HAVE_CMPXCHG128); =20 @@ -651,7 +651,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, Int128 oldv, cmpv, newv; uintptr_t ra =3D GETPC(); int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; =20 assert(HAVE_CMPXCHG128); =20 @@ -672,7 +672,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, Int128 oldv, cmpv, newv; uintptr_t ra =3D GETPC(); int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; =20 assert(HAVE_CMPXCHG128); =20 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 20761c9487..efb522dc44 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1930,7 +1930,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) =20 { bool threadmode, spsel; - TCGMemOpIdx oi; + MemOpIdx oi; ARMMMUIdx mmu_idx; uint32_t *frame_sp_p; uint32_t frameptr; diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 2da3cd14b6..0fd696f9c1 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -67,7 +67,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) { uintptr_t ra =3D GETPC(); int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ, mem_idx); + MemOpIdx oi =3D make_memop_idx(MO_TEQ, mem_idx); oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); } =20 @@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); =20 int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); =20 if (int128_eq(oldv, cmpv)) { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d006d1cb3e..5918a29516 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -785,7 +785,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, uintptr_t ra =3D GETPC(); #if defined(CONFIG_ATOMIC64) int mmu_idx =3D cpu_mmu_index(env, 0); - TCGMemOpIdx oi =3D make_memop_idx(MO_BEQ, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_BEQ, mmu_idx); #endif =20 if (parallel) { diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 04af54f66d..167d9a591c 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8211,9 +8211,9 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) =20 #if !defined(CONFIG_USER_ONLY) -#define MEMOP_IDX(DF) \ - TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); +#define MEMOP_IDX(DF) \ + MemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ + cpu_mmu_index(env, false)); #else #define MEMOP_IDX(DF) #endif diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 21a4de4067..ec88f5dbb0 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -238,7 +238,7 @@ static void do_access_memset(CPUS390XState *env, vaddr = vaddr, char *haddr, g_assert(haddr); memset(haddr, byte, size); #else - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); int i; =20 if (likely(haddr)) { @@ -281,7 +281,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, v= addr vaddr, char **haddr, #ifdef CONFIG_USER_ONLY return ldub_p(*haddr + offset); #else - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); uint8_t byte; =20 if (likely(*haddr)) { @@ -315,7 +315,7 @@ static void do_access_set_byte(CPUS390XState *env, vadd= r vaddr, char **haddr, #ifdef CONFIG_USER_ONLY stb_p(*haddr + offset, byte); #else - TCGMemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); =20 if (likely(*haddr)) { stb_p(*haddr + offset, byte); @@ -1803,7 +1803,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; Int128 oldv; bool fail; =20 @@ -1883,7 +1883,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint32_t *haddr =3D g2h(env_cpu(env), a1); ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); #else - TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_= idx); + MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx= ); ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra); #endif } else { @@ -1903,7 +1903,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, =20 if (parallel) { #ifdef CONFIG_ATOMIC64 - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_i= dx); + MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx); ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra); #else /* Note that we asserted !parallel above. */ @@ -1939,7 +1939,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); } else if (HAVE_CMPXCHG128) { - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_i= dx); ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc =3D !int128_eq(ov, cv); } else { @@ -1978,7 +1978,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, cpu_stq_data_ra(env, a2 + 0, svh, ra); cpu_stq_data_ra(env, a2 + 8, svl, ra); } else if (HAVE_ATOMIC128) { - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_i= dx); Int128 sv =3D int128_make128(svl, svh); cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra); } else { @@ -2474,7 +2474,7 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uin= t64_t addr) uintptr_t ra =3D GETPC(); uint64_t hi, lo; int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; Int128 v; =20 assert(HAVE_ATOMIC128); @@ -2505,7 +2505,7 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64= _t addr, { uintptr_t ra =3D GETPC(); int mem_idx; - TCGMemOpIdx oi; + MemOpIdx oi; Int128 v; =20 assert(HAVE_ATOMIC128); diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index ea163200a4..299fc386ea 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1313,7 +1313,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, case ASI_SNF: case ASI_SNFL: { - TCGMemOpIdx oi; + MemOpIdx oi; int idx =3D (env->pstate & PS_PRIV ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_= IDX) : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)= ); diff --git a/tcg/optimize.c b/tcg/optimize.c index 9876ac52a8..c239c3bd07 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1023,7 +1023,7 @@ void tcg_optimize(TCGContext *s) =20 CASE_OP_32_64(qemu_ld): { - TCGMemOpIdx oi =3D op->args[nb_oargs + nb_iargs]; + MemOpIdx oi =3D op->args[nb_oargs + nb_iargs]; MemOp mop =3D get_memop(oi); if (!(mop & MO_SIGN)) { mask =3D (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e01f68f44d..e1490c372e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2797,7 +2797,7 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, = bool is64, bool st) static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, MemOp memop, TCGArg idx) { - TCGMemOpIdx oi =3D make_memop_idx(memop, idx); + MemOpIdx oi =3D make_memop_idx(memop, idx); #if TARGET_LONG_BITS =3D=3D 32 tcg_gen_op3i_i32(opc, val, addr, oi); #else @@ -2812,7 +2812,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, MemOp memop, TCGArg idx) { - TCGMemOpIdx oi =3D make_memop_idx(memop, idx); + MemOpIdx oi =3D make_memop_idx(memop, idx); #if TARGET_LONG_BITS =3D=3D 32 if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); @@ -3132,7 +3132,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, tcg_temp_free_i32(t1); } else { gen_atomic_cx_i32 gen; - TCGMemOpIdx oi; + MemOpIdx oi; =20 gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); @@ -3171,7 +3171,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, } else if ((memop & MO_SIZE) =3D=3D MO_64) { #ifdef CONFIG_ATOMIC64 gen_atomic_cx_i64 gen; - TCGMemOpIdx oi; + MemOpIdx oi; =20 gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); @@ -3227,7 +3227,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr,= TCGv_i32 val, TCGArg idx, MemOp memop, void * const table[]) { gen_atomic_op_i32 gen; - TCGMemOpIdx oi; + MemOpIdx oi; =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 @@ -3269,7 +3269,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr,= TCGv_i64 val, if ((memop & MO_SIZE) =3D=3D MO_64) { #ifdef CONFIG_ATOMIC64 gen_atomic_op_i64 gen; - TCGMemOpIdx oi; + MemOpIdx oi; =20 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); diff --git a/tcg/tcg.c b/tcg/tcg.c index 4142d42d77..658be0c6b6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1910,7 +1910,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_pre= fs) case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: { - TCGMemOpIdx oi =3D op->args[k++]; + MemOpIdx oi =3D op->args[k++]; MemOp op =3D get_memop(oi); unsigned ix =3D get_mmuidx(oi); =20 diff --git a/tcg/tci.c b/tcg/tci.c index b672c7cae5..5c08dc0a9a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -61,7 +61,7 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) * i =3D immediate (uint32_t) * I =3D immediate (tcg_target_ulong) * l =3D label or pointer - * m =3D immediate (TCGMemOpIdx) + * m =3D immediate (MemOpIdx) * n =3D immediate (call return length) * r =3D register * s =3D signed ldst offset @@ -105,7 +105,7 @@ static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_= target_ulong *i1) } =20 static void tci_args_rrm(uint32_t insn, TCGReg *r0, - TCGReg *r1, TCGMemOpIdx *m2) + TCGReg *r1, MemOpIdx *m2) { *r0 =3D extract32(insn, 8, 4); *r1 =3D extract32(insn, 12, 4); @@ -145,7 +145,7 @@ static void tci_args_rrrc(uint32_t insn, } =20 static void tci_args_rrrm(uint32_t insn, - TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx = *m3) + TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3) { *r0 =3D extract32(insn, 8, 4); *r1 =3D extract32(insn, 12, 4); @@ -289,7 +289,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) } =20 static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, - TCGMemOpIdx oi, const void *tb_ptr) + MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi) & (MO_BSWAP | MO_SSIZE); uintptr_t ra =3D (uintptr_t)tb_ptr; @@ -374,7 +374,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_u= long taddr, } =20 static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, - TCGMemOpIdx oi, const void *tb_ptr) + MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi) & (MO_BSWAP | MO_SSIZE); uintptr_t ra =3D (uintptr_t)tb_ptr; @@ -482,7 +482,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t tmp32; uint64_t tmp64; uint64_t T1, T2; - TCGMemOpIdx oi; + MemOpIdx oi; int32_t ofs; void *ptr; =20 @@ -1148,7 +1148,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) tcg_target_ulong i1; int32_t s2; TCGCond c; - TCGMemOpIdx oi; + MemOpIdx oi; uint8_t pos, len; void *ptr; =20 diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6c0339f610..ebaa793464 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -14,7 +14,7 @@ */ =20 static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi) + MemOpIdx oi) { CPUState *cpu =3D env_cpu(env); uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); @@ -34,7 +34,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, targ= et_ulong addr, =20 #if HAVE_ATOMIC128 static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi) + MemOpIdx oi) { uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); =20 @@ -50,7 +50,7 @@ static void atomic_trace_ld_post(CPUArchState *env, targe= t_ulong addr, } =20 static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi) + MemOpIdx oi) { uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), tr= ue); =20 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 6f43c048a5..5edca8d44d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1545,7 +1545,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, #include "../tcg-ldst.c.inc" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * TCGMemOpIdx oi, uintptr_t ra) + * MemOpIdx oi, uintptr_t ra) */ static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { [MO_8] =3D helper_ret_ldub_mmu, @@ -1561,7 +1561,7 @@ static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { }; =20 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, TCGMemOpIdx oi, + * uintxx_t val, MemOpIdx oi, * uintptr_t ra) */ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { @@ -1586,7 +1586,7 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg = rd, const void *target) =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); MemOp size =3D opc & MO_SIZE; =20 @@ -1611,7 +1611,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); MemOp size =3D opc & MO_SIZE; =20 @@ -1629,7 +1629,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) return true; } =20 -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, TCGType ext, TCGReg data_reg, TCGReg addr_= reg, tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) { @@ -1778,7 +1778,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op memop, } =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - TCGMemOpIdx oi, TCGType ext) + MemOpIdx oi, TCGType ext) { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; @@ -1803,7 +1803,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - TCGMemOpIdx oi) + MemOpIdx oi) { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8939b2c2da..cbe3057a9d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1588,7 +1588,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrl= o, TCGReg addrhi, tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) @@ -1608,7 +1608,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); void *func; =20 @@ -1672,7 +1672,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1801,7 +1801,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, MemOp opc, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1906,7 +1906,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext = *s, MemOp opc, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 5fd4e4392f..1e42a877fb 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1740,7 +1740,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, * for a load or store, so that we can later generate the correct helper c= ode */ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - TCGMemOpIdx oi, + MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, tcg_insn_unit *raddr, @@ -1767,7 +1767,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); TCGReg data_reg; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; @@ -1852,7 +1852,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) */ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; @@ -2053,7 +2053,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; @@ -2142,7 +2142,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index cc279205d6..02dc4b63ae 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1140,7 +1140,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); * Clobbers TMP0, TMP1, TMP2, TMP3. */ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, TCGMemOpIdx oi, + TCGReg addrh, MemOpIdx oi, tcg_insn_unit *label_ptr[2], bool is_load) { MemOp opc =3D get_memop(oi); @@ -1216,7 +1216,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); } =20 -static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, TCGType ext, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, @@ -1241,7 +1241,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); TCGReg v0; int i; @@ -1295,7 +1295,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; int i; @@ -1454,7 +1454,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -1556,7 +1556,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3fef2aa6b2..2d4ca1f445 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2088,7 +2088,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2107,7 +2107,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); TCGReg hi, lo, arg =3D TCG_REG_R3; =20 @@ -2154,7 +2154,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; TCGReg hi, lo, arg =3D TCG_REG_R3; @@ -2218,7 +2218,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; @@ -2293,7 +2293,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6264e58b3a..c1b0c3764d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -850,7 +850,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) #include "../tcg-ldst.c.inc" =20 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * TCGMemOpIdx oi, uintptr_t ra) + * MemOpIdx oi, uintptr_t ra) */ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, @@ -875,7 +875,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { }; =20 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, TCGMemOpIdx oi, + * uintxx_t val, MemOpIdx oi, * uintptr_t ra) */ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { @@ -906,7 +906,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_= unit *target) } =20 static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, TCGMemOpIdx oi, + TCGReg addrh, MemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) { MemOp opc =3D get_memop(oi); @@ -959,7 +959,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); } =20 -static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, TCGType ext, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, @@ -980,7 +980,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_l= d, TCGMemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); TCGReg a0 =3D tcg_target_call_iarg_regs[0]; TCGReg a1 =3D tcg_target_call_iarg_regs[1]; @@ -1012,7 +1012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - TCGMemOpIdx oi =3D l->oi; + MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; TCGReg a0 =3D tcg_target_call_iarg_regs[0]; @@ -1104,7 +1104,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; @@ -1173,7 +1173,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; - TCGMemOpIdx oi; + MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 67a2ba5ff3..fd0b3316d2 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1547,7 +1547,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, return addr_reg; } =20 -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, TCGReg data, TCGReg addr, tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) { @@ -1565,7 +1565,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, @@ -1590,7 +1590,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; - TCGMemOpIdx oi =3D lb->oi; + MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, @@ -1644,7 +1644,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - TCGMemOpIdx oi) + MemOpIdx oi) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1671,7 +1671,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - TCGMemOpIdx oi) + MemOpIdx oi) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index b9bce29282..0e3f460584 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1140,7 +1140,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1= ] =3D { }; =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOpIdx oi, bool is_64) + MemOpIdx oi, bool is_64) { MemOp memop =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1222,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOpIdx oi) + MemOpIdx oi) { MemOp memop =3D get_memop(oi); #ifdef CONFIG_SOFTMMU diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index c3ce88e69d..6c6848d034 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -22,7 +22,7 @@ =20 typedef struct TCGLabelQemuLdst { bool is_ld; /* qemu_ld: true, qemu_st: false */ - TCGMemOpIdx oi; + MemOpIdx oi; TCGType type; /* result type of a load */ TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:19:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/66] tcg: Split out MemOpIdx to exec/memopidx.h Date: Wed, 18 Aug 2021 09:18:39 -1000 Message-Id: <20210818191920.390759-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315890339100001 Move this code from tcg/tcg.h to its own header. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/memopidx.h | 55 +++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 39 +---------------------------- 2 files changed, 56 insertions(+), 38 deletions(-) create mode 100644 include/exec/memopidx.h diff --git a/include/exec/memopidx.h b/include/exec/memopidx.h new file mode 100644 index 0000000000..83bce97874 --- /dev/null +++ b/include/exec/memopidx.h @@ -0,0 +1,55 @@ +/* + * Combine the MemOp and mmu_idx parameters into a single value. + * + * Authors: + * Richard Henderson + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC_MEMOPIDX_H +#define EXEC_MEMOPIDX_H 1 + +#include "exec/memop.h" + +typedef uint32_t MemOpIdx; + +/** + * make_memop_idx + * @op: memory operation + * @idx: mmu index + * + * Encode these values into a single parameter. + */ +static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx) +{ +#ifdef CONFIG_DEBUG_TCG + assert(idx <=3D 15); +#endif + return (op << 4) | idx; +} + +/** + * get_memop + * @oi: combined op/idx parameter + * + * Extract the memory operation from the combined value. + */ +static inline MemOp get_memop(MemOpIdx oi) +{ + return oi >> 4; +} + +/** + * get_mmuidx + * @oi: combined op/idx parameter + * + * Extract the mmu index from the combined value. + */ +static inline unsigned get_mmuidx(MemOpIdx oi) +{ + return oi & 15; +} + +#endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index f91ebd0743..e67ef34694 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -27,6 +27,7 @@ =20 #include "cpu.h" #include "exec/memop.h" +#include "exec/memopidx.h" #include "qemu/bitops.h" #include "qemu/plugin.h" #include "qemu/queue.h" @@ -1147,44 +1148,6 @@ static inline size_t tcg_current_code_size(TCGContex= t *s) return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); } =20 -/* Combine the MemOp and mmu_idx parameters into a single value. */ -typedef uint32_t MemOpIdx; - -/** - * make_memop_idx - * @op: memory operation - * @idx: mmu index - * - * Encode these values into a single parameter. - */ -static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx) -{ - tcg_debug_assert(idx <=3D 15); - return (op << 4) | idx; -} - -/** - * get_memop - * @oi: combined op/idx parameter - * - * Extract the memory operation from the combined value. - */ -static inline MemOp get_memop(MemOpIdx oi) -{ - return oi >> 4; -} - -/** - * get_mmuidx - * @oi: combined op/idx parameter - * - * Extract the mmu index from the combined value. - */ -static inline unsigned get_mmuidx(MemOpIdx oi) -{ - return oi & 15; -} - /** * tcg_qemu_tb_exec: * @env: pointer to CPUArchState for the CPU --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316258; cv=none; d=zohomail.com; s=zohoarc; b=EZwtjZ+AK57Xvg+r1yA1vwVkiBKaZKxtcOSfhycd9drVyBhk8F8/s9YOtVyhYuttzaCmAKZfajWJSp9ocSpgHsbSE8dqE7TkbhsAEtwFKvlVgLVbLDmBioQAe7AaFdKkzmjuWNfMcX3y2qwZDI6/BDf5xx1OCnZIfErS8Se+pxk= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:19:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 26/66] trace/mem: Pass MemOpIdx to trace_mem_get_info Date: Wed, 18 Aug 2021 09:18:40 -1000 Message-Id: <20210818191920.390759-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316260666100001 Content-Type: text/plain; charset="utf-8" We (will) often have the complete MemOpIdx handy, so use that. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- trace/mem.h | 32 +++++++++----------------- accel/tcg/cputlb.c | 12 ++++------ accel/tcg/user-exec.c | 42 +++++++++++++++++++++++------------ tcg/tcg-op.c | 8 +++---- accel/tcg/atomic_common.c.inc | 6 ++--- 5 files changed, 49 insertions(+), 51 deletions(-) diff --git a/trace/mem.h b/trace/mem.h index 2f27e7bdf0..699566c661 100644 --- a/trace/mem.h +++ b/trace/mem.h @@ -10,7 +10,7 @@ #ifndef TRACE__MEM_H #define TRACE__MEM_H =20 -#include "tcg/tcg.h" +#include "exec/memopidx.h" =20 #define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */ #define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */ @@ -19,45 +19,33 @@ #define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */ =20 /** - * trace_mem_build_info: + * trace_mem_get_info: * * Return a value for the 'info' argument in guest memory access traces. */ -static inline uint16_t trace_mem_build_info(int size_shift, bool sign_exte= nd, - MemOp endianness, bool store, - unsigned int mmu_idx) +static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store) { + MemOp op =3D get_memop(oi); + uint32_t size_shift =3D op & MO_SIZE; + bool sign_extend =3D op & MO_SIGN; + bool big_endian =3D (op & MO_BSWAP) =3D=3D MO_BE; uint16_t res; =20 res =3D size_shift & TRACE_MEM_SZ_SHIFT_MASK; if (sign_extend) { res |=3D TRACE_MEM_SE; } - if (endianness =3D=3D MO_BE) { + if (big_endian) { res |=3D TRACE_MEM_BE; } if (store) { res |=3D TRACE_MEM_ST; } #ifdef CONFIG_SOFTMMU - res |=3D mmu_idx << TRACE_MEM_MMU_SHIFT; + res |=3D get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT; #endif + return res; } =20 - -/** - * trace_mem_get_info: - * - * Return a value for the 'info' argument in guest memory access traces. - */ -static inline uint16_t trace_mem_get_info(MemOp op, - unsigned int mmu_idx, - bool store) -{ - return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN), - op & MO_BSWAP, store, - mmu_idx); -} - #endif /* TRACE__MEM_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2dfbc29a0c..c27658b8a2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2103,14 +2103,12 @@ static inline uint64_t cpu_load_helper(CPUArchState= *env, abi_ptr addr, int mmu_idx, uintptr_t retaddr, MemOp op, FullLoadHelper *full_load) { - uint16_t meminfo; - MemOpIdx oi; + MemOpIdx oi =3D make_memop_idx(op, mmu_idx); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; =20 - meminfo =3D trace_mem_get_info(op, mmu_idx, false); trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); =20 - oi =3D make_memop_idx(op, mmu_idx); ret =3D full_load(env, addr, oi, retaddr); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo); @@ -2542,13 +2540,11 @@ static inline void QEMU_ALWAYS_INLINE cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, int mmu_idx, uintptr_t retaddr, MemOp op) { - MemOpIdx oi; - uint16_t meminfo; + MemOpIdx oi =3D make_memop_idx(op, mmu_idx); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - meminfo =3D trace_mem_get_info(op, mmu_idx, true); trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); =20 - oi =3D make_memop_idx(op, mmu_idx); store_helper(env, addr, val, oi, retaddr, op); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index eab2b9804d..68d9c1b33d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -855,8 +855,9 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldub_p(g2h(env_cpu(env), ptr)); @@ -871,8 +872,9 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) =20 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); @@ -887,8 +889,9 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) =20 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); @@ -898,8 +901,9 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) =20 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); @@ -909,8 +913,9 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) =20 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); @@ -925,8 +930,9 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) =20 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); @@ -936,8 +942,9 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) =20 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) { + MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; - uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); @@ -1032,7 +1039,8 @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_pt= r ptr, uintptr_t retaddr) =20 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_UB, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stb_p(g2h(env_cpu(env), ptr), val); @@ -1041,7 +1049,8 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uin= t32_t val) =20 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stw_be_p(g2h(env_cpu(env), ptr), val); @@ -1050,7 +1059,8 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stl_be_p(g2h(env_cpu(env), ptr), val); @@ -1059,7 +1069,8 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stq_be_p(g2h(env_cpu(env), ptr), val); @@ -1068,7 +1079,8 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) =20 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stw_le_p(g2h(env_cpu(env), ptr), val); @@ -1077,7 +1089,8 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stl_le_p(g2h(env_cpu(env), ptr), val); @@ -1086,7 +1099,8 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) { - uint16_t meminfo =3D trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); + MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); + uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stq_le_p(g2h(env_cpu(env), ptr), val); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e1490c372e..37b440af7f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2866,7 +2866,7 @@ static inline void plugin_gen_mem_callbacks(TCGv vadd= r, uint16_t info) void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { MemOp orig_memop; - uint16_t info =3D trace_mem_get_info(memop, idx, 0); + uint16_t info =3D trace_mem_get_info(make_memop_idx(memop, idx), 0); =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -2904,7 +2904,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { TCGv_i32 swap =3D NULL; - uint16_t info =3D trace_mem_get_info(memop, idx, 1); + uint16_t info =3D trace_mem_get_info(make_memop_idx(memop, idx), 1); =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); @@ -2956,7 +2956,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); - info =3D trace_mem_get_info(memop, idx, 0); + info =3D trace_mem_get_info(make_memop_idx(memop, idx), 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 orig_memop =3D memop; @@ -3004,7 +3004,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); - info =3D trace_mem_get_info(memop, idx, 1); + info =3D trace_mem_get_info(make_memop_idx(memop, idx), 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index ebaa793464..6019a957b9 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -17,7 +17,7 @@ static uint16_t atomic_trace_rmw_pre(CPUArchState *env, t= arget_ulong addr, MemOpIdx oi) { CPUState *cpu =3D env_cpu(env); - uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); + uint16_t info =3D trace_mem_get_info(oi, false); =20 trace_guest_mem_before_exec(cpu, addr, info); trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); @@ -36,7 +36,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, targ= et_ulong addr, static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); + uint16_t info =3D trace_mem_get_info(oi, false); =20 trace_guest_mem_before_exec(env_cpu(env), addr, info); =20 @@ -52,7 +52,7 @@ static void atomic_trace_ld_post(CPUArchState *env, targe= t_ulong addr, static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), tr= ue); + uint16_t info =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), addr, info); =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315466; cv=none; d=zohomail.com; s=zohoarc; b=bL+/+t1IJFPBErQmVLmGuXHCViRL5uvfpQZaVR4vQLEoXXUgAcey0W4DQlDdEhVvudSE0m1bhKzDAyH0w92T2w2ImJ3f2QZNEoW6rHuiWTzrZMvzgqHYwX4KMp+n6+sc6b0TuoaLHUnF8GEOYEwhpACf4zqf+8ACeTQUCMUbLsw= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:19:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/66] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Date: Wed, 18 Aug 2021 09:18:41 -1000 Message-Id: <20210818191920.390759-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315467729100001 We will shortly use the MemOpIdx directly, but in the meantime re-compute the trace meminfo. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 48 +++++++++++++++++------------------ accel/tcg/atomic_common.c.inc | 30 +++++++++++----------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 4230ff2957..c08d859a8a 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -77,15 +77,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 + atomic_trace_rmw_pre(env, addr, oi); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, cmpv, newv); #else ret =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); #endif ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, info); + atomic_trace_rmw_post(env, addr, oi); return ret; } =20 @@ -97,11 +97,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); DATA_TYPE val; - uint16_t info =3D atomic_trace_ld_pre(env, addr, oi); =20 + atomic_trace_ld_pre(env, addr, oi); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; - atomic_trace_ld_post(env, addr, info); + atomic_trace_ld_post(env, addr, oi); return val; } =20 @@ -110,11 +110,11 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong = addr, ABI_TYPE val, { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); - uint16_t info =3D atomic_trace_st_pre(env, addr, oi); =20 + atomic_trace_st_pre(env, addr, oi); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; - atomic_trace_st_post(env, addr, info); + atomic_trace_st_post(env, addr, oi); } #endif #else @@ -124,11 +124,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_= ulong addr, ABI_TYPE val, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 + atomic_trace_rmw_pre(env, addr, oi); ret =3D qatomic_xchg__nocheck(haddr, val); ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, info); + atomic_trace_rmw_post(env, addr, oi); return ret; } =20 @@ -139,10 +139,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulo= ng addr, \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ + atomic_trace_rmw_pre(env, addr, oi); \ ret =3D qatomic_##X(haddr, val); \ ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, info); \ + atomic_trace_rmw_post(env, addr, oi); \ return ret; \ } =20 @@ -172,7 +172,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE cmp, old, new, val =3D xval; \ - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ + atomic_trace_rmw_pre(env, addr, oi); \ smp_mb(); \ cmp =3D qatomic_read__nocheck(haddr); \ do { \ @@ -180,7 +180,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ cmp =3D qatomic_cmpxchg__nocheck(haddr, old, new); \ } while (cmp !=3D old); \ ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, info); \ + atomic_trace_rmw_post(env, addr, oi); \ return RET; \ } =20 @@ -216,15 +216,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 + atomic_trace_rmw_pre(env, addr, oi); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); #else ret =3D qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); #endif ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, info); + atomic_trace_rmw_post(env, addr, oi); return BSWAP(ret); } =20 @@ -236,11 +236,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ul= ong addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); DATA_TYPE val; - uint16_t info =3D atomic_trace_ld_pre(env, addr, oi); =20 + atomic_trace_ld_pre(env, addr, oi); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; - atomic_trace_ld_post(env, addr, info); + atomic_trace_ld_post(env, addr, oi); return BSWAP(val); } =20 @@ -249,12 +249,12 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong = addr, ABI_TYPE val, { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); - uint16_t info =3D atomic_trace_st_pre(env, addr, oi); =20 + atomic_trace_st_pre(env, addr, oi); val =3D BSWAP(val); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; - atomic_trace_st_post(env, addr, info); + atomic_trace_st_post(env, addr, oi); } #endif #else @@ -264,11 +264,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_= ulong addr, ABI_TYPE val, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); ABI_TYPE ret; - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 + atomic_trace_rmw_pre(env, addr, oi); ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, info); + atomic_trace_rmw_post(env, addr, oi); return BSWAP(ret); } =20 @@ -279,10 +279,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulo= ng addr, \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ + atomic_trace_rmw_pre(env, addr, oi); \ ret =3D qatomic_##X(haddr, BSWAP(val)); \ ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, info); \ + atomic_trace_rmw_post(env, addr, oi); \ return BSWAP(ret); \ } =20 @@ -309,7 +309,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ - uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ + atomic_trace_rmw_pre(env, addr, oi); \ smp_mb(); \ ldn =3D qatomic_read__nocheck(haddr); \ do { \ @@ -317,7 +317,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ ldn =3D qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \ } while (ldo !=3D ldn); \ ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, info); \ + atomic_trace_rmw_post(env, addr, oi); \ return RET; \ } =20 diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6019a957b9..db81eb5e66 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -13,55 +13,55 @@ * See the COPYING file in the top-level directory. */ =20 -static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, - MemOpIdx oi) +static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, + MemOpIdx oi) { CPUState *cpu =3D env_cpu(env); uint16_t info =3D trace_mem_get_info(oi, false); =20 trace_guest_mem_before_exec(cpu, addr, info); trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); - - return info; } =20 static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, - uint16_t info) + MemOpIdx oi) { + uint16_t info =3D trace_mem_get_info(oi, false); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST); } =20 #if HAVE_ATOMIC128 -static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, - MemOpIdx oi) +static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, + MemOpIdx oi) { uint16_t info =3D trace_mem_get_info(oi, false); =20 trace_guest_mem_before_exec(env_cpu(env), addr, info); - - return info; } =20 static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, - uint16_t info) + MemOpIdx oi) { + uint16_t info =3D trace_mem_get_info(oi, false); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); } =20 -static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr, - MemOpIdx oi) +static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, + MemOpIdx oi) { uint16_t info =3D trace_mem_get_info(oi, true); =20 trace_guest_mem_before_exec(env_cpu(env), addr, info); - - return info; } =20 static void atomic_trace_st_post(CPUArchState *env, target_ulong addr, - uint16_t info) + MemOpIdx oi) { + uint16_t info =3D trace_mem_get_info(oi, false); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315590326100001 Content-Type: text/plain; charset="utf-8" Use the MemOpIdx directly, rather than the rearrangement of the same bits currently done by the trace infrastructure. Pass in enum qemu_plugin_mem_rw so that we are able to treat read-modify-write operations as a single operation. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/plugin.h | 26 ++++++++++++++++++++++++-- accel/tcg/cputlb.c | 4 ++-- accel/tcg/plugin-gen.c | 5 ++--- accel/tcg/user-exec.c | 28 ++++++++++++++-------------- plugins/api.c | 19 +++++++++++-------- plugins/core.c | 10 +++++----- tcg/tcg-op.c | 30 +++++++++++++++++++++--------- accel/tcg/atomic_common.c.inc | 13 +++---------- 8 files changed, 82 insertions(+), 53 deletions(-) diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 9a8438f683..b3172b147f 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "qemu/queue.h" #include "qemu/option.h" +#include "exec/memopidx.h" =20 /* * Events that plugins can subscribe to. @@ -36,6 +37,25 @@ enum qemu_plugin_event { struct qemu_plugin_desc; typedef QTAILQ_HEAD(, qemu_plugin_desc) QemuPluginList; =20 +/* + * Construct a qemu_plugin_meminfo_t. + */ +static inline qemu_plugin_meminfo_t +make_plugin_meminfo(MemOpIdx oi, enum qemu_plugin_mem_rw rw) +{ + return oi | (rw << 16); +} + +/* + * Extract the memory operation direction from a qemu_plugin_meminfo_t. + * Other portions may be extracted via get_memop and get_mmuidx. + */ +static inline enum qemu_plugin_mem_rw +get_plugin_meminfo_rw(qemu_plugin_meminfo_t i) +{ + return i >> 16; +} + #ifdef CONFIG_PLUGIN extern QemuOptsList qemu_plugin_opts; =20 @@ -180,7 +200,8 @@ qemu_plugin_vcpu_syscall(CPUState *cpu, int64_t num, ui= nt64_t a1, uint64_t a6, uint64_t a7, uint64_t a8); void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret); =20 -void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t memin= fo); +void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, + MemOpIdx oi, enum qemu_plugin_mem_rw rw); =20 void qemu_plugin_flush_cb(void); =20 @@ -244,7 +265,8 @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_= t num, int64_t ret) { } =20 static inline void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, - uint32_t meminfo) + MemOpIdx oi, + enum qemu_plugin_mem_rw rw) { } =20 static inline void qemu_plugin_flush_cb(void) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c27658b8a2..04436f98c8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2111,7 +2111,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *= env, abi_ptr addr, =20 ret =3D full_load(env, addr, oi, retaddr); =20 - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); =20 return ret; } @@ -2547,7 +2547,7 @@ cpu_store_helper(CPUArchState *env, target_ulong addr= , uint64_t val, =20 store_helper(env, addr, val, oi, retaddr, op); =20 - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 88e25c6df9..f5fd5f279c 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -45,7 +45,6 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" -#include "trace/mem.h" #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" @@ -211,9 +210,9 @@ static void gen_mem_wrapped(enum plugin_gen_cb type, const union mem_gen_fn *f, TCGv addr, uint32_t info, bool is_mem) { - int wr =3D !!(info & TRACE_MEM_ST); + enum qemu_plugin_mem_rw rw =3D get_plugin_meminfo_rw(info); =20 - gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, wr); + gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, rw); if (is_mem) { f->mem_fn(addr, info); } else { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 68d9c1b33d..d96d60a804 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -861,7 +861,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldub_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -878,7 +878,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr pt= r) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -895,7 +895,7 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -907,7 +907,7 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -919,7 +919,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr pt= r) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -936,7 +936,7 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -948,7 +948,7 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 @@ -1044,7 +1044,7 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uin= t32_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stb_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) @@ -1054,7 +1054,7 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stw_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) @@ -1064,7 +1064,7 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stl_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) @@ -1074,7 +1074,7 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stq_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) @@ -1084,7 +1084,7 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stw_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) @@ -1094,7 +1094,7 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stl_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) @@ -1104,7 +1104,7 @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) =20 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); stq_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); + qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, diff --git a/plugins/api.c b/plugins/api.c index 2d521e6ba8..bf4b9b9548 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -45,7 +45,6 @@ #include "qemu/plugin-memory.h" #include "hw/boards.h" #endif -#include "trace/mem.h" =20 /* Uninstall and Reset handlers */ =20 @@ -246,22 +245,25 @@ const char *qemu_plugin_insn_symbol(const struct qemu= _plugin_insn *insn) =20 unsigned qemu_plugin_mem_size_shift(qemu_plugin_meminfo_t info) { - return info & TRACE_MEM_SZ_SHIFT_MASK; + MemOp op =3D get_memop(info); + return op & MO_SIZE; } =20 bool qemu_plugin_mem_is_sign_extended(qemu_plugin_meminfo_t info) { - return !!(info & TRACE_MEM_SE); + MemOp op =3D get_memop(info); + return op & MO_SIGN; } =20 bool qemu_plugin_mem_is_big_endian(qemu_plugin_meminfo_t info) { - return !!(info & TRACE_MEM_BE); + MemOp op =3D get_memop(info); + return (op & MO_BSWAP) =3D=3D MO_BE; } =20 bool qemu_plugin_mem_is_store(qemu_plugin_meminfo_t info) { - return !!(info & TRACE_MEM_ST); + return get_plugin_meminfo_rw(info) & QEMU_PLUGIN_MEM_W; } =20 /* @@ -277,11 +279,12 @@ struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qem= u_plugin_meminfo_t info, { #ifdef CONFIG_SOFTMMU CPUState *cpu =3D current_cpu; - unsigned int mmu_idx =3D info >> TRACE_MEM_MMU_SHIFT; - hwaddr_info.is_store =3D info & TRACE_MEM_ST; + unsigned int mmu_idx =3D get_mmuidx(info); + enum qemu_plugin_mem_rw rw =3D get_plugin_meminfo_rw(info); + hwaddr_info.is_store =3D (rw & QEMU_PLUGIN_MEM_W) !=3D 0; =20 if (!tlb_plugin_lookup(cpu, vaddr, mmu_idx, - info & TRACE_MEM_ST, &hwaddr_info)) { + hwaddr_info.is_store, &hwaddr_info)) { error_report("invalid use of qemu_plugin_get_hwaddr"); return NULL; } diff --git a/plugins/core.c b/plugins/core.c index 6b2490f973..792262da08 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -27,7 +27,6 @@ #include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" -#include "trace/mem.h" /* mem_info macros */ #include "plugin.h" #include "qemu/compiler.h" =20 @@ -446,7 +445,8 @@ void exec_inline_op(struct qemu_plugin_dyn_cb *cb) } } =20 -void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info) +void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, + MemOpIdx oi, enum qemu_plugin_mem_rw rw) { GArray *arr =3D cpu->plugin_mem_cbs; size_t i; @@ -457,14 +457,14 @@ void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t = vaddr, uint32_t info) for (i =3D 0; i < arr->len; i++) { struct qemu_plugin_dyn_cb *cb =3D &g_array_index(arr, struct qemu_plugin_dyn_cb, i); - int w =3D !!(info & TRACE_MEM_ST) + 1; =20 - if (!(w & cb->rw)) { + if (!(rw & cb->rw)) { break; } switch (cb->type) { case PLUGIN_CB_REGULAR: - cb->f.vcpu_mem(cpu->cpu_index, info, vaddr, cb->userp); + cb->f.vcpu_mem(cpu->cpu_index, make_plugin_meminfo(oi, rw), + vaddr, cb->userp); break; case PLUGIN_CB_INLINE: exec_inline_op(cb); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 37b440af7f..af7bb851b5 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2853,10 +2853,12 @@ static inline TCGv plugin_prep_mem_callbacks(TCGv v= addr) return vaddr; } =20 -static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info) +static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi, + enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { + qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); plugin_gen_empty_mem_callback(vaddr, info); tcg_temp_free(vaddr); } @@ -2866,10 +2868,13 @@ static inline void plugin_gen_mem_callbacks(TCGv va= ddr, uint16_t info) void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { MemOp orig_memop; - uint16_t info =3D trace_mem_get_info(make_memop_idx(memop, idx), 0); + MemOpIdx oi; + uint16_t info; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); + oi =3D make_memop_idx(memop, idx); + info =3D trace_mem_get_info(oi, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 orig_memop =3D memop; @@ -2883,7 +2888,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 addr =3D plugin_prep_mem_callbacks(addr); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, info); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { @@ -2904,10 +2909,13 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, T= CGArg idx, MemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { TCGv_i32 swap =3D NULL; - uint16_t info =3D trace_mem_get_info(make_memop_idx(memop, idx), 1); + MemOpIdx oi; + uint16_t info; =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); + oi =3D make_memop_idx(memop, idx); + info =3D trace_mem_get_info(oi, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -2932,7 +2940,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) } else { gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } - plugin_gen_mem_callbacks(addr, info); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i32(swap); @@ -2942,6 +2950,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) { MemOp orig_memop; + MemOpIdx oi; uint16_t info; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { @@ -2956,7 +2965,8 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); - info =3D trace_mem_get_info(make_memop_idx(memop, idx), 0); + oi =3D make_memop_idx(memop, idx); + info =3D trace_mem_get_info(oi, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 orig_memop =3D memop; @@ -2970,7 +2980,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 addr =3D plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, info); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { int flags =3D (orig_memop & MO_SIGN @@ -2995,6 +3005,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) { TCGv_i64 swap =3D NULL; + MemOpIdx oi; uint16_t info; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { @@ -3004,7 +3015,8 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); - info =3D trace_mem_get_info(make_memop_idx(memop, idx), 1); + oi =3D make_memop_idx(memop, idx); + info =3D trace_mem_get_info(oi, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); =20 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -3028,7 +3040,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) =20 addr =3D plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, info); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i64(swap); diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index db81eb5e66..f3ab96e888 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -26,10 +26,7 @@ static void atomic_trace_rmw_pre(CPUArchState *env, targ= et_ulong addr, static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(oi, false); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW); } =20 #if HAVE_ATOMIC128 @@ -44,9 +41,7 @@ static void atomic_trace_ld_pre(CPUArchState *env, target= _ulong addr, static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(oi, false); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); } =20 static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, @@ -60,9 +55,7 @@ static void atomic_trace_st_pre(CPUArchState *env, target= _ulong addr, static void atomic_trace_st_post(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(oi, false); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } #endif =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316430289100001 There is no point in encoding load/store within a bit of the memory trace info operand. Represent atomic operations as a single read-modify-write tracepoint. Use MemOpIdx instead of inventing a form specifically for traces. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 1 - trace/mem.h | 51 ----------------------------------- accel/tcg/cputlb.c | 7 ++--- accel/tcg/user-exec.c | 43 ++++++++++------------------- tcg/tcg-op.c | 17 +++--------- accel/tcg/atomic_common.c.inc | 12 +++------ trace-events | 18 +++---------- 7 files changed, 27 insertions(+), 122 deletions(-) delete mode 100644 trace/mem.h diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index c08d859a8a..2d917b6b1f 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -19,7 +19,6 @@ */ =20 #include "qemu/plugin.h" -#include "trace/mem.h" =20 #if DATA_SIZE =3D=3D 16 # define SUFFIX o diff --git a/trace/mem.h b/trace/mem.h deleted file mode 100644 index 699566c661..0000000000 --- a/trace/mem.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Helper functions for guest memory tracing - * - * Copyright (C) 2016 Llu=C3=ADs Vilanova - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TRACE__MEM_H -#define TRACE__MEM_H - -#include "exec/memopidx.h" - -#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */ -#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */ -#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */ -#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */ -#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */ - -/** - * trace_mem_get_info: - * - * Return a value for the 'info' argument in guest memory access traces. - */ -static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store) -{ - MemOp op =3D get_memop(oi); - uint32_t size_shift =3D op & MO_SIZE; - bool sign_extend =3D op & MO_SIGN; - bool big_endian =3D (op & MO_BSWAP) =3D=3D MO_BE; - uint16_t res; - - res =3D size_shift & TRACE_MEM_SZ_SHIFT_MASK; - if (sign_extend) { - res |=3D TRACE_MEM_SE; - } - if (big_endian) { - res |=3D TRACE_MEM_BE; - } - if (store) { - res |=3D TRACE_MEM_ST; - } -#ifdef CONFIG_SOFTMMU - res |=3D get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT; -#endif - - return res; -} - -#endif /* TRACE__MEM_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 04436f98c8..3d8471810c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -34,7 +34,6 @@ #include "qemu/atomic128.h" #include "exec/translate-all.h" #include "trace/trace-root.h" -#include "trace/mem.h" #include "tb-hash.h" #include "internal.h" #ifdef CONFIG_PLUGIN @@ -2104,10 +2103,9 @@ static inline uint64_t cpu_load_helper(CPUArchState = *env, abi_ptr addr, MemOp op, FullLoadHelper *full_load) { MemOpIdx oi =3D make_memop_idx(op, mmu_idx); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); =20 ret =3D full_load(env, addr, oi, retaddr); =20 @@ -2541,9 +2539,8 @@ cpu_store_helper(CPUArchState *env, target_ulong addr= , uint64_t val, int mmu_idx, uintptr_t retaddr, MemOp op) { MemOpIdx oi =3D make_memop_idx(op, mmu_idx); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); + trace_guest_st_before_exec(env_cpu(env), addr, oi); =20 store_helper(env, addr, val, oi, retaddr, op); =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d96d60a804..246be4502d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,7 +27,6 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" -#include "trace/mem.h" #include "internal.h" =20 #undef EAX @@ -856,10 +855,9 @@ int cpu_signal_handler(int host_signum, void *pinfo, uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D ldub_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -873,10 +871,9 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -890,10 +887,9 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -902,10 +898,9 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr pt= r) uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -914,10 +909,9 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr pt= r) uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -931,10 +925,9 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint32_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -943,10 +936,9 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr pt= r) uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) { MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, false); uint64_t ret; =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_ld_before_exec(env_cpu(env), ptr, oi); ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); return ret; @@ -1040,9 +1032,8 @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_pt= r ptr, uintptr_t retaddr) void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stb_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1050,9 +1041,8 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uin= t32_t val) void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stw_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1060,9 +1050,8 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stl_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1070,9 +1059,8 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) { MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stq_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1080,9 +1068,8 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, = uint64_t val) void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stw_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1090,9 +1077,8 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) { MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stl_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } @@ -1100,9 +1086,8 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, = uint32_t val) void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) { MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); - uint16_t meminfo =3D trace_mem_get_info(oi, true); =20 - trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + trace_guest_st_before_exec(env_cpu(env), ptr, oi); stq_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); } diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index af7bb851b5..b1cfd36f29 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,7 +28,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "trace-tcg.h" -#include "trace/mem.h" #include "exec/plugin-gen.h" =20 /* Reduce the number of ifdefs below. This assumes that all uses of @@ -2869,13 +2868,11 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, T= CGArg idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; - uint16_t info; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); oi =3D make_memop_idx(memop, idx); - info =3D trace_mem_get_info(oi, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); + trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi); =20 orig_memop =3D memop; if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -2910,13 +2907,11 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, T= CGArg idx, MemOp memop) { TCGv_i32 swap =3D NULL; MemOpIdx oi; - uint16_t info; =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); oi =3D make_memop_idx(memop, idx); - info =3D trace_mem_get_info(oi, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); + trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi); =20 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { swap =3D tcg_temp_new_i32(); @@ -2951,7 +2946,6 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; - uint16_t info; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); @@ -2966,8 +2960,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); oi =3D make_memop_idx(memop, idx); - info =3D trace_mem_get_info(oi, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); + trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi); =20 orig_memop =3D memop; if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { @@ -3006,7 +2999,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) { TCGv_i64 swap =3D NULL; MemOpIdx oi; - uint16_t info; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); @@ -3016,8 +3008,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); oi =3D make_memop_idx(memop, idx); - info =3D trace_mem_get_info(oi, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info); + trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi); =20 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { swap =3D tcg_temp_new_i64(); diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index f3ab96e888..1df1f243e9 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -17,10 +17,8 @@ static void atomic_trace_rmw_pre(CPUArchState *env, targ= et_ulong addr, MemOpIdx oi) { CPUState *cpu =3D env_cpu(env); - uint16_t info =3D trace_mem_get_info(oi, false); =20 - trace_guest_mem_before_exec(cpu, addr, info); - trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); + trace_guest_rmw_before_exec(cpu, addr, oi); } =20 static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, @@ -33,9 +31,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, targ= et_ulong addr, static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(oi, false); - - trace_guest_mem_before_exec(env_cpu(env), addr, info); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); } =20 static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, @@ -47,9 +43,7 @@ static void atomic_trace_ld_post(CPUArchState *env, targe= t_ulong addr, static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, MemOpIdx oi) { - uint16_t info =3D trace_mem_get_info(oi, true); - - trace_guest_mem_before_exec(env_cpu(env), addr, info); + trace_guest_st_before_exec(env_cpu(env), addr, oi); } =20 static void atomic_trace_st_post(CPUArchState *env, target_ulong addr, diff --git a/trace-events b/trace-events index c4cca29939..a637a61eba 100644 --- a/trace-events +++ b/trace-events @@ -120,26 +120,16 @@ vcpu guest_cpu_reset(void) # tcg/tcg-op.c =20 # @vaddr: Access' virtual address. -# @info : Access' information (see below). +# @memopidx: Access' information (see below). # # Start virtual memory access (before any potential access violation). -# # Does not include memory accesses performed by devices. # -# Access information can be parsed as: -# -# struct mem_info { -# uint8_t size_shift : 4; /* interpreted as "1 << size_shift" bytes */ -# bool sign_extend: 1; /* sign-extended */ -# uint8_t endianness : 1; /* 0: little, 1: big */ -# bool store : 1; /* whether it is a store operation */ -# pad : 1; -# uint8_t mmuidx : 4; /* mmuidx (softmmu only) */ -# }; -# # Mode: user, softmmu # Targets: TCG(all) -vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=3D%d", "vaddr= =3D0x%016"PRIx64" info=3D%d" +vcpu tcg guest_ld_before(TCGv vaddr, uint32_t memopidx) "info=3D%d", "vadd= r=3D0x%016"PRIx64" memopidx=3D0x%x" +vcpu tcg guest_st_before(TCGv vaddr, uint32_t memopidx) "info=3D%d", "vadd= r=3D0x%016"PRIx64" memopidx=3D0x%x" +vcpu tcg guest_rmw_before(TCGv vaddr, uint32_t memopidx) "info=3D%d", "vad= dr=3D0x%016"PRIx64" memopidx=3D0x%x" =20 # include/user/syscall-trace.h =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:19:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 30/66] target/arm: Use MO_128 for 16 byte atomics Date: Wed, 18 Aug 2021 09:18:44 -1000 Message-Id: <20210818191920.390759-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315778487100001 Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 13d1e3f808..f06399f351 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -560,7 +560,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); @@ -630,7 +630,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); =20 /* * High and low need to be switched here because this is not actually a @@ -656,7 +656,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); @@ -677,7 +677,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315895; cv=none; d=zohomail.com; s=zohoarc; b=hQCuURWmBtBZivI4kcwvwmaWY5qN9hDpj30sAEoA44oZ72We7UYU6+wdxf1N3B9uHYj1bYWcnEMw/4/Pcz/BNbL9/huv+9Qq36L3VtNkxT4fMKEZlucNeS1V6U7GHxx+JwGhsep9Jk926T+wuHIGT5fQpFRmj4Nxa7kEPGPHy00= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:20:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/66] target/i386: Use MO_128 for 16 byte atomics Date: Wed, 18 Aug 2021 09:18:45 -1000 Message-Id: <20210818191920.390759-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315897103100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/tcg/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 0fd696f9c1..a207e624cb 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); =20 int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); =20 if (int128_eq(oldv, cmpv)) { --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316608; cv=none; d=zohomail.com; s=zohoarc; b=nG+cy2sqU72yk0ARl4K7P0Bw0UvYZuIWhFG/HySNyugrXbuJWooyVpEZA6Ur9AV86H/oSFu8q3R+nRUoEZp/Aoui73eJFVLHFLcHF5yACL7iRyKzJwvu0ycgBYd/WLUryMYOtv09JAVuvS5jc4Jy9Bqx0Z9B4LW6FWqPE5sAfqA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629316608; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316610279100001 Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..540efa858f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3461,10 +3461,12 @@ static void gen_std(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi =3D tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_i= dx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, + ctx->mem_idx)); gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_i= dx)); + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, + ctx->mem_idx)); gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); } tcg_temp_free_i32(oi); @@ -4066,11 +4068,11 @@ static void gen_lqarx(DisasContext *ctx) if (HAVE_ATOMIC128) { TCGv_i32 oi =3D tcg_temp_new_i32(); if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_AL= IGN, ctx->mem_idx)); gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_AL= IGN, ctx->mem_idx)); gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); } @@ -4121,7 +4123,7 @@ static void gen_stqcx_(DisasContext *ctx) =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { if (HAVE_CMPXCHG128) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); + TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); if (ctx->le_mode) { gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629315205390703.1897795480381; Wed, 18 Aug 2021 12:33:25 -0700 (PDT) Received: from localhost ([::1]:48540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGRJU-000368-BH for importer@patchew.org; Wed, 18 Aug 2021 15:33:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGR6d-000112-73 for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629315206580100001 Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ec88f5dbb0..3782c1c098 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1810,7 +1810,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); fail =3D !int128_eq(oldv, cmpv); =20 @@ -1939,7 +1939,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); } else if (HAVE_CMPXCHG128) { - MemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_i= dx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, = mem_idx); ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc =3D !int128_eq(ov, cv); } else { --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hexagon/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd3881..bde538fd5c 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -144,6 +144,15 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, target_ulong *pc, #endif } =20 +static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 18 Aug 2021 12:20:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 35/66] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Date: Wed, 18 Aug 2021 09:18:49 -1000 Message-Id: <20210818191920.390759-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317166350100001 Content-Type: text/plain; charset="utf-8" These functions are much closer to the softmmu helper functions, in that they take the complete MemOpIdx, and from that they may enforce required alignment. The previous cpu_ldst.h functions did not have alignment info, and so did not enforce it. Retain this by adding MO_UNALN to the MemOp that we create in calling the new functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/devel/loads-stores.rst | 52 ++++- include/exec/cpu_ldst.h | 245 ++++++++-------------- accel/tcg/cputlb.c | 392 ++++++++++++------------------------ accel/tcg/user-exec.c | 390 +++++++++++++++-------------------- accel/tcg/ldst_common.c.inc | 307 ++++++++++++++++++++++++++++ 5 files changed, 722 insertions(+), 664 deletions(-) create mode 100644 accel/tcg/ldst_common.c.inc diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index 568274baec..8f0035c821 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -68,15 +68,19 @@ Regexes for git grep - ``\`` - ``\`` =20 -``cpu_{ld,st}*_mmuidx_ra`` -~~~~~~~~~~~~~~~~~~~~~~~~~~ +``cpu_{ld,st}*_mmu`` +~~~~~~~~~~~~~~~~~~~~ =20 -These functions operate on a guest virtual address plus a context, -known as a "mmu index" or ``mmuidx``, which controls how that virtual -address is translated. The meaning of the indexes are target specific, -but specifying a particular index might be necessary if, for instance, -the helper requires an "always as non-privileged" access rather that -the default access for the current state of the guest CPU. +These functions operate on a guest virtual address, plus a context +known as a "mmu index" which controls how that virtual address is +translated, plus a ``MemOp`` which contains alignment requirements +among other things. The ``MemOp`` and mmu index are combined into +a single argument of type ``MemOpIdx``. + +The meaning of the indexes are target specific, but specifying a +particular index might be necessary if, for instance, the helper +requires a "always as non-privileged" access rather than the +default access for the current state of the guest CPU. =20 These functions may cause a guest CPU exception to be taken (e.g. for an alignment fault or MMU fault) which will result in @@ -99,6 +103,35 @@ function, which is a return address into the generated = code [#gpc]_. =20 Function names follow the pattern: =20 +load: ``cpu_ld{size}{end}_mmu(env, ptr, oi, retaddr)`` + +store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)`` + +``size`` + - ``b`` : 8 bits + - ``w`` : 16 bits + - ``l`` : 32 bits + - ``q`` : 64 bits + +``end`` + - (empty) : for target endian, or 8 bit sizes + - ``_be`` : big endian + - ``_le`` : little endian + +Regexes for git grep: + - ``\`` + - ``\`` + + +``cpu_{ld,st}*_mmuidx_ra`` +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +These functions work like the ``cpu_{ld,st}_mmu`` functions except +that the ``mmuidx`` parameter is not combined with a ``MemOp``, +and therefore there is no required alignment supplied or enforced. + +Function names follow the pattern: + load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)`` =20 store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)`` @@ -132,7 +165,8 @@ of the guest CPU, as determined by ``cpu_mmu_index(env,= false)``. =20 These are generally the preferred way to do accesses by guest virtual address from helper functions, unless the access should -be performed with a context other than the default. +be performed with a context other than the default, or alignment +should be enforced for the access. =20 Function names follow the pattern: =20 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ce6ce82618..a4dad0772f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -28,10 +28,12 @@ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr) * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr) * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr) + * cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr) * * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val) * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr) * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr) + * cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr) * * sign is: * (empty): for 32 and 64 bit sizes @@ -53,10 +55,15 @@ * The "mmuidx" suffix carries an extra mmu_idx argument that specifies * the index to use; the "data" and "code" suffixes take the index from * cpu_mmu_index(). + * + * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the + * MemOp including alignment requirements. The alignment will be enforced. */ #ifndef CPU_LDST_H #define CPU_LDST_H =20 +#include "exec/memopidx.h" + #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address * this can make bad result with g2h() and h2g() @@ -118,12 +125,10 @@ typedef target_ulong abi_ptr; =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr); uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr); - uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr); @@ -131,37 +136,31 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr p= tr); =20 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); =20 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val); - void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val); - void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val); =20 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); - void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); - void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t ra); void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, @@ -169,6 +168,71 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); =20 +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, + int mmu_idx, uintptr_t ra); + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, + int mmu_idx, uintptr_t ra); +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, + int mmu_idx, uintptr_t ra); + +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t= ra); +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, + MemOpIdx oi, uintptr_t ra); + +void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); + #if defined(CONFIG_USER_ONLY) =20 extern __thread uintptr_t helper_retaddr; @@ -193,119 +257,6 @@ static inline void clear_helper_retaddr(void) helper_retaddr =3D 0; } =20 -/* - * Provide the same *_mmuidx_ra interface as for softmmu. - * The mmu_idx argument is ignored. - */ - -static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldub_data_ra(env, addr, ra); -} - -static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsb_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_be_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_be_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_be_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, - int mmu_idx, uintptr_t ra) -{ - return cpu_lduw_le_data_ra(env, addr, ra); -} - -static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldsw_le_data_ra(env, addr, ra); -} - -static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldl_le_data_ra(env, addr, ra); -} - -static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr add= r, - int mmu_idx, uintptr_t ra) -{ - return cpu_ldq_le_data_ra(env, addr, ra); -} - -static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, uintptr_t = ra) -{ - cpu_stb_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_be_data_ra(env, addr, val, ra); -} - -static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stw_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stl_le_data_ra(env, addr, val, ra); -} - -static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, int mmu_idx, - uintptr_t ra) -{ - cpu_stq_le_data_ra(env, addr, val, ra); -} - #else =20 /* Needed for TCG_OVERSIZED_GUEST */ @@ -336,46 +287,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env= , uintptr_t mmu_idx, return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra); - -void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - -void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t retaddr); -void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t retaddr); - #endif /* defined(CONFIG_USER_ONLY) */ =20 #ifdef TARGET_WORDS_BIGENDIAN @@ -391,6 +302,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_be_mmu +# define cpu_ldl_mmu cpu_ldl_be_mmu +# define cpu_ldq_mmu cpu_ldq_be_mmu # define cpu_stw_data cpu_stw_be_data # define cpu_stl_data cpu_stl_be_data # define cpu_stq_data cpu_stq_be_data @@ -400,6 +314,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra +# define cpu_stw_mmu cpu_stw_be_mmu +# define cpu_stl_mmu cpu_stl_be_mmu +# define cpu_stq_mmu cpu_stq_be_mmu #else # define cpu_lduw_data cpu_lduw_le_data # define cpu_ldsw_data cpu_ldsw_le_data @@ -413,6 +330,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra +# define cpu_ldw_mmu cpu_ldw_le_mmu +# define cpu_ldl_mmu cpu_ldl_le_mmu +# define cpu_ldq_mmu cpu_ldq_le_mmu # define cpu_stw_data cpu_stw_le_data # define cpu_stl_data cpu_stl_le_data # define cpu_stq_data cpu_stq_le_data @@ -422,6 +342,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, # define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra +# define cpu_stw_mmu cpu_stw_le_mmu +# define cpu_stl_mmu cpu_stl_le_mmu +# define cpu_stq_mmu cpu_stq_le_mmu #endif =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3d8471810c..364d97636a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1830,6 +1830,25 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, cpu_loop_exit_atomic(env_cpu(env), retaddr); } =20 +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * In the case of the helper_*_mmu functions, we will have done this by + * using the MemOp to look up the helper during code generation. + * + * In the case of the cpu_*_mmu functions, this is up to the caller. + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) +{ +#ifdef CONFIG_DEBUG_TCG + MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have =3D=3D expected); +#endif +} + /* * Load Helpers * @@ -1983,6 +2002,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu= ); } =20 @@ -1995,6 +2015,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *en= v, target_ulong addr, static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUW); return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } @@ -2008,6 +2029,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUW); return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } @@ -2021,6 +2043,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEUL); return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } @@ -2034,6 +2057,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEUL); return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } @@ -2047,6 +2071,7 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env= , target_ulong addr, uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } @@ -2054,6 +2079,7 @@ uint64_t helper_le_ldq_mmu(CPUArchState *env, target_= ulong addr, uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); } @@ -2099,186 +2125,56 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *= env, target_ulong addr, */ =20 static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t retaddr, - MemOp op, FullLoadHelper *full_load) + MemOpIdx oi, uintptr_t retaddr, + FullLoadHelper *full_load) { - MemOpIdx oi =3D make_memop_idx(op, mmu_idx); uint64_t ret; =20 trace_guest_ld_before_exec(env_cpu(env), addr, oi); - ret =3D full_load(env, addr, oi, retaddr); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; } =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu); + return cpu_load_helper(env, addr, oi, ra, full_ldub_mmu); } =20 -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, ra, full_be_lduw_mmu); } =20 -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_be_ldul_mmu); } =20 -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); + return cpu_load_helper(env, addr, oi, MO_BEQ, helper_be_ldq_mmu); } =20 -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_le_lduw_mmu); } =20 -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_m= mu); + return cpu_load_helper(env, addr, oi, ra, full_le_ldul_mmu); } =20 -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_m= mu); -} - -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_m= mu); -} - -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_m= mu); -} - -uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr= ); -} - -int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retadd= r) -{ - return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr= ); -} - -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t ret= addr) -{ - return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t ret= addr) -{ - return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), reta= ddr); -} - -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr, - uintptr_t retaddr) -{ - return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retad= dr); -} - -uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldub_data_ra(env, ptr, 0); -} - -int cpu_ldsb_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsb_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_be_data_ra(env, ptr, 0); -} - -int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_be_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_be_data_ra(env, ptr, 0); -} - -uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_lduw_le_data_ra(env, ptr, 0); -} - -int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldsw_le_data_ra(env, ptr, 0); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldl_le_data_ra(env, ptr, 0); -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr) -{ - return cpu_ldq_le_data_ra(env, ptr, 0); + return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } =20 /* @@ -2315,6 +2211,9 @@ store_memop(void *haddr, uint64_t val, MemOp op) } } =20 +static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t va= l, + MemOpIdx oi, uintptr_t retaddr); + static void __attribute__((noinline)) store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, uintptr_t retaddr, size_t size, uintptr_t mmu_idx, @@ -2378,13 +2277,13 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, for (i =3D 0; i < size; ++i) { /* Big-endian extract. */ uint8_t val8 =3D val >> (((size - 1) * 8) - (i * 8)); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } else { for (i =3D 0; i < size; ++i) { /* Little-endian extract. */ uint8_t val8 =3D val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); + full_stb_mmu(env, addr + i, val8, oi, retaddr); } } } @@ -2487,46 +2386,83 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, store_memop(haddr, val, op); } =20 -void __attribute__((noinline)) -helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr) +static void __attribute__((noinline)) +full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_UB); store_helper(env, addr, val, oi, retaddr, MO_UB); } =20 +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + full_stb_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUW); + store_helper(env, addr, val, oi, retaddr, MO_LEUW); +} + void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUW); + full_le_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUW); + store_helper(env, addr, val, oi, retaddr, MO_BEUW); } =20 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUW); + full_be_stw_mmu(env, addr, val, oi, retaddr); +} + +static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_LEUL); + store_helper(env, addr, val, oi, retaddr, MO_LEUL); } =20 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_LEUL); + full_le_stl_mmu(env, addr, val, oi, retaddr); +} + +static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, + MemOpIdx oi, uintptr_t retaddr) +{ + validate_memop(oi, MO_BEUL); + store_helper(env, addr, val, oi, retaddr, MO_BEUL); } =20 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, MO_BEUL); + full_be_stl_mmu(env, addr, val, oi, retaddr); } =20 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_LEQ); store_helper(env, addr, val, oi, retaddr, MO_LEQ); } =20 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { + validate_memop(oi, MO_BEQ); store_helper(env, addr, val, oi, retaddr, MO_BEQ); } =20 @@ -2534,137 +2470,61 @@ void helper_be_stq_mmu(CPUArchState *env, target_u= long addr, uint64_t val, * Store Helpers for cpu_ldst.h */ =20 -static inline void QEMU_ALWAYS_INLINE -cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - int mmu_idx, uintptr_t retaddr, MemOp op) +typedef void FullStoreHelper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t retaddr); + +static inline void cpu_store_helper(CPUArchState *env, target_ulong addr, + uint64_t val, MemOpIdx oi, uintptr_t r= a, + FullStoreHelper *full_store) { - MemOpIdx oi =3D make_memop_idx(op, mmu_idx); - trace_guest_st_before_exec(env_cpu(env), addr, oi); - - store_helper(env, addr, val, oi, retaddr, op); - + full_store(env, addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val, - int mmu_idx, uintptr_t retaddr) +void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB); + cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu); } =20 -void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu); } =20 -void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu); } =20 -void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu); } =20 -void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu); } =20 -void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL); + cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu); } =20 -void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t v= al, - int mmu_idx, uintptr_t retaddr) +void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ); + cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } =20 -void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr); -} - -void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr, - uint32_t val, uintptr_t retaddr) -{ - cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr, - uint64_t val, uintptr_t retaddr) -{ - cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr= ); -} - -void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stb_data_ra(env, ptr, val, 0); -} - -void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_be_data_ra(env, ptr, val, 0); -} - -void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_be_data_ra(env, ptr, val, 0); -} - -void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_be_data_ra(env, ptr, val, 0); -} - -void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stw_le_data_ra(env, ptr, val, 0); -} - -void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val) -{ - cpu_stl_le_data_ra(env, ptr, val, 0); -} - -void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) -{ - cpu_stq_le_data_ra(env, ptr, val, 0); -} +#include "ldst_common.c.inc" =20 /* * First set of functions passes in OI and RETADDR. diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 246be4502d..46b74b5f70 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -852,300 +852,232 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) +/* + * Verify that we have passed the correct MemOp to the correct function. + * + * We could present one function to target code, and dispatch based on + * the MemOp, but so far we have worked hard to avoid an indirect function + * call along the memory path. + */ +static void validate_memop(MemOpIdx oi, MemOp expected) { - MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - uint32_t ret; +#ifdef CONFIG_DEBUG_TCG + MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); + assert(have =3D=3D expected); +#endif +} =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldub_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); +static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra, MMUAccessType type) +{ + MemOp mop =3D get_memop(oi); + int a_bits =3D get_alignment_bits(mop); + void *ret; + + /* Enforce guest required alignment. */ + if (unlikely(addr & ((1 << a_bits) - 1))) { + cpu_unaligned_access(env_cpu(env), addr, type, get_mmuidx(oi), ra); + } + + ret =3D g2h(env_cpu(env), addr); + set_helper_retaddr(ra); return ret; } =20 -int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data(env, ptr); -} + void *haddr; + uint8_t ret; =20 -uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D lduw_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_UB); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldub_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data(env, ptr); -} + void *haddr; + uint16_t ret; =20 -uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldl_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D lduw_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); + void *haddr; + uint32_t ret; + + validate_memop(oi, MO_BEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldl_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint64_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldq_be_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_BEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldq_be_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) +uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); + void *haddr; + uint16_t ret; + + validate_memop(oi, MO_LEUW); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D lduw_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} + +uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; uint32_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D lduw_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEUL); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldl_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) +uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data(env, ptr); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - uint32_t ret; - - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldl_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); + void *haddr; uint64_t ret; =20 - trace_guest_ld_before_exec(env_cpu(env), ptr, oi); - ret =3D ldq_le_p(g2h(env_cpu(env), ptr)); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R); + validate_memop(oi, MO_LEQ); + trace_guest_ld_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldq_le_p(haddr); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retadd= r) +void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldub_data(env, ptr); + validate_memop(oi, MO_UB); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stb_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ret= addr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_lduw_be_data(env, ptr); + validate_memop(oi, MO_BEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldl_be_data(env, ptr); + validate_memop(oi, MO_BEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldq_be_data(env, ptr); + validate_memop(oi, MO_BEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_be_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ret= addr) +void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - uint32_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_lduw_le_data(env, ptr); + validate_memop(oi, MO_LEUW); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stw_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) +void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr); -} + void *haddr; =20 -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) -{ - uint32_t ret; - - set_helper_retaddr(retaddr); - ret =3D cpu_ldl_le_data(env, ptr); + validate_memop(oi, MO_LEUL); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stl_le_p(haddr, val); clear_helper_retaddr(); - return ret; + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t reta= ddr) +void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { - uint64_t ret; + void *haddr; =20 - set_helper_retaddr(retaddr); - ret =3D cpu_ldq_le_data(env, ptr); - clear_helper_retaddr(); - return ret; -} - -void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_UB, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stb_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_be_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUW, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stw_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stl_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEQ, MMU_USER_IDX); - - trace_guest_st_before_exec(env_cpu(env), ptr, oi); - stq_le_p(g2h(env_cpu(env), ptr), val); - qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stb_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_be_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stw_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stl_le_data(env, ptr, val); - clear_helper_retaddr(); -} - -void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t retaddr) -{ - set_helper_retaddr(retaddr); - cpu_stq_le_data(env, ptr, val); + validate_memop(oi, MO_LEQ); + trace_guest_st_before_exec(env_cpu(env), addr, oi); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + stq_le_p(haddr, val); clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) @@ -1188,6 +1120,8 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) return ret; } =20 +#include "ldst_common.c.inc" + /* * Do not allow unaligned operations to proceed. Return the host address. * diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc new file mode 100644 index 0000000000..bfefb275e7 --- /dev/null +++ b/accel/tcg/ldst_common.c.inc @@ -0,0 +1,307 @@ +/* + * Routines common to user and system emulation of load/store. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + return cpu_ldb_mmu(env, addr, oi, ra); +} + +int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + return cpu_ldw_be_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + return cpu_ldl_be_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + return cpu_ldq_be_mmu(env, addr, oi, ra); +} + +uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + return cpu_ldw_le_mmu(env, addr, oi, ra); +} + +int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); +} + +uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + return cpu_ldl_le_mmu(env, addr, oi, ra); +} + +uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + return cpu_ldq_le_mmu(env, addr, oi, ra); +} + +void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + cpu_stw_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + cpu_stl_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx); + cpu_stq_be_mmu(env, addr, val, oi, ra); +} + +void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + cpu_stw_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + cpu_stl_le_mmu(env, addr, val, oi, ra); +} + +void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx); + cpu_stq_le_mmu(env, addr, val, oi, ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int8_t)cpu_ldub_data_ra(env, addr, ra); +} + +uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_data_ra(env, addr, ra); +} + +uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); +} + +void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, + uint32_t val, uintptr_t ra) +{ + cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, + uint64_t val, uintptr_t ra) +{ + cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); +} + +/*--------------------------*/ + +uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldub_data_ra(env, addr, 0); +} + +int cpu_ldsb_data(CPUArchState *env, abi_ptr addr) +{ + return (int8_t)cpu_ldub_data(env, addr); +} + +uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_be_data_ra(env, addr, 0); +} + +int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_be_data(env, addr); +} + +uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_be_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_be_data_ra(env, addr, 0); +} + +uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_le_data_ra(env, addr, 0); +} + +int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_le_data(env, addr); +} + +uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_le_data_ra(env, addr, 0); +} + +uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_le_data_ra(env, addr, 0); +} + +void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stb_data_ra(env, addr, val, 0); +} + +void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_be_data_ra(env, addr, val, 0); +} + +void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_be_data_ra(env, addr, val, 0); +} + +void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_be_data_ra(env, addr, val, 0); +} + +void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_le_data_ra(env, addr, val, 0); +} + +void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_le_data_ra(env, addr, val, 0); +} + +void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_le_data_ra(env, addr, val, 0); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316111747100001 The previous placement in tcg/tcg.h was not logical. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 87 +++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 87 ----------------------------------- target/arm/helper-a64.c | 1 - target/m68k/op_helper.c | 1 - target/ppc/mem_helper.c | 1 - target/s390x/tcg/mem_helper.c | 1 - 6 files changed, 87 insertions(+), 91 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a4dad0772f..a878fd0105 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,6 +63,7 @@ #define CPU_LDST_H =20 #include "exec/memopidx.h" +#include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address @@ -233,6 +234,92 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, ui= nt32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); =20 +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); + +#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ +TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ + (CPUArchState *env, target_ulong addr, TYPE val, \ + MemOpIdx oi, uintptr_t retaddr); + +#ifdef CONFIG_ATOMIC64 +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) +#else +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) +#endif + +GEN_ATOMIC_HELPER_ALL(fetch_add) +GEN_ATOMIC_HELPER_ALL(fetch_sub) +GEN_ATOMIC_HELPER_ALL(fetch_and) +GEN_ATOMIC_HELPER_ALL(fetch_or) +GEN_ATOMIC_HELPER_ALL(fetch_xor) +GEN_ATOMIC_HELPER_ALL(fetch_smin) +GEN_ATOMIC_HELPER_ALL(fetch_umin) +GEN_ATOMIC_HELPER_ALL(fetch_smax) +GEN_ATOMIC_HELPER_ALL(fetch_umax) + +GEN_ATOMIC_HELPER_ALL(add_fetch) +GEN_ATOMIC_HELPER_ALL(sub_fetch) +GEN_ATOMIC_HELPER_ALL(and_fetch) +GEN_ATOMIC_HELPER_ALL(or_fetch) +GEN_ATOMIC_HELPER_ALL(xor_fetch) +GEN_ATOMIC_HELPER_ALL(smin_fetch) +GEN_ATOMIC_HELPER_ALL(umin_fetch) +GEN_ATOMIC_HELPER_ALL(smax_fetch) +GEN_ATOMIC_HELPER_ALL(umax_fetch) + +GEN_ATOMIC_HELPER_ALL(xchg) + +#undef GEN_ATOMIC_HELPER_ALL +#undef GEN_ATOMIC_HELPER + +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); + +Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + MemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + MemOpIdx oi, uintptr_t retaddr); + #if defined(CONFIG_USER_ONLY) =20 extern __thread uintptr_t helper_retaddr; diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e67ef34694..114ad66b25 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -33,7 +33,6 @@ #include "qemu/queue.h" #include "tcg/tcg-mo.h" #include "tcg-target.h" -#include "qemu/int128.h" #include "tcg/tcg-cond.h" =20 /* XXX: make safe guess about sizes */ @@ -1306,92 +1305,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulo= ng addr, uint64_t val, #endif #endif /* CONFIG_SOFTMMU */ =20 -uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); - -#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, target_ulong addr, TYPE val, \ - MemOpIdx oi, uintptr_t retaddr); - -#ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) -#else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) -#endif - -GEN_ATOMIC_HELPER_ALL(fetch_add) -GEN_ATOMIC_HELPER_ALL(fetch_sub) -GEN_ATOMIC_HELPER_ALL(fetch_and) -GEN_ATOMIC_HELPER_ALL(fetch_or) -GEN_ATOMIC_HELPER_ALL(fetch_xor) -GEN_ATOMIC_HELPER_ALL(fetch_smin) -GEN_ATOMIC_HELPER_ALL(fetch_umin) -GEN_ATOMIC_HELPER_ALL(fetch_smax) -GEN_ATOMIC_HELPER_ALL(fetch_umax) - -GEN_ATOMIC_HELPER_ALL(add_fetch) -GEN_ATOMIC_HELPER_ALL(sub_fetch) -GEN_ATOMIC_HELPER_ALL(and_fetch) -GEN_ATOMIC_HELPER_ALL(or_fetch) -GEN_ATOMIC_HELPER_ALL(xor_fetch) -GEN_ATOMIC_HELPER_ALL(smin_fetch) -GEN_ATOMIC_HELPER_ALL(umin_fetch) -GEN_ATOMIC_HELPER_ALL(smax_fetch) -GEN_ATOMIC_HELPER_ALL(umax_fetch) - -GEN_ATOMIC_HELPER_ALL(xchg) - -#undef GEN_ATOMIC_HELPER_ALL -#undef GEN_ATOMIC_HELPER - -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); - -Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index f06399f351..f1a4089a4f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -32,7 +32,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 5918a29516..d2065fa992 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -22,7 +22,6 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "semihosting/semihost.h" -#include "tcg/tcg.h" =20 #if defined(CONFIG_USER_ONLY) =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index e2282baa8d..39945d9ea5 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" -#include "tcg/tcg.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 3782c1c098..b20a82a914 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -27,7 +27,6 @@ #include "exec/cpu_ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" -#include "tcg/tcg.h" =20 #if !defined(CONFIG_USER_ONLY) #include "hw/s390x/storage-keys.h" --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316256565100001 We should not have been using the helper_ret_* set of functions, as they are supposed to be private to tcg. Nor should we have been using the plain cpu_*_data set of functions, as they do not handle unwinding properly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 420 +++++++++++------------------------ 1 file changed, 135 insertions(+), 285 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 167d9a591c..a8880ce81c 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8222,79 +8222,42 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); + pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); #else - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif + pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); + pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); + pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); + pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); + pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); + pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); + pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); + pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); + pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); + pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); + pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); + pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); + pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); + pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); + pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); + pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); #endif } =20 @@ -8302,47 +8265,26 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); #else - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif + pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); + pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); + pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); + pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); + pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); + pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); + pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); + pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); #endif } =20 @@ -8350,31 +8292,18 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) + uintptr_t ra =3D GETPC(); + #if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); #else - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif + pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); + pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); + pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); + pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); #endif } =20 @@ -8382,14 +8311,10 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); - pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); -#else - pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif + uintptr_t ra =3D GETPC(); + + pwd->d[0] =3D cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); + pwd->d[1] =3D cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); } =20 #define MSA_PAGESPAN(x) \ @@ -8415,81 +8340,44 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); #else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif + cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); + cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); + cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); + cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); + cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); + cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); + cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); + cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); + cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); + cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); + cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); + cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); + cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); + cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); + cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); + cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); #endif } =20 @@ -8498,49 +8386,28 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); #else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif + cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); + cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); + cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); + cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); + cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); + cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); + cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); + cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); #endif } =20 @@ -8549,33 +8416,20 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); + + ensure_writable_pages(env, addr, mmu_idx, ra); =20 - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) #if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); #else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif + cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); + cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); + cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); + cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); #endif } =20 @@ -8584,14 +8438,10 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); + uintptr_t ra =3D GETPC(); =20 - MEMOP_IDX(DF_DOUBLE) ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif + + cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); + cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317340339100001 Rather than use 4-16 separate operations, use 2 operations plus some byte reordering as necessary. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/msa_helper.c | 201 +++++++++++++---------------------- 1 file changed, 71 insertions(+), 130 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index a8880ce81c..e40c1b7057 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8218,47 +8218,31 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, #define MEMOP_IDX(DF) #endif =20 +#ifdef TARGET_WORDS_BIGENDIAN +static inline uint64_t bswap16x4(uint64_t x) +{ + uint64_t m =3D 0x00ff00ff00ff00ffull; + return ((x & m) << 8) | ((x >> 8) & m); +} + +static inline uint64_t bswap32x2(uint64_t x) +{ + return ror64(bswap64(x), 32); +} +#endif + void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); - pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); -#else - pwd->b[0] =3D cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra); - pwd->b[1] =3D cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra); - pwd->b[2] =3D cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra); - pwd->b[3] =3D cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra); - pwd->b[4] =3D cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra); - pwd->b[5] =3D cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra); - pwd->b[6] =3D cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra); - pwd->b[7] =3D cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra); - pwd->b[8] =3D cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra); - pwd->b[9] =3D cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra); - pwd->b[10] =3D cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra); - pwd->b[11] =3D cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra); - pwd->b[12] =3D cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra); - pwd->b[13] =3D cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra); - pwd->b[14] =3D cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra); - pwd->b[15] =3D cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra); -#endif + /* Load 8 bytes at a time. Vector element ordering makes this LE. */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, @@ -8266,26 +8250,20 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); - pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); -#else - pwd->h[0] =3D cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra); - pwd->h[1] =3D cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra); - pwd->h[2] =3D cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra); - pwd->h[3] =3D cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra); - pwd->h[4] =3D cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra); - pwd->h[5] =3D cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra); - pwd->h[6] =3D cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra); - pwd->h[7] =3D cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then swap the four halfwords. + */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap16x4(d0); + d1 =3D bswap16x4(d1); #endif + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, @@ -8293,18 +8271,20 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); - pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); -#else - pwd->w[0] =3D cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra); - pwd->w[1] =3D cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra); - pwd->w[2] =3D cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra); - pwd->w[3] =3D cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra); + /* + * Load 8 bytes at a time. Use little-endian load, then for + * big-endian target, we must then bswap the two words. + */ + d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap32x2(d0); + d1 =3D bswap32x2(d1); #endif + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, @@ -8312,9 +8292,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 - pwd->d[0] =3D cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra); - pwd->d[1] =3D cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra); + d0 =3D cpu_ldq_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_data_ra(env, addr + 8, ra); + pwd->d[0] =3D d0; + pwd->d[1] =3D d1; } =20 #define MSA_PAGESPAN(x) \ @@ -8344,41 +8327,9 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra); -#else - cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra); - cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra); - cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra); - cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra); - cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra); - cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra); - cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra); - cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra); - cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra); - cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra); - cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra); - cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra); - cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra); - cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra); - cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra); - cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra); -#endif + /* Store 8 bytes at a time. Vector element ordering makes this LE. */ + cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra); } =20 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8387,28 +8338,19 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra); -#else - cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra); - cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra); - cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra); - cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra); - cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra); - cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra); - cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra); - cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra); + /* Store 8 bytes at a time. See helper_msa_ld_h. */ + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap16x4(d0); + d1 =3D bswap16x4(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8417,20 +8359,19 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D cpu_mmu_index(env, false); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, ra); =20 -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra); -#else - cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra); - cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra); - cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra); - cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra); + /* Store 8 bytes at a time. See helper_msa_ld_w. */ + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; +#ifdef TARGET_WORDS_BIGENDIAN + d0 =3D bswap32x2(d0); + d1 =3D bswap32x2(d1); #endif + cpu_stq_le_data_ra(env, addr + 0, d0, ra); + cpu_stq_le_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8442,6 +8383,6 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); =20 - cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra); - cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra); + cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1629315354745331.9869385126426; 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Wed, 18 Aug 2021 12:20:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 39/66] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Date: Wed, 18 Aug 2021 09:18:53 -1000 Message-Id: <20210818191920.390759-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629315356273100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b20a82a914..4115cadbd7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -248,13 +248,13 @@ static void do_access_memset(CPUS390XState *env, vadd= r vaddr, char *haddr, * page. This is especially relevant to speed up TLB_NOTDIRTY. */ g_assert(size > 0); - helper_ret_stb_mmu(env, vaddr, byte, oi, ra); + cpu_stb_mmu(env, vaddr, byte, oi, ra); haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); if (likely(haddr)) { memset(haddr + 1, byte, size - 1); } else { for (i =3D 1; i < size; i++) { - helper_ret_stb_mmu(env, vaddr + i, byte, oi, ra); + cpu_stb_mmu(env, vaddr + i, byte, oi, ra); } } } @@ -290,7 +290,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, v= addr vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - byte =3D helper_ret_ldub_mmu(env, vaddr + offset, oi, ra); + byte =3D cpu_ldb_mmu(env, vaddr + offset, oi, ra); *haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_LOAD, mmu_idx); return byte; #endif @@ -324,7 +324,7 @@ static void do_access_set_byte(CPUS390XState *env, vadd= r vaddr, char **haddr, * Do a single access and test if we can then get access to the * page. This is especially relevant to speed up TLB_NOTDIRTY. */ - helper_ret_stb_mmu(env, vaddr + offset, byte, oi, ra); + cpu_stb_mmu(env, vaddr + offset, byte, oi, ra); *haddr =3D tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); #endif } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316566; cv=none; d=zohomail.com; s=zohoarc; b=Vw/ppxWUh0NS2t5MUsQJt1EWEcheSfNtDdee9BsTTbqVlSuAZunLoQgne8frij/KMF8XvDKvYgFJGmaEektf6ZwZIyy6mMBRXILxycV/CQzOu6Immw2MZUGKFpvj1j7PLveAzsQHV9ucjtfS+R4Mo2JE8CMQVsk4YHIl6zodeGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629316566; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316568121100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 299fc386ea..a3e1cf9b6e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1328,27 +1328,27 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, oi =3D make_memop_idx(memop, idx); switch (size) { case 1: - ret =3D helper_ret_ldub_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldb_mmu(env, addr, oi, GETPC()); break; case 2: if (asi & 8) { - ret =3D helper_le_lduw_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldw_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_lduw_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldw_be_mmu(env, addr, oi, GETPC()); } break; case 4: if (asi & 8) { - ret =3D helper_le_ldul_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldl_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_ldul_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldl_be_mmu(env, addr, oi, GETPC()); } break; case 8: if (asi & 8) { - ret =3D helper_le_ldq_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldq_le_mmu(env, addr, oi, GETPC()); } else { - ret =3D helper_be_ldq_mmu(env, addr, oi, GETPC()); + ret =3D cpu_ldq_be_mmu(env, addr, oi, GETPC()); } break; default: --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315350; cv=none; d=zohomail.com; s=zohoarc; b=eqtJttx67LLZn0tbf/jP6Gr7wjuUDeiy6CyzZnl2IwNKpwmIA7bWFrHzeW/utShbvu/mJaviLZzU35msTsXk55siZEykLA/VTHkqQyXUJjBzst2o4v0f66/x03b8KAnXTwqkL0SQlESC/rl/8+BWb6mFMgny1x2EXw+RmDvKFeI= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:23:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/66] target/arm: Use cpu_*_mmu instead of helper_*_mmu Date: Wed, 18 Aug 2021 09:18:55 -1000 Message-Id: <20210818191920.390759-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315351825100001 The helper_*_mmu functions were the only thing available when this code was written. This could have been adjusted when we added cpu_*_mmuidx_ra, but now we can most easily use the newest set of interfaces. Cc: qemu-arm@nongnu.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 52 +++++++---------------------------------- target/arm/m_helper.c | 6 ++--- 2 files changed, 11 insertions(+), 47 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index f1a4089a4f..17c0ebebb2 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -512,37 +512,19 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env= , uint64_t addr, uintptr_t ra =3D GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o0 =3D ldq_le_p(haddr + 0); - o1 =3D ldq_le_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - clear_helper_retaddr(); -#else int mem_idx =3D cpu_mmu_index(env, false); MemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); =20 - o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); + o0 =3D cpu_ldq_le_mmu(env, addr + 0, oi0, ra); + o1 =3D cpu_ldq_le_mmu(env, addr + 8, oi1, ra); oldv =3D int128_make128(o0, o1); =20 success =3D int128_eq(oldv, cmpv); if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); } -#endif =20 return !success; } @@ -582,37 +564,19 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env= , uint64_t addr, uintptr_t ra =3D GETPC(); uint64_t o0, o1; bool success; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(env_cpu(env), addr); - - set_helper_retaddr(ra); - o1 =3D ldq_be_p(haddr + 0); - o0 =3D ldq_be_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - clear_helper_retaddr(); -#else int mem_idx =3D cpu_mmu_index(env, false); MemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); MemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); =20 - o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); + o1 =3D cpu_ldq_be_mmu(env, addr + 0, oi0, ra); + o0 =3D cpu_ldq_be_mmu(env, addr + 8, oi1, ra); oldv =3D int128_make128(o0, o1); =20 success =3D int128_eq(oldv, cmpv); if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); } -#endif =20 return !success; } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index efb522dc44..b6019595f5 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1947,9 +1947,9 @@ static bool do_v7m_function_return(ARMCPU *cpu) * do them as secure, so work out what MMU index that is. */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); - oi =3D make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); - newpc =3D helper_le_ldul_mmu(env, frameptr, oi, 0); - newpsr =3D helper_le_ldul_mmu(env, frameptr + 4, oi, 0); + oi =3D make_memop_idx(MO_LEUL, arm_to_core_mmu_idx(mmu_idx)); + newpc =3D cpu_ldl_le_mmu(env, frameptr, oi, 0); + newpsr =3D cpu_ldl_le_mmu(env, frameptr + 4, oi, 0); =20 /* Consistency checks on new IPSR */ newpsr_exc =3D newpsr & XPSR_EXCP; --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316739491100001 These functions have been replaced by cpu_*_mmu as the most proper interface to use from target code. Hide these declarations from code that should not use them. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 74 ++++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 71 ---------------------------------------- accel/tcg/cputlb.c | 1 + tcg/tcg.c | 1 + tcg/tci.c | 1 + 5 files changed, 77 insertions(+), 71 deletions(-) create mode 100644 include/tcg/tcg-ldst.h diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h new file mode 100644 index 0000000000..8c86365611 --- /dev/null +++ b/include/tcg/tcg-ldst.h @@ -0,0 +1,74 @@ +/* + * Memory helpers that will be used by TCG generated code. + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TCG_LDST_H +#define TCG_LDST_H 1 + +#ifdef CONFIG_SOFTMMU + +/* Value zero-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +/* Value sign-extended to tcg register size. */ +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); + +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); + +#endif /* CONFIG_SOFTMMU */ +#endif /* TCG_LDST_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 114ad66b25..82b4abfa31 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1234,77 +1234,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (qemu_build_not_reached_always(), 0)) \ : dup_const(VECE, C)) =20 -/* - * Memory helpers that will be used by TCG generated code. - */ -#ifdef CONFIG_SOFTMMU -/* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -/* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); - -/* Temporary aliases until backends are converted. */ -#ifdef TARGET_WORDS_BIGENDIAN -# define helper_ret_ldsw_mmu helper_be_ldsw_mmu -# define helper_ret_lduw_mmu helper_be_lduw_mmu -# define helper_ret_ldsl_mmu helper_be_ldsl_mmu -# define helper_ret_ldul_mmu helper_be_ldul_mmu -# define helper_ret_ldl_mmu helper_be_ldul_mmu -# define helper_ret_ldq_mmu helper_be_ldq_mmu -# define helper_ret_stw_mmu helper_be_stw_mmu -# define helper_ret_stl_mmu helper_be_stl_mmu -# define helper_ret_stq_mmu helper_be_stq_mmu -#else -# define helper_ret_ldsw_mmu helper_le_ldsw_mmu -# define helper_ret_lduw_mmu helper_le_lduw_mmu -# define helper_ret_ldsl_mmu helper_le_ldsl_mmu -# define helper_ret_ldul_mmu helper_le_ldul_mmu -# define helper_ret_ldl_mmu helper_le_ldul_mmu -# define helper_ret_ldq_mmu helper_le_ldq_mmu -# define helper_ret_stw_mmu helper_le_stw_mmu -# define helper_ret_stl_mmu helper_le_stl_mmu -# define helper_ret_stq_mmu helper_le_stq_mmu -#endif -#endif /* CONFIG_SOFTMMU */ - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 364d97636a..4836cb1c91 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -39,6 +39,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg/tcg-ldst.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 658be0c6b6..024a22cf39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -58,6 +58,7 @@ =20 #include "elf.h" #include "exec/log.h" +#include "tcg/tcg-ldst.h" #include "tcg-internal.h" =20 #ifdef CONFIG_TCG_INTERPRETER diff --git a/tcg/tci.c b/tcg/tci.c index 5c08dc0a9a..e76087ccac 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -22,6 +22,7 @@ #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ #include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-ldst.h" #include "qemu/compiler.h" #include =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1629316999413100003 Content-Type: text/plain; charset="utf-8" To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..bf40942de4 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong a= ddr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); =20 +#else + +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong add= r); +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong add= r); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 46b74b5f70..6a3fec3002 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #include "internal.h" =20 #undef EAX @@ -867,6 +868,18 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } =20 +void helper_unaligned_ld(CPUArchState *env, target_ulong addr) +{ + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + MMU_USER_IDX, GETPC()); +} + +void helper_unaligned_st(CPUArchState *env, target_ulong addr) +{ + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + MMU_USER_IDX, GETPC()); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) { --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317459; cv=none; d=zohomail.com; s=zohoarc; b=aKLRr6PLlem25ITPQ99HvAoVzH9vVxLIK8X9yPBdCFDUIUlN2/JQjnA/IJrS4qbFhgWkdDNRn9J7/DtRQspZRABxi91Om3HVpAQobb5bhv/Bs07Ko6T/F8pU5qDI7Ix1DdtpwmyZF2IMdfqzxiGsxGF6TVwIycCMVwvKZ8JW+B8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629317459; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317461796100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.h | 2 - tcg/i386/tcg-target.c.inc | 107 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 7 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b00a6da293..3b2c9437a0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -232,9 +232,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, =20 #define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 1e42a877fb..0561a8dc6e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -22,6 +22,7 @@ * THE SOFTWARE. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -420,8 +421,9 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 -#define OPC_GRP3_Ev (0xf7) -#define OPC_GRP5 (0xff) +#define OPC_GRP3_Eb (0xf6) +#define OPC_GRP3_Ev (0xf7) +#define OPC_GRP5 (0xff) #define OPC_GRP14 (0x73 | P_EXT | P_DATA16) =20 /* Group 1 opcode extensions for 0x80-0x83. @@ -443,6 +445,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define SHIFT_SAR 7 =20 /* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ +#define EXT3_TESTi 0 #define EXT3_NOT 2 #define EXT3_NEG 3 #define EXT3_MUL 4 @@ -1605,8 +1608,6 @@ static void tcg_out_nopn(TCGContext *s, int n) } =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1915,7 +1916,88 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); return true; } -#elif TCG_TARGET_REG_BITS =3D=3D 32 +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label; + + /* + * We are expecting a_bits to max out at 7, so we can usually use test= b. + * For i686, we have to use testl for %esi/%edi. + */ + if (a_mask <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || addrlo < 4))= { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo); + tcg_out8(s, a_mask); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo); + tcg_out32(s, a_mask); + } + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + + label =3D new_ldst_label(s); + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr + 4); + label->label_ptr[0] =3D s->code_ptr; + + s->code_ptr +=3D 4; +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4); + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + int ofs =3D 0; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); + ofs +=3D 4; + + tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); + ofs +=3D 4; + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); + ofs +=3D 4; + } + + tcg_out_pushi(s, (uintptr_t)l->raddr); + } else { + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); + + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, (uintptr_t)l->raddr); + tcg_out_push(s, TCG_REG_RAX); + } + + /* + * "Tail call" to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. + */ + tcg_out_jmp(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +#if TCG_TARGET_REG_BITS =3D=3D 32 # define x86_guest_base_seg 0 # define x86_guest_base_index -1 # define x86_guest_base_offset guest_base @@ -1949,6 +2031,7 @@ static inline int setup_guest_base_seg(void) return 0; } # endif +#endif #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2058,6 +2141,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2080,6 +2165,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, is64, opc); @@ -2147,6 +2237,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2169,6 +2261,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, opc); #endif --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315489; cv=none; d=zohomail.com; s=zohoarc; b=MntnDVil89rPg+DaWzVGZn4DcnnofmEI6Er+YOiVc0MOli1pv0v60itFlLmfn2Vhx9206lZDBQ3NvEKS69vVWn2N5IVviXcZah+DOpFIBilaZALvnAlz/yn+8NOEp6zx3AkrQzJRC4zQbnBaHqL7GjluhPxUUlFoJ+JkHFqvljQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629315489; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315491868100001 Content-Type: text/plain; charset="utf-8" A mostly generic test for unaligned access raising SIGBUS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 tests/tcg/multiarch/sigbus.c diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c new file mode 100644 index 0000000000..8134c5fd56 --- /dev/null +++ b/tests/tcg/multiarch/sigbus.c @@ -0,0 +1,68 @@ +#define _GNU_SOURCE 1 + +#include +#include +#include +#include + + +unsigned long long x =3D 0x8877665544332211ull; +void * volatile p =3D (void *)&x + 1; + +void sigbus(int sig, siginfo_t *info, void *uc) +{ + assert(sig =3D=3D SIGBUS); + assert(info->si_signo =3D=3D SIGBUS); +#ifdef BUS_ADRALN + assert(info->si_code =3D=3D BUS_ADRALN); +#endif + assert(info->si_addr =3D=3D p); + exit(EXIT_SUCCESS); +} + +int main() +{ + struct sigaction sa =3D { + .sa_sigaction =3D sigbus, + .sa_flags =3D SA_SIGINFO + }; + int allow_fail =3D 0; + int tmp; + + tmp =3D sigaction(SIGBUS, &sa, NULL); + assert(tmp =3D=3D 0); + + /* + * Select an operation that's likely to enforce alignment. + * On many guests that support unaligned accesses by default, + * this is often an atomic operation. + */ +#if defined(__aarch64__) + asm volatile("ldxr %w0,[%1]" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__alpha__) + asm volatile("ldl_l %0,0(%1)" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__arm__) + asm volatile("ldrex %0,[%1]" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__powerpc__) + asm volatile("lwarx %0,0,%1" : "=3Dr"(tmp) : "r"(p) : "memory"); +#elif defined(__riscv_atomic) + asm volatile("lr.w %0,(%1)" : "=3Dr"(tmp) : "r"(p) : "memory"); +#else + /* No insn known to fault unaligned -- try for a straight load. */ + allow_fail =3D 1; + tmp =3D *(volatile int *)p; +#endif + + assert(allow_fail); + + /* + * We didn't see a signal. + * We might as well validate the unaligned load worked. + */ + if (BYTE_ORDER =3D=3D LITTLE_ENDIAN) { + assert(tmp =3D=3D 0x55443322); + } else { + assert(tmp =3D=3D 0x77665544); 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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gNee4hhTlvWkz/5tdoJ4exWIgD810vPDkwtmNEyoiEo=; b=mJkIThBuEBU/itq1N4ryhFENEtZawXdDCyQ/QwBCsq94h5hAfOY31VS1pbHo7kQ+oc d7MvoA0KKJWsQwqNSHt2m0csg49LncNIuEIPFyMU4F8WD3wZEN0RTyntOMQDoZvWA4qD 2JQaqoY+g4NC5Sk2f/htBniUnENx3oV4NokkF3XfhpSLG1RSGuQxM5cMBbsWUtTKs5Ma +pS0J6njmnR9OnVGhbbtJ95djxU4Cvd/HcFZQeTFblxW45g/2av80eFAqIg+c7hGAeOC pkmYq39E6NJHa0QMqjxWOlYimJbjDn0VYkcr3Kk2wd/RMvTAZ6C0fVfqeOcxBdbafWsi CNww== X-Gm-Message-State: AOAM532a0ZIqbxPtfXcxQ77V2voOxugn1cfhGLUWw0WQbpf++nJIbvLf 7WDFrcTFigWQ9zENmuUnKKu/JVb6ivGZHA== X-Google-Smtp-Source: ABdhPJyWYBLWgJKTrA+PwMfubXN8PSt9APAnMUpJ3wFymanqXZ+izTGmnshW3fgMzy8jYh/MvpiHrg== X-Received: by 2002:a17:90a:3ec6:: with SMTP id k64mr10912998pjc.94.1629314600942; Wed, 18 Aug 2021 12:23:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 46/66] linux-user: Split out do_prctl and subroutines Date: Wed, 18 Aug 2021 09:19:00 -1000 Message-Id: <20210818191920.390759-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315569230100001 Content-Type: text/plain; charset="utf-8" Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 23 - linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_syscall.h | 6 - linux-user/syscall.c | 644 ++++++++++++++++------------ 4 files changed, 359 insertions(+), 320 deletions(-) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 76f6c3391d..819f112ab0 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -20,27 +20,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 =20 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIF= T) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_sysc= all.h index f59057493a..1ce0a5bbf4 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_= syscall.h index cd1e1b4969..74f12365bc 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } =20 -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ccd3892b2d..6e630745fa 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6282,9 +6282,366 @@ abi_long do_arch_prctl(CPUX86State *env, int code, = abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ =20 +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ +#ifdef TARGET_MIPS + abi_long ret =3D 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |=3D PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |=3D PR_FP_MODE_FRE; + } + return ret; +#else + return -TARGET_EINVAL; +#endif +} + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ +#ifdef TARGET_MIPS + bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); + bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr =3D arg2 & PR_FP_MODE_FR; + bool new_fre =3D arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits =3D PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=3D0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=3D1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr =3D env->active_fpu.fpr; + for (i =3D 0; i < 32 ; i +=3D 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |=3D (1 << CP0St_FR); + env->hflags |=3D MIPS_HFLAG_F64; + } else { + env->CP0_Status &=3D ~(1 << CP0St_FR); + env->hflags &=3D ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |=3D (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |=3D MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); + env->hflags &=3D ~MIPS_HFLAG_FRE; + } + + return 0; +#else + return -TARGET_EINVAL; +#endif +} + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ +#ifdef TARGET_AARCH64 + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } +#endif + return -TARGET_EINVAL; +} + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ +#ifdef TARGET_AARCH64 + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the current architectural maximum is VQ= =3D16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu =3D env_archcpu(env); + uint32_t vq, old_vq; + + old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } +#endif + return -TARGET_EINVAL; +} + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ +#ifdef TARGET_AARCH64 + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all =3D (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret =3D 0; + Error *err =3D NULL; + + if (arg2 =3D=3D 0) { + arg2 =3D all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |=3D qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret !=3D 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %= s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } +#endif + return -TARGET_EINVAL; +} + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long = arg2) +{ +#ifdef TARGET_AARCH64 + abi_ulong valid_mask =3D PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu =3D env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D PR_MTE_TCF_MASK; + valid_mask |=3D PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] =3D + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHI= FT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 =3D + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +#else + return -TARGET_EINVAL; +#endif +} + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ +#ifdef TARGET_AARCH64 + ARMCPU *cpu =3D env_archcpu(env); + abi_long ret =3D 0; + + if (env->tagged_addr_enable) { + ret |=3D PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |=3D extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHI= FT; + ret =3D deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +#else + return -TARGET_EINVAL; +#endif +} + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret =3D get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret =3D get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 =20 =20 @@ -10621,290 +10978,7 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret =3D get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name =3D lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name =3D lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret =3D get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - ret =3D 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |=3D TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |=3D TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env =3D ((CPUMIPSState *)cpu_env); - bool old_fr =3D env->CP0_Status & (1 << CP0St_FR); - bool old_fre =3D env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr =3D arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre =3D arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits =3D TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr =3D=3D new_fr && old_fre =3D=3D new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=3D0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=3D1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr =3D env->active_fpu.fpr; - for (i =3D 0; i < 32 ; i +=3D 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] =3D fpr[i + 1].w[FP_ENDIAN_ID= X]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] =3D fpr[i].w[!FP_ENDIAN_ID= X]; - } - } - - if (new_fr) { - env->CP0_Status |=3D (1 << CP0St_FR); - env->hflags |=3D MIPS_HFLAG_F64; - } else { - env->CP0_Status &=3D ~(1 << CP0St_FR); - env->hflags &=3D ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |=3D (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |=3D MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); - env->hflags &=3D ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=3D512, i.e. VL=3D8192, - * even though the current architectural maximum is VQ=3D16. - */ - ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - uint32_t vq, old_vq; - - old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; - vq =3D MAX(arg2 / 16, 1); - vq =3D MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] =3D vq - 1; - arm_rebuild_hflags(env); - ret =3D vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret =3D -TARGET_EINVAL; - { - ARMCPU *cpu =3D env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all =3D (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_API= BKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBK= EY | - TARGET_PR_PAC_APGAKEY); - int ret =3D 0; - Error *err =3D NULL; - - if (arg2 =3D=3D 0) { - arg2 =3D all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &er= r); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |=3D qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &er= r); - } - if (ret !=3D 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: = %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask =3D TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |=3D TARGET_PR_MTE_TCF_MASK; - valid_mask |=3D TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable =3D arg2 & TARGET_PR_TAGGED_ADDR_E= NABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] =3D - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 =3D - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret =3D 0; - CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |=3D TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |=3D (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret =3D deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315618; cv=none; d=zohomail.com; s=zohoarc; b=dMnC00Nytcg+LTqtp4vPUHrcK3TjLus0wCJGPL/dSh3Yzy+cBga9RKh2iB3T5KMSXKwpvVhqRv/Qfo2D3fnq62V/EavT/KMBgYAqWiqQHNMGqTjSBJsFYjQasAoCxOA4Q1qPT2od4Y0nmF+gJ7lr/BuzRVAhFEOHrfnItXc+9w4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629315618; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f2K4PGLb2oKqgETEBS112ablWl1xVg86v5mEsLdMH5A=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315619634100001 Content-Type: text/plain; charset="utf-8" Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 6e630745fa..e303a9da7f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6325,6 +6325,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif =20 static abi_long do_prctl_get_fp_mode(CPUArchState *env) { @@ -6632,13 +6639,54 @@ static abi_long do_prctl(CPUArchState *env, abi_lon= g option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on= . */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we nee= d. */ - return -TARGET_EINVAL; + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + /* Disable to prevent the target disabling stuff we need. */ + return -TARGET_EINVAL; } } =20 --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315798800100001 Content-Type: text/plain; charset="utf-8" Despite the comment, the members were not kept at the end. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bc864564ce..b7d5bc1200 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -131,7 +131,6 @@ struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); =20 - int reset_dump_flags; bool (*has_work)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -149,9 +148,6 @@ struct CPUClass { void (*disas_set_info)(CPUState *cpu, disassemble_info *info); =20 const char *deprecation_note; - /* Keep non-pointer data at the end to minimize holes. */ - int gdb_num_core_regs; - bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 /* when system emulation is not available, this pointer is NULL */ @@ -165,6 +161,13 @@ struct CPUClass { * class data that depends on the accelerator, see accel/accel-common.= c. */ void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); + + /* + * Keep non-pointer data at the end to minimize holes. + */ + int reset_dump_flags; + int gdb_num_core_regs; + bool gdb_stop_before_watchpoint; }; =20 /* --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317175; cv=none; d=zohomail.com; s=zohoarc; b=JSnjl65Lh1KrrXeviM1MQ7CIFUzzAN0wk9Kstu1WM/auQQe4wrr8cTsgMURAdQF2zCcS49R8rqyZKBlOmJ3FkVTPcN2BFghQMWtHfZZASGW6X0lJfJXpZANSUu4LzWF5LAUVpEVcDXvK9GunED970V7+2eWHd9fFnrp4Bwz20Xs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629317175; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317177141100001 Content-Type: text/plain; charset="utf-8" This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ linux-user/syscall.c | 21 +++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7d5bc1200..088b2d1adf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -412,6 +412,9 @@ struct CPUState { =20 bool ignore_memory_transaction_failures; =20 + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; =20 struct hvf_vcpu_state *hvf; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e303a9da7f..b2e3c28b41 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6640,6 +6640,25 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); =20 + /* + * We only implement PR_UNALIGN_SIGBUS, and only for those targets + * who have had their translator updated to insert MO_ALIGN. + */ +#if 0 + case PR_GET_UNALIGN: + { + CPUState *cs =3D env_cpu(env); + uint32_t res =3D PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |=3D PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); + } + case PR_SET_UNALIGN: + env_cpu(env)->prctl_unalign_sigbus =3D arg2 & PR_UNALIGN_SIGBUS; + return 0; +#endif + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6682,8 +6701,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: default: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317350; 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Wed, 18 Aug 2021 12:23:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 50/66] hw/core/cpu: Move cpu properties to cpu-sysemu.c Date: Wed, 18 Aug 2021 09:19:04 -1000 Message-Id: <20210818191920.390759-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317351485100001 Content-Type: text/plain; charset="utf-8" The comment in cpu-common.c is absolutely correct, we can't rely on the ifdef in a file built once. This was only "working" because we used ifndef. Signed-off-by: Richard Henderson --- hw/core/cpu-common.h | 17 +++++++++++++++++ hw/core/cpu-common.c | 18 ++---------------- hw/core/cpu-sysemu.c | 24 ++++++++++++++++++++++++ hw/core/cpu-user.c | 22 ++++++++++++++++++++++ hw/core/meson.build | 4 ++++ 5 files changed, 69 insertions(+), 16 deletions(-) create mode 100644 hw/core/cpu-common.h create mode 100644 hw/core/cpu-user.c diff --git a/hw/core/cpu-common.h b/hw/core/cpu-common.h new file mode 100644 index 0000000000..9049f74e67 --- /dev/null +++ b/hw/core/cpu-common.h @@ -0,0 +1,17 @@ +/* + * QEMU CPU model + * + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_CORE_CPU_COMMON_H +#define HW_CORE_CPU_COMMON_H + +void cpu_class_init_props(DeviceClass *dc); + +#endif diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..6406ea79f0 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -34,6 +34,7 @@ #include "hw/qdev-properties.h" #include "trace/trace-root.h" #include "qemu/plugin.h" +#include "cpu-common.h" =20 CPUState *cpu_by_arch_id(int64_t id) { @@ -257,21 +258,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } =20 -static Property cpu_common_props[] =3D { -#ifndef CONFIG_USER_ONLY - /* Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, fal= se), - DEFINE_PROP_END_OF_LIST(), -}; - static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -286,7 +272,7 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; dc->reset =3D cpu_common_reset; - device_class_set_props(dc, cpu_common_props); + cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 00253f8929..5a62960f3c 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -20,8 +20,11 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/memory.h" #include "hw/core/cpu.h" #include "hw/core/sysemu-cpu-ops.h" +#include "hw/qdev-properties.h" +#include "cpu-common.h" =20 bool cpu_paging_enabled(const CPUState *cpu) { @@ -143,3 +146,24 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cp= u) } return res; } + +/* + * This can't go in hw/core/cpu-common.c because that file is compiled only + * once for both user-mode and system builds. + */ +static Property cpu_sysemu_props[] =3D { + /* + * Create a memory property for softmmu CPU object, so users can wire + * up its memory. The default if no link is set up is to use the + * system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, fal= se), + DEFINE_PROP_END_OF_LIST(), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_sysemu_props); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c new file mode 100644 index 0000000000..62037e8669 --- /dev/null +++ b/hw/core/cpu-user.c @@ -0,0 +1,22 @@ +/* + * QEMU CPU model (user-only emulation specific) + * + * Copyright (c) 2021 Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/core/cpu.h" +#include "cpu-common.h" + +/* + * This can't go in hw/core/cpu-common.c because that file is compiled only + * once for both user-mode and system builds. + */ +void cpu_class_init_props(DeviceClass *dc) +{ +} diff --git a/hw/core/meson.build b/hw/core/meson.build index 18f44fb7c2..4b3de4e247 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -43,3 +43,7 @@ specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files( 'machine-qmp-cmds.c', 'numa.c', )) + +specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files( + 'cpu-user.c' +)) --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Will enable for each cpu that supports the feature. Signed-off-by: Richard Henderson --- hw/core/cpu-user.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index 62037e8669..23786865cb 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -11,12 +11,27 @@ =20 #include "qemu/osdep.h" #include "hw/core/cpu.h" +#include "hw/qdev-properties.h" #include "cpu-common.h" =20 /* * This can't go in hw/core/cpu-common.c because that file is compiled only * once for both user-mode and system builds. */ +static Property cpu_useronly_props[] =3D { + /* + * Create a memory property for softmmu CPU object, so users can wire + * up its memory. The default if no link is set up is to use the + * system address space. + */ +#if 0 + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#endif + DEFINE_PROP_END_OF_LIST(), +}; + void cpu_class_init_props(DeviceClass *dc) { + device_class_set_props(dc, cpu_useronly_props); } --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315874; cv=none; d=zohomail.com; s=zohoarc; b=brIZnJqNQNs1dGO+oUyurOzE2datNT7MroORaCUq52iM7KNylq9tFJNnx5LzAcUhG4ZiFWs3JT7sola9c2FfZg/q7FbZwPZmfxFK8iAF0MljgBySEIcAtSFGWtDD1u0LwAB0lbEtncK5o8ZzTwyZtr3rvZzzgw5v/tmh5yORhBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629315874; 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Wed, 18 Aug 2021 12:23:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 52/66] target/alpha: Reorg fp memory operations Date: Wed, 18 Aug 2021 09:19:06 -1000 Message-Id: <20210818191920.390759-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315876719100001 Content-Type: text/plain; charset="utf-8" Pass in the context to each mini-helper, instead of an incorrectly named "flags". Separate gen_load_fp and gen_store_fp, away from the integer helpers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/translate.c | 83 +++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index de6c0a8439..607b6c3da7 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -267,30 +267,47 @@ static inline DisasJumpType gen_invalid(DisasContext = *ctx) return gen_excp(ctx, EXCP_OPCDEC, 0); } =20 -static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags) +static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL); - gen_helper_memory_to_f(t0, tmp32); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 -static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags) +static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ); - gen_helper_memory_to_g(t0, tmp); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } =20 -static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags) +static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL); - gen_helper_memory_to_s(t0, tmp32); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 +static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) +{ + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); +} + +static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, + void (*func)(DisasContext *, TCGv, TCGv)) +{ + /* Loads to $f31 are prefetches, which we can treat as nops. */ + if (likely(ra !=3D 31)) { + TCGv addr =3D tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); + func(ctx, cpu_fir[ra], addr); + tcg_temp_free(addr); + } +} + static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) { tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL); @@ -338,30 +355,44 @@ static inline void gen_load_mem(DisasContext *ctx, tcg_temp_free(tmp); } =20 -static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags) +static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - gen_helper_f_to_memory(tmp32, t0); - tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL); + gen_helper_f_to_memory(tmp32, addr); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); tcg_temp_free_i32(tmp32); } =20 -static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) +static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - gen_helper_g_to_memory(tmp, t0); - tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ); + gen_helper_g_to_memory(tmp, src); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); tcg_temp_free(tmp); } =20 -static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags) +static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - gen_helper_s_to_memory(tmp32, t0); - tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL); + gen_helper_s_to_memory(tmp32, src); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); tcg_temp_free_i32(tmp32); } =20 +static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) +{ + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); +} + +static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, + void (*func)(DisasContext *, TCGv, TCGv)) +{ + TCGv addr =3D tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); + func(ctx, load_fpr(ctx, ra), addr); + tcg_temp_free(addr); +} + static inline void gen_store_mem(DisasContext *ctx, void (*tcg_gen_qemu_store)(TCGv t0, TCGv = t1, int flags), @@ -2776,42 +2807,42 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0x20: /* LDF */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldf); break; case 0x21: /* LDG */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldg); break; case 0x22: /* LDS */ REQUIRE_FEN; - gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_lds); break; case 0x23: /* LDT */ REQUIRE_FEN; - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); + gen_load_fp(ctx, ra, rb, disp16, gen_ldt); break; case 0x24: /* STF */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stf); break; case 0x25: /* STG */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stg); break; case 0x26: /* STS */ REQUIRE_FEN; - gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_sts); break; case 0x27: /* STT */ REQUIRE_FEN; - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); + gen_store_fp(ctx, ra, rb, disp16, gen_stt); break; case 0x28: /* LDL */ --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317464; cv=none; d=zohomail.com; s=zohoarc; b=gSe9P4KPhdStLxG60QQo34su7xS+SRLHDXiYIxjGK+eXqhQXwPgsxPOb9mLha9rHr95ku7W2e1Cm1O5Fw2kEhRiGN0Mxir0DQrxKfQTf22B4ukyP9BZ+o10nLF5jtBpbIIxbIWU8SoYYWncyZ24yQhhtI1IEmGRWezh2k/XCuYA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629317464; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317466382100001 Content-Type: text/plain; charset="utf-8" Pass in the MemOp instead of a callback. Drop the fp argument; add a locked argument. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/translate.c | 104 +++++++++++++++------------------------ 1 file changed, 40 insertions(+), 64 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 607b6c3da7..c14c1156a0 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -308,27 +308,10 @@ static void gen_load_fp(DisasContext *ctx, int ra, in= t rb, int32_t disp16, } } =20 -static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) +static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, + MemOp op, bool clear, bool locked) { - tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL); - tcg_gen_mov_i64(cpu_lock_addr, t1); - tcg_gen_mov_i64(cpu_lock_value, t0); -} - -static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags) -{ - tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ); - tcg_gen_mov_i64(cpu_lock_addr, t1); - tcg_gen_mov_i64(cpu_lock_value, t0); -} - -static inline void gen_load_mem(DisasContext *ctx, - void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, - int flags), - int ra, int rb, int32_t disp16, bool fp, - bool clear) -{ - TCGv tmp, addr, va; + TCGv addr, dest; =20 /* LDQ_U with ra $31 is UNOP. Other various loads are forms of prefetches, which we can treat as nops. No worries about @@ -337,22 +320,20 @@ static inline void gen_load_mem(DisasContext *ctx, return; } =20 - tmp =3D tcg_temp_new(); - addr =3D load_gpr(ctx, rb); - - if (disp16) { - tcg_gen_addi_i64(tmp, addr, disp16); - addr =3D tmp; - } + addr =3D tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { - tcg_gen_andi_i64(tmp, addr, ~0x7); - addr =3D tmp; + tcg_gen_andi_i64(addr, addr, ~0x7); } =20 - va =3D (fp ? cpu_fir[ra] : ctx->ir[ra]); - tcg_gen_qemu_load(va, addr, ctx->mem_idx); + dest =3D ctx->ir[ra]; + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op); =20 - tcg_temp_free(tmp); + if (locked) { + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, dest); + } + tcg_temp_free(addr); } =20 static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) @@ -393,30 +374,21 @@ static void gen_store_fp(DisasContext *ctx, int ra, i= nt rb, int32_t disp16, tcg_temp_free(addr); } =20 -static inline void gen_store_mem(DisasContext *ctx, - void (*tcg_gen_qemu_store)(TCGv t0, TCGv = t1, - int flags), - int ra, int rb, int32_t disp16, bool fp, - bool clear) +static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp1= 6, + MemOp op, bool clear) { - TCGv tmp, addr, va; + TCGv addr, src; =20 - tmp =3D tcg_temp_new(); - addr =3D load_gpr(ctx, rb); - - if (disp16) { - tcg_gen_addi_i64(tmp, addr, disp16); - addr =3D tmp; - } + addr =3D tcg_temp_new(); + tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { - tcg_gen_andi_i64(tmp, addr, ~0x7); - addr =3D tmp; + tcg_gen_andi_i64(addr, addr, ~0x7); } =20 - va =3D (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra)); - tcg_gen_qemu_store(va, addr, ctx->mem_idx); + src =3D load_gpr(ctx, ra); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op); =20 - tcg_temp_free(tmp); + tcg_temp_free(addr); } =20 static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int = rb, @@ -1511,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0x0A: /* LDBU */ REQUIRE_AMASK(BWX); - gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0); break; case 0x0B: /* LDQ_U */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0); break; case 0x0C: /* LDWU */ REQUIRE_AMASK(BWX); - gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0); break; case 0x0D: /* STW */ REQUIRE_AMASK(BWX); - gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0); break; case 0x0E: /* STB */ REQUIRE_AMASK(BWX); - gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_UB, 0); break; case 0x0F: /* STQ_U */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); + gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1); break; =20 case 0x10: @@ -2489,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ - gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL); + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, va); break; case 0x3: /* Quadword physical access with lock (hw_ldq_l/p) */ - gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ); + tcg_gen_mov_i64(cpu_lock_addr, addr); + tcg_gen_mov_i64(cpu_lock_value, va); break; case 0x4: /* Longword virtual PTE fetch (hw_ldl/v) */ @@ -2846,27 +2822,27 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) break; case 0x28: /* LDL */ - gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0); break; case 0x29: /* LDQ */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0); break; case 0x2A: /* LDL_L */ - gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1); break; case 0x2B: /* LDQ_L */ - gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); + gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1); break; case 0x2C: /* STL */ - gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0); break; case 0x2D: /* STQ */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); + gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0); break; case 0x2E: /* STL_C */ --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316079; cv=none; d=zohomail.com; s=zohoarc; b=BD8c+5CVotcUeCLne6nCJ2ZyKaHnHf0vBLb1pFqWkGH//o8xT0ZFOVQIAMIvWYaCgtQTS4w7LyU+0zQbaVxrDmM1THchwiiQy2lOuB7ftnlx7ZK4T9F5v4CWLLtOVJSqG+Ne9k0gvXD+JxLsfIBUGI60Gsxrrk/WpM6NBSeJRMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629316079; 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Wed, 18 Aug 2021 12:23:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 54/66] target/alpha: Implement prctl_unalign_sigbus Date: Wed, 18 Aug 2021 09:19:08 -1000 Message-Id: <20210818191920.390759-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316080584100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 +++++ hw/core/cpu-user.c | 2 +- linux-user/syscall.c | 2 +- target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 6eb3fcc63e..d9099ea188 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -387,6 +387,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; @@ -469,6 +471,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, *pc =3D env->pc; *cs_base =3D 0; *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #ifdef CONFIG_USER_ONLY diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index 23786865cb..daf8ff59b5 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -24,7 +24,7 @@ static Property cpu_useronly_props[] =3D { * up its memory. The default if no link is set up is to use the * system address space. */ -#if 0 +#if defined(TARGET_ALPHA) DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, prctl_unalign_sigbus, false), #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index b2e3c28b41..15080d0539 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6644,7 +6644,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, * We only implement PR_UNALIGN_SIGBUS, and only for those targets * who have had their translator updated to insert MO_ALIGN. */ -#if 0 +#if defined(TARGET_ALPHA) case PR_GET_UNALIGN: { CPUState *cs =3D env_cpu(env); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c14c1156a0..f6ba6a1a59 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *c= tx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv = addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCG= v addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int= rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |=3D UNALIGN(ctx); } =20 dest =3D ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv tmp =3D tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } =20 @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv= addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, in= t rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |=3D UNALIGN(ctx); } =20 src =3D load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) =20 #ifdef CONFIG_USER_ONLY ctx->ir =3D cpu_std_ir; + ctx->unalign =3D (ctx->tbflags & TB_FLAG_UNALIGN ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316232321100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 ++++- hw/core/cpu-user.c | 2 +- linux-user/syscall.c | 2 +- target/hppa/translate.c | 19 +++++++++++++++---- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 748270bfa3..332ca5de62 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState= *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 =20 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc =3D env->iaoq_f & -4; *cs_base =3D env->iaoq_b & -4; + flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index daf8ff59b5..6a5edcfb77 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -24,7 +24,7 @@ static Property cpu_useronly_props[] =3D { * up its memory. The default if no link is set up is to use the * system address space. */ -#if defined(TARGET_ALPHA) +#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, prctl_unalign_sigbus, false), #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 15080d0539..836a7eaee2 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6644,7 +6644,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, * We only implement PR_UNALIGN_SIGBUS, and only for those targets * who have had their translator updated to insert MO_ALIGN. */ -#if defined(TARGET_ALPHA) +#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) case PR_GET_UNALIGN: { CPUState *cs =3D env_cpu(env); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b18150ef8d..1cfa801533 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -275,8 +275,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1480,7 +1490,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1498,7 +1508,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1516,7 +1526,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1534,7 +1544,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4113,6 +4123,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->mmu_idx =3D MMU_USER_IDX; ctx->iaoq_f =3D ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b =3D ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign =3D (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIG= N); #else ctx->privilege =3D (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx =3D (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_ID= X); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316386; cv=none; d=zohomail.com; s=zohoarc; b=KJA6vdah7LQZLMYqoZ68C2rHCHJGChfogucz5fElgav8Z06axi1/YT8e0zEO89QStCxGRKm//wJe8Aw7YWb+WEHBU5lsTxF0HJWWgkAMZMktcIMlkQxScmsbVaumtNvBdlFcV4kMyi8fMxr6F42bVZ/phYcLd7R3hgkXbiMgk20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629316386; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316387677100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 4 ++++ hw/core/cpu-user.c | 2 +- linux-user/syscall.c | 2 +- target/sh4/translate.c | 50 ++++++++++++++++++++++++++++-------------- 4 files changed, 40 insertions(+), 18 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index a9191951f8..5f2dc551e3 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) =20 #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) =20 #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -376,6 +377,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *en= v, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-= 30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #endif /* SH4_CPU_H */ diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index 6a5edcfb77..0ad009f186 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -24,7 +24,7 @@ static Property cpu_useronly_props[] =3D { * up its memory. The default if no link is set up is to use the * system address space. */ -#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) +#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) || defined(TARGET_SH4) DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, prctl_unalign_sigbus, false), #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 836a7eaee2..784ced821d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6644,7 +6644,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, * We only implement PR_UNALIGN_SIGBUS, and only for those targets * who have had their translator updated to insert MO_ALIGN. */ -#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) +#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) || defined(TARGET_SH4) case PR_GET_UNALIGN: { CPUState *cs =3D env_cpu(env); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8704fea1ca..58ec6e8ac9 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif =20 /* Target-specific values for ctx->base.is_jmp. */ @@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 !=3D B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317613548100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/user-exec.c | 9 +++------ accel/tcg/trace-events | 3 +++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 6a3fec3002..1c9486c76d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "trace.h" #include "tcg/tcg-ldst.h" #include "internal.h" =20 @@ -45,8 +46,6 @@ =20 __thread uintptr_t helper_retaddr; =20 -//#define DEBUG_SIGNAL - /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ @@ -133,10 +132,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigi= nfo_t *info, abort(); } =20 -#if defined(DEBUG_SIGNAL) - printf("qemu: SIGSEGV pc=3D0x%08lx address=3D%08lx w=3D%d oldset=3D0x%= 08lx\n", - pc, address, is_write, *(unsigned long *)old_set); -#endif + trace_sigsegv(pc, address, is_write, *(unsigned long *)old_set); + /* XXX: locking issue */ /* Note that it is important that we don't call page_unprotect() unless * this is really a "write to nonwriteable page" fault, because diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 59eab96f26..d54416f2ee 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -8,3 +8,6 @@ exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flag= s=3D0x%x" =20 # translate-all.c translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x= %"PRIxPTR", tb_code:%p" + +# user-exec.c +sigsegv(uintptr_t pc, uintptr_t addr, int is_write, unsigned long old_set)= "pc:0x%"PRIxPTR", addr:0x%"PRIxPTR", w:%d, oldset:0x%lx" --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317738412100001 Content-Type: text/plain; charset="utf-8" There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 13 +++++++++++++ target/alpha/cpu.h | 6 ------ target/arm/cpu.h | 7 ------- target/avr/cpu.h | 2 -- target/cris/cpu.h | 8 -------- target/hexagon/cpu.h | 3 --- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 7 ------- target/m68k/cpu.h | 8 -------- target/microblaze/cpu.h | 7 ------- target/mips/cpu.h | 3 --- target/mips/internal.h | 2 -- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 7 ------- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 4 ---- target/s390x/cpu.h | 7 ------- target/sh4/cpu.h | 3 --- target/sparc/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 13 insertions(+), 89 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5d1b6d80fb..9d5987ba04 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env, } return addr; } + +/** + * cpu_signal_handler + * @signum: host signal number + * @pinfo: host siginfo_t + * @puc: host ucontext_t + * + * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions. Returns true if the signal was handled by + * the virtual CPU. + */ +int cpu_signal_handler(int signum, void *pinfo, void *puc); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d9099ea188..dfa34f93b4 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, uintptr_t retaddr) QEMU_NORETURN; =20 #define cpu_list alpha_cpu_list -#define cpu_signal_handler cpu_alpha_signal_handler =20 typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; @@ -442,11 +441,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU =20 void alpha_cpu_list(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_alpha_signal_handler(int host_signum, void *pinfo, - void *puc); bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d5..48f0cc490e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1117,12 +1117,6 @@ static inline bool is_a64(CPUARMState *env) return env->aarch64; } =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_arm_signal_handler(int host_signum, void *pinfo, - void *puc); - /** * pmu_op_start/finish * @env: CPUARMState @@ -3002,7 +2996,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU =20 -#define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list =20 /* ARM has the following "translation regimes" (as the ARM ARM calls them): diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 93e3faa0a9..dceacf3cd7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, in= t feature) } =20 #define cpu_list avr_cpu_list -#define cpu_signal_handler cpu_avr_signal_handler #define cpu_mmu_index avr_cpu_mmu_index =20 static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); =20 void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b6492909..c87987e95c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByte= Array *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_cris_signal_handler(int host_signum, void *pinfo, - void *puc); - void cris_initialize_tcg(void); void cris_initialize_crisv10_tcg(void); =20 @@ -250,8 +244,6 @@ enum { #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU =20 -#define cpu_signal_handler cpu_cris_signal_handler - /* MMU modes definitions */ #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index bde538fd5c..f90c187888 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -129,9 +129,6 @@ typedef struct HexagonCPU { =20 #include "cpu_bits.h" =20 -#define cpu_signal_handler cpu_hexagon_signal_handler -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); - static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong= *pc, target_ulong *cs_base, uint32_t *f= lags) { diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 332ca5de62..1a0907ec0f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -322,9 +322,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState= *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif =20 -#define cpu_signal_handler cpu_hppa_signal_handler - -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6c50d3ab4f..7045e46af4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1940,12 +1940,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr= , int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, - void *puc); - /* cpu.c */ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3); @@ -2011,7 +2005,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif =20 -#define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list =20 /* MMU modes definitions */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 997d588911..da7b6b2fab 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -175,13 +175,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); =20 void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_m68k_signal_handler(int host_signum, void *pinfo, - void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); @@ -561,7 +554,6 @@ enum { #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU =20 -#define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list =20 /* MMU modes definitions */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 620c3742e1..bda697494b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -383,16 +383,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, u= int32_t val) } =20 void mb_tcg_init(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_mb_signal_handler(int host_signum, void *pinfo, - void *puc); =20 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU =20 -#define cpu_signal_handler cpu_mb_signal_handler - /* MMU modes definitions */ #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1dfe69c6c0..56b1cbd091 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1193,7 +1193,6 @@ struct MIPSCPU { =20 void mips_cpu_list(void); =20 -#define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list =20 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); @@ -1277,8 +1276,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 =20 -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); - #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU diff --git a/target/mips/internal.h b/target/mips/internal.h index eecdd10116..daddb05fd4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ =20 -#define cpu_signal_handler cpu_mips_signal_handler - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 27227b1e88..a80587338a 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ struct Nios2CPU { =20 void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU =20 #define cpu_gen_code cpu_nios2_gen_code -#define cpu_signal_handler cpu_nios2_signal_handler =20 #define CPU_SAVE_VERSION 1 =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f8..456a0cb1a7 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -322,11 +322,9 @@ void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #define cpu_list cpu_openrisc_list -#define cpu_signal_handler cpu_openrisc_signal_handler =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 93d308ac8f..8e39f03bd0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; =20 /*************************************************************************= ****/ void ppc_translate_init(void); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -1362,7 +1356,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val); #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU =20 -#define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list =20 /* MMU modes definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a5b0047bfd..4b1141e0d1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -357,7 +357,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); =20 -#define cpu_signal_handler riscv_cpu_signal_handler #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index =20 @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64= _t (*fn)(uint32_t), void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 void riscv_translate_init(void); -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7b..56f99826ea 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -132,13 +132,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 void rx_translate_init(void); -int cpu_rx_signal_handler(int host_signum, void *pinfo, - void *puc); - void rx_cpu_list(void); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); =20 -#define cpu_signal_handler cpu_rx_signal_handler #define cpu_list rx_cpu_list =20 #include "exec/cpu-all.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..3153d053e9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t ge= n, uint8_t ec_ga, #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU =20 -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_signal_handler cpu_s390x_signal_handler - - /* interrupt.c */ #define RA_IGNORED 0 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t r= a); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 5f2dc551e3..d7ac67e0d3 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -216,8 +216,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, uintptr_t retaddr) QEMU_NORETURN; =20 void sh4_translate_init(void); -int cpu_sh4_signal_handler(int host_signum, void *pinfo, - void *puc); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -251,7 +249,6 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU =20 -#define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list =20 /* MMU modes definitions */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ff8ae73002..6b40d02237 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr, int mmu_idx); #endif #endif -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); =20 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU =20 -#define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list =20 /* MMU modes definitions */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f..c461387e71 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 void tricore_cpu_list(void); =20 -#define cpu_signal_handler cpu_tricore_signal_handler #define cpu_list tricore_cpu_list =20 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; =20 void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); =20 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong= *pc, target_ulong *cs_base, uint32_t *f= lags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index aa9c77d719..029a331f7e 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -582,7 +582,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; =20 -#define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list =20 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU @@ -611,7 +610,6 @@ void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); qemu_irq xtensa_get_runstall(CPUXtensaState *env); -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); void xtensa_cpu_list(void); void xtensa_sync_window_from_phys(CPUXtensaState *env); void xtensa_sync_phys_from_window(CPUXtensaState *env); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317589; cv=none; d=zohomail.com; s=zohoarc; b=MvfN4yLiZIWL6q2vUMo6sL39sA4OWUEN6jFr25a32+UziAAvBAjgRe5EEdK4y5a/excJFU1u1hV2kpXb8OIMhdQDeGUN3DCDAgtIgoU6Rxln2A4a8OnKLZH8Crt3BzHd+7EHbmJ1iLEbRk7Lxjlnl4ioODc4x2j0Qj7B/4krcPo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 18 Aug 2021 12:23:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 59/66] accel/tcg: Handle SIGBUS in handle_cpu_signal Date: Wed, 18 Aug 2021 09:19:13 -1000 Message-Id: <20210818191920.390759-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317591064100001 Content-Type: text/plain; charset="utf-8" We've been registering host SIGBUS, but then treating it exactly like SIGSEGV. Handle BUS_ADRALN via cpu_unaligned_access, but allow other SIGBUS si_codes to continue into the host-to-guest signal coversion code in host_signal_handler. Unwind the guest state so that we report the correct guest PC for the fault. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 188 +++++++++++++++++++++++++++-------------- linux-user/signal.c | 36 +++++--- accel/tcg/trace-events | 3 +- 3 files changed, 152 insertions(+), 75 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1c9486c76d..c7ee5accb3 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -57,17 +57,123 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(= CPUState *cpu, cpu_loop_exit_noexc(cpu); } =20 -/* 'pc' is the host PC at which the exception was raised. 'address' is - the effective address of the memory exception. 'is_write' is 1 if a - write caused the exception and otherwise 0'. 'old_set' is the - signal set which should be restored */ -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, - int is_write, sigset_t *old_set) +static bool handle_cpu_sigsegv(CPUState *cpu, uintptr_t pc, uintptr_t addr, + int si_code, MMUAccessType access_type, + sigset_t *old_set) +{ + trace_sigsegv(pc, addr, access_type, *(unsigned long *)old_set); + + /* XXX: locking issue */ + /* + * Note that it is important that we don't call page_unprotect() unless + * this is really a "write to nonwriteable page" fault, because + * page_unprotect() assumes that if it is called for an access to + * a page that's writeable this means we had two threads racing and + * another thread got there first and already made the page writeable; + * so we will retry the access. If we were to call page_unprotect() + * for some other kind of fault that should really be passed to the + * guest, we'd end up in an infinite loop of retrying the faulting + * access. + */ + if (access_type =3D=3D MMU_DATA_STORE + && si_code =3D=3D SEGV_ACCERR + && h2g_valid(addr)) { + switch (page_unprotect(h2g_nocheck(addr), pc)) { + case 0: + /* + * Fault not caused by a page marked unwritable to protect + * cached translations, must be the guest binary's problem. + */ + break; + case 1: + /* + * Fault caused by protection of cached translation; TBs + * invalidated, so resume execution. Retain helper_retaddr + * for a possible second fault. + */ + return true; + case 2: + /* + * Fault caused by protection of cached translation, and the + * currently executing TB was modified and must be exited + * immediately. Clear helper_retaddr for next execution. + */ + clear_helper_retaddr(); + cpu_exit_tb_from_sighandler(cpu, old_set); + /* NORETURN */ + default: + g_assert_not_reached(); + } + } + + /* + * Convert forcefully to guest address space, invalid addresses + * are still valid segv ones. + */ + addr =3D h2g_nocheck(addr); + + /* + * There is no way the target can handle this other than raising + * an exception. Undo signal and retaddr state prior to longjmp. + */ + sigprocmask(SIG_SETMASK, old_set, NULL); + clear_helper_retaddr(); + + CPUClass *cc =3D CPU_GET_CLASS(cpu); + cc->tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, = pc); + g_assert_not_reached(); +} + +static bool handle_cpu_sigbus(CPUState *cpu, uintptr_t pc, uintptr_t addr, + int si_code, MMUAccessType access_type, + sigset_t *old_set) +{ + trace_sigbus(pc, addr, access_type, *(unsigned long *)old_set); + + if (si_code =3D=3D BUS_ADRALN) { + /* + * We're expecting host alignment faults to correspond + * directly to guest alignment faults, and thus the host + * address must correspond to a guest address. + */ + addr =3D h2g(addr); + + /* Undo signal and retaddr state prior to longjmp. */ + sigprocmask(SIG_SETMASK, old_set, NULL); + clear_helper_retaddr(); + + cpu_unaligned_access(cpu, addr, access_type, MMU_USER_IDX, pc); + } + + /* + * Otherwise this is probably BUS_ADRERR or suchlike, which + * can be easily triggered by the guest playing with mmap + * and accessing past the end of the file. + * + * Use PC to unwind to the current guest address and then + * return false to pass on the host signal to the guest. + */ + cpu_restore_state(cpu, pc, true); + return false; +} + +/** + * handle_cpu_signal: + * @pc: the host PC at which the exception was raised, + * @address: the effective address of the memory exception, + * @is_write: true if a write caused the exception, + * @old_set: signal set which should be restored. + * + * Return true if the signal has been handled by the vcpu, + * false if the signal should be sent on to the guest. + */ +static bool handle_cpu_signal(uintptr_t pc, siginfo_t *info, + bool is_write, sigset_t *old_set) { CPUState *cpu =3D current_cpu; - CPUClass *cc; - unsigned long address =3D (unsigned long)info->si_addr; + uintptr_t addr =3D (uintptr_t)info->si_addr; MMUAccessType access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOA= D; + int code; =20 switch (helper_retaddr) { default: @@ -119,7 +225,8 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, break; } =20 - /* For synchronous signals we expect to be coming from the vCPU + /* + * For synchronous signals we expect to be coming from the vCPU * thread (so current_cpu should be valid) and either from running * code or during translation which can fault as we cross pages. * @@ -132,62 +239,15 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, abort(); } =20 - trace_sigsegv(pc, address, is_write, *(unsigned long *)old_set); - - /* XXX: locking issue */ - /* Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because - * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; - * so we will retry the access. If we were to call page_unprotect() - * for some other kind of fault that should really be passed to the - * guest, we'd end up in an infinite loop of retrying the faulting - * access. - */ - if (is_write && info->si_signo =3D=3D SIGSEGV && info->si_code =3D=3D = SEGV_ACCERR && - h2g_valid(address)) { - switch (page_unprotect(h2g(address), pc)) { - case 0: - /* Fault not caused by a page marked unwritable to protect - * cached translations, must be the guest binary's problem. - */ - break; - case 1: - /* Fault caused by protection of cached translation; TBs - * invalidated, so resume execution. Retain helper_retaddr - * for a possible second fault. - */ - return 1; - case 2: - /* Fault caused by protection of cached translation, and the - * currently executing TB was modified and must be exited - * immediately. Clear helper_retaddr for next execution. - */ - clear_helper_retaddr(); - cpu_exit_tb_from_sighandler(cpu, old_set); - /* NORETURN */ - - default: - g_assert_not_reached(); - } + code =3D info->si_code; + switch (info->si_signo) { + case SIGSEGV: + return handle_cpu_sigsegv(cpu, pc, addr, code, access_type, old_se= t); + case SIGBUS: + return handle_cpu_sigbus(cpu, pc, addr, code, access_type, old_set= ); + default: + g_assert_not_reached(); } - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ - address =3D h2g_nocheck(address); - - /* - * There is no way the target can handle this other than raising - * an exception. Undo signal and retaddr state prior to longjmp. - */ - sigprocmask(SIG_SETMASK, old_set, NULL); - clear_helper_retaddr(); - - cc =3D CPU_GET_CLASS(cpu); - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, - MMU_USER_IDX, false, pc); - g_assert_not_reached(); } =20 static int probe_access_internal(CPUArchState *env, target_ulong addr, diff --git a/linux-user/signal.c b/linux-user/signal.c index a8faea6f09..99b456a781 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -747,27 +747,37 @@ static inline void rewind_if_in_safe_syscall(void *pu= c) static void host_signal_handler(int host_signum, siginfo_t *info, void *puc) { - CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D env_cpu(env); + CPUState *cpu =3D thread_cpu; + CPUArchState *env =3D cpu->env_ptr; TaskState *ts =3D cpu->opaque; - int sig; target_siginfo_t tinfo; ucontext_t *uc =3D puc; struct emulated_sigtable *k; + bool must_exit =3D false; =20 - /* the CPU emulator uses some host signals to detect exceptions, - we forward to it some signals */ + /* + * The CPU emulator uses some host signals to detect exceptions, + * we forward to it some signals. + */ if ((host_signum =3D=3D SIGSEGV || host_signum =3D=3D SIGBUS) && info->si_code > 0) { - if (cpu_signal_handler(host_signum, info, puc)) + if (cpu_signal_handler(host_signum, info, puc)) { return; + } + /* + * E.g. SIGBUS, without BUS_ADRALN, which we want to pass on. + * We have unwound the TB to PC, so must use cpu_loop_exit below. + */ + must_exit =3D true; } =20 /* get target signal number */ sig =3D host_to_target_signal(host_signum); - if (sig < 1 || sig > TARGET_NSIG) + if (sig < 1 || sig > TARGET_NSIG) { + assert(!must_exit); return; + } trace_user_host_signal(env, host_signum, sig); =20 rewind_if_in_safe_syscall(puc); @@ -778,7 +788,8 @@ static void host_signal_handler(int host_signum, siginf= o_t *info, k->pending =3D sig; ts->signal_pending =3D 1; =20 - /* Block host signals until target signal handler entered. We + /* + * Block host signals until target signal handler entered. We * can't block SIGSEGV or SIGBUS while we're executing guest * code in case the guest code provokes one in the window between * now and it getting out to the main loop. Signals will be @@ -796,8 +807,13 @@ static void host_signal_handler(int host_signum, sigin= fo_t *info, sigdelset(&uc->uc_sigmask, SIGSEGV); sigdelset(&uc->uc_sigmask, SIGBUS); =20 - /* interrupt the virtual CPU as soon as possible */ - cpu_exit(thread_cpu); + /* Interrupt the virtual CPU as soon as possible. */ + if (must_exit) { + cpu->exception_index =3D EXCP_INTERRUPT; + cpu_loop_exit(cpu); + } else { + cpu_exit(cpu); + } } =20 /* do_sigaltstack() returns target values and errnos. */ diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index d54416f2ee..009fbdc124 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -10,4 +10,5 @@ exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p fl= ags=3D0x%x" translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x= %"PRIxPTR", tb_code:%p" =20 # user-exec.c -sigsegv(uintptr_t pc, uintptr_t addr, int is_write, unsigned long old_set)= "pc:0x%"PRIxPTR", addr:0x%"PRIxPTR", w:%d, oldset:0x%lx" +sigsegv(uintptr_t pc, uintptr_t addr, int access_type, unsigned long old_s= et) "pc:0x%"PRIxPTR", addr:0x%"PRIxPTR", at:%d, oldset:0x%lx" +sigbus(uintptr_t pc, uintptr_t addr, int access_type, unsigned long old_se= t) "pc:0x%"PRIxPTR", addr:0x%"PRIxPTR", at:%d, oldset:0x%lx" --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316557216100001 Content-Type: text/plain; charset="utf-8" Use load-acquire / store-release for the normal case of alignment matching the access size. Otherwise, emit a test + branch sequence invoking helper_unaligned_mmu. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 - tcg/aarch64/tcg-target.c.inc | 174 +++++++++++++++++++++++++++++++---- 2 files changed, 157 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 7a93ac8023..876af589ce 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -151,9 +151,7 @@ typedef enum { =20 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 5edca8d44d..f5664636cf 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -10,6 +10,7 @@ * See the COPYING file in the top-level directory for details. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" =20 @@ -390,6 +391,10 @@ typedef enum { I3305_LDR_v64 =3D 0x5c000000, I3305_LDR_v128 =3D 0x9c000000, =20 + /* Load/store exclusive */ + I3306_LDAR =3D 0x08808000 | LDST_LD << 22, /* plus MO << 30 */ + I3306_STLR =3D 0x08808000 | LDST_ST << 22, /* plus MO << 30 */ + /* Load/store register. Described here as 3.3.12, but the helper that emits them can transform to 3.3.10 or 3.3.13. */ I3312_STRB =3D 0x38000000 | LDST_ST << 22 | MO_8 << 30, @@ -443,6 +448,7 @@ typedef enum { I3404_ANDI =3D 0x12000000, I3404_ORRI =3D 0x32000000, I3404_EORI =3D 0x52000000, + I3404_ANDSI =3D 0x72000000, =20 /* Move wide immediate instructions. */ I3405_MOVN =3D 0x12800000, @@ -453,6 +459,9 @@ typedef enum { I3406_ADR =3D 0x10000000, I3406_ADRP =3D 0x90000000, =20 + /* Add/subtract extended register. */ + I3501_ADDEXT =3D 0x0b200000, + /* Add/subtract shifted register instructions (without a shift). */ I3502_ADD =3D 0x0b000000, I3502_ADDS =3D 0x2b000000, @@ -623,6 +632,14 @@ static void tcg_out_insn_3305(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); } =20 +static void G_GNUC_UNUSED +tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, MemOp sz, + TCGReg rs, TCGReg rt, TCGReg rt2, TCGReg rn) +{ + tcg_out32(s, insn | (sz << 30) | (rs << 16) | + (rt2 << 10) | (rn << 5) | rt); +} + static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, TCGReg rt, int imm19) { @@ -705,6 +722,13 @@ static void tcg_out_insn_3406(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | = rd); } =20 +static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, + TCGReg rm, MemOp ext) +{ + tcg_out32(s, insn | 1 << 31 | rm << 16 | ext << 13 | rn << 5 | rd); +} + /* This function is for both 3.5.2 (Add/Subtract shifted register), for the rare occasion when we actually want to supply a shift amount. */ static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, @@ -1328,8 +1352,9 @@ static void tcg_out_goto_long(TCGContext *s, const tc= g_insn_unit *target) if (offset =3D=3D sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, B, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + /* Choose X9 as a call-clobbered non-LR temporary. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X9, (intptr_t)target); + tcg_out_insn(s, 3207, BR, TCG_REG_X9); } } =20 @@ -1541,9 +1566,14 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -#ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.c.inc" +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} =20 +#ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1577,13 +1607,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D= { #endif }; =20 -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *targe= t) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; @@ -1714,15 +1737,85 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); } =20 +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, + unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + label->label_ptr[0] =3D s->code_ptr; + + /* b.ne slow_path */ + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + + /* + * "Tail call" to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. + */ + tcg_out_adr(s, TCG_REG_LR, l->raddr); + tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static void tcg_out_qemu_ld_acquire(TCGContext *s, MemOp memop, TCGType ex= t, + TCGReg data_r, TCGReg addr_r) +{ + MemOp size =3D memop & MO_SIZE; + + tcg_out_insn(s, 3306, LDAR, size, + TCG_REG_XZR, data_r, TCG_REG_XZR, addr_r); + if (memop & MO_SIGN) { + tcg_out_sxt(s, ext, size, data_r, data_r); + } +} + +static void tcg_out_qemu_st_release(TCGContext *s, MemOp memop, + TCGReg data_r, TCGReg addr_r) +{ + MemOp size =3D memop & MO_SIZE; + + tcg_out_insn(s, 3306, STLR, size, + TCG_REG_XZR, data_r, TCG_REG_XZR, addr_r); +} + #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1756,9 +1849,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); @@ -1782,6 +1872,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1792,6 +1886,28 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits =3D get_alignment_bits(memop); + + if (a_bits) { + /* + * If alignment required, and equals the access size, then + * use load-acquire for the size effect of alignment checking. + * Despite the extra memory barrier, for a ThunderX2 host, + * this is is about 40% faster. It is always smaller. + */ + if (a_bits =3D=3D (memop & MO_SIZE)) { + if (USE_GUEST_BASE) { + tcg_out_insn(s, 3501, ADDEXT, TCG_REG_TMP, TCG_REG_GUEST_B= ASE, + addr_reg, TARGET_LONG_BITS =3D=3D 64 ? MO_64 = : MO_32); + addr_reg =3D TCG_REG_TMP; + } + tcg_out_qemu_ld_acquire(s, memop, ext, data_reg, addr_reg); + return; + } + + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } + if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); @@ -1807,6 +1923,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1817,6 +1937,26 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ + unsigned a_bits =3D get_alignment_bits(memop); + + if (a_bits) { + /* + * If alignment required, and equals the access size, then + * use store-release for the size effect of alignment checking. + */ + if (a_bits =3D=3D (memop & MO_SIZE)) { + if (USE_GUEST_BASE) { + tcg_out_insn(s, 3501, ADDEXT, TCG_REG_TMP, TCG_REG_GUEST_B= ASE, + addr_reg, TARGET_LONG_BITS =3D=3D 64 ? MO_64 = : MO_32); + addr_reg =3D TCG_REG_TMP; + } + tcg_out_qemu_st_release(s, memop, data_reg, addr_reg); + return; + } + + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } + if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629315928; cv=none; d=zohomail.com; s=zohoarc; b=G7qNr8qIj6IU91oXw1VEsCqlmaU0Qkj92mDuNE8fyMaIsloFhw3LjrptKVz0oprPiBEzm2zb5HOFdEyz3on/C9/QRFrD7M5XMZ0AGWobKOd3nBB5+QdbS19aOU44Gkeo+oFAVipVnZVx02eENZVvfxfsu9VQ1TM3Fa+1DvnII9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629315928; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629315930321100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/ppc/tcg-target.h | 2 - tcg/ppc/tcg-target.c.inc | 102 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 94 insertions(+), 10 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0943192cde..c775c97b61 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -182,9 +182,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 2d4ca1f445..aa77cff09a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -24,6 +24,7 @@ =20 #include "elf.h" #include "../tcg-pool.c.inc" +#include "../tcg-ldst.c.inc" =20 #if defined _CALL_DARWIN || defined __APPLE__ #define TCG_TARGET_CALL_DARWIN @@ -1866,7 +1867,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintp= tr_t jmp_rx, } } =20 -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, int lk, + const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1877,7 +1879,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *target) =20 if (in_range_b(diff) && toc =3D=3D (uint32_t)toc) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); + tcg_out_b(s, lk, tgt); } else { /* Fold the low bits of the constant into the addresses below. */ intptr_t arg =3D (intptr_t)target; @@ -1892,7 +1894,7 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *target) tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 intptr_t diff; @@ -1906,16 +1908,21 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *target) =20 diff =3D tcg_pcrel_diff(s, target); if (in_range_b(diff)) { - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); } else { tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); + tcg_out32(s, BCCTR | BO_ALWAYS | lk); } #else - tcg_out_b(s, LK, target); + tcg_out_b(s, lk, target); #endif } =20 +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +{ + tcg_out_call_int(s, LK, target); +} + static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] =3D { [MO_UB] =3D LBZX, [MO_UW] =3D LHZX, @@ -1945,8 +1952,6 @@ static const uint32_t qemu_exts_opc[4] =3D { }; =20 #if defined (CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -2212,6 +2217,75 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_b(s, 0, lb->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *label =3D new_ldst_label(s); + + label->is_ld =3D is_ld; + label->addrlo_reg =3D addrlo; + label->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); + + label->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + + label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + TCGReg arg =3D TCG_REG_R4; +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |=3D 1; +#endif + if (l->addrlo_reg !=3D arg) { + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + } else if (l->addrhi_reg !=3D arg + 1) { + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); + tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); + tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); + } + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); + + /* + * "Tail call" to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. + */ + tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) @@ -2223,6 +2297,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2243,6 +2319,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); @@ -2298,6 +2378,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; +#else + unsigned a_bits; #endif =20 datalo =3D *args++; @@ -2318,6 +2400,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629316132; cv=none; d=zohomail.com; s=zohoarc; b=C+0zHFUQed+Gldq9zJ3r9oc7xQut0OwlzZNP7ILUv0RwJ92ve13NWVclz3J/vThJCctEWIMVQxMhQU/7CyKe/+3ZiPAUw8sjExYupAXcKkTfpU7fra6Y6DQ6fo5cJ/NLCmYTQA43k9Ol+fYSPwEClmeRtQQZVe1lNIp/d3HIHZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629316132; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ytbtEBmPvSIrsYJSIkW37yTJbTx1Gu3iDRC/cX/jYac=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629316134149100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/s390/tcg-target.h | 2 -- tcg/s390/tcg-target.c.inc | 63 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 61 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 2e4ede2ea2..04b59f2537 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -157,9 +157,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, uintptr_t jmp_rx, /* no need to flush icache explicitly */ } =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index fd0b3316d2..849457e01f 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -29,6 +29,7 @@ #error "unsupported code generation mode" #endif =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" =20 @@ -134,6 +135,7 @@ typedef enum S390Opcode { RI_OIHL =3D 0xa509, RI_OILH =3D 0xa50a, RI_OILL =3D 0xa50b, + RI_TMLL =3D 0xa701, =20 RIE_CGIJ =3D 0xec7c, RIE_CGRJ =3D 0xec64, @@ -1488,8 +1490,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); @@ -1626,6 +1626,57 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, + TCGReg addrlo, unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *l =3D new_ldst_label(s); + + l->is_ld =3D is_ld; + l->addrlo_reg =3D addrlo; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addrlo, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + l->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 1; + + l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); + + /* + * "Tail call" to the helper, with the return address back inline, + * just for the clarity of the debugging traceback -- the helper + * cannot return. + */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr); + tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unalign= ed_ld + : helper_unaligned_st)); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, TCGReg *index_reg, tcg_target_long *disp) { @@ -1664,7 +1715,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits =3D get_alignment_bits(opc); =20 + if (a_bits) { + tcg_out_test_alignment(s, true, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif @@ -1691,7 +1746,11 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, #else TCGReg index_reg; tcg_target_long disp; + unsigned a_bits =3D get_alignment_bits(opc); =20 + if (a_bits) { + tcg_out_test_alignment(s, false, addr_reg, a_bits); + } tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); #endif --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317667; cv=none; d=zohomail.com; s=zohoarc; b=Mr3ckx0CyPdH2ssnC+p4x4yob9GVaHMJ2ADJ7e6wptai4VYLcw7YsovqmRYjAg7MKyZk5vl53mJvkrcUcbjYZg+rLDrkvTmuhzXzaFevum1VmvgzN0wFkfGqQG8Qk/7X70plasMg52vjzD4iyudM5V7ogcG/Vx/IbX368dN7MVM= ARC-Message-Signature: i=1; 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Wed, 18 Aug 2021 12:23:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 63/66] tcg/tci: Support raising sigbus for user-only Date: Wed, 18 Aug 2021 09:19:17 -1000 Message-Id: <20210818191920.390759-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317669808100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e76087ccac..985c8a91cb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -296,7 +296,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_u= long taddr, uintptr_t ra =3D (uintptr_t)tb_ptr; =20 #ifdef CONFIG_SOFTMMU - switch (mop) { + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: return helper_ret_ldub_mmu(env, taddr, oi, ra); case MO_SB: @@ -326,10 +326,14 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target= _ulong taddr, } #else void *haddr =3D g2h(env_cpu(env), taddr); + unsigned a_mask =3D (1u << get_alignment_bits(mop)) - 1; uint64_t ret; =20 set_helper_retaddr(ra); - switch (mop) { + if (taddr & a_mask) { + helper_unaligned_ld(env, taddr); + } + switch (mop & (MO_BSWAP | MO_SSIZE)) { case MO_UB: ret =3D ldub_p(haddr); break; @@ -377,11 +381,11 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target= _ulong taddr, static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, MemOpIdx oi, const void *tb_ptr) { - MemOp mop =3D get_memop(oi) & (MO_BSWAP | MO_SSIZE); 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Wed, 18 Aug 2021 12:23:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 64/66] tcg: Canonicalize alignment flags in MemOp Date: Wed, 18 Aug 2021 09:19:18 -1000 Message-Id: <20210818191920.390759-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317858579100001 Content-Type: text/plain; charset="utf-8" Having observed e.g. al8+leq in dumps, canonicalize to al+leq. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b1cfd36f29..61b492d89f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2765,7 +2765,12 @@ void tcg_gen_lookup_and_goto_ptr(void) static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { /* Trigger the asserts within as early as possible. */ - (void)get_alignment_bits(op); + unsigned a_bits =3D get_alignment_bits(op); + + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ + if (a_bits =3D=3D (op & MO_SIZE)) { + op =3D (op & ~MO_AMASK) | MO_ALIGN; + } =20 switch (op & MO_SIZE) { case MO_8: --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 18 Aug 2021 12:23:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 65/66] tcg/riscv: Support raising sigbus for user-only Date: Wed, 18 Aug 2021 09:19:19 -1000 Message-Id: <20210818191920.390759-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317815711100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 -- tcg/riscv/tcg-target.c.inc | 64 +++++++++++++++++++++++++++++++++++--- 2 files changed, 60 insertions(+), 6 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ef78b99e98..11c9b3e4f4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -165,9 +165,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) =20 -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #define TCG_TARGET_NEED_POOL_LABELS =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c1b0c3764d..f75dcf88f8 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -27,6 +27,7 @@ * THE SOFTWARE. */ =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -847,8 +848,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) */ =20 #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) */ @@ -1053,6 +1052,53 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); return true; } +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, + unsigned a_bits) +{ + unsigned a_mask =3D (1 << a_bits) - 1; + TCGLabelQemuLdst *l =3D new_ldst_label(s); + + l->is_ld =3D is_ld; + l->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, so we can always use andi.= */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + l->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + + l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + /* resolve label address */ + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); + /* tail call, with the return address back inline for unwinding */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); + tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld + : helper_unaligned_st), true); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1108,6 +1154,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base =3D TCG_REG_TMP0; =20 @@ -1130,7 +1178,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } - + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, a_bits); + } if (guest_base =3D=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); } else { @@ -1177,6 +1228,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; +#else + unsigned a_bits; #endif TCGReg base =3D TCG_REG_TMP0; =20 @@ -1199,7 +1252,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } - + a_bits =3D get_alignment_bits(opc); + if (a_bits) { + tcg_out_test_alignment(s, false, addr_regl, a_bits); + } if (guest_base =3D=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); } else { --=20 2.25.1 From nobody Fri May 17 23:00:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1629317974; cv=none; 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Wed, 18 Aug 2021 12:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 66/66] tcg/riscv: Remove add with zero on user-only memory access Date: Wed, 18 Aug 2021 09:19:20 -1000 Message-Id: <20210818191920.390759-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818191920.390759-1-richard.henderson@linaro.org> References: <20210818191920.390759-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1629317975325100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/riscv/tcg-target.c.inc | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f75dcf88f8..b84a4e876b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1182,9 +1182,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, a_bits); } - if (guest_base =3D=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); @@ -1256,9 +1254,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) if (a_bits) { tcg_out_test_alignment(s, false, addr_regl, a_bits); } - if (guest_base =3D=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { + if (guest_base !=3D 0) { tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); --=20 2.25.1