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[2001:16b8:2b53:c500:4989:ea3b:b9da:8dea]) by smtp.gmail.com with ESMTPSA id w18sm4902609wrg.68.2021.08.18.00.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 00:09:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I4d5/jylUJng8gB+j35WYKKGet2c3NfEVZGEKd+aN0I=; b=MRnQfrHccQoIjUaBUepI9Hnrl4ZsTGld5djqOmR9bmU+BqS8rkom2SH/Ocj1PieROI hKS+ikA4vOCojBARyM8WuMMhC2X0tzQ5KMdGf/jqnpmmUFdx99o6w0uvqCINWF1jBxnA HxI6BReVQWZmFYKlQinv6WLOJRpUbDxcCeOTA5onGaZox7N1TjqkyGIrhCfkYXplVwYO ylh4CBv2c0qbBi5JrzOFj16dCHETX75e4RKoea7OjBqPkVT9K1Hxg7n2Vuz8h119derv oVq3MFNFD/BO+O9pFklQydiavyizguV0JvLE49enBtu8ZLPb1bZshxXng+eVfrq4uoSi hkCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I4d5/jylUJng8gB+j35WYKKGet2c3NfEVZGEKd+aN0I=; b=FAMkMMg0NhX2neV5dz5SBmcBKkIkpd27JHKKV2M/WzUxJvzkt3MkUIk+65FFjMkbYk dp1zUGgF7jvxuA//X9MbAYLwbI5yEUxx8vwY3IcJ5ilYwhwTmAZ/aCG7raAjcz7QJYZp ZQwoco7ywCy5lsHAeIW7CnVcLW63POhiimJhxe3NK4x1AM8nF1N/78O/VTKksLYL8tN2 X9Oa7nC6RPQoM6UfRnDm+Rqsxwh6u/xIXvP2MO2gUr5mJmhZvrN+kX1q4IxWpuU5uHGw WL+0yP/Wkg8IjySO8Ku/vXRvEWZPKL/56gvrXjL87FK2lsqAm8/LMl0mkIDQo44nvs/5 OMsA== X-Gm-Message-State: AOAM5307msOZhLa/iTOjQr9DdgnAwZbarbgRe0m1OnARtjCWqUV+MN3K D0Z8Qw8C3aYpzsYtDawIW5Cj9f3A8vA= X-Google-Smtp-Source: ABdhPJyNX/cOZfNLaisoqZodvmG7V1d/EOxAia2zOO72IBQ7Jtghk/unjcK0CL0nBbH++IBvwJ8svg== X-Received: by 2002:a1c:2547:: with SMTP id l68mr7221296wml.23.1629270545456; Wed, 18 Aug 2021 00:09:05 -0700 (PDT) From: Lara Lazier To: qemu-devel@nongnu.org Subject: [PATCH 2/4] target/i386: Added VGIF V_IRQ masking capability Date: Wed, 18 Aug 2021 09:08:36 +0200 Message-Id: <20210818070838.44344-4-laramglazier@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818070838.44344-1-laramglazier@gmail.com> References: <20210818070838.44344-1-laramglazier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=laramglazier@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, Lara Lazier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1629270736628100005 Content-Type: text/plain; charset="utf-8" VGIF provides masking capability for when virtual interrupts are taken. (APM2) Signed-off-by: Lara Lazier --- target/i386/cpu.c | 7 +++++-- target/i386/cpu.h | 2 ++ target/i386/tcg/sysemu/svm_helper.c | 12 ++++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5dcdab3b80..b2094175d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5649,6 +5649,7 @@ static void x86_cpu_reset(DeviceState *dev) /* init to reset state */ env->int_ctl =3D 0; env->hflags2 |=3D HF2_GIF_MASK; + env->hflags2 |=3D HF2_VGIF_MASK; env->hflags &=3D ~HF_GUEST_MASK; =20 cpu_x86_update_cr0(env, 0x60000010); @@ -6532,10 +6533,12 @@ int x86_cpu_pending_interrupt(CPUState *cs, int int= errupt_request) !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { return CPU_INTERRUPT_HARD; #if !defined(CONFIG_USER_ONLY) - } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && + } else if (env->hflags2 & HF2_VGIF_MASK) { + if((interrupt_request & CPU_INTERRUPT_VIRQ) && (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) { - return CPU_INTERRUPT_VIRQ; + return CPU_INTERRUPT_VIRQ; + } #endif } } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e27a1aab99..d26df6de6b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -203,6 +203,7 @@ typedef enum X86Seg { #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=3D0 */ +#define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ =20 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) @@ -212,6 +213,7 @@ typedef enum X86Seg { #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) +#define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) =20 #define CR0_PE_SHIFT 0 #define CR0_MP_SHIFT 1 diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 9ef2454779..2c44bdb243 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -130,6 +130,11 @@ static inline bool virtual_gif_enabled(CPUX86State *en= v) return false; } =20 +static inline bool virtual_gif_set(CPUX86State *env) +{ + return !virtual_gif_enabled(env) || (env->int_ctl & V_GIF_MASK); +} + void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { CPUState *cs =3D env_cpu(env); @@ -363,6 +368,10 @@ void helper_vmrun(CPUX86State *env, int aflag, int nex= t_eip_addend) cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ; } =20 + if (virtual_gif_set(env)) { + env->hflags2 |=3D HF2_VGIF_MASK; + } + /* maybe we need to inject an event */ event_inj =3D x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); @@ -519,6 +528,7 @@ void helper_stgi(CPUX86State *env) =20 if (virtual_gif_enabled(env)) { env->int_ctl |=3D V_GIF_MASK; + env->hflags2 |=3D HF2_VGIF_MASK; } else { env->hflags2 |=3D HF2_GIF_MASK; } @@ -530,6 +540,7 @@ void helper_clgi(CPUX86State *env) =20 if (virtual_gif_enabled(env)) { env->int_ctl &=3D ~V_GIF_MASK; + env->hflags2 &=3D ~HF2_VGIF_MASK; } else { env->hflags2 &=3D ~HF2_GIF_MASK; } @@ -811,6 +822,7 @@ void do_vmexit(CPUX86State *env) env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0); =20 env->hflags2 &=3D ~HF2_GIF_MASK; + env->hflags2 &=3D ~HF2_VGIF_MASK; /* FIXME: Resets the current ASID register to zero (host ASID). */ =20 /* Clears the V_IRQ and V_INTR_MASKING bits inside the processor. */ --=20 2.25.1