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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gy7QIjwsa6xMVXE5/WQWgxzP9shOsuOqrCvuoAh1kM0=; b=yjEztFIiLyTiFaUGHat3wweOHC+q7B1SVZktRxyNoKabbUmXzq9zgwbvQHWkRlskJR PH0GtkH6Js8m1bZRrw+PUP5heepK13l56bubLm8B8GNQSIKdnblBTW3yBugpEiH0qMmK aqUWHQX6fBC0xSWJn/4i9hkbNtzErj0qBLTrDoW44DpCiEQVEkN7LLd3QHgvirYs4ufx cS8557TZEjDNjxUb1ZUW0maKaeUMrHTzYIHJNDoW4oazsoF2rGbHFUvOgJPQfZO5JMF1 MA3hkthZJTZGv7a9+z43gWFUmnfTledZGrMOjx0/LPvx7YnBxNh53ZBGVskn0egqKfgY ywdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gy7QIjwsa6xMVXE5/WQWgxzP9shOsuOqrCvuoAh1kM0=; b=Q9dcF+J2T3k2FMDrr9x4fYizxN43IzggTK3i6F+D3P+q/4SZ7w+C9Y/HjSzeHoHQ5d mk3xZ/UWDBQwkZpv9IdB5q8xgdn0e30AAfn1V8U0zEKO3qSsgy6b6/49ShYSzC5SJ0jD EdGTwbQYSvziyH7WOuccBl1HlLb/w3XNIXpSAAcYU2LelWJIZPOM+KKCUExV3ahADHQw mQtUtaqOAQiyBuqiYaguFX6X/4QfK00jGaAbyQMQMLsMDwnxRbq30FlpXq/uq+GvMaKN lrJAfhm9yyHsaJplWxXMGcJj1aRRWHzwmfG9XLbZop+KCpJTxNsjOkjMli7lJkKoRlCl pHMw== X-Gm-Message-State: AOAM530MLoqzUZRyTUc9tosoG/R/LzUTHnIS/2zdRM1IU31l8MuDb+ha NRbV7f0aXHz8ELAA5rSHp6O1gw== X-Google-Smtp-Source: ABdhPJyOmXWFvfimkUSaqvHXtbMt4h2g9MAtAh2S8uua2F7zFr//AXorfDG4+o9BUr+dn1N8+A80eQ== X-Received: by 2002:a1c:f206:: with SMTP id s6mr14389545wmc.15.1628760845800; Thu, 12 Aug 2021 02:34:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Date: Thu, 12 Aug 2021 10:33:38 +0100 Message-Id: <20210812093356.1946-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761406308100001 Content-Type: text/plain; charset="utf-8" Wire up the cpuclk for the systick devices to the SSE object's existing mainclk clock. We do not wire up the refclk because the SSE subsystems do not provide a refclk. (This is documented in the IoTKit and SSE-200 TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the same approach.) When we update the systick device later to honour "no refclk connected" this will fix a minor emulation inaccuracy for the SSE-based boards. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Luc Michel --- hw/arm/armsse.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index a1456cb0f42..70b52c3d4b9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) int j; char *gpioname; =20 + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk); + /* The SSE subsystems do not wire up a systick refclk */ + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IR= QS); /* * In real hardware the initial Secure VTOR is set from the INITSV= TOR* --=20 2.20.1