From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628760928780554.7098149320482; Thu, 12 Aug 2021 02:35:28 -0700 (PDT) Received: from localhost ([::1]:45958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE77X-0000B8-IL for importer@patchew.org; Thu, 12 Aug 2021 05:35:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76C-00051z-H6 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:04 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:35546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE769-0007k8-Ku for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:03 -0400 Received: by mail-wr1-x42b.google.com with SMTP id q10so7378068wro.2 for ; Thu, 12 Aug 2021 02:34:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yLuII2N7SomdN1vXoXib6V3sTgzvv7Z37XwvXeMMKcE=; b=jDHSso3rMrxvfiMupg69eZQIq0SBAF9aZxq3yswNrsKnnOE9Vs/eCij4bhEWHaseGZ abrW+juaH4uVSbeqG7L3uv4IIqe2xD63wIp7wOYVyQrmH+2Ec2ayOf3SQxWVk0Y5LMO9 c9MJNvg1NfP1VCVkki3KS1wrPwEdYKV/wEAOzIM+wK4j+R5yhcG6r72pa563J9g+Kthw 3b49TWIx9K4ou9ni29ldrLdIiy1CdK1M3lqSqAOwUN4atA0qt7VGYh2+AHhbLBCL9MSH YcN9SHiT9zdBsbPbIF5bdzWXNVKo2AYNTGlsIuEEPVrzFsmj0rk/604ssMuFFssvmie6 SbxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yLuII2N7SomdN1vXoXib6V3sTgzvv7Z37XwvXeMMKcE=; b=rh2Z6d3PfiGNfLzikFTUcW6XjciLcbdcEyy1Qa/6kcqdpJvnOk5iLv4cT6kZGR6hWa ZRR3phOSURR1kWUsBZC6Djyvk4Ay8XJhQ+U6e2stbwxaorsdYSnzlQ1uNR4Zd4kwD9Gk YMupvu47P0lgB7bT4v9Y9NizNSE7GVCqa3u0xAmje7o4jaI2CZ+gOLzyCnC9iZD+sZUx RjX/exDFY7G6SEw6ttQPop8YS97mA10j/7Z/pT5Upqu7xbQ2NbRioz/wHqsyiKSXo5d+ 864ARYe3tGTg7h1UgLQUVD0RTQiC/1LS6YkFZ5ertu1dXO6YANVuxiBr79urA5o8V49x bDiA== X-Gm-Message-State: AOAM530IDm8AuT4bkqMVj8h/oh18LqpPAVAZDGcm2fbzbBYXS0V+JoSn wAq+8koEGJfgK9IOg9HY4Gzk5w== X-Google-Smtp-Source: ABdhPJzygXjdyvbSgyfCcnS6uN9RAWNQHoYCdWeiBLn4fskr4c8n6GXwcorxRMDyDuVJMmr1bJqexw== X-Received: by 2002:a05:6000:247:: with SMTP id m7mr2936992wrz.335.1628760840132; Thu, 12 Aug 2021 02:34:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Date: Thu, 12 Aug 2021 10:33:32 +0100 Message-Id: <20210812093356.1946-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761832288100001 Content-Type: text/plain; charset="utf-8" Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Damien Hedde Reviewed-by: Luc Michel --- include/hw/arm/armv7m.h | 2 + include/hw/intc/armv7m_nvic.h | 1 - include/hw/misc/armv7m_ras.h | 37 ++++++++++++++ hw/arm/armv7m.c | 12 +++++ hw/intc/armv7m_nvic.c | 56 --------------------- hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + hw/misc/meson.build | 2 + 8 files changed, 148 insertions(+), 57 deletions(-) create mode 100644 include/hw/misc/armv7m_ras.h create mode 100644 hw/misc/armv7m_ras.c diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index bc6733c5184..4cae0d7eeaa 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -12,6 +12,7 @@ =20 #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" +#include "hw/misc/armv7m_ras.h" #include "target/arm/idau.h" #include "qom/object.h" =20 @@ -58,6 +59,7 @@ struct ARMv7MState { NVICState nvic; BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; + ARMv7MRAS ras; =20 /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 39c71e15936..33b6d8810c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,7 +83,6 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; - MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; =20 diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h new file mode 100644 index 00000000000..f8773e65b14 --- /dev/null +++ b/include/hw/misc/armv7m_ras.h @@ -0,0 +1,37 @@ +/* + * Arm M-profile RAS block + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the RAS register block of an M-profile CPU + * (the registers starting at 0xE0005000 with ERRFRn). + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + * The QEMU implementation currently provides "minimal RAS" only. + */ + +#ifndef HW_MISC_ARMV7M_RAS_H +#define HW_MISC_ARMV7M_RAS_H + +#include "hw/sysbus.h" + +#define TYPE_ARMV7M_RAS "armv7m-ras" +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS) + +struct ARMv7MRAS { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; +}; + +#endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 9ce5c30cd5c..8964730d153 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 + /* If the CPU has RAS support, create the RAS register block */ + if (cpu_isar_feature(aa32_ras, s->cpu)) { + object_initialize_child(OBJECT(dev), "armv7m-ras", + &s->ras, TYPE_ARMV7M_RAS); + sbd =3D SYS_BUS_DEVICE(&s->ras); + if (!sysbus_realize(sbd, errp)) { + return; + } + memory_region_add_subregion_overlap(&s->container, 0xe0005000, + sysbus_mmio_get_region(sbd, 0)= , 1); + } + for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { if (s->enable_bitband) { Object *obj =3D OBJECT(&s->bitband[i]); diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1e7ddcb94cb..a5975592dfa 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 - -static MemTxResult ras_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - if (attrs.user) { - return MEMTX_ERROR; - } - - switch (addr) { - case 0xe10: /* ERRIIDR */ - /* architect field =3D Arm; product/variant/revision 0 */ - *data =3D 0x43b; - break; - case 0xfc8: /* ERRDEVID */ - /* Minimal RAS: we implement 0 error record indexes */ - *data =3D 0; - break; - default: - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", - (uint32_t)addr); - *data =3D 0; - break; - } - return MEMTX_OK; -} - -static MemTxResult ras_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - if (attrs.user) { - return MEMTX_ERROR; - } - - switch (addr) { - default: - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", - (uint32_t)addr); - break; - } - return MEMTX_OK; -} - -static const MemoryRegionOps ras_ops =3D { - .read_with_attrs =3D ras_read, - .write_with_attrs =3D ras_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) &s->systick_ns_mem, 1); } =20 - if (cpu_isar_feature(aa32_ras, s->cpu)) { - memory_region_init_io(&s->ras_mem, OBJECT(s), - &ras_ops, s, "nvic_ras", 0x1000); - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem); - } - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c new file mode 100644 index 00000000000..a2b4f4b8dc8 --- /dev/null +++ b/hw/misc/armv7m_ras.c @@ -0,0 +1,93 @@ +/* + * Arm M-profile RAS block + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "hw/misc/armv7m_ras.h" +#include "qemu/log.h" + +static MemTxResult ras_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + case 0xe10: /* ERRIIDR */ + /* architect field =3D Arm; product/variant/revision 0 */ + *data =3D 0x43b; + break; + case 0xfc8: /* ERRDEVID */ + /* Minimal RAS: we implement 0 error record indexes */ + *data =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", + (uint32_t)addr); + *data =3D 0; + break; + } + return MEMTX_OK; +} + +static MemTxResult ras_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + default: + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", + (uint32_t)addr); + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ras_ops =3D { + .read_with_attrs =3D ras_read, + .write_with_attrs =3D ras_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + + +static void armv7m_ras_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + ARMv7MRAS *s =3D ARMV7M_RAS(obj); + + memory_region_init_io(&s->iomem, obj, &ras_ops, + s, "armv7m-ras", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void armv7m_ras_class_init(ObjectClass *klass, void *data) +{ + /* This device has no state: no need for vmstate or reset */ +} + +static const TypeInfo armv7m_ras_info =3D { + .name =3D TYPE_ARMV7M_RAS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ARMv7MRAS), + .instance_init =3D armv7m_ras_init, + .class_init =3D armv7m_ras_class_init, +}; + +static void armv7m_ras_register_types(void) +{ + type_register_static(&armv7m_ras_info); +} + +type_init(armv7m_ras_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index 37b1a8e4428..3cac393bb48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c F: hw/misc/arm_l2x0.c +F: hw/misc/armv7m_ras.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h F: include/hw/timer/a9gtimer.h F: include/hw/timer/arm_mptimer.h F: include/hw/timer/armv7m_systick.h +F: include/hw/misc/armv7m_ras.h F: tests/qtest/test-arm-mptimer.c =20 Exynos diff --git a/hw/misc/meson.build b/hw/misc/meson.build index a53b849a5a0..3f41a3a5b27 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: = files('arm_integrator_d softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) =20 +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) + # Mac devices softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) =20 --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4yStbAadGLFzaQDEPuaZrd8+oAp5eaVKNNU2N0fxc5o=; b=lczIpAqZ4j27IWWi7OPuuU7xtrIsPkn5cwZY189FZzmH7qE5mSeAORIPF830o6cRMu ErG4Y1G0YkKgNTV1WpYDqW9qiz5Wknr/6owCximbKpT8PMxhkcZZCXDQcPR0rtevOVYA MlsIZo9CbqZGYrqtxm+XsnrcGIGfXauAq16/xhFg3K4+8lmJTVZoQEaw7OlH5UXFR3IJ HYye8iq5i/jd4beHMzveGGd6KoudEHyeaHGCS0YaFNWhQDs6OLZhDqZvboNjcbBv/BxL c+ON/w+n+27gT6cY5YBqOCypfYM0bPWGQhgSTX/9SLo55fZL/nbpLW2YyvyZj47yYWOP clvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4yStbAadGLFzaQDEPuaZrd8+oAp5eaVKNNU2N0fxc5o=; b=s7V0OpeONdkcc1I4uO9SkrMj3fHaordd4E/bopSl9bZadYVbejIorlksL1HdI856oJ IRk4p2ytu4IHO0LjaPeKKs5t7IUTi2XU6C4IrWaQqM7qvgLBNydFdGyMHXHi5jbYXB4M xz/mV8M/VopOcwr4Ct2xSm5lOjD6qsV/4KOTN13BuPziJibNyc4Y4WcYM1jfwX9Ko2CE ToBsW1zyNJNzaRYC5rqsmjKyf4nGpl2RZOYIdXqNhXDEsZmsLLFQ8XPxNWIoZYxlCDAh fulH54E1ztGKhQnnMfxgPgXE/7i3adBdN/ta8kwTsnf6Pd4sXyhIVQmnI4jzGGKDhKzQ hNfg== X-Gm-Message-State: AOAM532CWVduteGXIhLKTmijg3wyymKY7Gzl91EVd63+99KsfY+VNCmI jtqvHJOxX0ftsj2i6+Mvg26kZA== X-Google-Smtp-Source: ABdhPJwu1nPdajKfMg4QlbzGCEgwC32TdPnYPKejlEeW44WXJ3VFcxncQoG/3f+0MDhm7oFExi9yJw== X-Received: by 2002:a1c:2283:: with SMTP id i125mr2041173wmi.41.1628760841169; Thu, 12 Aug 2021 02:34:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Date: Thu, 12 Aug 2021 10:33:33 +0100 Message-Id: <20210812093356.1946-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761058996100001 Content-Type: text/plain; charset="utf-8" There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place. This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/armv7m.h | 12 ++++ include/hw/intc/armv7m_nvic.h | 4 -- hw/arm/armv7m.c | 125 ++++++++++++++++++++++++++++++++++ hw/intc/armv7m_nvic.c | 73 -------------------- 4 files changed, 137 insertions(+), 77 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 4cae0d7eeaa..360c35c5fb2 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -60,11 +60,23 @@ struct ARMv7MState { BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; ARMv7MRAS ras; + SysTickState systick[M_REG_NUM_BANKS]; =20 /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. */ MemoryRegion container; + /* + * MemoryRegion which passes the transaction to either the S or the + * NS systick device depending on the transaction attributes + */ + MemoryRegion systickmem; + /* + * MemoryRegion which enforces the S/NS handling of the systick + * device NS alias region and passes the transaction to the + * NS systick device if appropriate. + */ + MemoryRegion systick_ns_mem; =20 /* Properties */ char *cpu_type; diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 33b6d8810c7..6a6a99090c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -81,16 +81,12 @@ struct NVICState { =20 MemoryRegion sysregmem; MemoryRegion sysreg_ns_mem; - MemoryRegion systickmem; - MemoryRegion systick_ns_mem; MemoryRegion container; MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; qemu_irq sysresetreq; - - SysTickState systick[M_REG_NUM_BANKS]; }; =20 #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8964730d153..364ac069702 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -124,6 +124,85 @@ static const hwaddr bitband_output_addr[ARMV7M_NUM_BIT= BANDS] =3D { 0x22000000, 0x42000000 }; =20 +static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + MemoryRegion *mr =3D opaque; + + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attr= s); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; + } +} + +static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + MemoryRegion *mr =3D opaque; + + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_TE, attrs= ); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; + } +} + +static const MemoryRegionOps v7m_sysreg_ns_ops =3D { + .read_with_attrs =3D v7m_sysreg_ns_read, + .write_with_attrs =3D v7m_sysreg_ns_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + ARMv7MState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attrs); +} + +static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + ARMv7MState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, + attrs); +} + +static const MemoryRegionOps v7m_systick_ops =3D { + .read_with_attrs =3D v7m_systick_read, + .write_with_attrs =3D v7m_systick_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static void armv7m_instance_init(Object *obj) { ARMv7MState *s =3D ARMV7M(obj); @@ -137,6 +216,13 @@ static void armv7m_instance_init(Object *obj) object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq"); =20 + object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS], + TYPE_SYSTICK); + /* + * We can't initialize the secure systick here, as we don't know + * yet if we need it. + */ + for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { object_initialize_child(obj, "bitband[*]", &s->bitband[i], TYPE_BITBAND); @@ -231,6 +317,45 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 + /* Create and map the systick devices */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, + qdev_get_gpio_in_named(DEVICE(&s->nvic), + "systick-trigger", M_REG_NS)= ); + + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + /* + * We couldn't init the secure systick device in instance_init + * as we didn't know then if the CPU had the security extensions; + * so we have to do it here. + */ + object_initialize_child(OBJECT(dev), "systick-reg-s", + &s->systick[M_REG_S], TYPE_SYSTICK); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, + qdev_get_gpio_in_named(DEVICE(&s->nvic), + "systick-trigger", M_REG= _S)); + } + + memory_region_init_io(&s->systickmem, OBJECT(s), + &v7m_systick_ops, s, + "v7m_systick", 0xe0); + + memory_region_add_subregion_overlap(&s->container, 0xe000e010, + &s->systickmem, 1); + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + memory_region_init_io(&s->systick_ns_mem, OBJECT(s), + &v7m_sysreg_ns_ops, &s->systickmem, + "v7m_systick_ns", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0xe002e010, + &s->systick_ns_mem, 1); + } + /* If the CPU has RAS support, create the RAS register block */ if (cpu_isar_feature(aa32_ras, s->cpu)) { object_initialize_child(OBJECT(dev), "armv7m-ras", diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a5975592dfa..2b3e79a3da9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2517,38 +2517,6 @@ static const MemoryRegionOps nvic_sysreg_ns_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - NVICState *s =3D opaque; - MemoryRegion *mr; - - /* Direct the access to the correct systick */ - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attrs); -} - -static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - NVICState *s =3D opaque; - MemoryRegion *mr; - - /* Direct the access to the correct systick */ - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, - attrs); -} - -static const MemoryRegionOps nvic_systick_ops =3D { - .read_with_attrs =3D nvic_systick_read, - .write_with_attrs =3D nvic_systick_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2801,29 +2769,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) =20 s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; =20 - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, - qdev_get_gpio_in_named(dev, "systick-trigger", - M_REG_NS)); - - if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { - /* We couldn't init the secure systick device in instance_init - * as we didn't know then if the CPU had the security extensions; - * so we have to do it here. - */ - object_initialize_child(OBJECT(dev), "systick-reg-s", - &s->systick[M_REG_S], TYPE_SYSTICK); - - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, - qdev_get_gpio_in_named(dev, "systick-trigger", - M_REG_S)); - } - /* * This device provides a single sysbus memory region which * represents the whole of the "System PPB" space. This is the @@ -2877,23 +2822,11 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) "nvic_sysregs", 0x1000); memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); =20 - memory_region_init_io(&s->systickmem, OBJECT(s), - &nvic_systick_ops, s, - "nvic_systick", 0xe0); - - memory_region_add_subregion_overlap(&s->container, 0xe010, - &s->systickmem, 1); - if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); - memory_region_init_io(&s->systick_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, &s->systickmem, - "nvic_systick_ns", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x2e010, - &s->systick_ns_mem, 1); } =20 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); @@ -2905,12 +2838,6 @@ static void armv7m_nvic_instance_init(Object *obj) NVICState *nvic =3D NVIC(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS= ], - TYPE_SYSTICK); - /* We can't initialize the secure systick here, as we don't know - * yet if we need it. - */ - sysbus_init_irq(sbd, &nvic->excpout); qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16287609840008.182917405058902; Thu, 12 Aug 2021 02:36:24 -0700 (PDT) Received: from localhost ([::1]:49466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE78Q-0002VM-RO for importer@patchew.org; Thu, 12 Aug 2021 05:36:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76J-0005B8-JI for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:11 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:37625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76C-0007mT-75 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:10 -0400 Received: by mail-wm1-x32a.google.com with SMTP id l34-20020a05600c1d22b02902573c214807so6604299wms.2 for ; Thu, 12 Aug 2021 02:34:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vkRWNgQd3iVKvNvr6CG4AHm0mAPsQ03jgBqfcHJfmVo=; b=cG/0QJXNAN4FoHZORotyCcqwKVWz2NhSH+veKb2Te8zDQYoFzDNwNaIWMR5MuhCRZs hK7XtvjIzbNEz2eFFXJFkfGUnZAvD7c1dMHUzbuxWnCjLMaMeyMju9tJJHBMiwdQlsDF 12O8Hvro42L3rXw8Fpbf3RS3/W08nnQk2j52UOdncYEirWLx/IFh2ODwEUiVqONoP2ZW yVnoDbN/Ujwf/hOvLiS4mV9tw2/8mjB2SQFnNLRdhS3b/J7QM2ofFdzIlC453S9ySRcm mq0sUDNuZnB7J192HTsBFhiBGmsOcSvPRh8y6QzGGQKC3ZX7/tkP8vGVrWjUyuyNKlp5 4IBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vkRWNgQd3iVKvNvr6CG4AHm0mAPsQ03jgBqfcHJfmVo=; b=hpaQ33XY2OmeyMTfqcbQK0YxE7tMyyySeWeTjJTo5BPDgO3PsR8DY45DzFvEcFKcXD P/NZtgjOfYDjrnx8BHjEWuVmHE/RtIkYBJMVVReL0tN7PorjYJvl3nL7sP7sA49tURKy 9yvtDPVXMh1gyiuGybp9N12nVkDWa5BItpadpR9eNAwdy35gx7qOYDM31IgPnOusBIS2 7tQxlhiicjP9JGKx40oZ5rtVhv09ODZuH6JCfgJFGN7g2gmhZZ6x9Y5Xee1rAGbQ3G0n NAYu7IyWYTsxUK6jRdGLOHB5X0i1bHl+0EQ7LAdnoKUHKFDo5eKjFci95/18z/+IS1fT Yhng== X-Gm-Message-State: AOAM5322+sgh0LSopZBhW0SXB8CPkegd1qRAStN7pukAQXHKSa/gLTLH YjHzVI/4/jGef/TRFqoYl6FjsQ== X-Google-Smtp-Source: ABdhPJwACfzen5ziJRaYSvB9GNRABMCbQqTA3O1C4QID3SBNVXDbjC+RM0N9eSjvXHBPdWfGsQEWBg== X-Received: by 2002:a05:600c:19cd:: with SMTP id u13mr10376882wmq.143.1628760842236; Thu, 12 Aug 2021 02:34:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Date: Thu, 12 Aug 2021 10:33:34 +0100 Message-Id: <20210812093356.1946-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628760985028100001 Content-Type: text/plain; charset="utf-8" Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Luc Michel --- include/hw/arm/armv7m.h | 4 + include/hw/intc/armv7m_nvic.h | 3 - hw/arm/armv7m.c | 100 ++++++++++++++++++++++- hw/intc/armv7m_nvic.c | 145 +--------------------------------- 4 files changed, 107 insertions(+), 145 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 360c35c5fb2..fe8b248a6c6 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -77,6 +77,10 @@ struct ARMv7MState { * NS systick device if appropriate. */ MemoryRegion systick_ns_mem; + /* Ditto, for the sysregs region provided by the NVIC */ + MemoryRegion sysreg_ns_mem; + /* MR providing default PPB behaviour */ + MemoryRegion defaultmem; =20 /* Properties */ char *cpu_type; diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 6a6a99090c7..0180c7b0ca1 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -80,9 +80,6 @@ struct NVICState { int vectpending_prio; /* group prio of the exeception in vectpending */ =20 MemoryRegion sysregmem; - MemoryRegion sysreg_ns_mem; - MemoryRegion container; - MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 364ac069702..7e7fb7a3ad3 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -18,6 +18,7 @@ #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "qemu/log.h" #include "target/arm/idau.h" =20 /* Bitbanded IO. Each word corresponds to a single bit. */ @@ -203,6 +204,43 @@ static const MemoryRegionOps v7m_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +/* + * Unassigned portions of the PPB space are RAZ/WI for privileged + * accesses, and fault for non-privileged accesses. + */ +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; +} + +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ppb_default_ops =3D { + .read_with_attrs =3D ppb_default_read, + .write_with_attrs =3D ppb_default_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, +}; + static void armv7m_instance_init(Object *obj) { ARMv7MState *s =3D ARMV7M(obj); @@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **= errp) qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); =20 + /* + * We map various devices into the continer MR at their architected + * addresses. In particular, we map everything corresponding to the + * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff + * and includes the NVIC, the System Control Space (system registers), + * the systick timer, and for CPUs with the Security extension an NS + * banked version of all of these. + * + * The default behaviour for unimplemented registers/ranges + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) + * is to RAZ/WI for privileged access and BusFault for non-privileged + * access. + * + * The NVIC and System Control Space (SCS) starts at 0xe000e000 + * and looks like this: + * 0x004 - ICTR + * 0x010 - 0xff - systick + * 0x100..0x7ec - NVIC + * 0x7f0..0xcff - Reserved + * 0xd00..0xd3c - SCS registers + * 0xd40..0xeff - Reserved or Not implemented + * 0xf00 - STIR + * + * Some registers within this space are banked between security states. + * In v8M there is a second range 0xe002e000..0xe002efff which is the + * NonSecure alias SCS; secure accesses to this behave like NS accesses + * to the main SCS range, and non-secure accesses (including when + * the security extension is not implemented) are RAZ/WI. + * Note that both the main SCS range and the alias range are defined + * to be exempt from memory attribution (R_BLJT) and so the memory + * transaction attribute always matches the current CPU security + * state (attrs.secure =3D=3D env->v7m.secure). In the v7m_sysreg_ns_o= ps + * wrappers we change attrs.secure to indicate the NS access; so + * generally code determining which banked register to use should + * use attrs.secure; code determining actual behaviour of the system + * should use env->v7m.secure. + * + * Within the PPB space, some MRs overlap, and the priority + * of overlapping regions is: + * - default region (for RAZ/WI and BusFault) : -1 + * - system register regions (provided by the NVIC) : 0 + * - systick : 1 + * This is because the systick device is a small block of registers + * in the middle of the other system control registers. + */ + + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, + "nvic-default", 0x100000); + memory_region_add_subregion_overlap(&s->container, 0xe0000000, + &s->defaultmem, -1); + /* Wire the NVIC up to the CPU */ sbd =3D SYS_BUS_DEVICE(&s->nvic); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); =20 - memory_region_add_subregion(&s->container, 0xe0000000, + memory_region_add_subregion(&s->container, 0xe000e000, sysbus_mmio_get_region(sbd, 0)); + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + /* Create the NS alias region for the NVIC sysregs */ + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), + &v7m_sysreg_ns_ops, + sysbus_mmio_get_region(sbd, 0), + "nvic_sysregs_ns", 0x1000); + memory_region_add_subregion(&s->container, 0xe002e000, + &s->sysreg_ns_mem); + } =20 /* Create and map the systick devices */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b3e79a3da9..13df002ce4d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2470,90 +2470,6 @@ static const MemoryRegionOps nvic_sysreg_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - MemoryRegion *mr =3D opaque; - - if (attrs.secure) { - /* S accesses to the alias act like NS accesses to the real region= */ - attrs.secure =3D 0; - return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attr= s); - } else { - /* NS attrs are RAZ/WI for privileged, and BusFault for user */ - if (attrs.user) { - return MEMTX_ERROR; - } - return MEMTX_OK; - } -} - -static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - MemoryRegion *mr =3D opaque; - - if (attrs.secure) { - /* S accesses to the alias act like NS accesses to the real region= */ - attrs.secure =3D 0; - return memory_region_dispatch_read(mr, addr, data, - size_memop(size) | MO_TE, attrs= ); - } else { - /* NS attrs are RAZ/WI for privileged, and BusFault for user */ - if (attrs.user) { - return MEMTX_ERROR; - } - *data =3D 0; - return MEMTX_OK; - } -} - -static const MemoryRegionOps nvic_sysreg_ns_ops =3D { - .read_with_attrs =3D nvic_sysreg_ns_read, - .write_with_attrs =3D nvic_sysreg_ns_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -/* - * Unassigned portions of the PPB space are RAZ/WI for privileged - * accesses, and fault for non-privileged accesses. - */ -static MemTxResult ppb_default_read(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", - (uint32_t)addr); - if (attrs.user) { - return MEMTX_ERROR; - } - *data =3D 0; - return MEMTX_OK; -} - -static MemTxResult ppb_default_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) -{ - qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", - (uint32_t)addr); - if (attrs.user) { - return MEMTX_ERROR; - } - return MEMTX_OK; -} - -static const MemoryRegionOps ppb_default_ops =3D { - .read_with_attrs =3D ppb_default_read, - .write_with_attrs =3D ppb_default_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 8, -}; - static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -2770,66 +2686,13 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; =20 /* - * This device provides a single sysbus memory region which - * represents the whole of the "System PPB" space. This is the - * range from 0xe0000000 to 0xe00fffff and includes the NVIC, - * the System Control Space (system registers), the systick timer, - * and for CPUs with the Security extension an NS banked version - * of all of these. - * - * The default behaviour for unimplemented registers/ranges - * (for instance the Data Watchpoint and Trace unit at 0xe0001000) - * is to RAZ/WI for privileged access and BusFault for non-privileged - * access. - * - * The NVIC and System Control Space (SCS) starts at 0xe000e000 - * and looks like this: - * 0x004 - ICTR - * 0x010 - 0xff - systick - * 0x100..0x7ec - NVIC - * 0x7f0..0xcff - Reserved - * 0xd00..0xd3c - SCS registers - * 0xd40..0xeff - Reserved or Not implemented - * 0xf00 - STIR - * - * Some registers within this space are banked between security states. - * In v8M there is a second range 0xe002e000..0xe002efff which is the - * NonSecure alias SCS; secure accesses to this behave like NS accesses - * to the main SCS range, and non-secure accesses (including when - * the security extension is not implemented) are RAZ/WI. - * Note that both the main SCS range and the alias range are defined - * to be exempt from memory attribution (R_BLJT) and so the memory - * transaction attribute always matches the current CPU security - * state (attrs.secure =3D=3D env->v7m.secure). In the nvic_sysreg_ns_= ops - * wrappers we change attrs.secure to indicate the NS access; so - * generally code determining which banked register to use should - * use attrs.secure; code determining actual behaviour of the system - * should use env->v7m.secure. - * - * The container covers the whole PPB space. Within it the priority - * of overlapping regions is: - * - default region (for RAZ/WI and BusFault) : -1 - * - system register regions : 0 - * - systick : 1 - * This is because the systick device is a small block of registers - * in the middle of the other system control registers. + * This device provides a single memory region which covers the + * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the + * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF. */ - memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); - memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, - "nvic-default", 0x100000); - memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, = -1); memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); - memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); - - if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { - memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, &s->sysregmem, - "nvic_sysregs_ns", 0x1000); - memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); - } - - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem); } =20 static void armv7m_nvic_instance_init(Object *obj) --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628760928994659.4895901503353; Thu, 12 Aug 2021 02:35:28 -0700 (PDT) Received: from localhost ([::1]:46056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE77X-0000FK-UO for importer@patchew.org; Thu, 12 Aug 2021 05:35:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76H-00058q-UH for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:10 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:42561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76C-0007mg-D8 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:09 -0400 Received: by mail-wm1-x331.google.com with SMTP id w21-20020a7bc1150000b02902e69ba66ce6so4056199wmi.1 for ; Thu, 12 Aug 2021 02:34:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2pVr2aNOpSFLo/LYsO8eopoOEXQ86IrfFfAepPzciZQ=; b=F+WeSFxQpgKYzJxh3GXn8PpN8/kYg/REjMz1ksOK58AdeZIM8ntASqYUJOj17uKck0 QYgZNM2Av/qEcgLsQ/WIucKp9DkqyiZWaM6QH1vncsbtWJSGFE5eCl9sYw7S2GuYDhxN PamW4klwlbSqumRVqQgbipTSIzOmMXWDhb0yihNd6m9AsFRQ717hsQGFnfyCUIHXyBH4 sBx01wIi7WiDzr2y3eXHtqIKtkHd4i/dl+yY3/egX2/Ly5Z4svslJoEbNgKj3oAtcjFZ 5pytDkCOp1jdz+gguLNdiM+Yv6ZzwvdDm/jKJpqQ7zU0ltg+YlnDZMBUqSw6uuhWkCN5 T2Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2pVr2aNOpSFLo/LYsO8eopoOEXQ86IrfFfAepPzciZQ=; b=fBkcaHrepULx1KcJ0g3DpV1PP2OM35/oyx3b02bygLtYeb9q9KnCxjUdbK9Lf0mxdG CU6ToOcQnlNmv8gkk3KJid+PZcFs+DkTSZ/mhviCE31zcFtFUcrL5X68n8OKJiscqd+B DdJjJAK/lFqQ6KbUT8p37g/hpB2uvRaLV+0ul4LYN257YV3PkSLqyRQjFm1bCuMo3FLc WXy18yt09GNiW2m3YHkiiXCuEs4ZOuhui+x7sgr6vatmne+Z6PcY2WOMBx9nUyeV9mWG NGolmFp3foaw0uSwSjn5pRc2DrBS6xKM5kBXGFEgNeO972F2AFxTkAmye9UmsdPPvLUA CkZQ== X-Gm-Message-State: AOAM5321qQIYIEYLkQFYD5+l9HDi3DMv+2o4sTrTinKLZdTzWS/S1VDS 5zp1z3wD9mDVwDnQJc9rh5KwVg== X-Google-Smtp-Source: ABdhPJxt3WvidPMJB2hhb3GkWoGI/PDapByZ6yv0Cf8IiaU3MuT7J0GnHmUfYY4JmfHPLMwHK+qLeg== X-Received: by 2002:a7b:c3d6:: with SMTP id t22mr12317494wmj.117.1628760843141; Thu, 12 Aug 2021 02:34:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Date: Thu, 12 Aug 2021 10:33:35 +0100 Message-Id: <20210812093356.1946-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628760930376100003 Content-Type: text/plain; charset="utf-8" Add the usual-style QEMU interface comment documenting what properties, etc, this device exposes. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/timer/armv7m_systick.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 84496faaf96..685fc5bc0d7 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -20,6 +20,13 @@ =20 OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK) =20 +/* + * QEMU interface: + * + sysbus MMIO region 0 is the register interface (covering + * the registers which are mapped at address 0xE000E010) + * + sysbus IRQ 0 is the interrupt line to the NVIC + */ + struct SysTickState { /*< private >*/ SysBusDevice parent_obj; --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761067772733.3875848211165; Thu, 12 Aug 2021 02:37:47 -0700 (PDT) Received: from localhost ([::1]:55780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE79m-0006iT-Id for importer@patchew.org; Thu, 12 Aug 2021 05:37:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76K-0005DZ-8j for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:12 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:33476) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76D-0007nj-B7 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:11 -0400 Received: by mail-wr1-x42f.google.com with SMTP id r7so7425433wrs.0 for ; Thu, 12 Aug 2021 02:34:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HH+JYD3ePJ2M8XF+0f5Esmo3hxwe5zPdaITYbd/Hd/Y=; b=Z7JlLoN4vr0J9S8R+x9+SQ5T342bZj9pHK9VEf6Wfdl+T7tCdMA7apQRW4D72jeRFO KWX7YkCaJs4fsT5uU+n+AUwVAmR6OLtgNev8BOSHhjTSiGy0zramgR1lDOeeVOMPC0Ar 8BCFNLHG8B2meSAmZdYZyZowL5wCy38lnNR8+jKRm/slAjHoGNHeA+0U0pkTHyetm9jw /mhCe5OwT0y4dyeqgfZPcvc6+cFt+ZH4B/KWv4y7P9rfI6KECRwNZNgIMhQprMERCy7a v9sgNzjihsEE7g/E7gBvVOAHMIVy9fu23XaTKeHJJoCtQ0JQ8jmjQNHEMNdijlROEAPQ bXQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HH+JYD3ePJ2M8XF+0f5Esmo3hxwe5zPdaITYbd/Hd/Y=; b=ClpbE5DXQr/PMv7hhVIVbHeSFHGb6OKjxwpcA4JxgPGMNUCtbLBkn/LcwtJgP5caaJ HPs3n1TMWZ5jxnp6Csws3brPpofmnSjrFdE6kAcljNM+ItA3zFS3aRsBoWMf/rf2qyYG FxbELm/8NynflYWanc6ZuQ4K9wjoUL578t8JvcnQte2eFUrSuyB/Cn8HNgaNUEXbqzVx 1sQ9kn5MMZrLRvDntkloIWnU6kCvB9dCFm3X9wmO9wnUvFqyU5d9IJfZPosm8piP4RFH aXleRYURS0EraUZFOntoeQpk5goP3u5o3BAFpsDH/QtZ6XkaonUepuFuJVu7PjG9MtSE 9zng== X-Gm-Message-State: AOAM530nJIRnLBAgQGIjzik5oVF9PEkzVoL1hFaEmssEyeR8ND8h9R1F 5bkduWVkM5UI9KOkLSXTo4AYlA== X-Google-Smtp-Source: ABdhPJzaUyZZCFOzlQxt7StdEWDDvs/gsnM02q4kYCdyKX7dkr0dE7NgJqQ/64oLG97ss97+odS5xw== X-Received: by 2002:a05:6000:120f:: with SMTP id e15mr2877179wrx.399.1628760844033; Thu, 12 Aug 2021 02:34:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Date: Thu, 12 Aug 2021 10:33:36 +0100 Message-Id: <20210812093356.1946-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761068103100002 Content-Type: text/plain; charset="utf-8" The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE =3D=3D 0) * the main CPU clock (when SYST_CSR.CLKSOURCE =3D=3D 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/timer/armv7m_systick.h | 7 +++++++ hw/timer/armv7m_systick.c | 10 ++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 685fc5bc0d7..38adf8d274e 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "qom/object.h" #include "hw/ptimer.h" +#include "hw/clock.h" =20 #define TYPE_SYSTICK "armv7m_systick" =20 @@ -25,6 +26,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK) * + sysbus MMIO region 0 is the register interface (covering * the registers which are mapped at address 0xE000E010) * + sysbus IRQ 0 is the interrupt line to the NVIC + * + Clock input "refclk" is the external reference clock + * (used when SYST_CSR.CLKSOURCE =3D=3D 0) + * + Clock input "cpuclk" is the main CPU clock + * (used when SYST_CSR.CLKSOURCE =3D=3D 1) */ =20 struct SysTickState { @@ -38,6 +43,8 @@ struct SysTickState { ptimer_state *ptimer; MemoryRegion iomem; qemu_irq irq; + Clock *refclk; + Clock *cpuclk; }; =20 /* diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index 2f192011eb0..e43f74114e8 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" @@ -201,6 +202,9 @@ static void systick_instance_init(Object *obj) memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0= ); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); } =20 static void systick_realize(DeviceState *dev, Error **errp) @@ -215,9 +219,11 @@ static void systick_realize(DeviceState *dev, Error **= errp) =20 static const VMStateDescription vmstate_systick =3D { .name =3D "armv7m_systick", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(refclk, SysTickState), + VMSTATE_CLOCK(cpuclk, SysTickState), VMSTATE_UINT32(control, SysTickState), VMSTATE_INT64(tick, SysTickState), VMSTATE_PTIMER(ptimer, SysTickState), --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761155161760.8199960840396; Thu, 12 Aug 2021 02:39:15 -0700 (PDT) Received: from localhost ([::1]:36190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7BC-0003y6-5c for importer@patchew.org; Thu, 12 Aug 2021 05:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76J-0005BJ-Iw for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:11 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:46767) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76E-0007os-85 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:11 -0400 Received: by mail-wm1-x32c.google.com with SMTP id h24-20020a1ccc180000b029022e0571d1a0so4043923wmb.5 for ; Thu, 12 Aug 2021 02:34:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ylx+ciRLSX1VOp2PZHd/2EZv1BHv9jNlhqLtZX6B8Y0=; b=MGkLFDtNFqsalT3ezMKfPwRD55To5J7yqy0f9sNNcZYGd3EgXGShnvNdcVXCvOGq+c KP+yaU0gn8Sz4WYNhBH9ROfTW9rlGPqPt870pdFSRP9v8N6NaWLANyweKwfhQpN1qul0 DNvx9n1WK8+F4OCZUBjLk45DdPOytRnpmyb8ZuG+U0V1foh86TSM5UTPvbSy8Mdy2+NR YY/Z09gdeOlLXZrjHJWdEXtIHmnLLFRm6GiSAmzvON2Yrpp1P7RN5UezYBbmOgqWTJyk hFKglV7MXEUwzqzgVn8v0OQYJBrbqgDwRFg9PF0pxvEeM9lLOi1sKYYtOWcMA0h9yk6X x9XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ylx+ciRLSX1VOp2PZHd/2EZv1BHv9jNlhqLtZX6B8Y0=; b=sTKOfyx3Y2RIZQEfdmZtgRds6ccqIp0mCGVstjewwxP1ee7IBfru/CzuL5wx1t++o0 gfewv8+e0uQ5XtN8l+mkENH3SxJRf/3K1k8bcRu/j/e5HJcTJbIVsKuHDus+iKIlbmks JNmvS1m0e+YSOQEHCO/vxho0Byh5iRvOi8ZR2VRmATnAm5QOB/A9LC2F644hsl/ouGxq PXaGJDB/tSf5ZuTh73FunAU8npGUzKuoZ9mvwZwo5eqPq4/rsL6JGrh0LeOl4rJuGqtT alcMVcSgGCM1khfTUMQVI9bUSmm2JpGWHhFERfIdU8geEn1egrSFr4hpyzY1n5DEB/3p yMvA== X-Gm-Message-State: AOAM533UtZ9Lb+MemrvxksMKrqMc9pHMaTfE2aQ/BkdwVy+QxNxNavoJ 7wz6wEXKx5NGjxRv87FYWxU7Bw== X-Google-Smtp-Source: ABdhPJzgLUqI3i06ZMr43ipk+QVjSX/6ndn/hes1KsJjGVFeljwL5vv9fr5Gmo3glKu9Zz0vHw1diQ== X-Received: by 2002:a7b:c083:: with SMTP id r3mr3023821wmh.65.1628760844921; Thu, 12 Aug 2021 02:34:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks Date: Thu, 12 Aug 2021 10:33:37 +0100 Message-Id: <20210812093356.1946-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761155687100003 Content-Type: text/plain; charset="utf-8" Create input clocks on the armv7m container object which pass through to the systick timers, so that users of the armv7m object can specify the clocks being used. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/armv7m.h | 6 ++++++ hw/arm/armv7m.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index fe8b248a6c6..b7ba0ff409c 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -15,6 +15,7 @@ #include "hw/misc/armv7m_ras.h" #include "target/arm/idau.h" #include "qom/object.h" +#include "hw/clock.h" =20 #define TYPE_BITBAND "ARM-bitband-memory" OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND) @@ -51,6 +52,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO + * + Clock input "refclk" is the external reference clock for the systick = timers + * + Clock input "cpuclk" is the main CPU clock */ struct ARMv7MState { /*< private >*/ @@ -82,6 +85,9 @@ struct ARMv7MState { /* MR providing default PPB behaviour */ MemoryRegion defaultmem; =20 + Clock *refclk; + Clock *cpuclk; + /* Properties */ char *cpu_type; /* MemoryRegion the board provides to us (with its devices, RAM, etc) = */ diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 7e7fb7a3ad3..db1bfa98df0 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -14,12 +14,14 @@ #include "hw/arm/boot.h" #include "hw/loader.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "elf.h" #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/log.h" #include "target/arm/idau.h" +#include "migration/vmstate.h" =20 /* Bitbanded IO. Each word corresponds to a single bit. */ =20 @@ -265,6 +267,9 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "bitband[*]", &s->bitband[i], TYPE_BITBAND); } + + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); } =20 static void armv7m_realize(DeviceState *dev, Error **errp) @@ -416,6 +421,8 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) } =20 /* Create and map the systick devices */ + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refc= lk); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuc= lk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { return; } @@ -431,6 +438,10 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) */ object_initialize_child(OBJECT(dev), "systick-reg-s", &s->systick[M_REG_S], TYPE_SYSTICK); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", + s->refclk); + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk", + s->cpuclk); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) { return; @@ -504,11 +515,23 @@ static Property armv7m_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static const VMStateDescription vmstate_armv7m =3D { + .name =3D "armv7m", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(refclk, SysTickState), + VMSTATE_CLOCK(cpuclk, SysTickState), + VMSTATE_END_OF_LIST() + } +}; + static void armv7m_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D armv7m_realize; + dc->vmsd =3D &vmstate_armv7m; device_class_set_props(dc, armv7m_properties); } =20 --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761405860685.3536290878733; Thu, 12 Aug 2021 02:43:25 -0700 (PDT) Received: from localhost ([::1]:54826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7FE-0007uM-Ny for importer@patchew.org; Thu, 12 Aug 2021 05:43:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76L-0005Gb-A3 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:13 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:45964) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76F-0007pT-D2 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:12 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 203-20020a1c00d40000b02902e6a4e244e4so4045558wma.4 for ; Thu, 12 Aug 2021 02:34:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gy7QIjwsa6xMVXE5/WQWgxzP9shOsuOqrCvuoAh1kM0=; b=yjEztFIiLyTiFaUGHat3wweOHC+q7B1SVZktRxyNoKabbUmXzq9zgwbvQHWkRlskJR PH0GtkH6Js8m1bZRrw+PUP5heepK13l56bubLm8B8GNQSIKdnblBTW3yBugpEiH0qMmK aqUWHQX6fBC0xSWJn/4i9hkbNtzErj0qBLTrDoW44DpCiEQVEkN7LLd3QHgvirYs4ufx cS8557TZEjDNjxUb1ZUW0maKaeUMrHTzYIHJNDoW4oazsoF2rGbHFUvOgJPQfZO5JMF1 MA3hkthZJTZGv7a9+z43gWFUmnfTledZGrMOjx0/LPvx7YnBxNh53ZBGVskn0egqKfgY ywdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gy7QIjwsa6xMVXE5/WQWgxzP9shOsuOqrCvuoAh1kM0=; b=Q9dcF+J2T3k2FMDrr9x4fYizxN43IzggTK3i6F+D3P+q/4SZ7w+C9Y/HjSzeHoHQ5d mk3xZ/UWDBQwkZpv9IdB5q8xgdn0e30AAfn1V8U0zEKO3qSsgy6b6/49ShYSzC5SJ0jD EdGTwbQYSvziyH7WOuccBl1HlLb/w3XNIXpSAAcYU2LelWJIZPOM+KKCUExV3ahADHQw mQtUtaqOAQiyBuqiYaguFX6X/4QfK00jGaAbyQMQMLsMDwnxRbq30FlpXq/uq+GvMaKN lrJAfhm9yyHsaJplWxXMGcJj1aRRWHzwmfG9XLbZop+KCpJTxNsjOkjMli7lJkKoRlCl pHMw== X-Gm-Message-State: AOAM530MLoqzUZRyTUc9tosoG/R/LzUTHnIS/2zdRM1IU31l8MuDb+ha NRbV7f0aXHz8ELAA5rSHp6O1gw== X-Google-Smtp-Source: ABdhPJyOmXWFvfimkUSaqvHXtbMt4h2g9MAtAh2S8uua2F7zFr//AXorfDG4+o9BUr+dn1N8+A80eQ== X-Received: by 2002:a1c:f206:: with SMTP id s6mr14389545wmc.15.1628760845800; Thu, 12 Aug 2021 02:34:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Date: Thu, 12 Aug 2021 10:33:38 +0100 Message-Id: <20210812093356.1946-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761406308100001 Content-Type: text/plain; charset="utf-8" Wire up the cpuclk for the systick devices to the SSE object's existing mainclk clock. We do not wire up the refclk because the SSE subsystems do not provide a refclk. (This is documented in the IoTKit and SSE-200 TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the same approach.) When we update the systick device later to honour "no refclk connected" this will fix a minor emulation inaccuracy for the SSE-based boards. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Luc Michel --- hw/arm/armsse.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index a1456cb0f42..70b52c3d4b9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) int j; char *gpioname; =20 + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk); + /* The SSE subsystems do not wire up a systick refclk */ + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IR= QS); /* * In real hardware the initial Secure VTOR is set from the INITSV= TOR* --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761279841912.9484783076239; Thu, 12 Aug 2021 02:41:19 -0700 (PDT) Received: from localhost ([::1]:46020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7DC-00028i-KG for importer@patchew.org; Thu, 12 Aug 2021 05:41:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76K-0005FD-Ss for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:12 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:40740) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76G-0007ph-7A for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:12 -0400 Received: by mail-wm1-x32c.google.com with SMTP id f12-20020a05600c4e8c00b002e6bdd6ffe2so799790wmq.5 for ; Thu, 12 Aug 2021 02:34:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eLtRSxQp9aI5LH5KqNaJoE/wJcjISdPkDQo/OmFkPck=; b=jI744wL1TpAKshvebWyfa5xIKsxb8m3hnKx8eqvE8b0XD+xEzYhadWHloHSkAZ1BLr TFXYVFCy3FN6clRnCrJ8uKNm3EJZE7hsPNTacs55Ag8gQqN+CXmslOUs6nacu9ePWRl8 tpI+o5unD0sVHCyNO13VDSC+nHHwc7+RvVDzMS1sRNSbqVSgv2VAfzYs8JmfIQDtNlFV dVys1bwN70MI5ctMGKDum9YgbXYC/l6+XaX7Kkf49TqEmcP7T1VC36zm9RdPoGLu74OP sCtE2ntUboyemN3PHtcEBvOznee+WeGbsHFliZRYFU5CBlnoj3SIWx7Ejb3gM90JZkrY fXCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLtRSxQp9aI5LH5KqNaJoE/wJcjISdPkDQo/OmFkPck=; b=MvEuuNjh9cbvHkRb+Qas0yUKIdVQVKOIH8wViIsXTIwJuxW2ZNK3BriCYNW9H0BTIq 8B+s7/4HChgwBuMLJ1aWF1mZUP/+jRs0EMpIziPRTZNHPSFZBkVhRnxXQ0HyR/yB7mPQ Sue3Xah5mNxUr8R4ikvR6szit/HyIe4Vqw6jAXubb2WUAkJTJq3imtPrVE0ffkgpr2Ln qT4fcpX7q5BBiPEKnaAZPAnP0Qyw70vt+Cr2m01uaR94uqFPEmkHIm4DCcGhgLHdix/N d7qNdhZM+jZ2dH0yh2x3MrOgTAYfQB6ymq0e41a7wnxafeOydMQXxhXJI/YDXvmMtBd8 baCA== X-Gm-Message-State: AOAM530EIrTRnxvDsCKFuAH8oEVwWNlyC31af2UIQ/WXpVnedFACeH+n Kcy2+9DwZxumccRQ0TJ/Gr/X/Q== X-Google-Smtp-Source: ABdhPJzC5rHmFrcMWttRQdGnhLdxmiCm/iTcX2cq90mMKBFEgAP+nIFL880sqhjPGxZIXGNj8Gg6XQ== X-Received: by 2002:a1c:a905:: with SMTP id s5mr13589971wme.16.1628760846668; Thu, 12 Aug 2021 02:34:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks Date: Thu, 12 Aug 2021 10:33:39 +0100 Message-Id: <20210812093356.1946-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761281639100001 Content-Type: text/plain; charset="utf-8" Connect up the armv7m clocks on the mps2-an385/386/500/511. Connect up the armv7m object's clocks on the MPS boards defined in mps2.c. The documentation for these FPGA images doesn't specify what systick reference clock is used (if any), so for the moment we provide a 1MHz refclock, which will result in no behavioural change from the current hardwired 1MHz clock implemented in armv7m_systick.c:systick_scale(). Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/mps2.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 81413b7133e..3671f49ad7b 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -86,6 +86,7 @@ struct MPS2MachineState { CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; Clock *sysclk; + Clock *refclk; }; =20 #define TYPE_MPS2_MACHINE "mps2" @@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass,= MPS2_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 25000000 =20 +/* + * The Application Notes don't say anything about how the + * systick reference clock is configured. (Quite possibly + * they don't have one at all.) This 1MHz clock matches the + * pre-existing behaviour that used to be hardcoded in the + * armv7m_systick implementation. + */ +#define REFCLK_FRQ (1 * 1000 * 1000) + /* Initialize the auxiliary RAM region @mr and map it into * the memory map at @base. */ @@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine) mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); =20 + mms->refclk =3D clock_new(OBJECT(machine), "REFCLK"); + clock_set_hz(mms->refclk, REFCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine) default: g_assert_not_reached(); } + qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); + qdev_connect_clock_in(armv7m, "refclk", mms->refclk); qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&mms->armv7m), "memory", --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761153928531.9012225853601; Thu, 12 Aug 2021 02:39:13 -0700 (PDT) Received: from localhost ([::1]:36120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7BA-0003vR-Rr for importer@patchew.org; Thu, 12 Aug 2021 05:39:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76M-0005JV-0I for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:14 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:45700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76H-0007qk-6X for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:13 -0400 Received: by mail-wr1-x42f.google.com with SMTP id v4so234606wro.12 for ; Thu, 12 Aug 2021 02:34:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UVgw7AO0m4VkhMh5uz4efVOx0eI266AWuBpF1oyx+bo=; b=IFTVvxOU0rNfXGT9+5kkc10y+Qs3B7irl5seuip3uspEfYfOu/xDHZ+4Nnue1CJF3G /3w24TfFtQ7dCiYRgHi+0/gM5cH0XC/gfVnMS67ytCFTIwO9Bq/9w+6IhK8v0txjsnOA ZTyltqQwRTavjpKQo3xLtmt4oN/WpznMc8VnpMTILHHCr8K11/BxQ3GVaUsFCiEoGy1P qLGDgZv6l1fK7XcQwLIEM/tNmtO8DHYRVqzxR0Bi9yGZHDooKiIYu5Vp3OuYXhkszcGy TSYJfhz2zPzoNuIndJ/kn9SmM5Cz99jhlQdqaFeWFeq7hmdqKOc3MhpIeb7tyE5QctEe ghdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UVgw7AO0m4VkhMh5uz4efVOx0eI266AWuBpF1oyx+bo=; b=LkchDxgwS0IglOqhzGdraWO6zzFgrPi5F+8/bQ279MwnP7YS7mJ/hWCd+rDVMBT8me Id7G+dCjrJcD+XpGnz2mJV70izH+nx49V0yVMMzgt7sTKmjSWbST31l38CfbxQPAPk0v av0O4zgFAPfoDQ3sXDsDk5j6xvhdyXk5VTVEyDZZsmA/y/mHA6bhlTtYFSCaKOTuUrKi 3tFDDbwQShAehFueRJBkgr7EN4sXSL1EoxMHpq+lcdpwu06pfQZsBJ42gicqU/93pyia Wg9un0GkwYWhswyohFTQq34dfHeV5R+LY/w7h0vfEKu+XPra5r4b9eSTaDRL9vsSPVHb CEXQ== X-Gm-Message-State: AOAM53009xm07drcBhM4I20oua7XB8Hf1au68d98pLDgWy4fgJFlFpHv kblGdzvp1vYA+iGRrzLVilQmWQ== X-Google-Smtp-Source: ABdhPJz/0g2ydb+gPEnzcpKw/n/3uGE8HTeyQmx7VfKdCz/4o6rV2hE6y+8sZch4Aeb62L8p2GGrOw== X-Received: by 2002:adf:cf07:: with SMTP id o7mr2914341wrj.216.1628760847642; Thu, 12 Aug 2021 02:34:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Date: Thu, 12 Aug 2021 10:33:40 +0100 Message-Id: <20210812093356.1946-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761155633100001 Content-Type: text/plain; charset="utf-8" It is quite common for a clock tree to involve possibly programmable clock multipliers or dividers, where the frequency of a clock is for instance divided by 8 to produce a slower clock to feed to a particular device. Currently we provide no convenient mechanism for modelling this. You can implement it by having an input Clock and an output Clock, and manually setting the period of the output clock in the period-changed callback of the input clock, but that's quite clunky. This patch adds support in the Clock objects themselves for setting a multiplier or divider. The effect of setting this on a clock is that when the clock's period is changed, all the children of the clock are set to period * multiplier / divider, rather than being set to the same period as the parent clock. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Damien Hedde Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/devel/clocks.rst | 23 +++++++++++++++++++++++ include/hw/clock.h | 29 +++++++++++++++++++++++++++++ hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++- hw/core/clock.c | 29 +++++++++++++++++++++++++---- 4 files changed, 100 insertions(+), 5 deletions(-) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 956bd147ea0..430fbd842e5 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clo= ck 3* and *Clock 4*. It is not possible to disconnect a clock or to change the clock connection after it is connected. =20 +Clock multiplier and divider settings +------------------------------------- + +By default, when clocks are connected together, the child +clocks run with the same period as their source (parent) clock. +The Clock API supports a built-in period multiplier/divider +mechanism so you can configure a clock to make its children +run at a different period from its own. If you call the +``clock_set_mul_div()`` function you can specify the clock's +multiplier and divider values. The children of that clock +will all run with a period of ``parent_period * multiplier / divider``. +For instance, if the clock has a frequency of 8MHz and you set its +multiplier to 2 and its divider to 3, the child clocks will run +at 12MHz. + +You can change the multiplier and divider of a clock at runtime, +so you can use this to model clock controller devices which +have guest-programmable frequency multipliers or dividers. + +Note that ``clock_set_mul_div()`` does not automatically call +``clock_propagate()``. If you make a runtime change to the +multiplier or divider you must call clock_propagate() yourself.a + Unconnected input clocks ------------------------ =20 diff --git a/include/hw/clock.h b/include/hw/clock.h index a7187eab95e..11f67fb9701 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -81,6 +81,10 @@ struct Clock { void *callback_opaque; unsigned int callback_events; =20 + /* Ratio of the parent clock to run the child clocks at */ + uint32_t multiplier; + uint32_t divider; + /* Clocks are organized in a clock tree */ Clock *source; QLIST_HEAD(, Clock) children; @@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk) */ char *clock_display_freq(Clock *clk); =20 +/** + * clock_set_mul_div: set multiplier/divider for child clocks + * @clk: clock + * @multiplier: multiplier value + * @divider: divider value + * + * By default, a Clock's children will all run with the same period + * as their parent. This function allows you to adjust the multiplier + * and divider used to derive the child clock frequency. + * For example, setting a multiplier of 2 and a divider of 3 + * will run child clocks with a period 2/3 of the parent clock, + * so if the parent clock is an 8MHz clock the children will + * be 12MHz. + * + * Setting the multiplier to 0 will stop the child clocks. + * Setting the divider to 0 is a programming error (diagnosed with + * an assertion failure). + * Setting a multiplier value that results in the child period + * overflowing is not diagnosed. + * + * Note that this function does not call clock_propagate(); the + * caller should do that if necessary. + */ +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider); + #endif /* QEMU_HW_CLOCK_H */ diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c index 260b13fc2c8..07bb45d7ed4 100644 --- a/hw/core/clock-vmstate.c +++ b/hw/core/clock-vmstate.c @@ -14,6 +14,24 @@ #include "migration/vmstate.h" #include "hw/clock.h" =20 +static bool muldiv_needed(void *opaque) +{ + Clock *clk =3D opaque; + + return clk->multiplier !=3D 1 || clk->divider !=3D 1; +} + +const VMStateDescription vmstate_muldiv =3D { + .name =3D "clock/muldiv", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D muldiv_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(multiplier, Clock), + VMSTATE_UINT32(divider, Clock), + }, +}; + const VMStateDescription vmstate_clock =3D { .name =3D "clock", .version_id =3D 0, @@ -21,5 +39,9 @@ const VMStateDescription vmstate_clock =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT64(period, Clock), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_muldiv, + NULL + }, }; diff --git a/hw/core/clock.c b/hw/core/clock.c index fc5a99683f8..c371b9e977a 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period) return true; } =20 +static uint64_t clock_get_child_period(Clock *clk) +{ + /* + * Return the period to be used for child clocks, which is the parent + * clock period adjusted for for multiplier and divider effects. + */ + return muldiv64(clk->period, clk->multiplier, clk->divider); +} + static void clock_call_callback(Clock *clk, ClockEvent event) { /* @@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent = event) static void clock_propagate_period(Clock *clk, bool call_callbacks) { Clock *child; + uint64_t child_period =3D clock_get_child_period(clk); =20 QLIST_FOREACH(child, &clk->children, sibling) { - if (child->period !=3D clk->period) { + if (child->period !=3D child_period) { if (call_callbacks) { clock_call_callback(child, ClockPreUpdate); } - child->period =3D clk->period; + child->period =3D child_period; trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), - CLOCK_PERIOD_TO_HZ(clk->period), + CLOCK_PERIOD_TO_HZ(child->period), call_callbacks); if (call_callbacks) { clock_call_callback(child, ClockUpdate); @@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src) =20 trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src)); =20 - clk->period =3D src->period; + clk->period =3D clock_get_child_period(src); QLIST_INSERT_HEAD(&src->children, clk, sibling); clk->source =3D src; clock_propagate_period(clk, false); @@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk) return freq_to_str(clock_get_hz(clk)); } =20 +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider) +{ + assert(divider !=3D 0); + + clk->multiplier =3D multiplier; + clk->divider =3D divider; +} + static void clock_initfn(Object *obj) { Clock *clk =3D CLOCK(obj); =20 + clk->multiplier =3D 1; + clk->divider =3D 1; + QLIST_INIT(&clk->children); } =20 --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162876109523220.7016180034924; Thu, 12 Aug 2021 02:38:15 -0700 (PDT) Received: from localhost ([::1]:58400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7AE-0008RU-2c for importer@patchew.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZ34cRsgLtFiqWjLUrzVojRfLDZmQXmFHIvftQxhUGw=; b=yRx4qradlovMgIPQYHHX3TBntkvWqqJYA7i5X29khpZ4XoUJDetnKlX27tLiCC8KyP 0kpdwgB0z1Mmpf5J5x+j384ix4X33biY1cu9zpPC+itwc8N8zyyFwvfpLY0Od+d5WNhc R/lRTNd+KlWFn5qkXp/vO3aCyNesU1LOFeyV2ca/MCJNLh6FqB6lD5J8fCqf+e2zBSlT qsc5XCzZ0TMRH2EFkVulOVSlKY3BqFwfwnOp/5Nm9YTYFH37oIvk1uHHMgUMqBrmu2FJ c9Ak0zHl3io3VGxoPhA68QGPUNzfikUvmxdYw+6xQmTUPLDWIexpmEOdheyisivD+mEh IZpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZ34cRsgLtFiqWjLUrzVojRfLDZmQXmFHIvftQxhUGw=; b=TNOMBksx0CsFmiJmq81zHjtoqCa39Oo5JGZrEYyiF1+6V8Uz88/IZP15sfFbK/PEL5 FZ2U4jJ7tePe/FaoClKc0Un7e//LeD/czQ1SzRJOIUvKDgYut+T4myyV/1ubD1tj1NZ7 emS3gA3NiK8S+JAXJ6lmT7LTA3hGjn449D9cBnBHeL2EgAop3OKI9ziAcahPp3PHL8hx V1agNSXFdBnFAMpTAXLXLelUrIT/CfPfz5lixL2aH8b/IfpXnvenZRBlNQgCjtMubI5x QCcjFuidxBLXv4OjOp92cHqG/khVcwa7vL3zG32NRA/eOFc64UTT6AN48WTmbc8CXVav bCWg== X-Gm-Message-State: AOAM530OQCd914420F026A1m2JsxCqrIClQzs0fXi+ZOBBHm1FZ6qdTA xyGaSm0KkwyTLPMaA3izTk5JCg== X-Google-Smtp-Source: ABdhPJwXqd7Y7fUJgFliskb6YLbwGVhKFQ0RCr8XJUUGdme8h6MHc2QO5kP4Too/RidrKJ/skWYGEw== X-Received: by 2002:a05:600c:ad8:: with SMTP id c24mr14212401wmr.28.1628760848595; Thu, 12 Aug 2021 02:34:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Date: Thu, 12 Aug 2021 10:33:41 +0100 Message-Id: <20210812093356.1946-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761096468100001 Content-Type: text/plain; charset="utf-8" In the realize methods of the stm32f100 and stm32f205 SoC objects, we call g_new() to create new MemoryRegion objjects for the sram, flash, and flash_alias. This is unnecessary (and leaves open the possibility of leaking the allocations if we exit from realize with an error). Make these MemoryRegions member fields of the device state struct instead, as stm32f405 already does. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/stm32f100_soc.h | 4 ++++ include/hw/arm/stm32f205_soc.h | 4 ++++ hw/arm/stm32f100_soc.c | 17 +++++++---------- hw/arm/stm32f205_soc.c | 17 +++++++---------- 4 files changed, 22 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 71bffcf4fd5..b7d71c6c634 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -52,6 +52,10 @@ struct STM32F100State { =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; }; =20 #endif diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 985ff63aa9e..75251494917 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -63,6 +63,10 @@ struct STM32F205State { STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 qemu_or_irq *adc_irqs; + + MemoryRegion sram; + MemoryRegion flash; + MemoryRegion flash_alias; }; =20 #endif diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 0c4a5c66451..0be92b2c475 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); - MemoryRegion *flash =3D g_new(MemoryRegion, 1); - MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); =20 /* * Init flash region * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 */ - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash", + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash", FLASH_SIZE, &error_fatal); - memory_region_init_alias(flash_alias, OBJECT(dev_soc), - "STM32F100.flash.alias", flash, 0, FLASH_SIZE= ); - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); - memory_region_add_subregion(system_memory, 0, flash_alias); + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "STM32F100.flash.alias", &s->flash, 0, FLASH_= SIZE); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); =20 /* Init SRAM region */ - memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE, + memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 9cd41bf56da..0bd215aebd7 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); - MemoryRegion *flash =3D g_new(MemoryRegion, 1); - MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); =20 - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash", + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", FLASH_SIZE, &error_fatal); - memory_region_init_alias(flash_alias, OBJECT(dev_soc), - "STM32F205.flash.alias", flash, 0, FLASH_SIZE= ); + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "STM32F205.flash.alias", &s->flash, 0, FLASH_= SIZE); =20 - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); - memory_region_add_subregion(system_memory, 0, flash_alias); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); =20 - memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, + memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761072109571.1463144562454; Thu, 12 Aug 2021 02:37:52 -0700 (PDT) Received: from localhost ([::1]:56156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE79r-0006xa-2j for importer@patchew.org; Thu, 12 Aug 2021 05:37:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76N-0005Nh-85 for qemu-devel@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BbTX/NucXCYFIRoCKoRXjBrwppGdZQUWNSG930H1Tcg=; b=FOAjLsI2VCzlzcNPNrmjL3FwdR+VCfAW+M7oIEoQfgEY6rXwznDu12xEfFmef7fDVc pUHbuH3sRvzCqgWVTvSSHq9wEU9zqPSiAPgMEBFlIAHSZUZ4wQdXlQWuAJxQCEykHFmM 2fjpxNZUgKOnfL9P0Zxy8fztl1R9CYonWRgfIxeHm6Pj+RJGWmSdAodBbU8W4bhgLf3Q gksrV6SH/3WzIJJd5jTvEL3M0/l/GSY2Lpa4EOL3yNeOUU9VDuWgmWTvhvmfxVaD9Q1H 7aB8hjXpSouiEgmNcSR8V4iuOglWJgg+eJRt1ZQ0bUvnmK3xdZFZliV7qBCh55oEkRi4 44kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BbTX/NucXCYFIRoCKoRXjBrwppGdZQUWNSG930H1Tcg=; b=SXn4EhNeupR26cJomfWJW32TLi6pkXyF9Jt0jQCk78G2r+6mNb3ZW3Si+N+XbpeFU9 6Kz/nJI5/ZWftwuQWvr55JTlBCw2s5lYpAJRuHagdqAR0dRnR3l25B4XfJ8vWzJ4Fx2v 5mBU0bEovgndgW5DRgABbeO8indILrlbGoYZdFXsh6Z5ZeCaCvtov6OyfMuzlPePu0uX xWKW7yW6IzGZm2vOB9d94tu2M6+51jGRdixW9klKSSkcIdFs/Tw66ZVUNojpEnmRvwOf 9ghFw8cO5KeGPOGx3U+pcJn2PiwmTlT1fIRMdTz6Qqc/a/aUTeIvdc7gVi305EN3YH71 aARw== X-Gm-Message-State: AOAM53296eyLPIGZRhmO9TnyDeMGk2f23qNoJYaBQpgGQhgPGifqYnZt Tto9CPVzYGwm7g8RGDenQYEJgg== X-Google-Smtp-Source: ABdhPJy0o+kLAgttdNQFmFQJklUnvv68pRSw1ZLb653ljaB3nv0BmYRcrfwfNhTrjcDFGX2cVpG6wg== X-Received: by 2002:a7b:c144:: with SMTP id z4mr14184031wmi.55.1628760849526; Thu, 12 Aug 2021 02:34:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Date: Thu, 12 Aug 2021 10:33:42 +0100 Message-Id: <20210812093356.1946-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761072480100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/stm32f100_soc.h | 4 ++++ hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++ hw/arm/stm32vldiscovery.c | 12 +++++++----- 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index b7d71c6c634..40cd415b284 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -29,6 +29,7 @@ #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" #include "qom/object.h" +#include "hw/clock.h" =20 #define TYPE_STM32F100_SOC "stm32f100-soc" OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) @@ -56,6 +57,9 @@ struct STM32F100State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 0be92b2c475..f7b344ba9fb 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -30,6 +30,7 @@ #include "exec/address-spaces.h" #include "hw/arm/stm32f100_soc.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" =20 @@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj) for (i =3D 0; i < STM_NUM_SPIS; i++) { object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) @@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, = Error **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + /* * Init flash region * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 @@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, = Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 61); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 7e8191ebf5f..07e401a818d 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" @@ -39,16 +40,17 @@ static void stm32vldiscovery_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F100_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761186665555.7709759716482; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7atIIz9vNDvMRlAfoc+jUsWE/JQnMUBn7D/R0DKnTp8=; b=SUfytAJ4/bLBQRKB0By3vzo/tw74CQsIA0Jnd+f6YdzkErmQfUWV0UDGqeq9BgIr/u Cd++vzmjWkTnY3nF8FsJJYAqL2BB0qa5A8k8nlrTCZ8+p5eq/WyTN9bMuz43rUKDPJXM dDMJSRsShrexwLl0xgVncOYhXtygLyzYHAqtjuYKONx52dqBej6RvOP9G9Lm50OL596I /9eJ9hPPzrGJOGaX4qBrHwwA+eWg4MfAeFJICOdPO+b2rJgQJgsGvb3A6yJ+8qy4OUit vEXCjBRYLextUN2jCJGdyXFnMxx4dS94zEgU2dc71LYIMtDkaLifZAZWUPWP7vRVxg6M 8DIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7atIIz9vNDvMRlAfoc+jUsWE/JQnMUBn7D/R0DKnTp8=; b=k7jav7GKher1e/7r5BsJZeP8wFJTZbTbMoCXl7EJUAYDiC7yUuIvHDgxpnsWbjk91K mD32LnDSyeIjMuM0uycn+x8IoEjiKLg6g6Fc3rQjfSeytriI3JEB6skqVszEpm/685hV tCk/Bb2H3RkNm0crizrbMoI5rPLX1+J1paWXupOtd2oi0A4mG20kDpDvSYV5lHsFRLIN qPvnu/FGNhVGJ19PXFAODpQGh6m8S4AI+4DDotl+491zzgs3B5mi/5pKwqubI/c+ixTJ Asne1uMKTKOIc4vXXaCpY7mtrp4nf0NGA49xcMUklUaPl2HMh47+mDcvFDXysNfSLYGR lriw== X-Gm-Message-State: AOAM530GIH56q3fZiM2iCtyKkkmAo8RXWuo/5BPZ02TQIjaxJdKyHXIC zrT0ZfV2qx7GFBnsFLKEKLUlvg== X-Google-Smtp-Source: ABdhPJzVW59og7Ys99ExmhGON9Dl+1QQ7F/vW89p2VlSsac78LYuiybZODnjhEjIWKa0qm8lqan00g== X-Received: by 2002:adf:cd86:: with SMTP id q6mr2854280wrj.385.1628760850478; Thu, 12 Aug 2021 02:34:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk Date: Thu, 12 Aug 2021 10:33:43 +0100 Message-Id: <20210812093356.1946-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761188201100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/stm32f205_soc.h | 4 ++++ hw/arm/netduino2.c | 12 +++++++----- hw/arm/stm32f205_soc.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 75251494917..849d3ed8891 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -32,6 +32,7 @@ #include "hw/or-irq.h" #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_STM32F205_SOC "stm32f205-soc" @@ -67,6 +68,9 @@ struct STM32F205State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 1733b71507c..b5c0ba23ee5 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" @@ -36,16 +37,17 @@ static void netduino2_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F205_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 0bd215aebd7..c6b75a381d9 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -29,6 +29,7 @@ #include "exec/address-spaces.h" #include "hw/arm/stm32f205_soc.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "sysemu/sysemu.h" =20 /* At the moment only Timer 2 to 5 are modelled */ @@ -74,6 +75,9 @@ static void stm32f205_soc_initfn(Object *obj) for (i =3D 0; i < STM_NUM_SPIS; i++) { object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -85,6 +89,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, = Error **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", FLASH_SIZE, &error_fatal); memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), @@ -101,6 +129,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761305704571.1164007436656; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V9LPD/w5S2tICuCSVQyFMKgCCI7LpmXe58LRM4rK7Cs=; b=bUzvD/IN9TlDDyE4GFCUnRlOHY+XtI1kWAlXEXlCoxYAZxeseaw/QAz8qWlRjHzV6a ZxAi5RRpBxtiXYKuX95pTzaL9pYA7V+y5/ADBXeAPIznwnv7JnTIfKiwYx0RtJrAPVV9 mdIh0tUO/3gNOK/WvEtGXbd6dJfvMHxJH/jHA9NjbdRpAhPRHQN2kEH029M9U0IBX3pC gHF5tymJc3SYmjJ/bg57PTXpXrmL8E5fnbn2qohG7cjg8L+HLMf7LexQ26gsdA2QXEbA YfSq1XxtqgFnZyJoSntchoX0Vdv50SvDCIbW40V5kd/caw6UmMTPFfbn5cCgXBJ3PqsA 20jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V9LPD/w5S2tICuCSVQyFMKgCCI7LpmXe58LRM4rK7Cs=; b=m966cQ6qBYGDMhJeZluvF3xSTBnKc9A4NEJLLYq3ToF29ysYe8t5e1d9L2Ei8R7m3w Aa0bYS1GRqdvPZffwa+nU8G2ix6QUFmzFNy3M+S/NPK/3GC1h9Wd94fEmlJCFA3s0OG4 10tfACipbhOWsyV2S/ONIDYKTl5pRVnxyoKzoU9chbdrfC+MsTrLTJjOI/KFAr1WLzLK 8iZeo/CiBHhunFc0wtv7h7icVTQHmXuv+PJXELn61qGV5uh6vA2RfkErmszz2Bvov/c1 Yq9rFkDpo/aWyoupYvXjwfMODf9PoSqhjrfpik01ejscozFYFO3H1l+rx8MDZd1fDt7V tGKQ== X-Gm-Message-State: AOAM532P4Kvzzppiw2Y40TXFP1T+CF7z25IcVIG8lbg+Q8NNX2Fcu69m zm/WAnM6afrHPoiWgKLHW8wZZA== X-Google-Smtp-Source: ABdhPJytW823YPO6cCypDP/nFuzJ1Xdj90BcXt8BK+LLVtXCWh9hKznkADM3nqGsPu0G/PHPde4N7g== X-Received: by 2002:a7b:c204:: with SMTP id x4mr2985911wmi.70.1628760851426; Thu, 12 Aug 2021 02:34:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk Date: Thu, 12 Aug 2021 10:33:44 +0100 Message-Id: <20210812093356.1946-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761307962100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- include/hw/arm/stm32f405_soc.h | 3 +++ hw/arm/netduinoplus2.c | 12 +++++++----- hw/arm/stm32f405_soc.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 347105e709b..5bb0c8d5697 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -68,6 +68,9 @@ struct STM32F405State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; }; =20 #endif diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index d3ad7a2b675..a5a8999cc8c 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" @@ -36,16 +37,17 @@ static void netduinoplus2_init(MachineState *machine) { DeviceState *dev; + Clock *sysclk; =20 - /* - * TODO: ideally we would model the SoC RCC and let it handle - * system_clock_scale, including its ability to define different - * possible SYSCLK sources. - */ system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + dev =3D qdev_new(TYPE_STM32F405_SOC); qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 armv7m_load_kernel(ARM_CPU(first_cpu), diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cb04c111987..0019b7f4785 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/arm/stm32f405_soc.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 #define SYSCFG_ADD 0x40013800 @@ -80,6 +81,9 @@ static void stm32f405_soc_initfn(Object *obj) } =20 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } =20 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) @@ -91,6 +95,30 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, = Error **errp) Error *err =3D NULL; int i; =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board c= ode"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", FLASH_SIZE, &err); if (err !=3D NULL) { @@ -116,6 +144,8 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,= Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(system_memory), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16287615591621022.8028923915355; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3PDN4mKTf0zYjcvH+MYD67g3sSoLMbW7iWecHpCgpiM=; b=VYTqU7ZkZXuCe43Udu+Fyb+3iKVd9q9QEo09fE9N/yzB6sW+sg1CWSV9sx0wmkz7hM ZNyY66vSBRomLi/oQod9ycz9wCqJFH0Vb8xHSf/7nFOafDEMxzsdnqSR28yjznQBt/vL SnBpENRhG/TS9kKtW3crz9so5zclaUFvFHu/row1IacNDbj5HLvrGyahLi4pLz59wXe0 W9nlmlte6NCrogH7QUuADUmC8xByXBBkQ+gYxZhWvOg//ZqixonPwERhOqIkFhNCrWQ2 7nVirjf0I8gD8t5je9sXtD3EHtu3HY7pXatD1Q2IxBsGn5MxpX1x3wq8U0kvmPf74czO kXOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3PDN4mKTf0zYjcvH+MYD67g3sSoLMbW7iWecHpCgpiM=; b=remLd+OswaoAlkrFgaf29LXKhiMUOfYLeM+IL5cojd8+JdM5gvRYguEJqS4IGhCupA kb4HzuFqHRdU9cCp0Thr9fAWAfZ5LH52BCXB8SRG7U7lGIMTxYD4R+D+yID6DDpBuiym q8p9oSSX87HBZbu3am3K1L3CqVZQ4sxQg/53nRJFtTTSX6xPbJOTEsgDX7M79nKnbVza J4XxchZ0u91bTi03KFErKsMqXDV7jg/uBMBPZ/8IYlp1QLUROKHvZPyRAlf/JEvFcEij IdrFc46RweUB5jK73TUbaa5kkAIBMi/TxeekE/wsG1J2pl8q6z41hZVEjqZ1h+/Ra087 MqGw== X-Gm-Message-State: AOAM530+CRRNlnt0Uab33buMavtkNQvgMtc299HUOE1bMzBanaIqZ8Aw eIH0agcSv0DL2YnjGW/r2b0MKg== X-Google-Smtp-Source: ABdhPJwc58xJC6YVwUHo7xD7O4pyMjootkyML13W6KY4F+m74Nqlp4QBjgt3Fo4jESijLGVM4ZvpHQ== X-Received: by 2002:a7b:c309:: with SMTP id k9mr3104887wmj.48.1628760852323; Thu, 12 Aug 2021 02:34:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Date: Thu, 12 Aug 2021 10:33:45 +0100 Message-Id: <20210812093356.1946-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761560006100001 Content-Type: text/plain; charset="utf-8" Delete the trailing blank line at the end of the source file. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss Reviewed-by: Alistair Francis Reviewed-by: Luc Michel --- hw/arm/stm32vldiscovery.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 07e401a818d..9b79004703b 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *m= c) } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) - --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761449926335.91829858754204; Thu, 12 Aug 2021 02:44:09 -0700 (PDT) Received: from localhost ([::1]:58106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7Fw-0001eO-Mb for importer@patchew.org; Thu, 12 Aug 2021 05:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76R-0005f7-Cx for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:19 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:35641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76N-0007wE-7Y for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:19 -0400 Received: by mail-wm1-x32b.google.com with SMTP id q11-20020a7bce8b0000b02902e6880d0accso6629660wmj.0 for ; Thu, 12 Aug 2021 02:34:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I9TW5HgoQcdmb8WDggWO7uUKdFyUTLqM4EhcWbfGZhw=; b=adsc+FSfAP267D/IMPCTIeGQFSo8uUzkq7o0zeEYLxtc4vhw0eGVm5Lp4Pxj06anDz c4wsWOj/o7oO4yM/A0OZIUAugTvKEHBAG0jHpcD+nBWLEuxYeEXKduG4OkceAmjX+b/0 Zb5wLobsFwFHxX0hSSYxxhvio+kVtLGYNXcKyACpnH9huTZ8Coz1ewfrz0gWS9nqbA5r CA6FF8lVzAVBKwHt7xfqc4K35ZI85C3a8RXp4Hdjb4OqpgbZmHwlqF5wOA8Y5VYeZQFU EpaE2dIW0tJyyL6eAgGBiwOaPwVynBS5n/f+FfddRW4KfO1fYu5y9zuiwAcUA7/WQgRp 7E4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I9TW5HgoQcdmb8WDggWO7uUKdFyUTLqM4EhcWbfGZhw=; b=qldsnz/ukTShj6kHv95xNmOLqwb0Iy6XmO6txpXk3D61id/pZUD4dlIuedayaZw8BQ tVTPAEw26hi9sabLuFNyHfpbbA/2Hdh4jqQUDT6aRXe3DzCiN/aX9BUtziZFq5LuHUOT aK1dFAD3L1xdWxlp1nts2JPW9mXmAs8Hr0xWn8jmIV8n2iSzcqcmozEwolPG69PMkaOs /NE1UUeGEJ9X+tgbELx4CHC2dncleg2jygvb/Zm3tKuvt4RJ9dugECwHKHOq3CP6o2JD Uw9CRwlEgEjs7Mdppa4iOgA9K6eLM/ozYmobWeBgH9nRRL8kpFFgJUig4ZWpUtjYHX9t xs4Q== X-Gm-Message-State: AOAM5317D1E9arglZPGNOnUIXAVnro5Iz8K/T4TrHZfUnnnngPO6rZiC 7XQGyA7Mll4gu3uvwWan5JH8gA== X-Google-Smtp-Source: ABdhPJxujy/am+RZl0mQcarjq+vdVU/TPvgIniRUNQNU1QbpTVRW06dI9vKYPuGfI3Ai2h9thfq1RQ== X-Received: by 2002:a05:600c:246:: with SMTP id 6mr3000980wmj.36.1628760853197; Thu, 12 Aug 2021 02:34:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk Date: Thu, 12 Aug 2021 10:33:46 +0100 Message-Id: <20210812093356.1946-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761451348100001 Content-Type: text/plain; charset="utf-8" Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index f8a6725b775..e52a56e75e0 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -17,6 +17,7 @@ #include "hw/gpio/nrf51_gpio.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" @@ -50,6 +51,7 @@ struct NRF51State { =20 MemoryRegion container; =20 + Clock *sysclk; }; =20 #endif diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 9407c2f268b..e3e849a32b1 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/arm/boot.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "qemu/log.h" =20 @@ -66,6 +67,23 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) return; } =20 + /* + * HCLK on this SoC is fixed, so we set up sysclk ourselves and + * the board shouldn't connect it. + */ + if (clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must not be wired up by the board c= ode"); + return; + } + /* This clock doesn't need migration because it is fixed-frequency */ + clock_set_hz(s->sysclk, HCLK_FRQ); + qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); + /* + * This SoC has no systick device, so don't connect refclk. + * TODO: model the lack of systick (currently the armv7m object + * will always provide one). + */ + system_clock_scale =3D NANOSECONDS_PER_SECOND / HCLK_FRQ; =20 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->contain= er), @@ -191,6 +209,8 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_TIMER); =20 } + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 static Property nrf51_soc_properties[] =3D { --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761168496247.05198351004617; Thu, 12 Aug 2021 02:39:28 -0700 (PDT) Received: from localhost ([::1]:37590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7BP-0004sW-7J for importer@patchew.org; Thu, 12 Aug 2021 05:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76R-0005gt-Rv for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:20 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:54230) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76P-0007xc-3p for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:19 -0400 Received: by mail-wm1-x334.google.com with SMTP id k4so3998643wms.3 for ; Thu, 12 Aug 2021 02:34:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ziCsEIjr/6TL4DulcAYvJ5WYZ2Dy4YbpYnG7GIAD+KQ=; b=uLI4GHlrahoEjmoi9UbRyyOH2CvIYVp0nKK6wuNVR9wIej28PUgEpsdbdhQWId79ub piv5iObOY/1xfZZ0HKGLSs+kqOaFPBmzU/Q1wpL3Z9Tnqczi7pj+tBjDZ7Vt32MxSZZl P3zQuCkF67R2WmeNB20rvd2T2qxFQT4E6JR60GwRGp98xBosY1FN8mPKKR9F1z3mrJUr 8UlU0Zk4XBtsXEFggXGcuxe31k1wZdZ7/Znoh1g6UFm3Sb/iTs+x5okkbI04uWGX6xr+ X74QsoqSHneNy/Rrj5yET5HbJ0JMorDiv8DdVouhdYxYK6vdz+S820b8/35LZD152EEm Dwng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ziCsEIjr/6TL4DulcAYvJ5WYZ2Dy4YbpYnG7GIAD+KQ=; b=NhVvHsVwLaHT6D6SFCYiV+MkOCXpqPRN4eiH6aYca4FAuseE938I8KaCPd8KCaOKxe nA2ulrqx3QAILLIb+eSpcYUUcfqyxRiGLW+JodNmKMfpVaGzgc9YwFzbA8MEkCaLy21y vCDR80/lmb6HanXneSLdfhg90Q75LwKKv1BlHwkSGnBjo/Zp1H7XbYtcWY0ydgmmcRXP THJFZeVBVZmkzeqzwyMy+oWoldPBpVPwgDsq3Lo/Hbvnd9oB1l59QI+hnpe7wi4QAkeW zNPrrlVT5aCzEkIFoDh0rSDYBDsj7Xq2HdIGQQHvwM8FaYzC9zwnV7UbuB8oo29FXnd8 +G8A== X-Gm-Message-State: AOAM530G3dkL5GCnBX7Fa9OH2Kk3PhY15jXG0lPnvySTELVAUie74Jlz LTcmaw7Iabr+nXHlSOv8smDdUQ== X-Google-Smtp-Source: ABdhPJzfZwInhL8G2jZEVr9C6XfJXwEHjYi1sVc93LpHtzvM3iQIT5p+/FhwzzxsVHXqLATEa1ttXg== X-Received: by 2002:a1c:27c5:: with SMTP id n188mr1085350wmn.126.1628760854226; Thu, 12 Aug 2021 02:34:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init() Date: Thu, 12 Aug 2021 10:33:47 +0100 Message-Id: <20210812093356.1946-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761168832100001 Content-Type: text/plain; charset="utf-8" Currently the stellaris_sys_init() function creates the TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its MMIO region and connects its IRQ. In order to support wiring the sysclk up to the armv7m object, we need to split this function apart, because to connect the clock output of the STELLARIS_SYS object to the armv7m object we need to create the STELLARIS_SYS object before the armv7m object, but we can't wire up the IRQ until after we've created the armv7m object. Remove the stellaris_sys_init() function, and instead put the create/configure/realize parts before we create the armv7m object and the mmio/irq connection parts afterwards. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- hw/arm/stellaris.c | 56 +++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ad48cf26058..bf24abd44fd 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -755,33 +755,6 @@ static void stellaris_sys_instance_init(Object *obj) s->sysclk =3D qdev_init_clock_out(DEVICE(s), "SYSCLK"); } =20 -static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, - stellaris_board_info *board, - uint8_t *macaddr) -{ - DeviceState *dev =3D qdev_new(TYPE_STELLARIS_SYS); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - - /* Most devices come preprogrammed with a MAC address in the user data= . */ - qdev_prop_set_uint32(dev, "user0", - macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 1= 6)); - qdev_prop_set_uint32(dev, "user1", - macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 1= 6)); - qdev_prop_set_uint32(dev, "did0", board->did0); - qdev_prop_set_uint32(dev, "did1", board->did1); - qdev_prop_set_uint32(dev, "dc0", board->dc0); - qdev_prop_set_uint32(dev, "dc1", board->dc1); - qdev_prop_set_uint32(dev, "dc2", board->dc2); - qdev_prop_set_uint32(dev, "dc3", board->dc3); - qdev_prop_set_uint32(dev, "dc4", board->dc4); - - sysbus_realize_and_unref(sbd, &error_fatal); - sysbus_mmio_map(sbd, 0, base); - sysbus_connect_irq(sbd, 0, irq); - - return dev; -} - /* I2C controller. */ =20 #define TYPE_STELLARIS_I2C "stellaris-i2c" @@ -1349,6 +1322,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) DeviceState *ssys_dev; int i; int j; + uint8_t *macaddr; =20 MemoryRegion *sram =3D g_new(MemoryRegion, 1); MemoryRegion *flash =3D g_new(MemoryRegion, 1); @@ -1366,6 +1340,26 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) &error_fatal); memory_region_add_subregion(system_memory, 0x20000000, sram); =20 + /* + * Create the system-registers object early, because we will + * need its sysclk output. + */ + ssys_dev =3D qdev_new(TYPE_STELLARIS_SYS); + /* Most devices come preprogrammed with a MAC address in the user data= . */ + macaddr =3D nd_table[0].macaddr.a; + qdev_prop_set_uint32(ssys_dev, "user0", + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 1= 6)); + qdev_prop_set_uint32(ssys_dev, "user1", + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 1= 6)); + qdev_prop_set_uint32(ssys_dev, "did0", board->did0); + qdev_prop_set_uint32(ssys_dev, "did1", board->did1); + qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); + qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); + qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); + qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); + qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); + nvic =3D qdev_new(TYPE_ARMV7M); qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); @@ -1375,6 +1369,10 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) /* This will exit with an error if the user passed us a bad cpu_type */ sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); =20 + /* Now we can wire up the IRQ and MMIO of the system registers */ + sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); + sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic,= 28)); + if (board->dc1 & (1 << 16)) { dev =3D sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), @@ -1397,10 +1395,6 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) } } =20 - ssys_dev =3D stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), - board, nd_table[0].macaddr.a); - - if (board->dc1 & (1 << 3)) { /* watchdog present */ dev =3D qdev_new(TYPE_LUMINARY_WATCHDOG); =20 --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761282153253.41928918381075; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UWrCXYmtjRAj4C2W/jwTV681ZVj1OFk4kh1hAJn5cf8=; b=ldLtkpcQfIO4X9+Fs0T3dRlRaZw9qUzoA3obUNyGcTPXsVSuU/7VIN1FC7AZ7OJqe4 czs9/8JexnaqVQrk0qQNYMW+6EGjEXosVauGqOZSMO0MNqcworSvhWjNUafGyP1JjW0/ +498IjTp2iuNBFZJBB51gk3SL7GKMzUq1pnek6HsM1zUI7ZbLGNeV1RZACKrbTuGuFo5 z2X7Xzniy7U+GAD1srek2QRXHjKb1ZZrA+YxtjRCdce4DM2ikeehVnv6DoybgHCYAp5V Fvhl7KwreuhB7wm+Ezhbw3e7E3s/ZEXXi7huPy7+LX2A9u30RFdNfOPGdRTSc3zu21tg 3Z1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UWrCXYmtjRAj4C2W/jwTV681ZVj1OFk4kh1hAJn5cf8=; b=q3YHulR70Lhx2DRWJ9zO+YdsjTQ71S2n46/rSjAX9UDSVfACvXSpofEKPUN/e+fiJX c9LRtzfHCb4fFRPaeM+uTvJvg2NVoJkp89INbb419T4exGJKrMk14YQJuIVrvnik00Ss v29xx6arAGzhpj3Qb7a6wGiNRa9v4B95jCrZQdG4DDgq8TCCIWUpSuCt+8lPaR0+k8W3 wtaH/syD/HSVhJWaKmKVeLF22HGwdh228gvhcpg0WeOitkXYZqD2m5TO8AvWkNa+aY0p i7F6x5meYotKqsxtFg3k70COnaYWVSJjCwcwuPOm2QJ4bblrSdlthmfZRp+HflsXOTli e+rw== X-Gm-Message-State: AOAM531Wt07Hc3QEJFkjkqMeQ+nN9xHqRAc23zrzd9fNUbykAwaTpAbZ q9DerV6WoWMWXaijBoVUPbgtnA== X-Google-Smtp-Source: ABdhPJwrGb1qWvf4WyppYanKBJDB4Mt2ZJE0Uf+bGT67LGbi5GDWgC3sk5+7HxoHaDFVStlSv51ztA== X-Received: by 2002:a05:600c:19cd:: with SMTP id u13mr10377886wmq.143.1628760855171; Thu, 12 Aug 2021 02:34:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m Date: Thu, 12 Aug 2021 10:33:48 +0100 Message-Id: <20210812093356.1946-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761283738100001 Content-Type: text/plain; charset="utf-8" Connect the sysclk to the armv7m object. This board's SoC does not connect up the systick reference clock, so we don't need to connect a refclk. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- hw/arm/stellaris.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index bf24abd44fd..8c8bd39e2fe 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1322,7 +1322,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) DeviceState *ssys_dev; int i; int j; - uint8_t *macaddr; + const uint8_t *macaddr; =20 MemoryRegion *sram =3D g_new(MemoryRegion, 1); MemoryRegion *flash =3D g_new(MemoryRegion, 1); @@ -1364,6 +1364,9 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); + qdev_connect_clock_in(nvic, "cpuclk", + qdev_get_clock_out(ssys_dev, "SYSCLK")); + /* This SoC does not connect the systick reference clock */ object_property_set_link(OBJECT(nvic), "memory", OBJECT(get_system_memory()), &error_abort); /* This will exit with an error if the user passed us a bad cpu_type */ --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761646202480.4429237121261; Thu, 12 Aug 2021 02:47:26 -0700 (PDT) Received: from localhost ([::1]:43394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7J7-0002CJ-5X for importer@patchew.org; Thu, 12 Aug 2021 05:47:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76V-0005vl-0R for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:23 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:41536) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76P-0007zy-LT for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:22 -0400 Received: by mail-wm1-x32e.google.com with SMTP id c129-20020a1c35870000b02902e6b6135279so2590217wma.0 for ; Thu, 12 Aug 2021 02:34:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imRDz2WYhnYhneAl1HiaVMr6cnP1w4n/2P4u8XAGN8c=; b=nzQlu9UbuecwMnDj1dD9HLhEgjf3SegmOh3BR4BCfZD+NCH/YYTzlnjSzaEOw7agZI FioZxYTi+e5WXz7uI8epar175x+SVjPyhtV9N1fRGeyUXUkSwCTZb+u7vm59k+1Duuz1 1K1cLJrFV2Vpta8t836ZFZQYOb5egnRQTC/QpIAI/ED87C3z/eYYVVcSSem2vRpw5ccL Mg3CQsj3JQ4MofloffFqLd4UZ6LwfyZzYre4YDHAmdIOV/dEfR/fOjjAI7nr/3N+6vPS MzAlQT5oj0V4N3xFrUorwr19o/AYTGqE5TDAmksVb8IVrmv/GiV+tTClIC98rPiJqsVY t/kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=imRDz2WYhnYhneAl1HiaVMr6cnP1w4n/2P4u8XAGN8c=; b=T0v5IDSYTUX8wqpwtpcP8WkFYIqTJuo9/UIcAU/JmCoDqHD1CsRyWk6vexB7akINJd UWNWR8NuP9a3A5v52+GGwRc3usrosg9NNuT97x14TuMv5h5A3BjKOkheLblZ6lCqMPDk sWg51zmWw50VVKlFUH773k6IKBWf0QhYH2nw2sZHOCOzlz9/tLl6id9wfnvKgJMjnOGK t05en4BRAy0m9M96WHeSlWFmugqvN3tdnWgnqsFhISS5S2KPjFfEwYPAtWKznm1O6E7m KxHJJbGd90uStE8wSQMe1r/tXupAvbka30LdblXPvsJTvQzH6r4JTVukXWnGlv1TWq4O WHXQ== X-Gm-Message-State: AOAM532B/HrPoTNx3xwwV4KwHL3xBNO4rbzRqPMQppgf8t+uTSfmZiul bAp4n9fjRntzbjd0ia+vENijAA== X-Google-Smtp-Source: ABdhPJwCQF097XnMMyn9H36kTzz1Y3iWuZTVOHVuvtWcLiWhiY6mDt1uKizjgqkg8PmaeiZDKPkvkw== X-Received: by 2002:a1c:7506:: with SMTP id o6mr11762646wmc.112.1628760856135; Thu, 12 Aug 2021 02:34:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Date: Thu, 12 Aug 2021 10:33:49 +0100 Message-Id: <20210812093356.1946-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761647283100001 Content-Type: text/plain; charset="utf-8" In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- include/hw/arm/msf2-soc.h | 4 ++++ hw/arm/msf2-soc.c | 17 +++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index d4061846855..38e10ce20aa 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -65,6 +65,10 @@ struct MSF2State { MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; MSF2EmacState emac; + + MemoryRegion nvm; + MemoryRegion nvm_alias; + MemoryRegion sram; }; =20 #endif diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 5cfe7caf834..f36788054b3 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -83,11 +83,8 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) int i; =20 MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *nvm =3D g_new(MemoryRegion, 1); - MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); - MemoryRegion *sram =3D g_new(MemoryRegion, 1); =20 - memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size, + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* * On power-on, the eNVM region 0x60000000 is automatically @@ -95,15 +92,15 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) * start address (0x0). We do not support remapping other eNVM, * eSRAM and DDR regions by guest(via Sysreg) currently. */ - memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm,= 0, - s->envm_size); + memory_region_init_alias(&s->nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", + &s->nvm, 0, s->envm_size); =20 - memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); - memory_region_add_subregion(system_memory, 0, nvm_alias); + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, &s->nvm); + memory_region_add_subregion(system_memory, 0, &s->nvm_alias); =20 - memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, + memory_region_init_ram(&s->sram, NULL, "MSF2.eSRAM", s->esram_size, &error_fatal); - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761589379820.6230575461284; Thu, 12 Aug 2021 02:46:29 -0700 (PDT) Received: from localhost ([::1]:39314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7IC-0007wA-BA for importer@patchew.org; Thu, 12 Aug 2021 05:46:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76U-0005s0-8W for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:22 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:33720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76Q-00080T-Fc for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:21 -0400 Received: by mail-wm1-x32b.google.com with SMTP id l10-20020a05600c4f0a00b002e6be174c29so546892wmq.0 for ; Thu, 12 Aug 2021 02:34:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rD6Gs6UZYHCYOmO7OPcudD+C6p8+ffTj/hCxqJpj3NU=; b=gqaBm9OrUHr0znGAbo/QVByRruWa0JaFkdbyFoAiN8MzH9sBsnLRWlcNe5V9VHdD9i xWn3gVQEmVn5TA5ajQ0fgJxKSYnUmfj068xSuOqZtcb+r1g0HJGLJH17QZjDcNhHIXDR B8FD/9CQymY8h/YqjZqClrVpgYKa8xcnmFUg9JfVcr+f2CqV9AhsirBtpjlSMBP5mm/Z x7cQHdC6Q2f9969Eh2YG3PhdllanveyCyW+DmjIknF3FlFj+6gCwydXF2w22A7EJ8wQ/ iUAz5EvMfnR/WuYvhehaBtsF3agjm71Op3Qr1bhX9IXBRcWnGs5Mt1E5WSY1rHqleMZS eg5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rD6Gs6UZYHCYOmO7OPcudD+C6p8+ffTj/hCxqJpj3NU=; b=boKuBlfC9dUhqu0HZEf2s4g5rrOOCFDYnIdY5EJOT7sTPdVPUIcYo2+I/BYysdrY55 JiCiQYC2eV4Culc54IV4g8CRorAntnRr3Md6zlGvxxiItjdvMbaydrYaq7YTvGJBkv+8 7T7kMl/07qV1hIu6hNU0QmsOnjBHpySvtdsmMOfeLfTEMcyFj2Lcs8XTPJG0htUPn44Y cms7laa42zOJzX3cTmQ0k75Qb7ErBCP9KvnP1OY5UyUNxpoaFytsX20E/F/5U2RwysXj 4gjc6PYjstFAIMgNmpaxb36TvWW5Q1jz/Pg8sr5BoVeQA0wW+E6x+GOF72wOmJTTbNdT Vt7Q== X-Gm-Message-State: AOAM533IqvkeoZ2uUiDap60KG8VOaCiT4/t0Mu2E9dPYS6n6UEcDuhul 3aLO2p/qOXyRqt8JiThM8xtz5w== X-Google-Smtp-Source: ABdhPJyA5JZYE9IAxxPBr7hm7anAB7nu8IdRnmb7Y6xx6ARsFpJ/gXUgJaupu7u7KRUzVmAZCp8fVA== X-Received: by 2002:a1c:7c19:: with SMTP id x25mr5340208wmc.172.1628760857087; Thu, 12 Aug 2021 02:34:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Date: Thu, 12 Aug 2021 10:33:50 +0100 Message-Id: <20210812093356.1946-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761590925100001 Content-Type: text/plain; charset="utf-8" Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- include/hw/arm/msf2-soc.h | 3 ++- hw/arm/msf2-soc.c | 28 +++++++++++++++++----------- hw/arm/msf2-som.c | 7 ++++++- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 38e10ce20aa..01f904cec47 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -30,6 +30,7 @@ #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" #include "hw/net/msf2-emac.h" +#include "hw/clock.h" #include "qom/object.h" =20 #define TYPE_MSF2_SOC "msf2-soc" @@ -57,7 +58,7 @@ struct MSF2State { uint64_t envm_size; uint64_t esram_size; =20 - uint32_t m3clk; + Clock *m3clk; uint8_t apb0div; uint8_t apb1div; =20 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index f36788054b3..0a1e594aee6 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -29,6 +29,7 @@ #include "hw/char/serial.h" #include "hw/arm/msf2-soc.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "sysemu/sysemu.h" =20 #define MSF2_TIMER_BASE 0x40004000 @@ -73,6 +74,8 @@ static void m2sxxx_soc_initfn(Object *obj) } =20 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); + + s->m3clk =3D qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -84,6 +87,11 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) =20 MemoryRegion *system_memory =3D get_system_memory(); =20 + if (!clock_has_source(s->m3clk)) { + error_setg(errp, "m3clk must be wired up by the board code"); + return; + } + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* @@ -106,19 +114,14 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, = Error **errp) qdev_prop_set_uint32(armv7m, "num-irq", 81); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { return; } =20 - if (!s->m3clk) { - error_setg(errp, "Invalid m3clk value"); - error_append_hint(errp, "m3clk can not be zero\n"); - return; - } - - system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk; + system_clock_scale =3D clock_ticks_to_ns(s->m3clk, 1); =20 for (i =3D 0; i < MSF2_NUM_UARTS; i++) { if (serial_hd(i)) { @@ -129,8 +132,13 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, E= rror **errp) } =20 dev =3D DEVICE(&s->timer); - /* APB0 clock is the timer input clock */ - qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); + /* + * APB0 clock is the timer input clock. + * TODO: ideally the MSF2 timer device should use a Clock rather than a + * clock-frequency integer property. + */ + qdev_prop_set_uint32(dev, "clock-frequency", + clock_get_hz(s->m3clk) / s->apb0div); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { return; } @@ -207,8 +215,6 @@ static Property m2sxxx_soc_properties[] =3D { DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SI= ZE), DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_MAX_SIZE), - /* Libero GUI shows 100Mhz as default for clocks */ - DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), /* default divisors in Libero GUI */ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 343ec977c07..396e8b99138 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/qdev-clock.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" =20 @@ -49,6 +50,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) BusState *spi_bus; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *ddr =3D g_new(MemoryRegion, 1); + Clock *m3clk; =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { error_report("This board can only be used with CPU %s", @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machin= e) * in Libero. CPU clock is divided by APB0 and APB1 divisors for * peripherals. Emcraft's SoM kit comes with these settings by default. */ - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); + /* This clock doesn't need migration because it is fixed-frequency */ + m3clk =3D clock_new(OBJECT(machine), "m3clk"); + clock_set_hz(m3clk, 142 * 1000000); + qdev_connect_clock_in(dev, "m3clk", m3clk); qdev_prop_set_uint32(dev, "apb0div", 2); qdev_prop_set_uint32(dev, "apb1div", 2); =20 --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761325909560.3473073367959; Thu, 12 Aug 2021 02:42:05 -0700 (PDT) Received: from localhost ([::1]:49518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7Dw-0004Sl-RN for importer@patchew.org; Thu, 12 Aug 2021 05:42:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76V-0005yb-LZ for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:23 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:41747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76R-000818-F8 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:23 -0400 Received: by mail-wr1-x431.google.com with SMTP id x10so1042362wrt.8 for ; Thu, 12 Aug 2021 02:34:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xBEpy6tnaeq4pLl7s09XSomDfvd35EGGhyYCRV+jECc=; b=zajkclg7tnMK4LOSn+oRqTVHUgYxgmFkuEMFqsXD8X8AxcJ/fNvKMdpkwKRQavNprv i56vxOevPTb9F83cN5d+VJmygBywK+Y43syTkmdq+EymwPkMOgvMkAIYJMHzSmARXu8M 6DSDPayODoBZbipzJCHX7dnJx1fGHN2zX9rCStZ3G/WrfyMqgVDcmxKUXjXWbadMGvYG 4wuI4JlvTSRq1RJqr0f1bCcTz7Mu+r2fA5QiO/gm0hVjKBxPGNpQxSVxIig3BvsXId8L rRRk5YwbkQZPbT840i7chnRznRcKQpecpgvI3A47cU22ap2GdmaGKgmgH8quNuafkiE7 rI+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xBEpy6tnaeq4pLl7s09XSomDfvd35EGGhyYCRV+jECc=; b=MkwD+GMPCaqc2jdl3FmChzi2JhW4C0wbOb9+ICnKi1l2cWtyQcgQfswRnKHgFSF6+b K6UwOH5rhPnU/cMZtIwdb2kk6xwBZI0sQApgP9bPu8ODyN+S5jMvKgUH+pDP50qq+tYg q8ovri0f1A3oohdafgz4OH2/LuvwU6XUoHc7EQdtYRSdDGQzpoqpLwQ2TTubtSg7NC3k Ttp12dL+/KQPRWk3ysEtj8LXrSLXN3o2XAv9juNdx8Af32do8dcdfpHDV6oV135NlNqX hchKfN1oTu710M6BJLdSEnY7eMl0n0+RmDzssN0sgWivMb5XDbZVlX2OF525Dd4do2GC MucA== X-Gm-Message-State: AOAM533wAPCFr+M1H1Y7BY8RC8A/IgaA7U/NYh9kYRrH6KhsE08uRLU6 YNpptsi8QX0DeGc65UPUkfJJqg== X-Google-Smtp-Source: ABdhPJwR08nBuNtIHgARsZC5LRGHTja7MICc5B7oNPg0WcoMF2a8wlBA0QSWLrJVP2+oIBqUQz2brw== X-Received: by 2002:adf:db83:: with SMTP id u3mr2991184wri.363.1628760858040; Thu, 12 Aug 2021 02:34:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk Date: Thu, 12 Aug 2021 10:33:51 +0100 Message-Id: <20210812093356.1946-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761327760100001 Content-Type: text/plain; charset="utf-8" Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde --- include/hw/arm/msf2-soc.h | 1 + hw/arm/msf2-soc.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 01f904cec47..ce417a6266a 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -59,6 +59,7 @@ struct MSF2State { uint64_t esram_size; =20 Clock *m3clk; + Clock *refclk; uint8_t apb0div; uint8_t apb1div; =20 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 0a1e594aee6..dbc6d936a76 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -76,6 +76,7 @@ static void m2sxxx_soc_initfn(Object *obj) object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); =20 s->m3clk =3D qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -92,6 +93,27 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } =20 + /* + * We use s->refclk internally and only define it with qdev_init_clock= _in() + * so it is correctly parented and not leaked on an init/deinit; it is= not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk must not be wired up by the board code"); + return; + } + + /* + * TODO: ideally we should model the SoC SYSTICK_CR register at 0xe004= 2038, + * which allows the guest to program the divisor between the m3clk and + * the systick refclk to either /4, /8, /16 or /32, as well as setting + * the value the guest can read in the STCALIB register. Currently we + * implement the divisor as a fixed /32, which matches the reset value + * of SYSTICK_CR. + */ + clock_set_mul_div(s->refclk, 32, 1); + clock_set_source(s->refclk, s->m3clk); + memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_= size, &error_fatal); /* @@ -115,6 +137,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(get_system_memory()), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761769466947.9191699030097; Thu, 12 Aug 2021 02:49:29 -0700 (PDT) Received: from localhost ([::1]:51108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7L6-0007HG-E3 for importer@patchew.org; Thu, 12 Aug 2021 05:49:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76Y-0006AT-GJ for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:26 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:40643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76S-00082i-Km for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:26 -0400 Received: by mail-wr1-x432.google.com with SMTP id k29so7338411wrd.7 for ; Thu, 12 Aug 2021 02:34:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yxHixJ6WSk35tVi/GCaYOMNr6wprUi4sMKeyCo0OWKc=; b=HJhcN6LoqGzTv1EiUyCS3/QMXND98SVx0VhaXSAz1vXtB2TlDYYFBDgvYkTF+H5YGH RGRlXw5Q+qmg7QC50QSUPy3plfPS+G3KMDK2FtNP1S8FcPshi3BOmH3r1HCp+4LTrTJO fbhxbmJmBC2E2+f18W0rLt4IsTGEORyfh6MFx5U1yW86CSdhDXAfBgDL2bdkVel7WuE9 47EkjFcbEDPsS8TVqHHcra3yqLBEr/Jd1Run8saPpsvGEQWD+YOCfq77++AB8SOhL4lT JfYNi7qPO1OuJZcML8hGCwfnRS+j/Cf5VgIFGLKFM6uTfr2GuRIS5SVPWKdeXzF8nndl 6f0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yxHixJ6WSk35tVi/GCaYOMNr6wprUi4sMKeyCo0OWKc=; b=IZtZ9DcHSsJX7fwjtA9IX7gyQbOm9FFAMYud+4gRsq6sNR7A1Ni+rCjttu/9orlNyl 1rwdPslguYpS7aHJqDrc0GBt++5RmZoSKkSO9sKPGh3qfr1lcrl8rczCGDMS31A0rsVp Sx0T6s81JHu3/03S+MChLE89xxC9lixft50kq9W74/SsFc6MVXhr371MPei/iCwwdrKy 9f+vNok0TG/0Q9ZHUKAlh+Qt7O67t9lyEKTFQLFhLm9/taXVlFonJXvOCB4A1LETShhJ Y14H1StbPDsRWHprwc7qFMphv684Lk9pbBhkjC2YjsV/n4lCbhlj5H5nWjjLamNCRBAc NRzg== X-Gm-Message-State: AOAM532iOSzSJ1fB5jQvib5g+uOv94ylYokarANevvlr6ZiDf3yOfZ8x 9fguqkSanShDJvxrosdogPBtVKlPgvAr5g== X-Google-Smtp-Source: ABdhPJx/HiZFf84MKUMR9oW5yORJyJHIrRXCzYPc9mx9QsWBb6GIQxh/cvalD/36GO2rMjU60qZTFQ== X-Received: by 2002:a5d:4d8e:: with SMTP id b14mr2867938wru.422.1628760859103; Thu, 12 Aug 2021 02:34:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Date: Thu, 12 Aug 2021 10:33:52 +0100 Message-Id: <20210812093356.1946-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761769817100001 Content-Type: text/plain; charset="utf-8" Now that all users of the systick devices wire up the clock inputs, use those instead of the system_clock_scale and the hardwired 1MHz value for the reference clock. This will fix various board models where we were incorrectly providing a 1MHz reference clock instead of some other value or instead of providing no reference clock at all. Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde --- hw/timer/armv7m_systick.c | 110 ++++++++++++++++++++++++++++---------- 1 file changed, 82 insertions(+), 28 deletions(-) diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index e43f74114e8..39cca206cfd 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -18,25 +18,29 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qapi/error.h" #include "trace.h" =20 -/* qemu timers run at 1GHz. We want something closer to 1MHz. */ -#define SYSTICK_SCALE 1000ULL - #define SYSTICK_ENABLE (1 << 0) #define SYSTICK_TICKINT (1 << 1) #define SYSTICK_CLKSOURCE (1 << 2) #define SYSTICK_COUNTFLAG (1 << 16) =20 +#define SYSCALIB_NOREF (1U << 31) +#define SYSCALIB_SKEW (1U << 30) + int system_clock_scale; =20 -/* Conversion factor from qemu timer to SysTick frequencies. */ -static inline int64_t systick_scale(SysTickState *s) +static void systick_set_period_from_clock(SysTickState *s) { + /* + * Set the ptimer period from whichever clock is selected. + * Must be called from within a ptimer transaction block. + */ if (s->control & SYSTICK_CLKSOURCE) { - return system_clock_scale; + ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); } else { - return 1000; + ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); } } =20 @@ -83,7 +87,27 @@ static MemTxResult systick_read(void *opaque, hwaddr add= r, uint64_t *data, val =3D ptimer_get_count(s->ptimer); break; case 0xc: /* SysTick Calibration Value. */ - val =3D 10000; + /* + * In real hardware it is possible to make this register report + * a different value from what the reference clock is actually + * running at. We don't model that (which usually happens due + * to integration errors in the real hardware) and instead always + * report the theoretical correct value as described in the + * knowledgebase article at + * https://developer.arm.com/documentation/ka001325/latest + * If necessary, we could implement an extra QOM property on this + * device to force the STCALIB value to something different from + * the "correct" value. + */ + if (!clock_has_source(s->refclk)) { + val =3D SYSCALIB_NOREF; + break; + } + val =3D clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1; + if (clock_ticks_to_ns(s->refclk, val + 1) !=3D 10 * SCALE_MS) { + /* report that tick count does not yield exactly 10ms */ + val |=3D SYSCALIB_SKEW; + } break; default: val =3D 0; @@ -115,6 +139,11 @@ static MemTxResult systick_write(void *opaque, hwaddr = addr, { uint32_t oldval; =20 + if (!clock_has_source(s->refclk)) { + /* This bit is always 1 if there is no external refclk */ + value |=3D SYSTICK_CLKSOURCE; + } + ptimer_transaction_begin(s->ptimer); oldval =3D s->control; s->control &=3D 0xfffffff8; @@ -122,19 +151,14 @@ static MemTxResult systick_write(void *opaque, hwaddr= addr, =20 if ((oldval ^ value) & SYSTICK_ENABLE) { if (value & SYSTICK_ENABLE) { - /* - * Always reload the period in case board code has - * changed system_clock_scale. If we ever replace that - * global with a more sensible API then we might be able - * to set the period only when it actually changes. - */ - ptimer_set_period(s->ptimer, systick_scale(s)); ptimer_run(s->ptimer, 0); } else { ptimer_stop(s->ptimer); } - } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) { - ptimer_set_period(s->ptimer, systick_scale(s)); + } + + if ((oldval ^ value) & SYSTICK_CLKSOURCE) { + systick_set_period_from_clock(s); } ptimer_transaction_commit(s->ptimer); break; @@ -177,20 +201,42 @@ static void systick_reset(DeviceState *dev) { SysTickState *s =3D SYSTICK(dev); =20 - /* - * Forgetting to set system_clock_scale is always a board code - * bug. We can't check this earlier because for some boards - * (like stellaris) it is not yet configured at the point where - * the systick device is realized. - */ - assert(system_clock_scale !=3D 0); - ptimer_transaction_begin(s->ptimer); s->control =3D 0; + if (!clock_has_source(s->refclk)) { + /* This bit is always 1 if there is no external refclk */ + s->control |=3D SYSTICK_CLKSOURCE; + } ptimer_stop(s->ptimer); ptimer_set_count(s->ptimer, 0); ptimer_set_limit(s->ptimer, 0, 0); - ptimer_set_period(s->ptimer, systick_scale(s)); + systick_set_period_from_clock(s); + ptimer_transaction_commit(s->ptimer); +} + +static void systick_cpuclk_update(void *opaque, ClockEvent event) +{ + SysTickState *s =3D SYSTICK(opaque); + + if (!(s->control & SYSTICK_CLKSOURCE)) { + /* currently using refclk, we can ignore cpuclk changes */ + } + + ptimer_transaction_begin(s->ptimer); + ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); + ptimer_transaction_commit(s->ptimer); +} + +static void systick_refclk_update(void *opaque, ClockEvent event) +{ + SysTickState *s =3D SYSTICK(opaque); + + if (s->control & SYSTICK_CLKSOURCE) { + /* currently using cpuclk, we can ignore refclk changes */ + } + + ptimer_transaction_begin(s->ptimer); + ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); ptimer_transaction_commit(s->ptimer); } =20 @@ -203,8 +249,10 @@ static void systick_instance_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); =20 - s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); - s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", + systick_refclk_update, s, ClockUpdate); + s->cpuclk =3D qdev_init_clock_in(DEVICE(obj), "cpuclk", + systick_cpuclk_update, s, ClockUpdate); } =20 static void systick_realize(DeviceState *dev, Error **errp) @@ -215,6 +263,12 @@ static void systick_realize(DeviceState *dev, Error **= errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); + + if (!clock_has_source(s->cpuclk)) { + error_setg(errp, "systick: cpuclk must be connected"); + return; + } + /* It's OK not to connect the refclk */ } =20 static const VMStateDescription vmstate_systick =3D { --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16287614382334.2865893055617335; Thu, 12 Aug 2021 02:43:58 -0700 (PDT) Received: from localhost ([::1]:57550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7Fl-0001GU-62 for importer@patchew.org; Thu, 12 Aug 2021 05:43:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76Y-00068Q-0C for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:26 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:37631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76T-00083l-AV for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:25 -0400 Received: by mail-wm1-x32e.google.com with SMTP id l34-20020a05600c1d22b02902573c214807so6605107wms.2 for ; Thu, 12 Aug 2021 02:34:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S85mczGKeYB6Z3kjaTFVhQoQPK+mNif0lbrV6vtdZ2g=; b=A+niVkl7heApCx6WM+MSahWmhsNtnl/zzMMWg1nez2HXFsT13hGVvdF9Icp/kxXqF3 x9W5AcMHV1fDHha3H+nDScX4Kr3vI2NAvx7xTVGSjfZg/S7COAcPLD5mSIInXmqRL7OA 5nzn5xJvfbq8r6iR01HUtQPg0XjHfYrMUpxliOQynPGj7upG+3ClBjslku5/7BD69Zwq CoL3dgBpxIzFG0k+c235ZTwOKM/GYDjkate8beJ7TwJghjRkWsrlYdYfJbUWrFqINlkP z1tvAxzlPAjH6MgyvzHaoC3O6xj1omZCPi7kZdaJM0FvWczfWrdw7SvDbTYP41576mRh b/2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S85mczGKeYB6Z3kjaTFVhQoQPK+mNif0lbrV6vtdZ2g=; b=doCxioYRLL5oLz4uhxf1K7jRbE8lzlLNT6h45dBhi7ANyEEU5CDcMlolhxIsU5xNBD jbL8LR6W9v99gZN9a1R0niH4tCmKxN2CpkvMpnmYdnndv8Jb1LwbgRirG/BFKTuBqC4e MptvI/SmkpHJVV2xN5seorPV7qTNlB5sR1JzHEs0VwzdC7aq/eC5LMnR2SR+CV+LUU3n asQ9BORZ8cj/ioK9qud7B8JrGlTm6YcnAT3gdFrySsgCJ4FqyMkAJCMoCLT2QfXDwPXl NqlzgFAGETQHCfRBfh7yTPGnjj3lGE6V1LPpcoNmeae9Cl8trwlEkIvbjqP8wSKrwDSd pAZg== X-Gm-Message-State: AOAM531Jzy3VWNuySo3o0TaH5M+f+4TYX48uYr4yXcaf5lTDohyUl9ss uznYfLYxuG+99z/O3BhrWJSlgg== X-Google-Smtp-Source: ABdhPJz6+xlg0KILbQe1/2JdIkwBzer8iw9QlwHhD1FHhXQlcGw1f/qvRQcP9GpN4zvhQ9zYzdx84w== X-Received: by 2002:a05:600c:a49:: with SMTP id c9mr13057935wmq.159.1628760859973; Thu, 12 Aug 2021 02:34:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code Date: Thu, 12 Aug 2021 10:33:53 +0100 Message-Id: <20210812093356.1946-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761438434100001 Content-Type: text/plain; charset="utf-8" Fix the code style issues in the Stellaris general purpose timer module code, so that when we move it to a different file in a following patch checkpatch doesn't complain. Signed-off-by: Peter Maydell Reviewed-by: Alexandre Iooss --- hw/arm/stellaris.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8c8bd39e2fe..a32c567ce11 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -97,10 +97,11 @@ static void gptm_stop(gptm_state *s, int n) static void gptm_reload(gptm_state *s, int n, int reset) { int64_t tick; - if (reset) + if (reset) { tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - else + } else { tick =3D s->tick[n]; + } =20 if (s->config =3D=3D 0) { /* 32-bit CountDown. */ @@ -227,9 +228,11 @@ static void gptm_write(void *opaque, hwaddr offset, gptm_state *s =3D (gptm_state *)opaque; uint32_t oldval; =20 - /* The timers should be disabled before changing the configuration. - We take advantage of this and defer everything until the timer - is enabled. */ + /* + * The timers should be disabled before changing the configuration. + * We take advantage of this and defer everything until the timer + * is enabled. + */ switch (offset) { case 0x00: /* CFG */ s->config =3D value; --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761575364256.50184103652384; Thu, 12 Aug 2021 02:46:15 -0700 (PDT) Received: from localhost ([::1]:37768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7Hy-0006vc-8f for importer@patchew.org; Thu, 12 Aug 2021 05:46:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76a-0006HW-8C for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:28 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:35554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76U-00085R-Uc for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:27 -0400 Received: by mail-wr1-x430.google.com with SMTP id q10so7379338wro.2 for ; Thu, 12 Aug 2021 02:34:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ohWM8OWbk1iWiPzDar2gc3/n7qlkWreHSd+FbDbzw4=; b=dXbbU1Ow+65aQcHovQA7Awmq/i9b7Rz0OAzPBIVSFzjyJLKFL7rDBL9wnGH3m+XYFf Kddao1imyy6/gApvGKoLlRHNKzyIkgUk0H3qOtCnx/MCbS2d2oME4VCIrvofBYlg95xQ dkOcWzIZQyWNNo6djRnzLGlXt9EEhEmK+TzgLFJV0dqQOBVML+yaIUBKHtPLWQPkK7P8 oc3UHfze+PuaQ6H2iooYNIzLoj/2K0nNUQLc5pL87x9K59+SrfWfaW1XDHo56MQ9ghOM 0ZE5HvuELcAN9FseWJzzZ4AruNoKxGTjFTAewN7qEY4BnHG/qNYA5pMTNsssM8O+kT5F Z0Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ohWM8OWbk1iWiPzDar2gc3/n7qlkWreHSd+FbDbzw4=; b=BzuF7rMS78g8Bu8yjfsxa4zjoGT4kuJQbGiToL89wsRoW2jtoq2vqYZxHqiTaAno0J aUsl2YRhDcrqddYDjT84aJS7GLN3re1jJmo86fLc+8fa2YKPa0z4o1xYgk+VkpvO4WwY JzE4/B035t4njMKBeeAoTWXofGrIsc0co1L5ycOIw4jxm6s4hyJoF7ptWBoQ+vWZXIEQ jnbe8HSDYV3AgNwg1zrUcNSDGkMnfU9AFbaw28dH5eUhZCBYUdYcBA75DuNJcJovn+P6 hxSm9SwqehfitQaChao1fgMFYTX8rK+pA2uofZGLmHu57DPPMoGINy1gexFBMJ2ycmQx F3rw== X-Gm-Message-State: AOAM532viwV4y37PMxmcV6SPbaFxgzwdRsztyk9mAwEt44seSvhFYwYI WqeNK44A0fEv54AY8e7+v+Fbng== X-Google-Smtp-Source: ABdhPJxPErvFKE2Lb3PHIWeR0Xevv5Ynt5wWiT+jp8WKmZ6w/yq0yOgT1AAAaRotbYKY56VH5jDG2Q== X-Received: by 2002:a5d:6908:: with SMTP id t8mr1863582wru.182.1628760861252; Thu, 12 Aug 2021 02:34:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file Date: Thu, 12 Aug 2021 10:33:54 +0100 Message-Id: <20210812093356.1946-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761577318100001 Content-Type: text/plain; charset="utf-8" The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell Reviewed-by: Damien Hedde --- include/hw/timer/stellaris-gptm.h | 48 +++++ hw/arm/stellaris.c | 321 +----------------------------- hw/timer/stellaris-gptm.c | 314 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/timer/Kconfig | 3 + hw/timer/meson.build | 1 + 6 files changed, 368 insertions(+), 320 deletions(-) create mode 100644 include/hw/timer/stellaris-gptm.h create mode 100644 hw/timer/stellaris-gptm.c diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris= -gptm.h new file mode 100644 index 00000000000..b8fa43c94bf --- /dev/null +++ b/include/hw/timer/stellaris-gptm.h @@ -0,0 +1,48 @@ +/* + * Luminary Micro Stellaris General Purpose Timer Module + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#ifndef HW_TIMER_STELLARIS_GPTM_H +#define HW_TIMER_STELLARIS_GPTM_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_STELLARIS_GPTM "stellaris-gptm" +OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) + +/* + * QEMU interface: + * + sysbus MMIO region 0: register bank + * + sysbus IRQ 0: timer interrupt + * + unnamed GPIO output 0: trigger output for the ADC + */ +struct gptm_state { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t config; + uint32_t mode[2]; + uint32_t control; + uint32_t state; + uint32_t mask; + uint32_t load[2]; + uint32_t match[2]; + uint32_t prescale[2]; + uint32_t match_prescale[2]; + uint32_t rtc; + int64_t tick[2]; + struct gptm_state *opaque[2]; + QEMUTimer *timer[2]; + /* The timers have an alternate output used to trigger the ADC. */ + qemu_irq trigger; + qemu_irq irq; +}; + +#endif diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index a32c567ce11..8c547f146a9 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -26,6 +26,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" #include "hw/misc/unimp.h" +#include "hw/timer/stellaris-gptm.h" #include "hw/qdev-clock.h" #include "qom/object.h" =20 @@ -55,309 +56,6 @@ typedef const struct { uint32_t peripherals; } stellaris_board_info; =20 -/* General purpose timer module. */ - -#define TYPE_STELLARIS_GPTM "stellaris-gptm" -OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) - -struct gptm_state { - SysBusDevice parent_obj; - - MemoryRegion iomem; - uint32_t config; - uint32_t mode[2]; - uint32_t control; - uint32_t state; - uint32_t mask; - uint32_t load[2]; - uint32_t match[2]; - uint32_t prescale[2]; - uint32_t match_prescale[2]; - uint32_t rtc; - int64_t tick[2]; - struct gptm_state *opaque[2]; - QEMUTimer *timer[2]; - /* The timers have an alternate output used to trigger the ADC. */ - qemu_irq trigger; - qemu_irq irq; -}; - -static void gptm_update_irq(gptm_state *s) -{ - int level; - level =3D (s->state & s->mask) !=3D 0; - qemu_set_irq(s->irq, level); -} - -static void gptm_stop(gptm_state *s, int n) -{ - timer_del(s->timer[n]); -} - -static void gptm_reload(gptm_state *s, int n, int reset) -{ - int64_t tick; - if (reset) { - tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } else { - tick =3D s->tick[n]; - } - - if (s->config =3D=3D 0) { - /* 32-bit CountDown. */ - uint32_t count; - count =3D s->load[0] | (s->load[1] << 16); - tick +=3D (int64_t)count * system_clock_scale; - } else if (s->config =3D=3D 1) { - /* 32-bit RTC. 1Hz tick. */ - tick +=3D NANOSECONDS_PER_SECOND; - } else if (s->mode[n] =3D=3D 0xa) { - /* PWM mode. Not implemented. */ - } else { - qemu_log_mask(LOG_UNIMP, - "GPTM: 16-bit timer mode unimplemented: 0x%x\n", - s->mode[n]); - return; - } - s->tick[n] =3D tick; - timer_mod(s->timer[n], tick); -} - -static void gptm_tick(void *opaque) -{ - gptm_state **p =3D (gptm_state **)opaque; - gptm_state *s; - int n; - - s =3D *p; - n =3D p - s->opaque; - if (s->config =3D=3D 0) { - s->state |=3D 1; - if ((s->control & 0x20)) { - /* Output trigger. */ - qemu_irq_pulse(s->trigger); - } - if (s->mode[0] & 1) { - /* One-shot. */ - s->control &=3D ~1; - } else { - /* Periodic. */ - gptm_reload(s, 0, 0); - } - } else if (s->config =3D=3D 1) { - /* RTC. */ - uint32_t match; - s->rtc++; - match =3D s->match[0] | (s->match[1] << 16); - if (s->rtc > match) - s->rtc =3D 0; - if (s->rtc =3D=3D 0) { - s->state |=3D 8; - } - gptm_reload(s, 0, 0); - } else if (s->mode[n] =3D=3D 0xa) { - /* PWM mode. Not implemented. */ - } else { - qemu_log_mask(LOG_UNIMP, - "GPTM: 16-bit timer mode unimplemented: 0x%x\n", - s->mode[n]); - } - gptm_update_irq(s); -} - -static uint64_t gptm_read(void *opaque, hwaddr offset, - unsigned size) -{ - gptm_state *s =3D (gptm_state *)opaque; - - switch (offset) { - case 0x00: /* CFG */ - return s->config; - case 0x04: /* TAMR */ - return s->mode[0]; - case 0x08: /* TBMR */ - return s->mode[1]; - case 0x0c: /* CTL */ - return s->control; - case 0x18: /* IMR */ - return s->mask; - case 0x1c: /* RIS */ - return s->state; - case 0x20: /* MIS */ - return s->state & s->mask; - case 0x24: /* CR */ - return 0; - case 0x28: /* TAILR */ - return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); - case 0x2c: /* TBILR */ - return s->load[1]; - case 0x30: /* TAMARCHR */ - return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); - case 0x34: /* TBMATCHR */ - return s->match[1]; - case 0x38: /* TAPR */ - return s->prescale[0]; - case 0x3c: /* TBPR */ - return s->prescale[1]; - case 0x40: /* TAPMR */ - return s->match_prescale[0]; - case 0x44: /* TBPMR */ - return s->match_prescale[1]; - case 0x48: /* TAR */ - if (s->config =3D=3D 1) { - return s->rtc; - } - qemu_log_mask(LOG_UNIMP, - "GPTM: read of TAR but timer read not supported\n"); - return 0; - case 0x4c: /* TBR */ - qemu_log_mask(LOG_UNIMP, - "GPTM: read of TBR but timer read not supported\n"); - return 0; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", - offset); - return 0; - } -} - -static void gptm_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - gptm_state *s =3D (gptm_state *)opaque; - uint32_t oldval; - - /* - * The timers should be disabled before changing the configuration. - * We take advantage of this and defer everything until the timer - * is enabled. - */ - switch (offset) { - case 0x00: /* CFG */ - s->config =3D value; - break; - case 0x04: /* TAMR */ - s->mode[0] =3D value; - break; - case 0x08: /* TBMR */ - s->mode[1] =3D value; - break; - case 0x0c: /* CTL */ - oldval =3D s->control; - s->control =3D value; - /* TODO: Implement pause. */ - if ((oldval ^ value) & 1) { - if (value & 1) { - gptm_reload(s, 0, 1); - } else { - gptm_stop(s, 0); - } - } - if (((oldval ^ value) & 0x100) && s->config >=3D 4) { - if (value & 0x100) { - gptm_reload(s, 1, 1); - } else { - gptm_stop(s, 1); - } - } - break; - case 0x18: /* IMR */ - s->mask =3D value & 0x77; - gptm_update_irq(s); - break; - case 0x24: /* CR */ - s->state &=3D ~value; - break; - case 0x28: /* TAILR */ - s->load[0] =3D value & 0xffff; - if (s->config < 4) { - s->load[1] =3D value >> 16; - } - break; - case 0x2c: /* TBILR */ - s->load[1] =3D value & 0xffff; - break; - case 0x30: /* TAMARCHR */ - s->match[0] =3D value & 0xffff; - if (s->config < 4) { - s->match[1] =3D value >> 16; - } - break; - case 0x34: /* TBMATCHR */ - s->match[1] =3D value >> 16; - break; - case 0x38: /* TAPR */ - s->prescale[0] =3D value; - break; - case 0x3c: /* TBPR */ - s->prescale[1] =3D value; - break; - case 0x40: /* TAPMR */ - s->match_prescale[0] =3D value; - break; - case 0x44: /* TBPMR */ - s->match_prescale[0] =3D value; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", - offset); - } - gptm_update_irq(s); -} - -static const MemoryRegionOps gptm_ops =3D { - .read =3D gptm_read, - .write =3D gptm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static const VMStateDescription vmstate_stellaris_gptm =3D { - .name =3D "stellaris_gptm", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { - VMSTATE_UINT32(config, gptm_state), - VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), - VMSTATE_UINT32(control, gptm_state), - VMSTATE_UINT32(state, gptm_state), - VMSTATE_UINT32(mask, gptm_state), - VMSTATE_UNUSED(8), - VMSTATE_UINT32_ARRAY(load, gptm_state, 2), - VMSTATE_UINT32_ARRAY(match, gptm_state, 2), - VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), - VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), - VMSTATE_UINT32(rtc, gptm_state), - VMSTATE_INT64_ARRAY(tick, gptm_state, 2), - VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), - VMSTATE_END_OF_LIST() - } -}; - -static void stellaris_gptm_init(Object *obj) -{ - DeviceState *dev =3D DEVICE(obj); - gptm_state *s =3D STELLARIS_GPTM(obj); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - - sysbus_init_irq(sbd, &s->irq); - qdev_init_gpio_out(dev, &s->trigger, 1); - - memory_region_init_io(&s->iomem, obj, &gptm_ops, s, - "gptm", 0x1000); - sysbus_init_mmio(sbd, &s->iomem); - - s->opaque[0] =3D s->opaque[1] =3D s; -} - -static void stellaris_gptm_realize(DeviceState *dev, Error **errp) -{ - gptm_state *s =3D STELLARIS_GPTM(dev); - s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); - s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); -} - /* System controller. */ =20 #define TYPE_STELLARIS_SYS "stellaris-sys" @@ -1642,22 +1340,6 @@ static const TypeInfo stellaris_i2c_info =3D { .class_init =3D stellaris_i2c_class_init, }; =20 -static void stellaris_gptm_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->vmsd =3D &vmstate_stellaris_gptm; - dc->realize =3D stellaris_gptm_realize; -} - -static const TypeInfo stellaris_gptm_info =3D { - .name =3D TYPE_STELLARIS_GPTM, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(gptm_state), - .instance_init =3D stellaris_gptm_init, - .class_init =3D stellaris_gptm_class_init, -}; - static void stellaris_adc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1696,7 +1378,6 @@ static const TypeInfo stellaris_sys_info =3D { static void stellaris_register_types(void) { type_register_static(&stellaris_i2c_info); - type_register_static(&stellaris_gptm_info); type_register_static(&stellaris_adc_info); type_register_static(&stellaris_sys_info); } diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c new file mode 100644 index 00000000000..7846fe5f84e --- /dev/null +++ b/hw/timer/stellaris-gptm.c @@ -0,0 +1,314 @@ +/* + * Luminary Micro Stellaris General Purpose Timer Module + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" +#include "hw/timer/stellaris-gptm.h" +#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale= */ + +static void gptm_update_irq(gptm_state *s) +{ + int level; + level =3D (s->state & s->mask) !=3D 0; + qemu_set_irq(s->irq, level); +} + +static void gptm_stop(gptm_state *s, int n) +{ + timer_del(s->timer[n]); +} + +static void gptm_reload(gptm_state *s, int n, int reset) +{ + int64_t tick; + if (reset) { + tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } else { + tick =3D s->tick[n]; + } + + if (s->config =3D=3D 0) { + /* 32-bit CountDown. */ + uint32_t count; + count =3D s->load[0] | (s->load[1] << 16); + tick +=3D (int64_t)count * system_clock_scale; + } else if (s->config =3D=3D 1) { + /* 32-bit RTC. 1Hz tick. */ + tick +=3D NANOSECONDS_PER_SECOND; + } else if (s->mode[n] =3D=3D 0xa) { + /* PWM mode. Not implemented. */ + } else { + qemu_log_mask(LOG_UNIMP, + "GPTM: 16-bit timer mode unimplemented: 0x%x\n", + s->mode[n]); + return; + } + s->tick[n] =3D tick; + timer_mod(s->timer[n], tick); +} + +static void gptm_tick(void *opaque) +{ + gptm_state **p =3D (gptm_state **)opaque; + gptm_state *s; + int n; + + s =3D *p; + n =3D p - s->opaque; + if (s->config =3D=3D 0) { + s->state |=3D 1; + if ((s->control & 0x20)) { + /* Output trigger. */ + qemu_irq_pulse(s->trigger); + } + if (s->mode[0] & 1) { + /* One-shot. */ + s->control &=3D ~1; + } else { + /* Periodic. */ + gptm_reload(s, 0, 0); + } + } else if (s->config =3D=3D 1) { + /* RTC. */ + uint32_t match; + s->rtc++; + match =3D s->match[0] | (s->match[1] << 16); + if (s->rtc > match) + s->rtc =3D 0; + if (s->rtc =3D=3D 0) { + s->state |=3D 8; + } + gptm_reload(s, 0, 0); + } else if (s->mode[n] =3D=3D 0xa) { + /* PWM mode. Not implemented. */ + } else { + qemu_log_mask(LOG_UNIMP, + "GPTM: 16-bit timer mode unimplemented: 0x%x\n", + s->mode[n]); + } + gptm_update_irq(s); +} + +static uint64_t gptm_read(void *opaque, hwaddr offset, + unsigned size) +{ + gptm_state *s =3D (gptm_state *)opaque; + + switch (offset) { + case 0x00: /* CFG */ + return s->config; + case 0x04: /* TAMR */ + return s->mode[0]; + case 0x08: /* TBMR */ + return s->mode[1]; + case 0x0c: /* CTL */ + return s->control; + case 0x18: /* IMR */ + return s->mask; + case 0x1c: /* RIS */ + return s->state; + case 0x20: /* MIS */ + return s->state & s->mask; + case 0x24: /* CR */ + return 0; + case 0x28: /* TAILR */ + return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); + case 0x2c: /* TBILR */ + return s->load[1]; + case 0x30: /* TAMARCHR */ + return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); + case 0x34: /* TBMATCHR */ + return s->match[1]; + case 0x38: /* TAPR */ + return s->prescale[0]; + case 0x3c: /* TBPR */ + return s->prescale[1]; + case 0x40: /* TAPMR */ + return s->match_prescale[0]; + case 0x44: /* TBPMR */ + return s->match_prescale[1]; + case 0x48: /* TAR */ + if (s->config =3D=3D 1) { + return s->rtc; + } + qemu_log_mask(LOG_UNIMP, + "GPTM: read of TAR but timer read not supported\n"); + return 0; + case 0x4c: /* TBR */ + qemu_log_mask(LOG_UNIMP, + "GPTM: read of TBR but timer read not supported\n"); + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", + offset); + return 0; + } +} + +static void gptm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + gptm_state *s =3D (gptm_state *)opaque; + uint32_t oldval; + + /* + * The timers should be disabled before changing the configuration. + * We take advantage of this and defer everything until the timer + * is enabled. + */ + switch (offset) { + case 0x00: /* CFG */ + s->config =3D value; + break; + case 0x04: /* TAMR */ + s->mode[0] =3D value; + break; + case 0x08: /* TBMR */ + s->mode[1] =3D value; + break; + case 0x0c: /* CTL */ + oldval =3D s->control; + s->control =3D value; + /* TODO: Implement pause. */ + if ((oldval ^ value) & 1) { + if (value & 1) { + gptm_reload(s, 0, 1); + } else { + gptm_stop(s, 0); + } + } + if (((oldval ^ value) & 0x100) && s->config >=3D 4) { + if (value & 0x100) { + gptm_reload(s, 1, 1); + } else { + gptm_stop(s, 1); + } + } + break; + case 0x18: /* IMR */ + s->mask =3D value & 0x77; + gptm_update_irq(s); + break; + case 0x24: /* CR */ + s->state &=3D ~value; + break; + case 0x28: /* TAILR */ + s->load[0] =3D value & 0xffff; + if (s->config < 4) { + s->load[1] =3D value >> 16; + } + break; + case 0x2c: /* TBILR */ + s->load[1] =3D value & 0xffff; + break; + case 0x30: /* TAMARCHR */ + s->match[0] =3D value & 0xffff; + if (s->config < 4) { + s->match[1] =3D value >> 16; + } + break; + case 0x34: /* TBMATCHR */ + s->match[1] =3D value >> 16; + break; + case 0x38: /* TAPR */ + s->prescale[0] =3D value; + break; + case 0x3c: /* TBPR */ + s->prescale[1] =3D value; + break; + case 0x40: /* TAPMR */ + s->match_prescale[0] =3D value; + break; + case 0x44: /* TBPMR */ + s->match_prescale[0] =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", + offset); + } + gptm_update_irq(s); +} + +static const MemoryRegionOps gptm_ops =3D { + .read =3D gptm_read, + .write =3D gptm_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription vmstate_stellaris_gptm =3D { + .name =3D "stellaris_gptm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(config, gptm_state), + VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), + VMSTATE_UINT32(control, gptm_state), + VMSTATE_UINT32(state, gptm_state), + VMSTATE_UINT32(mask, gptm_state), + VMSTATE_UNUSED(8), + VMSTATE_UINT32_ARRAY(load, gptm_state, 2), + VMSTATE_UINT32_ARRAY(match, gptm_state, 2), + VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), + VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), + VMSTATE_UINT32(rtc, gptm_state), + VMSTATE_INT64_ARRAY(tick, gptm_state, 2), + VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), + VMSTATE_END_OF_LIST() + } +}; + +static void stellaris_gptm_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + gptm_state *s =3D STELLARIS_GPTM(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + sysbus_init_irq(sbd, &s->irq); + qdev_init_gpio_out(dev, &s->trigger, 1); + + memory_region_init_io(&s->iomem, obj, &gptm_ops, s, + "gptm", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + + s->opaque[0] =3D s->opaque[1] =3D s; +} + +static void stellaris_gptm_realize(DeviceState *dev, Error **errp) +{ + gptm_state *s =3D STELLARIS_GPTM(dev); + s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); + s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); +} + +static void stellaris_gptm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_stellaris_gptm; + dc->realize =3D stellaris_gptm_realize; +} + +static const TypeInfo stellaris_gptm_info =3D { + .name =3D TYPE_STELLARIS_GPTM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(gptm_state), + .instance_init =3D stellaris_gptm_init, + .class_init =3D stellaris_gptm_class_init, +}; + +static void stellaris_gptm_register_types(void) +{ + type_register_static(&stellaris_gptm_info); +} + +type_init(stellaris_gptm_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4ba0aca0676..a261b6f13bd 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -237,6 +237,7 @@ config STELLARIS select SSI_SD select STELLARIS_INPUT select STELLARIS_ENET # ethernet + select STELLARIS_GPTM # general purpose timer module select UNIMP =20 config STM32VLDISCOVERY diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index bac25117155..1e73da7e120 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -52,5 +52,8 @@ config SSE_COUNTER config SSE_TIMER bool =20 +config STELLARIS_GPTM + bool + config AVR_TIMER16 bool diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 1aa3cd22844..e67478a8f10 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -31,6 +31,7 @@ softmmu_ss.add(when: 'CONFIG_SH_TIMER', if_true: files('s= h_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) +softmmu_ss.add(when: 'CONFIG_STELLARIS_GPTM', if_true: files('stellaris-gp= tm.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_t= imer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c')) --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761674117770.1185007983242; Thu, 12 Aug 2021 02:47:54 -0700 (PDT) Received: from localhost ([::1]:44688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7JY-00032Z-Up for importer@patchew.org; Thu, 12 Aug 2021 05:47:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76c-0006Pa-80 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:43880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76V-00086G-RQ for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:29 -0400 Received: by mail-wm1-x32f.google.com with SMTP id k5-20020a05600c1c85b02902e699a4d20cso4055709wms.2 for ; Thu, 12 Aug 2021 02:34:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HhvybS859OcUptSSqet3BEb/fRS6bALyy8jbPeiYrJ4=; b=XA/zqOI17ahAlXSqhm0owgAV/izId0SqYJfOHJO6ZSbt+PpjUFiVHWjVU5mJ5cNafX FE89Vi0/WO8fPiCTMLBi+kslKG5y41sVjIbYnFU+T6suHNAPehb5amgyBAGU5YHA5k0H Bs3zwU2kgJ0Frkyc+VPTqAB370+p/MmOd7jRdOcnKFQ8/lqpBfWqM+8YI9upYvG6tzOM ewPHxvcD7G5K1XgNoRXx2N9h3jU6/YrIz41hqCYg65pOLpUmhs64s+L7HkHbMbL5tjGH 53QcYfZ+d5OgkK0C+ErdB+R5iwDbTG5VrcRvYOA1D96UMW9OOtAj6KAQrnEQD9BYtzMH cSxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HhvybS859OcUptSSqet3BEb/fRS6bALyy8jbPeiYrJ4=; b=seYhIriGcvkNXwsFCYJrn96MsrtsB8mHxqQ9PJ2OSSnt1Ae60zg8IP+pijaeb9Qw8+ eJxFiKR60P3AoUwlUj7DtJ6LM4eo9+uIbUrWYAY8OK9ErpDoPv96Dm2KHyu4K7hXNOVZ fiLe2dDDLy4z1B+mVv4nxSb8adTGBsYCioqHfBysGHwVJPDwXMj8EBIgyf/YeJfk5yF9 F4UbpnCGbMrzw/OhRyay1cFBtg1uAuBaHrD4gR1sqks5WjJHXmBoeuRoVE7gwETwaEj4 sTH4gjWfvGSYgXxofN7h0IqrKYfFKaP+Qs+IuBD5ibTL8VAZbsXKJmWGsVbk7hGxP/YE WgYg== X-Gm-Message-State: AOAM532jmMFPymg9pXMSnu+Z476mv2PE/4CDUlTGBhy/xUyp7tXdpJmk ZnKvVL3wlSBvMwj3wFkdo7NZgA== X-Google-Smtp-Source: ABdhPJxzWpirhQjdHhApTdnw3T7J4Qp0qwMqK/YKRA+yktx5EiBixk7Ix9MHKiswfI+KGDQilMb9cg== X-Received: by 2002:a7b:c144:: with SMTP id z4mr14184996wmi.55.1628760862280; Thu, 12 Aug 2021 02:34:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Date: Thu, 12 Aug 2021 10:33:55 +0100 Message-Id: <20210812093356.1946-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761675255100001 Content-Type: text/plain; charset="utf-8" The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell --- As noted in the comment, ideally we would convert the device to use ptimer for its downcounter, which supports frequency changes while the counter is running and would also allow reading the timer value. But I don't want to make and test that change to a minor timer device in a board model I wouldn't recommend anybody actually use; this series is long enough as it is... --- include/hw/timer/stellaris-gptm.h | 3 +++ hw/arm/stellaris.c | 12 +++++++++--- hw/timer/stellaris-gptm.c | 26 ++++++++++++++++++++++---- 3 files changed, 34 insertions(+), 7 deletions(-) diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris= -gptm.h index b8fa43c94bf..fde1fc6f0c7 100644 --- a/include/hw/timer/stellaris-gptm.h +++ b/include/hw/timer/stellaris-gptm.h @@ -13,6 +13,7 @@ #include "qom/object.h" #include "hw/sysbus.h" #include "hw/irq.h" +#include "hw/clock.h" =20 #define TYPE_STELLARIS_GPTM "stellaris-gptm" OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) @@ -22,6 +23,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) * + sysbus MMIO region 0: register bank * + sysbus IRQ 0: timer interrupt * + unnamed GPIO output 0: trigger output for the ADC + * + Clock input "clk": the 32-bit countdown timer runs at this speed */ struct gptm_state { SysBusDevice parent_obj; @@ -43,6 +45,7 @@ struct gptm_state { /* The timers have an alternate output used to trigger the ADC. */ qemu_irq trigger; qemu_irq irq; + Clock *clk; }; =20 #endif diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8c547f146a9..3e7d1dabad1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1090,9 +1090,15 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) } for (i =3D 0; i < 4; i++) { if (board->dc2 & (0x10000 << i)) { - dev =3D sysbus_create_simple(TYPE_STELLARIS_GPTM, - 0x40030000 + i * 0x1000, - qdev_get_gpio_in(nvic, timer_irq[i]= )); + SysBusDevice *sbd; + + dev =3D qdev_new(TYPE_STELLARIS_GPTM); + sbd =3D SYS_BUS_DEVICE(dev); + qdev_connect_clock_in(dev, "clk", + qdev_get_clock_out(ssys_dev, "SYSCLK")); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]= )); /* TODO: This is incorrect, but we get away with it because the ADC output is only ever pulsed. */ qdev_connect_gpio_out(dev, 0, adc); diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c index 7846fe5f84e..fd71c79be48 100644 --- a/hw/timer/stellaris-gptm.c +++ b/hw/timer/stellaris-gptm.c @@ -10,9 +10,10 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qapi/error.h" #include "migration/vmstate.h" +#include "hw/qdev-clock.h" #include "hw/timer/stellaris-gptm.h" -#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale= */ =20 static void gptm_update_irq(gptm_state *s) { @@ -39,7 +40,7 @@ static void gptm_reload(gptm_state *s, int n, int reset) /* 32-bit CountDown. */ uint32_t count; count =3D s->load[0] | (s->load[1] << 16); - tick +=3D (int64_t)count * system_clock_scale; + tick +=3D clock_ticks_to_ns(s->clk, count); } else if (s->config =3D=3D 1) { /* 32-bit RTC. 1Hz tick. */ tick +=3D NANOSECONDS_PER_SECOND; @@ -247,8 +248,8 @@ static const MemoryRegionOps gptm_ops =3D { =20 static const VMStateDescription vmstate_stellaris_gptm =3D { .name =3D "stellaris_gptm", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(config, gptm_state), VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), @@ -263,6 +264,7 @@ static const VMStateDescription vmstate_stellaris_gptm = =3D { VMSTATE_UINT32(rtc, gptm_state), VMSTATE_INT64_ARRAY(tick, gptm_state, 2), VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), + VMSTATE_CLOCK(clk, gptm_state), VMSTATE_END_OF_LIST() } }; @@ -281,11 +283,27 @@ static void stellaris_gptm_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); =20 s->opaque[0] =3D s->opaque[1] =3D s; + + /* + * TODO: in an ideal world we would model the effects of changing + * the input clock frequency while the countdown timer is active. + * The best way to do this would be to convert the device to use + * ptimer instead of hand-rolling its own timer. This would also + * make it easy to implement reading the current count from the + * TAR and TBR registers. + */ + s->clk =3D qdev_init_clock_in(dev, "clk", NULL, NULL, 0); } =20 static void stellaris_gptm_realize(DeviceState *dev, Error **errp) { gptm_state *s =3D STELLARIS_GPTM(dev); + + if (!clock_has_source(s->clk)) { + error_setg(errp, "stellaris-gptm: clk must be connected"); + return; + } + s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [0]); s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque= [1]); } --=20 2.20.1 From nobody Sun May 19 16:58:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628761985439623.0092627303441; Thu, 12 Aug 2021 02:53:05 -0700 (PDT) Received: from localhost ([::1]:58234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE7Oa-0003iD-Bw for importer@patchew.org; Thu, 12 Aug 2021 05:53:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE76d-0006Uv-FE for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:31 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:45704) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mE76W-000875-O8 for qemu-devel@nongnu.org; Thu, 12 Aug 2021 05:34:31 -0400 Received: by mail-wr1-x431.google.com with SMTP id v4so235623wro.12 for ; Thu, 12 Aug 2021 02:34:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JrO8pXzBjKu0CYeoFLRGkh6olNA2hx/ha44oSWqPp6c=; b=I3glhpa/FzBgLVPthKziZ6PuybZux2jd5E09mE2lu41sX4fmy4pORIOU9zZncIXGIQ ImPG+afXJfjB0fTZyQx0Novx9eDrHehiFW87W1Mmk/nG/ScwVBvx1KDhUkliW5YOe0mG GH5kQgkpXnLa0H1BkT+ecJU43o8fYYQqQIXmo23lRKmOsDMN07/bb2pBnqlITX8pfJYP B2sqgN8aPqGwvv3AotLWIxJpkMBi2R7ZrubsybPuo9KQ8ot5+Fkd6IP81KnXokhGkZul G+cL/qxzTwjgJO+2W4QEVlwa1t6M1FK/tfWe+HfpXgsgIrilAM9lfjkUvjBMkXuWNwBi 53Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JrO8pXzBjKu0CYeoFLRGkh6olNA2hx/ha44oSWqPp6c=; b=h7F0G5J7PHkpoVEfuI55V01NnP5iqkVy3jNm8dCdLdiKXI37NUe7pNlWd8LUB/WUWM Tc2XUysMe1ndBsvSbno5ycrN8reOdWzkP+4GDhB/MBUqef2Yd54hyS1e+H+UYr6Ox6Pm TDKEYIsdBMfDB5nLDEHtiRrzMsthM5IuBd3Qk8CnhQvA97AsxIMgIKEE5rDU2/hLpNdM 3Ex6LJGFVZqGeWSdznXNe6+WhIgxSQgsnq4nzxOeZfxtvSwQM4m/bNspXII7tKZTmkJ+ EEe+lr9D0yBfyANNcTfSJUbEwrx9EufU8V9Nd0Q47lEuKvArALcct71WClKayrDIIDf0 kGcA== X-Gm-Message-State: AOAM5330KSUWkhRgSueHviAY7LvrdSZPerEsNJAgKC4Owg6oXx4rZzrc N7WZt+aeTqyvP2z7cde2fVWIuQ== X-Google-Smtp-Source: ABdhPJw8HPKkx/GqNVmIxmc0mls4fnr2EtoknO1TwzjdoY8FBTOzjrL1ZbUSWjB1tW5F+kZ3unCp5Q== X-Received: by 2002:adf:ba4d:: with SMTP id t13mr2902037wrg.424.1628760863212; Thu, 12 Aug 2021 02:34:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 25/25] arm: Remove system_clock_scale global Date: Thu, 12 Aug 2021 10:33:56 +0100 Message-Id: <20210812093356.1946-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628761986225100001 Content-Type: text/plain; charset="utf-8" All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis --- include/hw/timer/armv7m_systick.h | 22 ---------------------- hw/arm/armsse.c | 17 +---------------- hw/arm/mps2.c | 2 -- hw/arm/msf2-soc.c | 2 -- hw/arm/netduino2.c | 2 -- hw/arm/netduinoplus2.c | 2 -- hw/arm/nrf51_soc.c | 2 -- hw/arm/stellaris.c | 7 ++++--- hw/arm/stm32vldiscovery.c | 2 -- hw/timer/armv7m_systick.c | 2 -- 10 files changed, 5 insertions(+), 55 deletions(-) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 38adf8d274e..ee09b138810 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -47,26 +47,4 @@ struct SysTickState { Clock *cpuclk; }; =20 -/* - * Multiplication factor to convert from system clock ticks to qemu timer - * ticks. This should be set (by board code, usually) to a value - * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency - * in Hz of the CPU. - * - * This value is used by the systick device when it is running in - * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE =3D=3D 1) to - * set how fast the timer should tick. - * - * TODO: we should refactor this so that rather than using a global - * we use a device property or something similar. This is complicated - * because (a) the property would need to be plumbed through from the - * board code down through various layers to the systick device - * and (b) the property needs to be modifiable after realize, because - * the stellaris board uses this to implement the behaviour where the - * guest can reprogram the PLL registers to downclock the CPU, and the - * systick device needs to react accordingly. Possibly this should - * be deferred until we have a good API for modelling clock trees. - */ -extern int system_clock_scale; - #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 70b52c3d4b9..aecdeb9815a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -689,17 +689,6 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } =20 -static void armsse_mainclk_update(void *opaque, ClockEvent event) -{ - ARMSSE *s =3D ARM_SSE(opaque); - - /* - * Set system_clock_scale from our Clock input; this is what - * controls the tick rate of the CPU SysTick timer. - */ - system_clock_scale =3D clock_ticks_to_ns(s->mainclk, 1); -} - static void armsse_init(Object *obj) { ARMSSE *s =3D ARM_SSE(obj); @@ -711,8 +700,7 @@ static void armsse_init(Object *obj) assert(info->sram_banks <=3D MAX_SRAM_BANKS); assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 - s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", - armsse_mainclk_update, s, ClockUpdate); + s->mainclk =3D qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0); s->s32kclk =3D qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); =20 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); @@ -1654,9 +1642,6 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * devices in the ARMSSE. */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); - - /* Set initial system_clock_scale from MAINCLK */ - armsse_mainclk_update(s, ClockUpdate); } =20 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 3671f49ad7b..4634aa1a1ca 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -439,8 +439,6 @@ static void mps2_common_init(MachineState *machine) qdev_get_gpio_in(armv7m, mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); } diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index dbc6d936a76..b5fe9f364d5 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -144,8 +144,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) return; } =20 - system_clock_scale =3D clock_ticks_to_ns(s->m3clk, 1); - for (i =3D 0; i < MSF2_NUM_UARTS; i++) { if (serial_hd(i)) { serial_mm_init(get_system_memory(), uart_addr[i], 2, diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index b5c0ba23ee5..3365da11bf7 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -39,8 +39,6 @@ static void netduino2_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index a5a8999cc8c..76cea8e4891 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -39,8 +39,6 @@ static void netduinoplus2_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e3e849a32b1..34da0d62f00 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -84,8 +84,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) * will always provide one). */ =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / HCLK_FRQ; - object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->contain= er), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 3e7d1dabad1..78827ace6b8 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -263,17 +263,18 @@ static bool ssys_use_rcc2(ssys_state *s) */ static void ssys_calculate_system_clock(ssys_state *s, bool propagate_cloc= k) { + int period_ns; /* * SYSDIV field specifies divisor: 0 =3D=3D /1, 1 =3D=3D /2, etc. Inp= ut * clock is 200MHz, which is a period of 5 ns. Dividing the clock * frequency by X is the same as multiplying the period by X. */ if (ssys_use_rcc2(s)) { - system_clock_scale =3D 5 * (((s->rcc2 >> 23) & 0x3f) + 1); + period_ns =3D 5 * (((s->rcc2 >> 23) & 0x3f) + 1); } else { - system_clock_scale =3D 5 * (((s->rcc >> 23) & 0xf) + 1); + period_ns =3D 5 * (((s->rcc >> 23) & 0xf) + 1); } - clock_set_ns(s->sysclk, system_clock_scale); + clock_set_ns(s->sysclk, period_ns); if (propagate_clock) { clock_propagate(s->sysclk); } diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 9b79004703b..04036da3ee0 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -42,8 +42,6 @@ static void stm32vldiscovery_init(MachineState *machine) DeviceState *dev; Clock *sysclk; =20 - system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; - /* This clock doesn't need migration because it is fixed-frequency */ sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(sysclk, SYSCLK_FRQ); diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index 39cca206cfd..9f92830968b 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -29,8 +29,6 @@ #define SYSCALIB_NOREF (1U << 31) #define SYSCALIB_SKEW (1U << 30) =20 -int system_clock_scale; - static void systick_set_period_from_clock(SysTickState *s) { /* --=20 2.20.1