From nobody Sun May 19 15:29:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628749449090543.1854706616693; Wed, 11 Aug 2021 23:24:09 -0700 (PDT) Received: from localhost ([::1]:58676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE48O-0000lh-1P for importer@patchew.org; Thu, 12 Aug 2021 02:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46J-0004xW-Ul; Thu, 12 Aug 2021 02:21:59 -0400 Received: from esa6.hc1455-7.c3s2.iphmx.com ([68.232.139.139]:6650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46H-00014F-BN; Thu, 12 Aug 2021 02:21:59 -0400 Received: from unknown (HELO yto-r3.gw.nic.fujitsu.com) ([218.44.52.219]) by esa6.hc1455-7.c3s2.iphmx.com with ESMTP; 12 Aug 2021 15:21:53 +0900 Received: from yto-m1.gw.nic.fujitsu.com (yto-nat-yto-m1.gw.nic.fujitsu.com [192.168.83.64]) by yto-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 3ADF06DB27; Thu, 12 Aug 2021 15:21:52 +0900 (JST) Received: from yto-om2.fujitsu.com (yto-om2.o.css.fujitsu.com [10.128.89.163]) by yto-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id 80BDCC9CCE; Thu, 12 Aug 2021 15:21:51 +0900 (JST) Received: from localhost.localdomain (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om2.fujitsu.com (Postfix) with ESMTP id 612344007B802; Thu, 12 Aug 2021 15:21:51 +0900 (JST) IronPort-SDR: vuq6E+nTZJwfP8Mh/kl1afXj8qf/CCTnRIVCz8IkEKt89+hMJymE4htmqE719MxjkZGMtrGxIF zVRRF1z2dAgxIQX/msdlfLLQnc7Z6yXoXqVsIckgaLBSfI7L4xvozKyuUih2CHVdm145sFzzOr OP9xeyTEg8Oqzlv0JlJSlw4p5aWhbK5JBDs0vnef+qOgTXnqqEh3CzVD2nPM/10CZHV1iaqtOw VAkTPiHOEmms+CmBtYfPd/TfoKbKvbnPWgWTM9O12FZ5ZOijwqgdkY3xINvRoItIym4yWZWqQq HNiqC9sj/PjeA6mPr6pBUkh/ X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="39964537" X-IronPort-AV: E=Sophos;i="5.84,315,1620658800"; d="scan'208";a="39964537" From: Shuuichirou Ishii To: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v4 1/3] target-arm: Add support for Fujitsu A64FX Date: Thu, 12 Aug 2021 15:04:38 +0900 Message-Id: <20210812060440.1330348-2-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> References: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.139.139; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa6.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628749451228100005 Content-Type: text/plain; charset="utf-8" Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector length= s. Signed-off-by: Shuuichirou Ishii Reviewed-by: Andrew Jones --- target/arm/cpu.c | 27 +++++++++++++++++++++++---- target/arm/cpu.h | 1 + target/arm/cpu64.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2866dd7658..162e46afc3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1345,15 +1345,34 @@ static void arm_cpu_finalizefn(Object *obj) #endif } =20 +static void a64fx_cpu_set_sve(ARMCPU *cpu) +{ + /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + bitmap_zero(cpu->sve_vq_map, ARM_MAX_VQ); + bitmap_zero(cpu->sve_vq_init, ARM_MAX_VQ); + set_bit(0, cpu->sve_vq_map); /* 128bit */ + set_bit(0, cpu->sve_vq_init); + set_bit(1, cpu->sve_vq_map); /* 256bit */ + set_bit(1, cpu->sve_vq_init); + set_bit(3, cpu->sve_vq_map); /* 512bit */ + set_bit(3, cpu->sve_vq_init); + + cpu->sve_max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; +} + void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) { Error *local_err =3D NULL; =20 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; + if (arm_feature(&cpu->env, ARM_FEATURE_A64FX)) { + a64fx_cpu_set_sve(cpu); + } else { + arm_cpu_sve_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d5..84ebca731a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2145,6 +2145,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + ARM_FEATURE_A64FX, /* Fujitsu A64FX processor */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c690318a9b..5e7e885f9d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -847,10 +847,52 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL); } =20 +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_A64FX); + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* TODO: Add A64FX specific HPC extension registers */ +} + static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, }; =20 --=20 2.27.0 From nobody Sun May 19 15:29:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628749436947723.9630074470099; Wed, 11 Aug 2021 23:23:56 -0700 (PDT) Received: from localhost ([::1]:57576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE48B-0008RP-VF for importer@patchew.org; Thu, 12 Aug 2021 02:23:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46J-0004xG-IV; Thu, 12 Aug 2021 02:21:59 -0400 Received: from esa2.hc1455-7.c3s2.iphmx.com ([207.54.90.48]:20526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46H-00014q-70; Thu, 12 Aug 2021 02:21:59 -0400 Received: from unknown (HELO yto-r3.gw.nic.fujitsu.com) ([218.44.52.219]) by esa2.hc1455-7.c3s2.iphmx.com with ESMTP; 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d="scan'208";a="39794798" From: Shuuichirou Ishii To: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v4 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Date: Thu, 12 Aug 2021 15:04:39 +0900 Message-Id: <20210812060440.1330348-3-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> References: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.54.90.48; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa2.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628749438554100001 Content-Type: text/plain; charset="utf-8" Add -cpu a64fx to use A64FX processor when -machine virt option is specifie= d. In addition, add a64fx to the Supported guest CPU types in the virt.rst doc= ument. Signed-off-by: Shuuichirou Ishii --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 59acf0eeaf..850787495b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 81eda46b0b..10286d3fd6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -200,6 +200,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; --=20 2.27.0 From nobody Sun May 19 15:29:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=fujitsu.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628749424939170.87314268925923; Wed, 11 Aug 2021 23:23:44 -0700 (PDT) Received: from localhost ([::1]:56472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mE47z-0007iI-63 for importer@patchew.org; Thu, 12 Aug 2021 02:23:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46J-0004xH-Lw; Thu, 12 Aug 2021 02:21:59 -0400 Received: from esa6.hc1455-7.c3s2.iphmx.com ([68.232.139.139]:35174) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mE46H-00015F-L1; Thu, 12 Aug 2021 02:21:59 -0400 Received: from unknown (HELO yto-r1.gw.nic.fujitsu.com) ([218.44.52.217]) by esa6.hc1455-7.c3s2.iphmx.com with ESMTP; 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d="scan'208";a="39964541" From: Shuuichirou Ishii To: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v4 3/3] tests/arm-cpu-features: Add A64FX processor related tests Date: Thu, 12 Aug 2021 15:04:40 +0900 Message-Id: <20210812060440.1330348-4-ishii.shuuichir@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> References: <20210812060440.1330348-1-ishii.shuuichir@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.139.139; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa6.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-devel@nongnu.org, ishii.shuuichir@fujitsu.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628749427274100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Shuuichirou Ishii --- tests/qtest/arm-cpu-features.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..6d704bc947 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -472,6 +472,8 @@ static void test_query_cpu_model_expansion(const void *= data) assert_has_feature_enabled(qts, "max", "sve128"); assert_has_feature_enabled(qts, "cortex-a57", "pmu"); assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); + assert_has_feature_enabled(qts, "a64fx", "pmu"); + assert_has_feature_enabled(qts, "a64fx", "aarch64"); =20 sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); --=20 2.27.0