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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=ma.mandourr@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Iooss , Mahmoud Mandour , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628603499466100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mahmoud Mandour Reviewed-by: Alex Benn=C3=A9e --- contrib/plugins/cache.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index a1e03ca882..a255e26e25 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -614,6 +614,9 @@ static void plugin_exit(qemu_plugin_id_t id, void *p) caches_free(dcaches); caches_free(icaches); =20 + g_free(dcache_locks); + g_free(icache_locks); + g_hash_table_destroy(miss_ht); } =20 --=20 2.25.1 From nobody Sun May 19 10:38:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628603588214939.5093176453888; Tue, 10 Aug 2021 06:53:08 -0700 (PDT) Received: from localhost ([::1]:60034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mDSBn-0006TD-32 for importer@patchew.org; Tue, 10 Aug 2021 09:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDS7p-0007XP-Lk for qemu-devel@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4OeyL5avmNVOjpFxGDSZQyOpcaoDi34m5YhQCj2SVog=; b=lyUUb699oz9i/Je9EOYnFCQFfFz1IloprRW0ZC/CEfdvfH8MBTKe53yfjG86QkOeDQ Rp8wKW4UTZeyzzYu/gi0qt88ge/1v1ZBJXL5eBOI1dVwM2ki7qbQ1HbZ5y0c3zihQUdm P+3TtkzQRfQm4kPQVWuxx/qvDpRxCNFMqqymKN4HAfHHusEO3I3AAeYYiAXiWlFPRvPM r3eFZgA/Yw2/7qLeXu9b96y1GE5HVCna/3B1dg9VVda1wrBPyAXZBgvE2k6QZ3VO+fMr pvUSHQzItC4T1OM8NsCVbOluWm2jhCxbbuWBgESChVa9+Ky4COsYaGdG/4k64sTsinlC 1dkw== X-Gm-Message-State: AOAM530BX9HtilyqTFMI0IyM8x8EEpIuF6H6zjBbfspbqR76c8WZT3xH dDqvxRwRanCxJ+i7qHn2Y/c6mRfJEJw= X-Google-Smtp-Source: ABdhPJy074RRlub/FfmEyfQn4aol3FF/kFzegSiIyKKweCrKSHT/3LsKYFJtt2qY/R20HtmuXcu3Bg== X-Received: by 2002:a05:600c:ad8:: with SMTP id c24mr4820533wmr.28.1628603336884; Tue, 10 Aug 2021 06:48:56 -0700 (PDT) From: Mahmoud Mandour To: qemu-devel@nongnu.org Subject: [PATCH 2/5] plugins/cache: implement unified L2 cache emulation Date: Tue, 10 Aug 2021 15:48:41 +0200 Message-Id: <20210810134844.166490-3-ma.mandourr@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210810134844.166490-1-ma.mandourr@gmail.com> References: <20210810134844.166490-1-ma.mandourr@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=ma.mandourr@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Iooss , Mahmoud Mandour , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628603589828100001 Content-Type: text/plain; charset="utf-8" This adds an implementation of a simple L2 configuration, in which a unified L2 cache (stores both blocks of instructions and data) is maintained for each core separately, with no inter-core interaction taken in account. The L2 cache is used as a backup for L1 and is only accessed if the wanted block does not exist in L1. In terms of multi-threaded user-space emulation, the same approximation of L1 is done, a static number of caches is maintained, and each and every memory access initiated by a thread will have to go through one of the available caches. An atomic increment is used to maintain the number of L2 misses per instruction. The default cache parameters of L2 caches is: 2MB cache size 16-way associativity 64-byte blocks Signed-off-by: Mahmoud Mandour Reviewed-by: Alex Benn=C3=A9e --- contrib/plugins/cache.c | 256 +++++++++++++++++++++++++++------------- 1 file changed, 175 insertions(+), 81 deletions(-) diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index a255e26e25..908c967a09 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -82,8 +82,9 @@ typedef struct { char *disas_str; const char *symbol; uint64_t addr; - uint64_t dmisses; - uint64_t imisses; + uint64_t l1_dmisses; + uint64_t l1_imisses; + uint64_t l2_misses; } InsnData; =20 void (*update_hit)(Cache *cache, int set, int blk); @@ -93,15 +94,20 @@ void (*metadata_init)(Cache *cache); void (*metadata_destroy)(Cache *cache); =20 static int cores; -static Cache **dcaches, **icaches; +static Cache **l1_dcaches, **l1_icaches; +static Cache **l2_ucaches; =20 -static GMutex *dcache_locks; -static GMutex *icache_locks; +static GMutex *l1_dcache_locks; +static GMutex *l1_icache_locks; +static GMutex *l2_ucache_locks; =20 -static uint64_t all_dmem_accesses; -static uint64_t all_imem_accesses; -static uint64_t all_imisses; -static uint64_t all_dmisses; +static uint64_t l1_dmem_accesses; +static uint64_t l1_imem_accesses; +static uint64_t l1_imisses; +static uint64_t l1_dmisses; + +static uint64_t l2_mem_accesses; +static uint64_t l2_misses; =20 static int pow_of_two(int num) { @@ -382,6 +388,7 @@ static void vcpu_mem_access(unsigned int vcpu_index, qe= mu_plugin_meminfo_t info, struct qemu_plugin_hwaddr *hwaddr; int cache_idx; InsnData *insn; + bool hit_in_l1; =20 hwaddr =3D qemu_plugin_get_hwaddr(info, vaddr); if (hwaddr && qemu_plugin_hwaddr_is_io(hwaddr)) { @@ -391,14 +398,29 @@ static void vcpu_mem_access(unsigned int vcpu_index, = qemu_plugin_meminfo_t info, effective_addr =3D hwaddr ? qemu_plugin_hwaddr_phys_addr(hwaddr) : vad= dr; cache_idx =3D vcpu_index % cores; =20 - g_mutex_lock(&dcache_locks[cache_idx]); - if (!access_cache(dcaches[cache_idx], effective_addr)) { + g_mutex_lock(&l1_dcache_locks[cache_idx]); + hit_in_l1 =3D access_cache(l1_dcaches[cache_idx], effective_addr); + if (!hit_in_l1) { + insn =3D (InsnData *) userdata; + __atomic_fetch_add(&insn->l1_dmisses, 1, __ATOMIC_SEQ_CST); + l1_dcaches[cache_idx]->misses++; + } + l1_dcaches[cache_idx]->accesses++; + g_mutex_unlock(&l1_dcache_locks[cache_idx]); + + if (hit_in_l1) { + /* No need to access L2 */ + return; + } + + g_mutex_lock(&l2_ucache_locks[cache_idx]); + if (!access_cache(l2_ucaches[cache_idx], effective_addr)) { insn =3D (InsnData *) userdata; - __atomic_fetch_add(&insn->dmisses, 1, __ATOMIC_SEQ_CST); - dcaches[cache_idx]->misses++; + __atomic_fetch_add(&insn->l2_misses, 1, __ATOMIC_SEQ_CST); + l2_ucaches[cache_idx]->misses++; } - dcaches[cache_idx]->accesses++; - g_mutex_unlock(&dcache_locks[cache_idx]); + l2_ucaches[cache_idx]->accesses++; + g_mutex_unlock(&l2_ucache_locks[cache_idx]); } =20 static void vcpu_insn_exec(unsigned int vcpu_index, void *userdata) @@ -406,18 +428,34 @@ static void vcpu_insn_exec(unsigned int vcpu_index, v= oid *userdata) uint64_t insn_addr; InsnData *insn; int cache_idx; + bool hit_in_l1; =20 insn_addr =3D ((InsnData *) userdata)->addr; =20 cache_idx =3D vcpu_index % cores; - g_mutex_lock(&icache_locks[cache_idx]); - if (!access_cache(icaches[cache_idx], insn_addr)) { + g_mutex_lock(&l1_icache_locks[cache_idx]); + hit_in_l1 =3D access_cache(l1_icaches[cache_idx], insn_addr); + if (!hit_in_l1) { + insn =3D (InsnData *) userdata; + __atomic_fetch_add(&insn->l1_imisses, 1, __ATOMIC_SEQ_CST); + l1_icaches[cache_idx]->misses++; + } + l1_icaches[cache_idx]->accesses++; + g_mutex_unlock(&l1_icache_locks[cache_idx]); + + if (hit_in_l1) { + /* No need to access L2 */ + return; + } + + g_mutex_lock(&l2_ucache_locks[cache_idx]); + if (!access_cache(l2_ucaches[cache_idx], insn_addr)) { insn =3D (InsnData *) userdata; - __atomic_fetch_add(&insn->imisses, 1, __ATOMIC_SEQ_CST); - icaches[cache_idx]->misses++; + __atomic_fetch_add(&insn->l2_misses, 1, __ATOMIC_SEQ_CST); + l2_ucaches[cache_idx]->misses++; } - icaches[cache_idx]->accesses++; - g_mutex_unlock(&icache_locks[cache_idx]); + l2_ucaches[cache_idx]->accesses++; + g_mutex_unlock(&l2_ucache_locks[cache_idx]); } =20 static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) @@ -493,30 +531,28 @@ static void caches_free(Cache **caches) } } =20 -static int dcmp(gconstpointer a, gconstpointer b) -{ - InsnData *insn_a =3D (InsnData *) a; - InsnData *insn_b =3D (InsnData *) b; - - return insn_a->dmisses < insn_b->dmisses ? 1 : -1; -} - -static void append_stats_line(GString *line, uint64_t daccess, uint64_t dm= isses, - uint64_t iaccess, uint64_t imisses) +static void append_stats_line(GString *line, uint64_t l1_daccess, + uint64_t l1_dmisses, uint64_t l1_iaccess, + uint64_t l1_imisses, uint64_t l2_access, + uint64_t l2_misses) { - double dmiss_rate, imiss_rate; + double l1_dmiss_rate, l1_imiss_rate, l2_miss_rate; =20 - dmiss_rate =3D ((double) dmisses) / (daccess) * 100.0; - imiss_rate =3D ((double) imisses) / (iaccess) * 100.0; + l1_dmiss_rate =3D ((double) l1_dmisses) / (l1_daccess) * 100.0; + l1_imiss_rate =3D ((double) l1_imisses) / (l1_iaccess) * 100.0; + l2_miss_rate =3D ((double) l2_misses) / (l2_access) * 100.0; =20 g_string_append_printf(line, "%-14lu %-12lu %9.4lf%% %-14lu %-12lu" - " %9.4lf%%\n", - daccess, - dmisses, - daccess ? dmiss_rate : 0.0, - iaccess, - imisses, - iaccess ? imiss_rate : 0.0); + " %9.4lf%% %-12lu %-11lu %10.4lf%%\n", + l1_daccess, + l1_dmisses, + l1_daccess ? l1_dmiss_rate : 0.0, + l1_iaccess, + l1_imisses, + l1_iaccess ? l1_imiss_rate : 0.0, + l2_access, + l2_misses, + l2_access ? l2_miss_rate : 0.0); } =20 static void sum_stats(void) @@ -525,43 +561,66 @@ static void sum_stats(void) =20 g_assert(cores > 1); for (i =3D 0; i < cores; i++) { - all_imisses +=3D icaches[i]->misses; - all_dmisses +=3D dcaches[i]->misses; - all_imem_accesses +=3D icaches[i]->accesses; - all_dmem_accesses +=3D dcaches[i]->accesses; + l1_imisses +=3D l1_icaches[i]->misses; + l1_dmisses +=3D l1_dcaches[i]->misses; + l1_imem_accesses +=3D l1_icaches[i]->accesses; + l1_dmem_accesses +=3D l1_dcaches[i]->accesses; + + l2_misses +=3D l2_ucaches[i]->misses; + l2_mem_accesses +=3D l2_ucaches[i]->accesses; } } =20 +static int dcmp(gconstpointer a, gconstpointer b) +{ + InsnData *insn_a =3D (InsnData *) a; + InsnData *insn_b =3D (InsnData *) b; + + return insn_a->l1_dmisses < insn_b->l1_dmisses ? 1 : -1; +} + static int icmp(gconstpointer a, gconstpointer b) { InsnData *insn_a =3D (InsnData *) a; InsnData *insn_b =3D (InsnData *) b; =20 - return insn_a->imisses < insn_b->imisses ? 1 : -1; + return insn_a->l1_imisses < insn_b->l1_imisses ? 1 : -1; +} + +static int l2_cmp(gconstpointer a, gconstpointer b) +{ + InsnData *insn_a =3D (InsnData *) a; + InsnData *insn_b =3D (InsnData *) b; + + return insn_a->l2_misses < insn_b->l2_misses ? 1 : -1; } =20 static void log_stats(void) { int i; - Cache *icache, *dcache; + Cache *icache, *dcache, *l2_cache; =20 g_autoptr(GString) rep =3D g_string_new("core #, data accesses, data m= isses," " dmiss rate, insn accesses," - " insn misses, imiss rate\n"); + " insn misses, imiss rate," + " l2 accesses, l2 misses," + " l2 miss rate\n"); =20 for (i =3D 0; i < cores; i++) { g_string_append_printf(rep, "%-8d", i); - dcache =3D dcaches[i]; - icache =3D icaches[i]; + dcache =3D l1_dcaches[i]; + icache =3D l1_icaches[i]; + l2_cache =3D l2_ucaches[i]; append_stats_line(rep, dcache->accesses, dcache->misses, - icache->accesses, icache->misses); + icache->accesses, icache->misses, l2_cache->accesses, + l2_cache->misses); } =20 if (cores > 1) { sum_stats(); g_string_append_printf(rep, "%-8s", "sum"); - append_stats_line(rep, all_dmem_accesses, all_dmisses, - all_imem_accesses, all_imisses); + append_stats_line(rep, l1_dmem_accesses, l1_dmisses, + l1_imem_accesses, l1_imisses, l2_mem_accesses, l2_misses); } =20 g_string_append(rep, "\n"); @@ -585,7 +644,7 @@ static void log_top_insns(void) if (insn->symbol) { g_string_append_printf(rep, " (%s)", insn->symbol); } - g_string_append_printf(rep, ", %ld, %s\n", insn->dmisses, + g_string_append_printf(rep, ", %ld, %s\n", insn->l1_dmisses, insn->disas_str); } =20 @@ -598,7 +657,20 @@ static void log_top_insns(void) if (insn->symbol) { g_string_append_printf(rep, " (%s)", insn->symbol); } - g_string_append_printf(rep, ", %ld, %s\n", insn->imisses, + g_string_append_printf(rep, ", %ld, %s\n", insn->l1_imisses, + insn->disas_str); + } + + miss_insns =3D g_list_sort(miss_insns, l2_cmp); + g_string_append_printf(rep, "%s", "\naddress, L2 misses, instruction\n= "); + + for (curr =3D miss_insns, i =3D 0; curr && i < limit; i++, curr =3D cu= rr->next) { + insn =3D (InsnData *) curr->data; + g_string_append_printf(rep, "0x%" PRIx64, insn->addr); + if (insn->symbol) { + g_string_append_printf(rep, " (%s)", insn->symbol); + } + g_string_append_printf(rep, ", %ld, %s\n", insn->l2_misses, insn->disas_str); } =20 @@ -611,11 +683,13 @@ static void plugin_exit(qemu_plugin_id_t id, void *p) log_stats(); log_top_insns(); =20 - caches_free(dcaches); - caches_free(icaches); + caches_free(l1_dcaches); + caches_free(l1_icaches); + caches_free(l2_ucaches); =20 - g_free(dcache_locks); - g_free(icache_locks); + g_free(l1_dcache_locks); + g_free(l1_icache_locks); + g_free(l2_ucache_locks); =20 g_hash_table_destroy(miss_ht); } @@ -647,19 +721,24 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qe= mu_info_t *info, int argc, char **argv) { int i; - int iassoc, iblksize, icachesize; - int dassoc, dblksize, dcachesize; + int l1_iassoc, l1_iblksize, l1_icachesize; + int l1_dassoc, l1_dblksize, l1_dcachesize; + int l2_assoc, l2_blksize, l2_cachesize; =20 limit =3D 32; sys =3D info->system_emulation; =20 - dassoc =3D 8; - dblksize =3D 64; - dcachesize =3D dblksize * dassoc * 32; + l1_dassoc =3D 8; + l1_dblksize =3D 64; + l1_dcachesize =3D l1_dblksize * l1_dassoc * 32; + + l1_iassoc =3D 8; + l1_iblksize =3D 64; + l1_icachesize =3D l1_iblksize * l1_iassoc * 32; =20 - iassoc =3D 8; - iblksize =3D 64; - icachesize =3D iblksize * iassoc * 32; + l2_assoc =3D 16; + l2_blksize =3D 64; + l2_cachesize =3D l2_assoc * l2_blksize * 2048; =20 policy =3D LRU; =20 @@ -668,21 +747,27 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qe= mu_info_t *info, for (i =3D 0; i < argc; i++) { char *opt =3D argv[i]; if (g_str_has_prefix(opt, "iblksize=3D")) { - iblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); + l1_iblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); } else if (g_str_has_prefix(opt, "iassoc=3D")) { - iassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); + l1_iassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); } else if (g_str_has_prefix(opt, "icachesize=3D")) { - icachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); + l1_icachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); } else if (g_str_has_prefix(opt, "dblksize=3D")) { - dblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); + l1_dblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); } else if (g_str_has_prefix(opt, "dassoc=3D")) { - dassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); + l1_dassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); } else if (g_str_has_prefix(opt, "dcachesize=3D")) { - dcachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); + l1_dcachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); } else if (g_str_has_prefix(opt, "limit=3D")) { limit =3D g_ascii_strtoll(opt + 6, NULL, 10); } else if (g_str_has_prefix(opt, "cores=3D")) { cores =3D g_ascii_strtoll(opt + 6, NULL, 10); + } else if (g_str_has_prefix(opt, "l2cachesize=3D")) { + l2_cachesize =3D g_ascii_strtoll(opt + 6, NULL, 10); + } else if (g_str_has_prefix(opt, "l2blksize=3D")) { + l2_blksize =3D g_ascii_strtoll(opt + 6, NULL, 10); + } else if (g_str_has_prefix(opt, "l2assoc=3D")) { + l2_assoc =3D g_ascii_strtoll(opt + 6, NULL, 10); } else if (g_str_has_prefix(opt, "evict=3D")) { gchar *p =3D opt + 6; if (g_strcmp0(p, "rand") =3D=3D 0) { @@ -703,24 +788,33 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qe= mu_info_t *info, =20 policy_init(); =20 - dcaches =3D caches_init(dblksize, dassoc, dcachesize); - if (!dcaches) { - const char *err =3D cache_config_error(dblksize, dassoc, dcachesiz= e); + l1_dcaches =3D caches_init(l1_dblksize, l1_dassoc, l1_dcachesize); + if (!l1_dcaches) { + const char *err =3D cache_config_error(l1_dblksize, l1_dassoc, l1_= dcachesize); fprintf(stderr, "dcache cannot be constructed from given parameter= s\n"); fprintf(stderr, "%s\n", err); return -1; } =20 - icaches =3D caches_init(iblksize, iassoc, icachesize); - if (!icaches) { - const char *err =3D cache_config_error(iblksize, iassoc, icachesiz= e); + l1_icaches =3D caches_init(l1_iblksize, l1_iassoc, l1_icachesize); + if (!l1_icaches) { + const char *err =3D cache_config_error(l1_iblksize, l1_iassoc, l1_= icachesize); fprintf(stderr, "icache cannot be constructed from given parameter= s\n"); fprintf(stderr, "%s\n", err); return -1; } =20 - dcache_locks =3D g_new0(GMutex, cores); - icache_locks =3D g_new0(GMutex, cores); + l2_ucaches =3D caches_init(l2_blksize, l2_assoc, l2_cachesize); + if (!l2_ucaches) { + const char *err =3D cache_config_error(l2_blksize, l2_assoc, l2_ca= chesize); + fprintf(stderr, "L2 cache cannot be constructed from given paramet= ers\n"); + fprintf(stderr, "%s\n", err); + return -1; + } + + l1_dcache_locks =3D g_new0(GMutex, cores); + l1_icache_locks =3D g_new0(GMutex, cores); + l2_ucache_locks =3D g_new0(GMutex, cores); =20 qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans); qemu_plugin_register_atexit_cb(id, plugin_exit, NULL); --=20 2.25.1 From nobody Sun May 19 10:38:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628603729062177.91483709473778; Tue, 10 Aug 2021 06:55:29 -0700 (PDT) Received: from localhost ([::1]:36464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mDSE3-0001J6-Vn for importer@patchew.org; Tue, 10 Aug 2021 09:55:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDS7p-0007Xo-TO for qemu-devel@nongnu.org; Tue, 10 Aug 2021 09:49:01 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:51070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mDS7n-0008KA-Kc for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=ma.mandourr@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Iooss , Mahmoud Mandour , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628603730601100001 Content-Type: text/plain; charset="utf-8" This way of handling args is more lenient and sets a better framework to parse boolean command line arguments. Signed-off-by: Mahmoud Mandour --- contrib/plugins/cache.c | 57 ++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index 908c967a09..ff325beb9f 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -11,6 +11,8 @@ =20 #include =20 +#define STRTOLL(x) g_ascii_strtoll(x, NULL, 10) + QEMU_PLUGIN_EXPORT int qemu_plugin_version =3D QEMU_PLUGIN_VERSION; =20 static enum qemu_plugin_mem_rw rw =3D QEMU_PLUGIN_MEM_RW; @@ -746,35 +748,36 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qe= mu_info_t *info, =20 for (i =3D 0; i < argc; i++) { char *opt =3D argv[i]; - if (g_str_has_prefix(opt, "iblksize=3D")) { - l1_iblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); - } else if (g_str_has_prefix(opt, "iassoc=3D")) { - l1_iassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); - } else if (g_str_has_prefix(opt, "icachesize=3D")) { - l1_icachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); - } else if (g_str_has_prefix(opt, "dblksize=3D")) { - l1_dblksize =3D g_ascii_strtoll(opt + 9, NULL, 10); - } else if (g_str_has_prefix(opt, "dassoc=3D")) { - l1_dassoc =3D g_ascii_strtoll(opt + 7, NULL, 10); - } else if (g_str_has_prefix(opt, "dcachesize=3D")) { - l1_dcachesize =3D g_ascii_strtoll(opt + 11, NULL, 10); - } else if (g_str_has_prefix(opt, "limit=3D")) { - limit =3D g_ascii_strtoll(opt + 6, NULL, 10); - } else if (g_str_has_prefix(opt, "cores=3D")) { - cores =3D g_ascii_strtoll(opt + 6, NULL, 10); - } else if (g_str_has_prefix(opt, "l2cachesize=3D")) { - l2_cachesize =3D g_ascii_strtoll(opt + 6, NULL, 10); - } else if (g_str_has_prefix(opt, "l2blksize=3D")) { - l2_blksize =3D g_ascii_strtoll(opt + 6, NULL, 10); - } else if (g_str_has_prefix(opt, "l2assoc=3D")) { - l2_assoc =3D g_ascii_strtoll(opt + 6, NULL, 10); - } else if (g_str_has_prefix(opt, "evict=3D")) { - gchar *p =3D opt + 6; - if (g_strcmp0(p, "rand") =3D=3D 0) { + g_autofree char **tokens =3D g_strsplit(opt, "=3D", 2); + + if (g_strcmp0(tokens[0], "iblksize") =3D=3D 0) { + l1_iblksize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "iassoc") =3D=3D 0) { + l1_iassoc =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "icachesize") =3D=3D 0) { + l1_icachesize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "dblksize") =3D=3D 0) { + l1_dblksize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "dassoc") =3D=3D 0) { + l1_dassoc =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "dcachesize") =3D=3D 0) { + l1_dcachesize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "limit") =3D=3D 0) { + limit =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "cores") =3D=3D 0) { + cores =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "l2cachesize") =3D=3D 0) { + l2_cachesize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "l2blksize") =3D=3D 0) { + l2_blksize =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "l2assoc") =3D=3D 0) { + l2_assoc =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "evict") =3D=3D 0) { + if (g_strcmp0(tokens[1], "rand") =3D=3D 0) { policy =3D RAND; - } else if (g_strcmp0(p, "lru") =3D=3D 0) { + } else if (g_strcmp0(tokens[1], "lru") =3D=3D 0) { policy =3D LRU; - } else if (g_strcmp0(p, "fifo") =3D=3D 0) { + } else if (g_strcmp0(tokens[1], "fifo") =3D=3D 0) { policy =3D FIFO; } else { fprintf(stderr, "invalid eviction policy: %s\n", opt); --=20 2.25.1 From nobody Sun May 19 10:38:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628603450673865.2787705868069; Tue, 10 Aug 2021 06:50:50 -0700 (PDT) Received: from localhost ([::1]:54004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mDS9Z-0002KR-Hv for importer@patchew.org; Tue, 10 Aug 2021 09:50:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDS7s-0007cq-FG for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=ma.mandourr@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Iooss , Mahmoud Mandour , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628603452611100001 Content-Type: text/plain; charset="utf-8" By default L2 is not enabled and is enabled by either using the newly-introduced "l2" boolean argument, or by setting any of the L2 cache parameters using args. On specifying "l2=3Don", the default cache configuration is used. Signed-off-by: Mahmoud Mandour --- contrib/plugins/cache.c | 76 +++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 22 deletions(-) diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index ff325beb9f..b9226e7c40 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -97,6 +97,8 @@ void (*metadata_destroy)(Cache *cache); =20 static int cores; static Cache **l1_dcaches, **l1_icaches; + +static bool use_l2; static Cache **l2_ucaches; =20 static GMutex *l1_dcache_locks; @@ -410,7 +412,7 @@ static void vcpu_mem_access(unsigned int vcpu_index, qe= mu_plugin_meminfo_t info, l1_dcaches[cache_idx]->accesses++; g_mutex_unlock(&l1_dcache_locks[cache_idx]); =20 - if (hit_in_l1) { + if (hit_in_l1 || !use_l2) { /* No need to access L2 */ return; } @@ -445,7 +447,7 @@ static void vcpu_insn_exec(unsigned int vcpu_index, voi= d *userdata) l1_icaches[cache_idx]->accesses++; g_mutex_unlock(&l1_icache_locks[cache_idx]); =20 - if (hit_in_l1) { + if (hit_in_l1 || !use_l2) { /* No need to access L2 */ return; } @@ -542,19 +544,25 @@ static void append_stats_line(GString *line, uint64_t= l1_daccess, =20 l1_dmiss_rate =3D ((double) l1_dmisses) / (l1_daccess) * 100.0; l1_imiss_rate =3D ((double) l1_imisses) / (l1_iaccess) * 100.0; - l2_miss_rate =3D ((double) l2_misses) / (l2_access) * 100.0; =20 g_string_append_printf(line, "%-14lu %-12lu %9.4lf%% %-14lu %-12lu" - " %9.4lf%% %-12lu %-11lu %10.4lf%%\n", + " %9.4lf%%", l1_daccess, l1_dmisses, l1_daccess ? l1_dmiss_rate : 0.0, l1_iaccess, l1_imisses, - l1_iaccess ? l1_imiss_rate : 0.0, - l2_access, - l2_misses, - l2_access ? l2_miss_rate : 0.0); + l1_iaccess ? l1_imiss_rate : 0.0); + + if (use_l2) { + l2_miss_rate =3D ((double) l2_misses) / (l2_access) * 100.0; + g_string_append_printf(line, " %-12lu %-11lu %10.4lf%%", + l2_access, + l2_misses, + l2_access ? l2_miss_rate : 0.0); + } + + g_string_append(line, "\n"); } =20 static void sum_stats(void) @@ -568,8 +576,10 @@ static void sum_stats(void) l1_imem_accesses +=3D l1_icaches[i]->accesses; l1_dmem_accesses +=3D l1_dcaches[i]->accesses; =20 - l2_misses +=3D l2_ucaches[i]->misses; - l2_mem_accesses +=3D l2_ucaches[i]->accesses; + if (use_l2) { + l2_misses +=3D l2_ucaches[i]->misses; + l2_mem_accesses +=3D l2_ucaches[i]->accesses; + } } } =20 @@ -604,25 +614,31 @@ static void log_stats(void) =20 g_autoptr(GString) rep =3D g_string_new("core #, data accesses, data m= isses," " dmiss rate, insn accesses," - " insn misses, imiss rate," - " l2 accesses, l2 misses," - " l2 miss rate\n"); + " insn misses, imiss rate"); + + if (use_l2) { + g_string_append(rep, ", l2 accesses, l2 misses, l2 miss rate"); + } + + g_string_append(rep, "\n"); =20 for (i =3D 0; i < cores; i++) { g_string_append_printf(rep, "%-8d", i); dcache =3D l1_dcaches[i]; icache =3D l1_icaches[i]; - l2_cache =3D l2_ucaches[i]; + l2_cache =3D use_l2 ? l2_ucaches[i] : NULL; append_stats_line(rep, dcache->accesses, dcache->misses, - icache->accesses, icache->misses, l2_cache->accesses, - l2_cache->misses); + icache->accesses, icache->misses, + l2_cache ? l2_cache->accesses : 0, + l2_cache ? l2_cache->misses : 0); } =20 if (cores > 1) { sum_stats(); g_string_append_printf(rep, "%-8s", "sum"); append_stats_line(rep, l1_dmem_accesses, l1_dmisses, - l1_imem_accesses, l1_imisses, l2_mem_accesses, l2_misses); + l1_imem_accesses, l1_imisses, + l2_cache ? l2_mem_accesses : 0, l2_cache ? l2_misses : 0); } =20 g_string_append(rep, "\n"); @@ -663,6 +679,10 @@ static void log_top_insns(void) insn->disas_str); } =20 + if (!use_l2) { + goto finish; + } + miss_insns =3D g_list_sort(miss_insns, l2_cmp); g_string_append_printf(rep, "%s", "\naddress, L2 misses, instruction\n= "); =20 @@ -676,6 +696,7 @@ static void log_top_insns(void) insn->disas_str); } =20 +finish: qemu_plugin_outs(rep->str); g_list_free(miss_insns); } @@ -687,11 +708,14 @@ static void plugin_exit(qemu_plugin_id_t id, void *p) =20 caches_free(l1_dcaches); caches_free(l1_icaches); - caches_free(l2_ucaches); =20 g_free(l1_dcache_locks); g_free(l1_icache_locks); - g_free(l2_ucache_locks); + + if (use_l2) { + caches_free(l2_ucaches); + g_free(l2_ucache_locks); + } =20 g_hash_table_destroy(miss_ht); } @@ -767,11 +791,19 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qe= mu_info_t *info, } else if (g_strcmp0(tokens[0], "cores") =3D=3D 0) { cores =3D STRTOLL(tokens[1]); } else if (g_strcmp0(tokens[0], "l2cachesize") =3D=3D 0) { + use_l2 =3D true; l2_cachesize =3D STRTOLL(tokens[1]); } else if (g_strcmp0(tokens[0], "l2blksize") =3D=3D 0) { + use_l2 =3D true; l2_blksize =3D STRTOLL(tokens[1]); } else if (g_strcmp0(tokens[0], "l2assoc") =3D=3D 0) { + use_l2 =3D true; l2_assoc =3D STRTOLL(tokens[1]); + } else if (g_strcmp0(tokens[0], "l2") =3D=3D 0) { + if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &use_l2)) { + fprintf(stderr, "boolean argument parsing failed: %s\n", o= pt); + return -1; + } } else if (g_strcmp0(tokens[0], "evict") =3D=3D 0) { if (g_strcmp0(tokens[1], "rand") =3D=3D 0) { policy =3D RAND; @@ -807,8 +839,8 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu= _info_t *info, return -1; } =20 - l2_ucaches =3D caches_init(l2_blksize, l2_assoc, l2_cachesize); - if (!l2_ucaches) { + l2_ucaches =3D use_l2 ? caches_init(l2_blksize, l2_assoc, l2_cachesize= ) : NULL; + if (!l2_ucaches && use_l2) { const char *err =3D cache_config_error(l2_blksize, l2_assoc, l2_ca= chesize); fprintf(stderr, "L2 cache cannot be constructed from given paramet= ers\n"); fprintf(stderr, "%s\n", err); @@ -817,7 +849,7 @@ int qemu_plugin_install(qemu_plugin_id_t id, const qemu= _info_t *info, =20 l1_dcache_locks =3D g_new0(GMutex, cores); l1_icache_locks =3D g_new0(GMutex, cores); - l2_ucache_locks =3D g_new0(GMutex, cores); + l2_ucache_locks =3D use_l2 ? g_new0(GMutex, cores) : NULL; =20 qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans); qemu_plugin_register_atexit_cb(id, plugin_exit, NULL); --=20 2.25.1 From nobody Sun May 19 10:38:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 10 Aug 2021 06:49:00 -0700 (PDT) From: Mahmoud Mandour To: qemu-devel@nongnu.org Subject: [PATCH 5/5] docs/tcg-plugins: add L2 arguments to cache docs Date: Tue, 10 Aug 2021 15:48:44 +0200 Message-Id: <20210810134844.166490-6-ma.mandourr@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210810134844.166490-1-ma.mandourr@gmail.com> References: <20210810134844.166490-1-ma.mandourr@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=ma.mandourr@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Iooss , Mahmoud Mandour , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628603436381100005 Content-Type: text/plain; charset="utf-8" cache plugin now allows optional L2 per-core cache emulation that can be configured through plugin arguments, this commit adds this functionality to the docs. While I'm at it, I editted the bullet point for cache plugin to say: contrib/plugins/cache.c instead of contrib/plugins/cache to match other plugins. Signed-off-by: Mahmoud Mandour --- docs/devel/tcg-plugins.rst | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index fcc460bf7b..ee3fab75bd 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -360,10 +360,11 @@ which will output an execution trace following this s= tructure:: 0, 0xd34, 0xf9c8f000, "bl #0x10c8" 0, 0x10c8, 0xfff96c43, "ldr r3, [r0, #0x44]", load, 0x200000e4, RAM =20 -- contrib/plugins/cache +- contrib/plugins/cache.c =20 -Cache modelling plugin that measures the performance of a given cache -configuration when a given working set is run:: +Cache modelling plugin that measures the performance of a given L1 cache +configuration, and optionally a unified L2 per-core cache when a given wor= king +set is run:: =20 qemu-x86_64 -plugin ./contrib/plugins/libcache.so \ -d plugin -D cache.log ./tests/tcg/x86_64-linux-user/float_convs @@ -421,3 +422,18 @@ The plugin has a number of arguments, all of them are = optional: Sets the number of cores for which we maintain separate icache and dcach= e. (default: for linux-user, N =3D 1, for full system emulation: N =3D cores available to guest) + + * l2=3Don + + Simulates a unified L2 cache (stores blocks for both instructions and da= ta) + using the default L2 configuration (cache size =3D 2MB, associativity = =3D 16-way, + block size =3D 64B). + + * l2cachesize=3DN + * l2blksize=3DB + * l2assoc=3DA + + L2 cache configuration arguments. They specify the cache size, block siz= e, and + associativity of the L2 cache, respectively. Setting any of the L2 + configuration arguments implies ``l2=3Don``. + (default: N =3D 2097152 (2MB), B =3D 64, A =3D 16) --=20 2.25.1