From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628514803727283.06849116557646; Mon, 9 Aug 2021 06:13:23 -0700 (PDT) Received: from localhost ([::1]:48208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD55m-00055Z-L5 for importer@patchew.org; Mon, 09 Aug 2021 09:13:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD53g-00024p-2k; Mon, 09 Aug 2021 09:11:12 -0400 Received: from mail-qk1-x731.google.com ([2607:f8b0:4864:20::731]:34310) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mD53e-00019t-60; Mon, 09 Aug 2021 09:11:11 -0400 Received: by mail-qk1-x731.google.com with SMTP id w197so16906100qkb.1; Mon, 09 Aug 2021 06:11:09 -0700 (PDT) Received: from rekt.ibmuc.com ([191.19.172.190]) by smtp.gmail.com with ESMTPSA id f3sm6757435qti.65.2021.08.09.06.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 06:11:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DGlUQPK9e7epKwUBSBa5Q0ZSUZZqLkFNIDCZO/0kZRQ=; b=Hh4mP8xuT9pt3Vt0hdIO+ov7n/iqMrlhtCR7L1MfhC4X4RVJ+FaWuGPecjG9J+CaW3 8BQmNITgavnmvAEyFu1+9smuTCALYkezzb1qlDhg6B1MXiqCmU7AW/Z/tt5KpiNZQBzM Md824C+ARJSh/fRHgCYlfawzTFfNCFKh2TF57yk8kacYulUo53UDKuG5DeYZ6i61tBNk B5wsN1C6ei5QPR0Uha9M8pcped42KvIIK10UIF+t56vCen8YTLp3EoORK3vXsjdZiYUs n2d711g7J97qcCs1q754EWARLyw4Ymw38s3gQOmmv3hSjhJk9pgtoeNC7SkOqs0FdOGU NY7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DGlUQPK9e7epKwUBSBa5Q0ZSUZZqLkFNIDCZO/0kZRQ=; b=P8Q52ZoOuMMo5EV2d4mqiQKpQRbCPyf/B+1E4nF3VtUbYWJgh3LGxTyynhb5VHpqzB W3IstTbthyH3hHo5DI4sdJ1f8ufmHd+g4jbFei0ZTKQLH/2Uio4JSjzjPmuNUbEs7W1d pWsd1oKxvEIFehPaIqyUY2dxR4s491xkjnJLKxDrkm/lwW60A+9rmXWFOdSEK4H+FBB4 6mww9dxZuWEaZOhIrvxixDzi7D9GxPcSUPuQWmnlBzeTaFVrjdhoE3/DyKojGi2M01sM NENexbPewje10RPdCfuBIyszsaVOpvGa+NBUromzGQsJ2HL1Qcqx0w17OTKARlV0sUjI 3UJg== X-Gm-Message-State: AOAM530NUO/EAjhX9MxQc9Ob5thRewsW/IltnnMBvdwWFihf/3nTkyuM 3a8CN0GVnunx6as6LA1rav/NdbutxEJxLg== X-Google-Smtp-Source: ABdhPJzHT+U1Thv18v7oW0fhMgRcswsLwBd5N0hUgUZsyGl96jvZD4ebqCOtKzp2LSDravYvMjyZXA== X-Received: by 2002:a37:6888:: with SMTP id d130mr4181772qkc.391.1628514668799; Mon, 09 Aug 2021 06:11:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 01/19] target/ppc: add exclusive Book3S PMU reg read/write functions Date: Mon, 9 Aug 2021 10:10:39 -0300 Message-Id: <20210809131057.1694145-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x731.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628514804670100002 Content-Type: text/plain; charset="utf-8" The PowerPC PMU, as described by PowerISA v3.1, has a lot of functions that freezes, resets and sets counters to specific values depending on the circuntances. Some of these are trigged based on read/value of the PMU registers (MMCR0, MMCR1, MMCR2, MMCRA and PMC counters). Having to handle the PMU logic using the generic read/write functions can impact all other registers that has nothing to do with the PMU that uses these functions. This patch creates two new functions, spr_read_pmu_generic() and spr_write_pmu_generic, that will be used later on to handle PMU logic together with the read/write of PMU registers. We're not ready to add specific PMU logic in these new functions yet, so for now these are just stubs that calls spr_read/write_generic(). No functional change is made. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 24 ++++++++++++------------ target/ppc/spr_tcg.h | 2 ++ target/ppc/translate.c | 12 ++++++++++++ 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 505a0ed6ac..021c1bc750 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6821,47 +6821,47 @@ static void register_book3s_pmu_sup_sprs(CPUPPCStat= e *env) { spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_MMCR0, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_MMCR1, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, spr_write_pmu_generic, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_SIAR, 0x00000000); spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_SDAR, 0x00000000); } =20 @@ -6941,7 +6941,7 @@ static void register_power8_pmu_sup_sprs(CPUPPCState = *env) { spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_pmu_generic, &spr_write_pmu_generic, KVM_REG_PPC_MMCR2, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 0be5f347d5..2aab5878a0 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -25,6 +25,8 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn); +void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..c8f3878002 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -385,6 +385,12 @@ void spr_read_generic(DisasContext *ctx, int gprn, int= sprn) spr_load_dump_spr(sprn); } =20 +void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn) +{ + /* For now it's just a call to spr_read_generic() */ + spr_read_generic(ctx, gprn, sprn); +} + static void spr_store_dump_spr(int sprn) { #ifdef PPC_DUMP_SPR_ACCESSES @@ -400,6 +406,12 @@ void spr_write_generic(DisasContext *ctx, int sprn, in= t gprn) spr_store_dump_spr(sprn); } =20 +void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn) +{ + /* For now it's just a call to spr_write_generic() */ + spr_write_generic(ctx, sprn, gprn); +} + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628514954513745.5734386047575; Mon, 9 Aug 2021 06:15:54 -0700 (PDT) Received: from localhost ([::1]:56956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD58C-0002VQ-Ge for importer@patchew.org; Mon, 09 Aug 2021 09:15:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD53i-0002CQ-W4; Mon, 09 Aug 2021 09:11:15 -0400 Received: from mail-qk1-x72c.google.com ([2607:f8b0:4864:20::72c]:36460) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mD53g-0001Bp-Tv; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Gustavo Romero , Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628514956172100001 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero User read on PowerPC PMU regs requires extra handling in some instances. Instead of changing the existing read ureg function (spr_read_ureg) this patch adds a specific read function for user PMU SPRs, spr_read_pmu_ureg(). This function does extra handling of UMMCR0 and UMMCR2 and falls back to the default behavior for the not yet handled regs. Aside for UMMCR0 and UMMCR2 reads, no functional change is made. CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 8 ++++++++ target/ppc/cpu_init.c | 26 +++++++++++++------------- target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 41 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 61 insertions(+), 15 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 500205229c..4d96015f81 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -342,6 +342,14 @@ typedef struct ppc_v3_pate_t { #define MSR_RI 1 /* Recoverable interrupt 1 = */ #define MSR_LE 0 /* Little-endian mode 1 hfla= gs */ =20 +/* PMU bits */ +#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ +#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ +#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */ +#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ +#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ +#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 021c1bc750..d30aa0fe1e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6868,47 +6868,47 @@ static void register_book3s_pmu_sup_sprs(CPUPPCStat= e *env) static void register_book3s_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC1, "UPMC1", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC2, "UPMC2", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC3, "UPMC3", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC4, "UPMC4", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIAR, "USIAR", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USDAR, "USDAR", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); } @@ -6976,8 +6976,8 @@ static void register_power8_pmu_sup_sprs(CPUPPCState = *env) static void register_power8_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, + &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIER, "USIER", &spr_read_generic, SPR_NOACCESS, diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 2aab5878a0..84ecba220f 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -27,6 +27,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sp= rn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn); +void spr_read_pmu_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c8f3878002..d3a4d42ff8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -522,8 +522,6 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gpr= n) =20 /* User read access to SPR */ /* USPRx */ -/* UMMCRx */ -/* UPMCx */ /* USIA */ /* UDECR */ void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) @@ -531,6 +529,45 @@ void spr_read_ureg(DisasContext *ctx, int gprn, int sp= rn) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); } =20 +/* User special read access to PMU SPRs */ +void spr_read_pmu_ureg(DisasContext *ctx, int gprn, int sprn) +{ + TCGv t0 =3D tcg_temp_new(); + int effective_sprn =3D sprn + 0x10; + + switch (effective_sprn) { + case SPR_POWER_MMCR0: + /* + * Filter out all bits but FC, PMAO, and PMAE, according + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, + * fourth paragraph. + */ + gen_load_spr(t0, effective_sprn); + tcg_gen_andi_tl(t0, t0, MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE); + tcg_gen_mov_tl(cpu_gpr[gprn], t0); + break; + case SPR_POWER_MMCR2: + /* + * On read, filter out all bits that are not FCnP0 bits. + * When MMCR0[PMCC] is set to 0b10 or 0b11, providing + * problem state programs read/write access to MMCR2, + * only the FCnP0 bits can be accessed. All other bits are + * not changed when mtspr is executed in problem state, and + * all other bits return 0s when mfspr is executed in problem + * state, according to ISA v3.1, section 10.4.6 Monitor Mode + * Control Register 2, p. 1316, third paragraph. + */ + gen_load_spr(t0, effective_sprn); + tcg_gen_andi_tl(t0, t0, 0x4020100804020000UL); + tcg_gen_mov_tl(cpu_gpr[gprn], t0); + break; + default: + gen_load_spr(cpu_gpr[gprn], effective_sprn); + } + + tcg_temp_free(t0); +} + #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) { --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628514826160247.02463744644604; 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Mon, 09 Aug 2021 06:11:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 03/19] target/ppc: add exclusive user write function for PMU regs Date: Mon, 9 Aug 2021 10:10:41 -0300 Message-Id: <20210809131057.1694145-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x730.google.com X-Spam_score_int: 1 X-Spam_score: 0.1 X-Spam_bar: / X-Spam_report: (0.1 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Gustavo Romero , Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628514827336100003 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Similar to the previous patch, write read on PowerPC PMU regs requires extra handling than the generic write ureg functions. This patch adds a specific write function for user PMU SPRs, spr_write_pmu_ureg(). MMCR0 and PMC1 are being treated before write, all other registers will be default to what is done in spr_write_ureg(), for now. Since spr_write_pmu_ureg() needs to have a look in SPR_POWER_MMCR0 to validate if the write is valid or not, we're adding a 'spr' array in DisasContext that points to env->spr. CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 26 +++++++++++++------------- target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 13 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d30aa0fe1e..71062809c8 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6868,47 +6868,47 @@ static void register_book3s_pmu_sup_sprs(CPUPPCStat= e *env) static void register_book3s_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC1, "UPMC1", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC2, "UPMC2", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC3, "UPMC3", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC4, "UPMC4", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC5, "UPMC5", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC6, "UPMC6", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIAR, "USIAR", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USDAR, "USDAR", - &spr_read_pmu_ureg, SPR_NOACCESS, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); } @@ -6976,8 +6976,8 @@ static void register_power8_pmu_sup_sprs(CPUPPCState = *env) static void register_power8_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", - &spr_read_pmu_ureg, SPR_NOACCESS, - &spr_read_pmu_ureg, &spr_write_ureg, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, + &spr_read_pmu_ureg, &spr_write_pmu_ureg, 0x00000000); spr_register(env, SPR_POWER_USIER, "USIER", &spr_read_generic, SPR_NOACCESS, diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 84ecba220f..40b5de34b9 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int g= prn); void spr_read_pmu_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn); void spr_read_pmu_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_write_pmu_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d3a4d42ff8..29b0a340a9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -176,6 +176,7 @@ struct DisasContext { bool tm_enabled; bool gtse; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ + target_ulong *spr; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; uint64_t insns_flags; @@ -573,6 +574,46 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int g= prn) { gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); } + +/* User special write access to PMU SPRs */ +void spr_write_pmu_ureg(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0, t1; + int effective_sprn =3D sprn + 0x10; + + if (((ctx->spr[SPR_POWER_MMCR0] & MMCR0_PMCC) >> 18) =3D=3D 0) { + /* Hypervisor Emulation Assistance interrupt */ + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); + return; + } + + switch (effective_sprn) { + case SPR_POWER_MMCR0: + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + /* + * Filter out all bits but FC, PMAO, and PMAE, according + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, + * fourth paragraph. + */ + tcg_gen_andi_tl(t0, cpu_gpr[gprn], + MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE); + gen_load_spr(t1, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)); + /* Keep all other bits intact */ + tcg_gen_or_tl(t1, t1, t0); + gen_store_spr(effective_sprn, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + break; + default: + gen_store_spr(effective_sprn, cpu_gpr[gprn]); + break; + } +} + #endif =20 /* SPR common to all non-embedded PowerPC */ @@ -8563,6 +8604,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) uint32_t hflags =3D ctx->base.tb->flags; =20 ctx->spr_cb =3D env->spr_cb; + ctx->spr =3D env->spr; ctx->pr =3D (hflags >> HFLAGS_PR) & 1; ctx->mem_idx =3D (hflags >> HFLAGS_DMMU_IDX) & 7; ctx->dr =3D (hflags >> HFLAGS_DR) & 1; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628514964465734.253137572719; Mon, 9 Aug 2021 06:16:04 -0700 (PDT) Received: from localhost ([::1]:57858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD58N-0003CC-Bl for importer@patchew.org; Mon, 09 Aug 2021 09:16:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD53p-0002TJ-C0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x831.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628514966302100001 Content-Type: text/plain; charset="utf-8" The PMCC (PMC Control) bit in the MMCR0 register controls whether the counters PMC5 and PMC6 are being part of the performance monitor facility in a specific time. If PMCC allows it, PMC5 and PMC6 will always be used to measure instructions completed and cycles, respectively. This patch adds the barebones of the Book3s PMU logic by enabling instruction counting, using the icount framework, using the performance monitor counters 5 and 6. The overall logic goes as follows: - a helper is added to control the PMU state on each MMCR0 write. This allows for the PMU to start/stop as quick as possible; - only PMC5 and PMC6 are being set. PMC6 (cycles) is default to 4*insns (for cycles per instruction) for now; - the intended usage is to freeze the counters by setting MMCR0_FC, do any additional setting via MMCR1 (not implemented yet) and setting initial counter values, and enable the PMU by zeroing MMCR0_FC. Software must freeze counters to read the results - on the fly reading of the PMCs will return the starting value of each one. Since there will be more PMU exclusive code to be added next, let's also put the PMU logic in its own helper to keep all in the same place. The code is also repetitive and not really extensible to add more PMCs, but we'll handle this in the next patches. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 4 ++ target/ppc/cpu_init.c | 4 +- target/ppc/helper.h | 1 + target/ppc/meson.build | 1 + target/ppc/pmu_book3s_helper.c | 78 ++++++++++++++++++++++++++++++++++ target/ppc/translate.c | 14 ++++-- 6 files changed, 97 insertions(+), 5 deletions(-) create mode 100644 target/ppc/pmu_book3s_helper.c diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4d96015f81..229abfe7ee 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1175,6 +1175,10 @@ struct CPUPPCState { uint32_t tm_vscr; uint64_t tm_dscr; uint64_t tm_tar; + + /* PMU registers icount state */ + uint64_t pmc5_base_icount; + uint64_t pmc6_base_icount; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 71062809c8..fce89ee994 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6822,7 +6822,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_pmu_generic, &spr_write_pmu_generic, - KVM_REG_PPC_MMCR0, 0x00000000); + KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_pmu_generic, &spr_write_pmu_generic, @@ -6870,7 +6870,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState= *env) spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, - 0x00000000); + 0x80000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", &spr_read_pmu_ureg, &spr_write_pmu_ureg, &spr_read_ureg, &spr_write_ureg, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4076aa281e..5122632784 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -20,6 +20,7 @@ DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_mmcr0, void, env, tl) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b85f295703..bf252ca3ac 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -14,6 +14,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( 'int_helper.c', 'mem_helper.c', 'misc_helper.c', + 'pmu_book3s_helper.c', 'timebase_helper.c', 'translate.c', )) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c new file mode 100644 index 0000000000..fe16fcfce0 --- /dev/null +++ b/target/ppc/pmu_book3s_helper.c @@ -0,0 +1,78 @@ +/* + * PowerPC Book3s PMU emulation helpers for QEMU TCG + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +static uint64_t get_insns(void) +{ + return (uint64_t)icount_get_raw(); +} + +static uint64_t get_cycles(uint64_t insns) +{ + /* Placeholder value */ + return insns * 4; +} + +/* PMC5 always count instructions */ +static void freeze_PMC5_value(CPUPPCState *env) +{ + uint64_t insns =3D get_insns() - env->pmc5_base_icount; + + env->spr[SPR_POWER_PMC5] +=3D insns; + env->pmc5_base_icount +=3D insns; +} + +/* PMC6 always count cycles */ +static void freeze_PMC6_value(CPUPPCState *env) +{ + uint64_t insns =3D get_insns() - env->pmc6_base_icount; + + env->spr[SPR_POWER_PMC6] +=3D get_cycles(insns); + env->pmc6_base_icount +=3D insns; +} + +void helper_store_mmcr0(CPUPPCState *env, target_ulong value) +{ + bool curr_FC =3D env->spr[SPR_POWER_MMCR0] & MMCR0_FC; + bool new_FC =3D value & MMCR0_FC; + + /* + * In an frozen count (FC) bit change: + * + * - if PMCs were running (curr_FC =3D false) and we're freezing + * them (new_FC =3D true), save the PMCs values in the registers. + * + * - if PMCs were frozen (curr_FC =3D true) and we're activating + * them (new_FC =3D false), calculate the current icount for each + * register to allow for subsequent reads to calculate the insns + * passed. + */ + if (curr_FC !=3D new_FC) { + if (!curr_FC) { + freeze_PMC5_value(env); + freeze_PMC6_value(env); + } else { + uint64_t curr_icount =3D get_insns(); + + env->pmc5_base_icount =3D curr_icount; + env->pmc6_base_icount =3D curr_icount; + } + } + + env->spr[SPR_POWER_MMCR0] =3D value; +} diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 29b0a340a9..62356cfadf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -409,8 +409,14 @@ void spr_write_generic(DisasContext *ctx, int sprn, in= t gprn) =20 void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn) { - /* For now it's just a call to spr_write_generic() */ - spr_write_generic(ctx, sprn, gprn); + switch (sprn) { + case SPR_POWER_MMCR0: + gen_icount_io_start(ctx); + gen_helper_store_mmcr0(cpu_env, cpu_gpr[gprn]); + break; + default: + spr_write_generic(ctx, sprn, gprn); + } } =20 #if !defined(CONFIG_USER_ONLY) @@ -592,6 +598,8 @@ void spr_write_pmu_ureg(DisasContext *ctx, int sprn, in= t gprn) t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); =20 + gen_icount_io_start(ctx); + /* * Filter out all bits but FC, PMAO, and PMAE, according * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, @@ -603,7 +611,7 @@ void spr_write_pmu_ureg(DisasContext *ctx, int sprn, in= t gprn) tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)); /* Keep all other bits intact */ tcg_gen_or_tl(t1, t1, t0); - gen_store_spr(effective_sprn, t1); + gen_helper_store_mmcr0(cpu_env, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628514872672942.160638296259; Mon, 9 Aug 2021 06:14:32 -0700 (PDT) Received: from localhost ([::1]:53352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD56t-0008WL-Ie for importer@patchew.org; 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Mon, 09 Aug 2021 06:11:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 05/19] target/ppc/pmu_book3s_helper.c: eliminate code repetition Date: Mon, 9 Aug 2021 10:10:43 -0300 Message-Id: <20210809131057.1694145-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628514874070100001 Content-Type: text/plain; charset="utf-8" We don't need a base_icount value in CPUPPCState for each PMC. All the calculation done after freeze will use the same base start value. Use a single 'pmu_base_icount' attribute that can be use to all PMCs. Likewise, the freeze count operations are going to be done for all available PMCs, so eliminate both freeze_PMC5_value() and freeze_PMC6_value() and use the new update_PMCs_on_freeze() that will update all PMCs. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 8 +++++--- target/ppc/pmu_book3s_helper.c | 33 +++++++++++++-------------------- 2 files changed, 18 insertions(+), 23 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 229abfe7ee..8cea8f2aca 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1176,9 +1176,11 @@ struct CPUPPCState { uint64_t tm_dscr; uint64_t tm_tar; =20 - /* PMU registers icount state */ - uint64_t pmc5_base_icount; - uint64_t pmc6_base_icount; + /* + * PMU icount base value used by the PMU to calculate + * instructions and cycles. + */ + uint64_t pmu_base_icount; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index fe16fcfce0..0994531f65 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -28,22 +28,19 @@ static uint64_t get_cycles(uint64_t insns) return insns * 4; } =20 -/* PMC5 always count instructions */ -static void freeze_PMC5_value(CPUPPCState *env) -{ - uint64_t insns =3D get_insns() - env->pmc5_base_icount; - - env->spr[SPR_POWER_PMC5] +=3D insns; - env->pmc5_base_icount +=3D insns; -} - -/* PMC6 always count cycles */ -static void freeze_PMC6_value(CPUPPCState *env) +/* + * Set all PMCs values after a PMU freeze via MMCR0_FC. + * + * There is no need to update the base icount of each PMC since + * the PMU is not running. + */ +static void update_PMCs_on_freeze(CPUPPCState *env) { - uint64_t insns =3D get_insns() - env->pmc6_base_icount; + uint64_t curr_icount =3D get_insns(); =20 - env->spr[SPR_POWER_PMC6] +=3D get_cycles(insns); - env->pmc6_base_icount +=3D insns; + env->spr[SPR_POWER_PMC5] +=3D curr_icount - env->pmu_base_icount; + env->spr[SPR_POWER_PMC6] +=3D get_cycles(curr_icount - + env->pmu_base_icount); } =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) @@ -64,13 +61,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong v= alue) */ if (curr_FC !=3D new_FC) { if (!curr_FC) { - freeze_PMC5_value(env); - freeze_PMC6_value(env); + update_PMCs_on_freeze(env); } else { - uint64_t curr_icount =3D get_insns(); - - env->pmc5_base_icount =3D curr_icount; - env->pmc6_base_icount =3D curr_icount; + env->pmu_base_icount =3D get_insns(); } } =20 --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628515224679925.5302042356178; Mon, 9 Aug 2021 06:20:24 -0700 (PDT) Received: from localhost ([::1]:39068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD5CZ-0001Dq-Is for importer@patchew.org; Mon, 09 Aug 2021 09:20:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD53s-0002gQ-SD; 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charset="utf-8" So far the PMU logic was using PMC5 for instruction counting (linux kernel PM_INST_CMPL) and PMC6 to count cycles (PM_CYC). We aren't using PMCs 1-4. Let's enable all PMCs to count these 2 events we already provide. The logic used to calculate PMC5 is now being provided by update_PMC_PM_INST_CMPL() and PMC6 logic is now implemented in update_PMC_PM_CYC(). The enablement of these 2 events for all PMUs are done by using the Linux kernel definition of those events: 0x02 for PM_INST_CMPL and 0x1e for PM_CYC, all of those defined by specific bits in MMCR1 for each PMC. PMCs 1-4 relies on the correct event to be defined in MMCR1. PMC5 and PMC6 will count PM_INST_CMPL and PMC_CYC, respectively, regardless of MMCR1 setup. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 8 +++++ target/ppc/pmu_book3s_helper.c | 60 ++++++++++++++++++++++++++++++++-- 2 files changed, 65 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8cea8f2aca..afd9cd402b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -350,6 +350,14 @@ typedef struct ppc_v3_pate_t { #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ =20 +#define MMCR1_PMC1SEL_SHIFT (63 - 39) +#define MMCR1_PMC1SEL PPC_BITMASK(32, 39) +#define MMCR1_PMC2SEL_SHIFT (63 - 47) +#define MMCR1_PMC2SEL PPC_BITMASK(40, 47) +#define MMCR1_PMC3SEL_SHIFT (63 - 55) +#define MMCR1_PMC3SEL PPC_BITMASK(48, 55) +#define MMCR1_PMC4SEL PPC_BITMASK(56, 63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 0994531f65..99e62bd37b 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -28,6 +28,56 @@ static uint64_t get_cycles(uint64_t insns) return insns * 4; } =20 +static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn, + uint64_t curr_icount) +{ + env->spr[sprn] +=3D curr_icount - env->pmu_base_icount; +} + +static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, + uint64_t curr_icount) +{ + uint64_t insns =3D curr_icount - env->pmu_base_icount; + env->spr[sprn] +=3D get_cycles(insns); +} + +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, + uint64_t curr_icount) +{ + int event; + + switch (sprn) { + case SPR_POWER_PMC1: + event =3D MMCR1_PMC1SEL & env->spr[SPR_POWER_MMCR1]; + event =3D event >> MMCR1_PMC1SEL_SHIFT; + break; + case SPR_POWER_PMC2: + event =3D MMCR1_PMC2SEL & env->spr[SPR_POWER_MMCR1]; + event =3D event >> MMCR1_PMC2SEL_SHIFT; + break; + case SPR_POWER_PMC3: + event =3D MMCR1_PMC3SEL & env->spr[SPR_POWER_MMCR1]; + event =3D event >> MMCR1_PMC3SEL_SHIFT; + break; + case SPR_POWER_PMC4: + event =3D MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1]; + break; + default: + return; + } + + switch (event) { + case 0x2: + update_PMC_PM_INST_CMPL(env, sprn, curr_icount); + break; + case 0x1E: + update_PMC_PM_CYC(env, sprn, curr_icount); + break; + default: + return; + } +} + /* * Set all PMCs values after a PMU freeze via MMCR0_FC. * @@ -37,10 +87,14 @@ static uint64_t get_cycles(uint64_t insns) static void update_PMCs_on_freeze(CPUPPCState *env) { uint64_t curr_icount =3D get_insns(); + int sprn; + + for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, curr_icount); + } =20 - env->spr[SPR_POWER_PMC5] +=3D curr_icount - env->pmu_base_icount; - env->spr[SPR_POWER_PMC6] +=3D get_cycles(curr_icount - - env->pmu_base_icount); + update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, curr_icount); + update_PMC_PM_CYC(env, SPR_POWER_PMC6, curr_icount); } =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 09 Aug 2021 06:11:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 07/19] target/ppc/pmu_book3s_helper.c: icount fine tuning Date: Mon, 9 Aug 2021 10:10:45 -0300 Message-Id: <20210809131057.1694145-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x730.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515210812100003 Content-Type: text/plain; charset="utf-8" In the helper logic we're making 2 icount_get_raw() calls (via get_insns()) in different places: one in update_PMCs() and another in the helper_store_mmcr0() when the new base_icount is set. We don't need two distinct calls in two different places. In fact, calling them in the same point brings more consistency when turning the PMU on/off during heavy load. We're also want to retrieve the current icount value as soon as possible to avoid counting extra instructions. To do that, we're introducing the concept of 'icount_delta', which is the icount difference between the time PMU started and the time where we are updating the counters. Also, to behave more like the real hardware, discount the mtspr() calls that turns the PMU on/off when we're about to set the PMCs values. With these changes, running a pseries TCG with an icount shift of zero, in an Intel i7-8650U laptop running Fedora 34, the kernel PMU 'count_instructions' test (kernel tree, tools/testing/selftests/powerpc/pmu) gives a 99.9% average accurracy when sampling 10M instructions: [root@localhost powerpc]# ./pmu/count_instructions test: count_instructions tags: git_version:v5.13-5357-gdbe69e433722 Binding to cpu 0 main test running as pid 652 Overhead of null loop: 2315 instructions instructions: result 1002315 running/enabled 1582058 cycles: result 4005276 running/enabled 1343324 Looped for 1000000 instructions, overhead 2315 Expected 1002315 Actual 1002315 Delta 0, 0.000000% instructions: result 10010235 running/enabled 11598016 cycles: result 40036956 running/enabled 11356940 Looped for 10000000 instructions, overhead 2315 Expected 10002315 Actual 10010235 Delta 7920, 0.079119% This accuracy is good enough to validate the EBB (Event-Based Branch) support that we're going to implement shortly. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 46 ++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 99e62bd37b..6292b96db9 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -17,32 +17,27 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" =20 -static uint64_t get_insns(void) -{ - return (uint64_t)icount_get_raw(); -} =20 -static uint64_t get_cycles(uint64_t insns) +static uint64_t get_cycles(uint64_t icount_delta) { /* Placeholder value */ - return insns * 4; + return icount_delta * 4; } =20 static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn, - uint64_t curr_icount) + uint64_t icount_delta) { - env->spr[sprn] +=3D curr_icount - env->pmu_base_icount; + env->spr[sprn] +=3D icount_delta; } =20 static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, - uint64_t curr_icount) + uint64_t icount_delta) { - uint64_t insns =3D curr_icount - env->pmu_base_icount; - env->spr[sprn] +=3D get_cycles(insns); + env->spr[sprn] +=3D get_cycles(icount_delta); } =20 static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, - uint64_t curr_icount) + uint64_t icount_delta) { int event; =20 @@ -68,10 +63,10 @@ static void update_programmable_PMC_reg(CPUPPCState *en= v, int sprn, =20 switch (event) { case 0x2: - update_PMC_PM_INST_CMPL(env, sprn, curr_icount); + update_PMC_PM_INST_CMPL(env, sprn, icount_delta); break; case 0x1E: - update_PMC_PM_CYC(env, sprn, curr_icount); + update_PMC_PM_CYC(env, sprn, icount_delta); break; default: return; @@ -84,21 +79,21 @@ static void update_programmable_PMC_reg(CPUPPCState *en= v, int sprn, * There is no need to update the base icount of each PMC since * the PMU is not running. */ -static void update_PMCs_on_freeze(CPUPPCState *env) +static void update_PMCs(CPUPPCState *env, uint64_t icount_delta) { - uint64_t curr_icount =3D get_insns(); int sprn; =20 for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { - update_programmable_PMC_reg(env, sprn, curr_icount); + update_programmable_PMC_reg(env, sprn, icount_delta); } =20 - update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, curr_icount); - update_PMC_PM_CYC(env, SPR_POWER_PMC6, curr_icount); + update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, icount_delta); + update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); } =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { + uint64_t curr_icount =3D (uint64_t)icount_get_raw(); bool curr_FC =3D env->spr[SPR_POWER_MMCR0] & MMCR0_FC; bool new_FC =3D value & MMCR0_FC; =20 @@ -115,9 +110,18 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) */ if (curr_FC !=3D new_FC) { if (!curr_FC) { - update_PMCs_on_freeze(env); + uint64_t icount_delta =3D (curr_icount - env->pmu_base_icount); + + /* Exclude both mtsprs() that opened and closed the timer */ + icount_delta -=3D 2; + + /* + * Update the counter with the instructions run + * until the freeze. + */ + update_PMCs(env, icount_delta); } else { - env->pmu_base_icount =3D get_insns(); + env->pmu_base_icount =3D curr_icount; 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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fLVm1fBACGLmXLYfVgA5+6MFgswf6f1qbtuCJmUJ8As=; b=UB79B+QPjyI3WegGMhib3UCmFfH2VK4PR8QsWEQ8pWxTE76noaRn/uJKAu5U4A/0cV 4LhyGYSbKC6z9X1a5Fg6C/LmcSqEMaLyn0OokpT/nLCfprQmX7VYskOxeZX2J63Q3XEN rTMcPNbQL33y1Pn32H1iTWNaEWPDV4rRjYuvuzRMDPncRKpuRwq/SukExw4yJc6lo4gZ 4+Fr5K0o/tcTk8wJlgQ4KRyy1zMJJrY1Q8rlcYiLJ36A5GC/mLUiwQecC08rPLKhPpmh qocJzMjcAWZjnTPDz0LZGFa8m+sEj7EfenhMurD3/9Ih7WXac6fmt5hg+jjiiNfWcZjg ayaw== X-Gm-Message-State: AOAM530q/6TOs8biyhsIPIppNoiXwlVFouvetNS77IF/yXwJS+ePCey4 lW0AL+ZEWSuOGMn/9TyG86d4/Aql7jzVfA== X-Google-Smtp-Source: ABdhPJxm1/Wu5hp33mHCALgQZQWzYlaKyBpxUKgRU7kFmKXku/joH+u//lYu6eonM2SoZ6n9AW09og== X-Received: by 2002:a37:9f0b:: with SMTP id i11mr1311137qke.458.1628514686536; Mon, 09 Aug 2021 06:11:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 08/19] target/ppc/pmu_book3s_helper.c: do an actual cycles calculation Date: Mon, 9 Aug 2021 10:10:46 -0300 Message-Id: <20210809131057.1694145-9-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We've been considering that PM_CYC is always 4x the number of instructions sampled. This is not accurate due to several reasons, including icount shift. Replace it with a more accurate logic that returns the elapsed cycle count of the sampled period, based on what the ARM CPU already does in target/arm/helper.c, cycles_get_count(). Multiply the amount of ns passed in the icount period (which considers icount shift) with the CPU frequency. The PPC CPU clock frequency has different values depending on the CPU implementation. We're defaulting it to 1GHz since it's the same value used by PNV and pSeries CPUs. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 6292b96db9..91bb82e699 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -17,11 +17,16 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" =20 +/* + * Set arbitrarily based on clock-frequency values used in PNV + * and SPAPR code. + */ +#define PPC_CPU_FREQ 1000000000 =20 static uint64_t get_cycles(uint64_t icount_delta) { - /* Placeholder value */ - return icount_delta * 4; + return muldiv64(icount_to_ns(icount_delta), PPC_CPU_FREQ, + NANOSECONDS_PER_SECOND); } =20 static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn, --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 09 Aug 2021 06:11:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 09/19] PPC64/TCG: Implement 'rfebb' instruction Date: Mon, 9 Aug 2021 10:10:47 -0300 Message-Id: <20210809131057.1694145-10-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x729.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Gustavo Romero , Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515588385100001 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The EBB will: - set the Global Enable (GE) bit of BESCR to 0; - set bits 0-61 of the Event-Based Branch Return Register (EBBRR) to the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but next patches will use the remaining bits. Note that we're implementing the extended rfebb mnemonic (BESCR_GE is being always set to 1). The basic rfebb instruction would accept an operand that would be used to set GE. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 12 ++++++++++++ target/ppc/translate.c | 21 +++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index afd9cd402b..ae431e65be 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -358,6 +358,18 @@ typedef struct ppc_v3_pate_t { #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) =20 +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 62356cfadf..afc254a03f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2701,6 +2701,26 @@ static void gen_darn(DisasContext *ctx) } } } + +/* rfebb */ +static void gen_rfebb(DisasContext *ctx) +{ + TCGv target =3D tcg_temp_new(); + TCGv bescr =3D tcg_temp_new(); + + gen_load_spr(target, SPR_EBBRR); + tcg_gen_mov_tl(cpu_nip, target); + + gen_load_spr(bescr, SPR_BESCR); + tcg_gen_ori_tl(bescr, bescr, BESCR_GE); + gen_store_spr(SPR_BESCR, bescr); + + ctx->base.is_jmp =3D DISAS_EXIT; + + tcg_temp_free(target); + tcg_temp_free(bescr); +} + #endif =20 /*** Integer rotate = ***/ @@ -7724,6 +7744,7 @@ GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PP= C_POPCNTWD), GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(rfebb, 0x13, 0x12, 0x04, 0x03FFF001, PPC_NONE, PPC2_ISA207S), GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_IS= A206), #endif --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Gustavo Romero Following up the rfebb implementation, this patch adds the EBB exception support that are triggered by Performance Monitor alerts. This exception occurs when an enabled PMU condition or event happens and both MMCR0_EBE and BESCR_PME are set. The supported PM alerts will consist of counter negative conditions of the PMU counters. This will be achieved by a timer mechanism that will predict when a counter becomes negative. The PMU timer callback will set the appropriate bits in MMCR0 and fire a PMC interrupt. The EBB exception code will then set the appropriate BESCR bits, set the next instruction pointer to the address pointed by the return register (SPR_EBBRR), and redirect execution to the handler (pointed by SPR_EBBHR). This patch sets the basic structure of interrupts and the timer. The following patches will add the counter negative logic for the registers. The goal is to use the EBB selftests of the powerpc kernel to validate the EBB implementation, thus we'll add more PMU bits as we go along. CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr_cpu_core.c | 6 ++++++ target/ppc/cpu.h | 9 +++++++- target/ppc/excp_helper.c | 28 +++++++++++++++++++++++++ target/ppc/pmu_book3s_helper.c | 38 ++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 4f316a6f9d..41b443bde2 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/pmu_book3s_helper.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" @@ -266,6 +267,11 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprM= achineState *spapr, return false; } =20 + /* Init PMU interrupt timer (TCG only) */ + if (!kvm_enabled()) { + cpu_ppc_pmu_timer_init(env); + } + if (!sc->pre_3_0_migration) { vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, cpu->machine_data); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ae431e65be..1d38b8cf7a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -129,8 +129,9 @@ enum { /* ISA 3.00 additions */ POWERPC_EXCP_HVIRT =3D 101, POWERPC_EXCP_SYSCALL_VECTORED =3D 102, /* scv exception = */ + POWERPC_EXCP_EBB =3D 103, /* Event-based branch exception = */ /* EOL = */ - POWERPC_EXCP_NB =3D 103, + POWERPC_EXCP_NB =3D 104, /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ }; @@ -1201,6 +1202,11 @@ struct CPUPPCState { * instructions and cycles. */ uint64_t pmu_base_icount; + + /* + * Timer used to fire performance monitor alerts and interrupts. + */ + QEMUTimer *pmu_intr_timer; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ @@ -2417,6 +2423,7 @@ enum { PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ + PPC_INTERRUPT_PMC, /* Performance Monitor Counter interrupt= */ }; =20 /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a79a0ed465..b866209b6e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -821,6 +821,22 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); break; + case POWERPC_EXCP_EBB: /* Event-based branch exception = */ + if ((env->spr[SPR_BESCR] & BESCR_GE) && + (env->spr[SPR_BESCR] & BESCR_PME)) { + target_ulong nip; + + env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ + env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ + env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ + nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + powerpc_set_excp_state(cpu, nip, env->msr); + } + /* + * This interrupt is handled by userspace. No need + * to proceed. + */ + return; default: excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -1068,6 +1084,18 @@ static void ppc_hw_interrupt(CPUPPCState *env) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); return; } + /* PMC -> Event-based branch exception */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_PMC)) { + /* + * Performance Monitor event-based exception can only + * occur in problem state. + */ + if (msr_pr =3D=3D 1) { + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_PMC); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EBB); + return; + } + } } =20 if (env->resume_as_sreset) { diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 91bb82e699..43cc0eb722 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -10,12 +10,15 @@ * See the COPYING file in the top-level directory. */ =20 +#include "pmu_book3s_helper.h" + #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "hw/ppc/ppc.h" =20 /* * Set arbitrarily based on clock-frequency values used in PNV @@ -96,6 +99,41 @@ static void update_PMCs(CPUPPCState *env, uint64_t icoun= t_delta) update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); } =20 +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + CPUPPCState *env =3D &cpu->env; + uint64_t mmcr0; + + mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + if (env->spr[SPR_POWER_MMCR0] & MMCR0_EBE) { + /* freeeze counters if needed */ + if (mmcr0 & MMCR0_FCECE) { + mmcr0 &=3D ~MMCR0_FCECE; + mmcr0 |=3D MMCR0_FC; + } + + /* Clear PMAE and set PMAO */ + if (mmcr0 & MMCR0_PMAE) { + mmcr0 &=3D ~MMCR0_PMAE; + mmcr0 |=3D MMCR0_PMAO; + } + env->spr[SPR_POWER_MMCR0] =3D mmcr0; + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); + } +} + +void cpu_ppc_pmu_timer_init(CPUPPCState *env) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + QEMUTimer *timer; + + timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_pmu_timer_cb, cpu); + env->pmu_intr_timer =3D timer; +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { uint64_t curr_icount =3D (uint64_t)icount_get_raw(); --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The current logic is only considering event-based exceptions triggered by the performance monitor. This is true now, but we might want to add support for external event-based exceptions in the future. Let's make it a bit easier to do so by adding the bit logic that would happen in case we were dealing with an external event-based exception. While we're at it, add a few comments explaining why we're setting and clearing BESCR bits. Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 45 ++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b866209b6e..504b3130f2 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -822,14 +822,47 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) "is not implemented yet !\n"); break; case POWERPC_EXCP_EBB: /* Event-based branch exception = */ - if ((env->spr[SPR_BESCR] & BESCR_GE) && - (env->spr[SPR_BESCR] & BESCR_PME)) { + if (env->spr[SPR_BESCR] & BESCR_GE) { target_ulong nip; =20 - env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ - env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ - env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ - nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + /* + * If we have Performance Monitor Event-Based exception + * enabled (BESCR_PME) and a Performance Monitor alert + * occurred (MMCR0_PMAO), clear BESCR_PME and set BESCR_PMEO + * (Performance Monitor Event-Based Exception Occurred). + * + * Software is responsible for clearing both BESCR_PMEO and + * MMCR0_PMAO after the event has been handled. + */ + if ((env->spr[SPR_BESCR] & BESCR_PME) && + (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_PME; + env->spr[SPR_BESCR] |=3D BESCR_PMEO; + } + + /* + * In the case of External Event-Based exceptions, do a + * similar logic with BESCR_EE and BESCR_EEO. BESCR_EEO must + * also be cleared by software. + * + * PowerISA 3.1 considers that we'll not have BESCR_PMEO and + * BESCR_EEO set at the same time. We can check for BESCR_PMEO + * being not set in step above to see if this exception was + * trigged by an external event. + */ + if (env->spr[SPR_BESCR] & BESCR_EE && + !(env->spr[SPR_BESCR] & BESCR_PMEO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_EE; + env->spr[SPR_BESCR] |=3D BESCR_EEO; + } + + /* + * Clear BESCR_GE, save NIP for 'rfebb' and point the + * execution to the event handler (SPR_EBBHR) address. + */ + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + env->spr[SPR_EBBRR] =3D env->nip; + nip =3D env->spr[SPR_EBBHR]; powerpc_set_excp_state(cpu, nip, env->msr); } /* --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628515223137974.7273669619857; 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Mon, 09 Aug 2021 06:11:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 12/19] target/ppc/pmu_book3s_helper.c: enable PMC1 counter negative EBB Date: Mon, 9 Aug 2021 10:10:50 -0300 Message-Id: <20210809131057.1694145-13-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515224821100001 Content-Type: text/plain; charset="utf-8" This patch starts the counter negative EBB support by enabling PMC1 counter negative condition. A counter negative condition happens when a performance monitor counter reaches the value 0x80000000. When that happens, if a counter negative condition is enabled in that counter, a performance monitor alert is triggered. For PMC1, this condition is enabled by MMCR0_PMC1CE. An icount-based logic is used to predict when we need to wake up the timer to trigger the alert in both PM_INST_CMPL (0x2) and PM_CYC (0x1E) events. The timer callback will then trigger a PPC_INTERRUPT_PMC which will become a event-based exception later. Some EBB powerpc kernel selftests are passing after this patch, but a substancial amount of them relies on other PMCs to be enabled and events that we don't support at this moment. We'll address that in the next patches. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/pmu_book3s_helper.c | 127 +++++++++++++++++++++++---------- 2 files changed, 92 insertions(+), 36 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1d38b8cf7a..5c81d459f4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -350,6 +350,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ +#define MMCR0_PMC1CE PPC_BIT(48) =20 #define MMCR1_PMC1SEL_SHIFT (63 - 39) #define MMCR1_PMC1SEL PPC_BITMASK(32, 39) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 43cc0eb722..58ae65e22b 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -25,6 +25,7 @@ * and SPAPR code. */ #define PPC_CPU_FREQ 1000000000 +#define COUNTER_NEGATIVE_VAL 0x80000000 =20 static uint64_t get_cycles(uint64_t icount_delta) { @@ -32,22 +33,9 @@ static uint64_t get_cycles(uint64_t icount_delta) NANOSECONDS_PER_SECOND); } =20 -static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn, - uint64_t icount_delta) -{ - env->spr[sprn] +=3D icount_delta; -} - -static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, - uint64_t icount_delta) -{ - env->spr[sprn] +=3D get_cycles(icount_delta); -} - -static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, - uint64_t icount_delta) +static uint8_t get_PMC_event(CPUPPCState *env, int sprn) { - int event; + int event =3D 0x0; =20 switch (sprn) { case SPR_POWER_PMC1: @@ -65,11 +53,35 @@ static void update_programmable_PMC_reg(CPUPPCState *en= v, int sprn, case SPR_POWER_PMC4: event =3D MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1]; break; + case SPR_POWER_PMC5: + event =3D 0x2; + break; + case SPR_POWER_PMC6: + event =3D 0x1E; + break; default: - return; + break; } =20 - switch (event) { + return event; +} + +static void update_PMC_PM_INST_CMPL(CPUPPCState *env, int sprn, + uint64_t icount_delta) +{ + env->spr[sprn] +=3D icount_delta; +} + +static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, + uint64_t icount_delta) +{ + env->spr[sprn] +=3D get_cycles(icount_delta); +} + +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, + uint64_t icount_delta) +{ + switch (get_PMC_event(env, sprn)) { case 0x2: update_PMC_PM_INST_CMPL(env, sprn, icount_delta); break; @@ -99,30 +111,57 @@ static void update_PMCs(CPUPPCState *env, uint64_t ico= unt_delta) update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); } =20 +static void set_PMU_excp_timer(CPUPPCState *env) +{ + uint64_t timeout, now, remaining_val; + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { + return; + } + + remaining_val =3D COUNTER_NEGATIVE_VAL - env->spr[SPR_POWER_PMC1]; + + switch (get_PMC_event(env, SPR_POWER_PMC1)) { + case 0x2: + timeout =3D icount_to_ns(remaining_val); + break; + case 0x1e: + timeout =3D muldiv64(remaining_val, NANOSECONDS_PER_SECOND, + PPC_CPU_FREQ); + break; + default: + return; + } + + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + timer_mod(env->pmu_intr_timer, now + timeout); +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu =3D opaque; CPUPPCState *env =3D &cpu->env; - uint64_t mmcr0; - - mmcr0 =3D env->spr[SPR_POWER_MMCR0]; - if (env->spr[SPR_POWER_MMCR0] & MMCR0_EBE) { - /* freeeze counters if needed */ - if (mmcr0 & MMCR0_FCECE) { - mmcr0 &=3D ~MMCR0_FCECE; - mmcr0 |=3D MMCR0_FC; - } + uint64_t icount_delta =3D (uint64_t)icount_get_raw() - env->pmu_base_i= count; =20 - /* Clear PMAE and set PMAO */ - if (mmcr0 & MMCR0_PMAE) { - mmcr0 &=3D ~MMCR0_PMAE; - mmcr0 |=3D MMCR0_PMAO; - } - env->spr[SPR_POWER_MMCR0] =3D mmcr0; + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } + + update_PMCs(env, icount_delta); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_FC; + } =20 - /* Fire the PMC hardware exception */ - ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_PMAO; } + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); } =20 void cpu_ppc_pmu_timer_init(CPUPPCState *env) @@ -134,12 +173,19 @@ void cpu_ppc_pmu_timer_init(CPUPPCState *env) env->pmu_intr_timer =3D timer; } =20 +static bool mmcr0_counter_neg_cond_enabled(uint64_t mmcr0) +{ + return mmcr0 & MMCR0_PMC1CE; +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { uint64_t curr_icount =3D (uint64_t)icount_get_raw(); bool curr_FC =3D env->spr[SPR_POWER_MMCR0] & MMCR0_FC; bool new_FC =3D value & MMCR0_FC; =20 + env->spr[SPR_POWER_MMCR0] =3D value; + /* * In an frozen count (FC) bit change: * @@ -163,10 +209,19 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulon= g value) * until the freeze. */ update_PMCs(env, icount_delta); + + /* delete pending timer */ + timer_del(env->pmu_intr_timer); } else { env->pmu_base_icount =3D curr_icount; + + /* + * Start performance monitor alert timer for counter negative + * events, if needed. + */ + if (mmcr0_counter_neg_cond_enabled(env->spr[SPR_POWER_MMCR0]))= { + set_PMU_excp_timer(env); + } } } - - env->spr[SPR_POWER_MMCR0] =3D value; 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charset="utf-8" The initial PMU support were made under the assumption that the counters would be set before running the PMU and read after either freezing the PMU manually or via a performance monitor alert. Turns out that some EBB powerpc kernel tests set the counters after unfreezing the counters. Setting a PMC value when the PMU is running means that, at that moment, the baseline for calculating the events (set in env->pmu_base_icount) needs to be updated. Updating this baseline means that we need to update all the PMCs with their actual value at that moment. Any existing counter negative timer needs to be discarded an a new one, with the updated values, must be set again. This patch does that via a new 'helper_store_pmc()' that is called in the mtspr() callbacks of the PMU registers, spr_write_pmu_ureg() and spr_write_pmu_generic() in target/ppc/translate.c With this change, EBB powerpc kernel tests such as 'no_handler_test' are now passing. Signed-off-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 + target/ppc/pmu_book3s_helper.c | 36 ++++++++++++++++++++++++++++++++-- target/ppc/translate.c | 27 +++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5122632784..757665b360 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 58ae65e22b..e7af273cb6 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -173,7 +173,7 @@ void cpu_ppc_pmu_timer_init(CPUPPCState *env) env->pmu_intr_timer =3D timer; } =20 -static bool mmcr0_counter_neg_cond_enabled(uint64_t mmcr0) +static bool counter_negative_cond_enabled(uint64_t mmcr0) { return mmcr0 & MMCR0_PMC1CE; } @@ -219,9 +219,41 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) * Start performance monitor alert timer for counter negative * events, if needed. */ - if (mmcr0_counter_neg_cond_enabled(env->spr[SPR_POWER_MMCR0]))= { + if (counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { set_PMU_excp_timer(env); } } } } + +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + bool pmu_frozen =3D env->spr[SPR_POWER_MMCR0] & MMCR0_FC; + uint64_t curr_icount, icount_delta; + + if (pmu_frozen) { + env->spr[sprn] =3D value; + return; + } + + curr_icount =3D (uint64_t)icount_get_raw(); + icount_delta =3D curr_icount - env->pmu_base_icount; + + /* Update the counter with the events counted so far */ + update_PMCs(env, icount_delta); + + /* Set the counter to the desirable value after update_PMCs() */ + env->spr[sprn] =3D value; + + /* + * Delete the current timer and restart a new one with the + * updated values. + */ + timer_del(env->pmu_intr_timer); + + env->pmu_base_icount =3D curr_icount; + + if (counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { + set_PMU_excp_timer(env); + } +} diff --git a/target/ppc/translate.c b/target/ppc/translate.c index afc254a03f..3e890cc4d8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -409,11 +409,25 @@ void spr_write_generic(DisasContext *ctx, int sprn, i= nt gprn) =20 void spr_write_pmu_generic(DisasContext *ctx, int sprn, int gprn) { + TCGv_i32 t_sprn; + switch (sprn) { case SPR_POWER_MMCR0: gen_icount_io_start(ctx); gen_helper_store_mmcr0(cpu_env, cpu_gpr[gprn]); break; + case SPR_POWER_PMC1: + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + case SPR_POWER_PMC5: + case SPR_POWER_PMC6: + gen_icount_io_start(ctx); + + t_sprn =3D tcg_const_i32(sprn); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + tcg_temp_free_i32(t_sprn); + break; default: spr_write_generic(ctx, sprn, gprn); } @@ -585,6 +599,7 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gp= rn) void spr_write_pmu_ureg(DisasContext *ctx, int sprn, int gprn) { TCGv t0, t1; + TCGv_i32 t_sprn; int effective_sprn =3D sprn + 0x10; =20 if (((ctx->spr[SPR_POWER_MMCR0] & MMCR0_PMCC) >> 18) =3D=3D 0) { @@ -616,6 +631,18 @@ void spr_write_pmu_ureg(DisasContext *ctx, int sprn, i= nt gprn) tcg_temp_free(t0); tcg_temp_free(t1); break; + case SPR_POWER_PMC1: + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + case SPR_POWER_PMC5: + case SPR_POWER_PMC6: + gen_icount_io_start(ctx); + + t_sprn =3D tcg_const_i32(effective_sprn); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + tcg_temp_free_i32(t_sprn); + break; default: gen_store_spr(effective_sprn, cpu_gpr[gprn]); break; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628515571887225.4708524686838; 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Mon, 09 Aug 2021 06:11:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 14/19] target/ppc/pmu_book3s_helper.c: add generic timeout helpers Date: Mon, 9 Aug 2021 10:10:52 -0300 Message-Id: <20210809131057.1694145-15-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515573653100003 Content-Type: text/plain; charset="utf-8" Before adding counter negative condition support for the other 5 counters, create generic helpers that retrieves the elapsed timeout to counter negative based on the event being sampled. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 41 +++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index e7af273cb6..7126e9b3d5 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -111,23 +111,52 @@ static void update_PMCs(CPUPPCState *env, uint64_t ic= ount_delta) update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); } =20 +static int64_t get_INST_CMPL_timeout(CPUPPCState *env, int sprn) +{ + int64_t remaining_insns; + + if (env->spr[sprn] =3D=3D 0) { + return icount_to_ns(COUNTER_NEGATIVE_VAL); + } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + remaining_insns =3D COUNTER_NEGATIVE_VAL - env->spr[sprn]; + return icount_to_ns(remaining_insns); +} + +static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) +{ + int64_t remaining_cyc; + + if (env->spr[sprn] =3D=3D 0) { + return icount_to_ns(COUNTER_NEGATIVE_VAL); + } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + remaining_cyc =3D COUNTER_NEGATIVE_VAL - env->spr[sprn]; + return muldiv64(remaining_cyc, NANOSECONDS_PER_SECOND, PPC_CPU_FREQ); +} + static void set_PMU_excp_timer(CPUPPCState *env) { - uint64_t timeout, now, remaining_val; + uint64_t timeout, now; =20 if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { return; } =20 - remaining_val =3D COUNTER_NEGATIVE_VAL - env->spr[SPR_POWER_PMC1]; - switch (get_PMC_event(env, SPR_POWER_PMC1)) { case 0x2: - timeout =3D icount_to_ns(remaining_val); + timeout =3D get_INST_CMPL_timeout(env, SPR_POWER_PMC1); break; case 0x1e: - timeout =3D muldiv64(remaining_val, NANOSECONDS_PER_SECOND, - PPC_CPU_FREQ); + timeout =3D get_CYC_timeout(env, SPR_POWER_PMC1); break; default: return; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 09 Aug 2021 06:11:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 15/19] target/ppc/pmu_book3s_helper: enable counter negative for all PMCs Date: Mon, 9 Aug 2021 10:10:53 -0300 Message-Id: <20210809131057.1694145-16-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x730.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515793626100001 Content-Type: text/plain; charset="utf-8" All performance monitor counters can trigger a counter negative condition if the proper MMCR0 bits are set. This patch does that by doing the following: - pmc_counter_negative_enabled() will check whether a given PMC is eligible to trigger the counter negative alert; - get_counter_neg_timeout() will return the timeout for the counter negative condition for a given PMC, or -1 if the PMC is not able to trigger this alert; - the existing counter_negative_cond_enabled() now must consider the counter negative bit for PMCs 2-6, MMCR0_PMCjCE; - set_PMU_excp_timer() will now search all existing PMCs for the shortest counter negative timeout. The shortest timeout will be used to set the PMC interrupt timer. This change makes most EBB powepc kernel tests pass, validating that the existing EBB logic is consistent. There are a few tests that aren't passing due to additional PMU bits and perf events that aren't covered yet. We'll attempt to cover some of those in the next patches. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/pmu_book3s_helper.c | 96 ++++++++++++++++++++++++++++++---- 2 files changed, 87 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5c81d459f4..1aa1fd42af 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -351,6 +351,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_PMC1CE PPC_BIT(48) +#define MMCR0_PMCjCE PPC_BIT(49) =20 #define MMCR1_PMC1SEL_SHIFT (63 - 39) #define MMCR1_PMC1SEL PPC_BITMASK(32, 39) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 7126e9b3d5..c5c5ab38c9 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -143,22 +143,98 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int = sprn) return muldiv64(remaining_cyc, NANOSECONDS_PER_SECOND, PPC_CPU_FREQ); } =20 -static void set_PMU_excp_timer(CPUPPCState *env) +static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) { - uint64_t timeout, now; + switch (sprn) { + case SPR_POWER_PMC1: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; =20 - if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { - return; + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + case SPR_POWER_PMC5: + case SPR_POWER_PMC6: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; + + default: + break; } =20 - switch (get_PMC_event(env, SPR_POWER_PMC1)) { - case 0x2: - timeout =3D get_INST_CMPL_timeout(env, SPR_POWER_PMC1); + return false; +} + +static int64_t get_counter_neg_timeout(CPUPPCState *env, int sprn) +{ + int64_t timeout =3D -1; + + if (!pmc_counter_negative_enabled(env, sprn)) { + return -1; + } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + switch (sprn) { + case SPR_POWER_PMC1: + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + switch (get_PMC_event(env, sprn)) { + case 0x2: + timeout =3D get_INST_CMPL_timeout(env, sprn); + break; + case 0x1E: + timeout =3D get_CYC_timeout(env, sprn); + break; + } + break; - case 0x1e: - timeout =3D get_CYC_timeout(env, SPR_POWER_PMC1); + case SPR_POWER_PMC5: + timeout =3D get_INST_CMPL_timeout(env, sprn); + break; + case SPR_POWER_PMC6: + timeout =3D get_CYC_timeout(env, sprn); break; default: + break; + } + + return timeout; +} + +static void set_PMU_excp_timer(CPUPPCState *env) +{ + int64_t timeout =3D -1; + uint64_t now; + int i; + + /* + * Scroll through all PMCs and check which one is closer to a + * counter negative timeout. + */ + for (i =3D SPR_POWER_PMC1; i <=3D SPR_POWER_PMC6; i++) { + int64_t curr_timeout =3D get_counter_neg_timeout(env, i); + + if (curr_timeout =3D=3D -1) { + continue; + } + + if (curr_timeout =3D=3D 0) { + timeout =3D 0; + break; + } + + if (timeout =3D=3D -1 || timeout > curr_timeout) { + timeout =3D curr_timeout; + } + } + + /* + * This can happen if counter negative conditions were enabled + * without any events to be sampled. + */ + if (timeout =3D=3D -1) { return; } =20 @@ -204,7 +280,7 @@ void cpu_ppc_pmu_timer_init(CPUPPCState *env) =20 static bool counter_negative_cond_enabled(uint64_t mmcr0) { - return mmcr0 & MMCR0_PMC1CE; + return mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE); } =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628515173144289.47128477654235; Mon, 9 Aug 2021 06:19:33 -0700 (PDT) Received: from localhost ([::1]:37340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD5Bj-0008Su-Qr for importer@patchew.org; Mon, 09 Aug 2021 09:19:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD54I-0003Vs-0H; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515173773100001 The PowerISA 3.1 defines the 0xFA event as instructions completed when the thread's CTRL register is set. Some EBB powerpc kernel tests use this event to exercise both the PMU and the EBB support. We don't have a way at this moment to tell whether an instruction was completed under those conditions. What we can do is to make it equivalent to the existing PM_INST_COMPL event that counts all instructions completed. For our current purposes with the PMU support this is enough. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index c5c5ab38c9..388263688b 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -52,6 +52,20 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn) break; case SPR_POWER_PMC4: event =3D MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1]; + + /* + * Event 0xFA for PMC4SEL is described as follows in + * PowerISA v3.1: + * + * "The thread has completed an instruction when the RUN bit of + * the thread=E2=80=99s CTRL register contained 1" + * + * Our closest equivalent for this event at this moment is plain + * INST_CMPL (event 0x2) + */ + if (event =3D=3D 0xFA) { + event =3D 0x2; + } break; case SPR_POWER_PMC5: event =3D 0x2; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515736230100001 Content-Type: text/plain; charset="utf-8" We're missing two counter freeze bits that are used to further control how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes PMCs 5 and 6. The EBB powerpc kernel test 'pmc56_overflow' exercises this logic. Let's add it in the PMU logic to make this test pass. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 ++ target/ppc/pmu_book3s_helper.c | 23 +++++++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1aa1fd42af..204f0d58ee 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -352,6 +352,8 @@ typedef struct ppc_v3_pate_t { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_PMC1CE PPC_BIT(48) #define MMCR0_PMCjCE PPC_BIT(49) +#define MMCR0_FC14 PPC_BIT(58) +#define MMCR0_FC56 PPC_BIT(59) =20 #define MMCR1_PMC1SEL_SHIFT (63 - 39) #define MMCR1_PMC1SEL PPC_BITMASK(32, 39) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index 388263688b..ae7050cd62 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -115,14 +115,20 @@ static void update_programmable_PMC_reg(CPUPPCState *= env, int sprn, */ static void update_PMCs(CPUPPCState *env, uint64_t icount_delta) { + bool PMC14_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + bool PMC56_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); int sprn; =20 - for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { - update_programmable_PMC_reg(env, sprn, icount_delta); + if (PMC14_running) { + for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, icount_delta); + } } =20 - update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, icount_delta); - update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); + if (PMC56_running) { + update_PMC_PM_INST_CMPL(env, SPR_POWER_PMC5, icount_delta); + update_PMC_PM_CYC(env, SPR_POWER_PMC6, icount_delta); + } } =20 static int64_t get_INST_CMPL_timeout(CPUPPCState *env, int sprn) @@ -159,16 +165,21 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int = sprn) =20 static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) { + bool PMC14_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + bool PMC56_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); + switch (sprn) { case SPR_POWER_PMC1: - return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE && PMC14_running; =20 case SPR_POWER_PMC2: case SPR_POWER_PMC3: case SPR_POWER_PMC4: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE && PMC14_running; + case SPR_POWER_PMC5: case SPR_POWER_PMC6: - return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE && PMC56_running; =20 default: break; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628515863432759.4533982240655; Mon, 9 Aug 2021 06:31:03 -0700 (PDT) Received: from localhost ([::1]:45594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD5Ms-00087r-7I for importer@patchew.org; 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Mon, 09 Aug 2021 06:11:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH 18/19] target/ppc/pmu_book3s_helper.c: add PM_CMPLU_STALL mock events Date: Mon, 9 Aug 2021 10:10:56 -0300 Message-Id: <20210809131057.1694145-19-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809131057.1694145-1-danielhb413@gmail.com> References: <20210809131057.1694145-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x72d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628515864236100001 Content-Type: text/plain; charset="utf-8" EBB powerpc kernel test 'multi_counter_test' uses PM_CMPLU_STALL events that we do not support. These events are related to CPU stalled/wasted cycles while waiting for resources, cache misses and so on. Unlike the 0xFA event added previously, there's no available equivalent for us to use, and at this moment we can't sample those events as well. What we can do is mock those events as if we were calculating them. This patch implements PM_CMPLU_STALL, PM_CMPLU_STALL_FXU, PM_CMPLU_STALL_OTHER_CMPL and PM_CMPLU_STALL_THRD mock events by giving them a fixed amount of the total elapsed cycles. The chosen sample values for these events (25% of total cycles for PM_CMPLU_STALL and 5% for the other three) were chosen at random and has no intention of being truthful with what a real PowerPC hardware would give us. Our intention here is to make 'multi_counter_test' EBB test pass. Signed-off-by: Daniel Henrique Barboza --- target/ppc/pmu_book3s_helper.c | 81 +++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c index ae7050cd62..32cf76b77f 100644 --- a/target/ppc/pmu_book3s_helper.c +++ b/target/ppc/pmu_book3s_helper.c @@ -92,16 +92,54 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int spr= n, env->spr[sprn] +=3D get_cycles(icount_delta); } =20 +static int get_stall_ratio(uint8_t stall_event) +{ + int stall_ratio =3D 0; + + switch (stall_event) { + case 0xA: + stall_ratio =3D 25; + break; + case 0x6: + case 0x16: + case 0x1C: + stall_ratio =3D 5; + break; + default: + break; + } + + return stall_ratio; +} + +static void update_PMC_PM_STALL(CPUPPCState *env, int sprn, + uint64_t icount_delta, + uint8_t stall_event) +{ + int stall_ratio =3D get_stall_ratio(stall_event); + uint64_t cycles =3D muldiv64(get_cycles(icount_delta), stall_ratio, 10= 0); + + env->spr[sprn] +=3D cycles; +} + static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, uint64_t icount_delta) { - switch (get_PMC_event(env, sprn)) { + uint8_t event =3D get_PMC_event(env, sprn); + + switch (event) { case 0x2: update_PMC_PM_INST_CMPL(env, sprn, icount_delta); break; case 0x1E: update_PMC_PM_CYC(env, sprn, icount_delta); break; + case 0xA: + case 0x6: + case 0x16: + case 0x1C: + update_PMC_PM_STALL(env, sprn, icount_delta, event); + break; default: return; } @@ -163,6 +201,34 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int s= prn) return muldiv64(remaining_cyc, NANOSECONDS_PER_SECOND, PPC_CPU_FREQ); } =20 +static int64_t get_stall_timeout(CPUPPCState *env, int sprn, + uint8_t stall_event) +{ + uint64_t remaining_cyc; + int stall_multiplier; + + if (env->spr[sprn] =3D=3D 0) { + return icount_to_ns(COUNTER_NEGATIVE_VAL); + } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + remaining_cyc =3D COUNTER_NEGATIVE_VAL - env->spr[sprn]; + + /* + * Consider that for this stall event we'll advance the counter + * in a lower rate, thus requiring more cycles to overflow. + * E.g. for PM_CMPLU_STALL (0xA), ratio 25, it'll require + * 100/25 =3D 4 times the same amount of cycles to overflow. + */ + stall_multiplier =3D 100 / get_stall_ratio(stall_event); + remaining_cyc *=3D stall_multiplier; + + return muldiv64(remaining_cyc, NANOSECONDS_PER_SECOND, PPC_CPU_FREQ); +} + static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) { bool PMC14_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); @@ -191,6 +257,7 @@ static bool pmc_counter_negative_enabled(CPUPPCState *e= nv, int sprn) static int64_t get_counter_neg_timeout(CPUPPCState *env, int sprn) { int64_t timeout =3D -1; + uint8_t event; =20 if (!pmc_counter_negative_enabled(env, sprn)) { return -1; @@ -205,13 +272,23 @@ static int64_t get_counter_neg_timeout(CPUPPCState *e= nv, int sprn) case SPR_POWER_PMC2: case SPR_POWER_PMC3: case SPR_POWER_PMC4: - switch (get_PMC_event(env, sprn)) { + event =3D get_PMC_event(env, sprn); + + switch (event) { case 0x2: timeout =3D get_INST_CMPL_timeout(env, sprn); break; case 0x1E: timeout =3D get_CYC_timeout(env, sprn); break; + case 0xA: + case 0x6: + case 0x16: + case 0x1c: + timeout =3D get_stall_timeout(env, sprn, event); + break; + default: + break; } =20 break; --=20 2.31.1 From nobody Sun May 19 10:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628516064459119.16963814579924; Mon, 9 Aug 2021 06:34:24 -0700 (PDT) Received: from localhost ([::1]:54040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mD5Q7-0005SJ-BV for importer@patchew.org; Mon, 09 Aug 2021 09:34:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mD54P-0003uR-KD; Mon, 09 Aug 2021 09:11:58 -0400 Received: from mail-qt1-x82e.google.com ([2607:f8b0:4864:20::82e]:35461) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mD54N-0001l2-Ts; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x82e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628516065145100001 Content-Type: text/plain; charset="utf-8" Since we didn't implement a fully fledged Book3s PMU in TCG, add a new doc page in the specs dir to register the current capabilities of the new PPC64 TCG PMU. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/ppc-tcg-pmu-ebb.rst | 71 ++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 docs/specs/ppc-tcg-pmu-ebb.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index b7b08ea30d..a44fa93f4c 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -10,6 +10,7 @@ guest hardware that is specific to QEMU. ppc-xive ppc-spapr-xive ppc-spapr-numa + ppc-tcg-pmu-ebb acpi_hw_reduced_hotplug tpm acpi_hest_ghes diff --git a/docs/specs/ppc-tcg-pmu-ebb.rst b/docs/specs/ppc-tcg-pmu-ebb.rst new file mode 100644 index 0000000000..d40276b3f0 --- /dev/null +++ b/docs/specs/ppc-tcg-pmu-ebb.rst @@ -0,0 +1,71 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +QEMU TCG PMU-EBB support for PPC64 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +QEMU version 6.2 introduces an EBB (Event-Based Branch) implementation +for PPC64 TCG guests. It was introduced together with a simple PMU +(Performance Monitor Unit) implementation which was only introduced +as a means to validate EBB using the Linux kernel selftests located +in the kernel tree at tools/testing/selftests/powerpc/pmu/ebb. + +The goal of this document is to give a brief explanation of what +to expect, and more important, what to not expect from this existing +PMU implementation. + + +EBB support +----------- + +The existing EBB support can be summarized as follows: + + - all bits from BESCR are implemented; + - rfebb instruction is implemented as the mnemonic 'rfebb 1', i.e. the + instruction will always set BESCR_GE; + - support for both Performance Monitor and External event-based exceptions + are included, although there is no code that triggers an external excepti= on + at this moment. + + +PMU support +----------- + +The existing PMU logic is capable of counting instructions (perf event +PM_INST_CMPL) and cycles (perf event PM_CYC) using QEMU's icount +framework. A handful of PM_STALL events were added as fixed ratio of +the total cycles as a means to enable one of the EBB tests. + +Everything that is not mentioned above is not supported in the PMU. Most +notably: + + - reading unfrozen (running) PMCs will return their last set value. The P= MCs + are only updated after they're frozen; + - no MMCR2 and MMCRA support. The registers can be read and written at wi= ll, + but the PMU will ignore it; + - as a consequence of not supporting MMCRA, no random events and no thres= hold + event counters are enabled; + - no form of BHRB support is implemented; + - several MMCR0 bits are not supported; + - access control of the PMCs is only partially done. For example, setting + MMCR0_PMCC to 0b11 will not exclude PMC5 and PMC6 from the PMU. + + +icount usage +------------ + +The development of both the PMU and EBB support were tested with icount sh= ift +zero with alignment, e.g. this command line option: + +``-icount shift=3D0,align=3Don`` + +Different 'shift' options will degrade the performance of the PMU tests an= d some +EBB tests that relies on small count error margins (e.g. 'count_instructio= ns'). + +Running PMU and EBB tests without any icount support will not give reliable +results due to how the instructions and cycles relies on icount to work. + +It's also worth mentioning that all these icount restrictions and conditio= ns +are exclusive to the PMU logic. The Event-Based Branch code does not rely = on +the icount availability or configuration to work. --=20 2.31.1