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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id d7sm16794868wrs.39.2021.08.08.10.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Ip7dNqBR9CCs37W148txuk2ntTuwtUF2p4pRZfBcEc=; b=POJXZoKM49dhjifHYhA54TernPftxyeGVFHAU3EfjFjRDzLg00rmvBZvSg01EK1N0X o5BoUYVhSUHiG9DMR3BVxkhUBIKpK8sZ8tZJePTa4z/sg3zkY25KgfSDgXVcSHPkRLXx q4MkNlUuaWulBOiWW1wYXrlfXUDqqPe/eTFlxICKTScrpptE7G46gC61FyAi1AhzFOWv TlYc5lWYoxADXHQtTHFpHJAxOtKhhyV/1JEwvKDzdQhsK/yyThqGwCiEfqVUSbNoTxeR xZ/2VR44i5W7WdHAdEXdo/rEDhOFfZrd52oXPdvtEFT4fFuVIfsYD/lcnrPlmPILV3Ap UP7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2Ip7dNqBR9CCs37W148txuk2ntTuwtUF2p4pRZfBcEc=; b=mVJEZbq6R00M6Fw0YANae+J22IFcGAGN6+8WxOMklIgxxkLAsYMRdayAUEy/aaDJcL YOdlYRg9swaFtb4dJngA3l5Go4QkzoYZUyEZrZQIirpS6JU3A6nTW8zD0S+3+oyc8LLn kjPlf2wtZEAoQN7NghedZwvcX0pds47FgyA/WxnPvnkq41F1PiIcM7iM18HqlDg7Qlff Je3jmsSDOwhXXm1rCcu/3t6DJz8duc4RYI8HNgVVYkaSzcipAMwT6GAOpx3VGID0KNTX DXE4BGX1MJkaQ2H4nlSAAV7SB/YSXWrFpwTlX9UAtoB1+pPedq4Qgk2OC14PkQEQayxh HOfw== X-Gm-Message-State: AOAM530lCLngPoHOVV5LoTKn01r8VQb2PrkQzZTfwildAxYLft130X7K zBFbBAF/QXFKhDaS5K0V6os= X-Google-Smtp-Source: ABdhPJyIFEPwW3Hs9yxY4z5a1DYi+lrKoMTi8GP64+mayczuiAan5beEBxPlaFoYXvEYB4PFiNEoAQ== X-Received: by 2002:a05:6000:10c6:: with SMTP id b6mr21125723wrx.110.1628443845785; Sun, 08 Aug 2021 10:30:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 5/7] target/mips: Convert Vr54xx MACC* opcodes to decodetree Date: Sun, 8 Aug 2021 19:30:16 +0200 Message-Id: <20210808173018.90960-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443848486100001 Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/vr54xx.decode | 9 ++++++++ target/mips/tcg/translate.c | 16 --------------- target/mips/tcg/vr54xx_translate.c | 33 ++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index f6b3e42c999..73778f101a5 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -6,3 +6,12 @@ # # Reference: VR5432 Microprocessor User=E2=80=99s Manual # (Document Number U13751EU5V0UM00) + +&r rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r + +MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd +MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd +MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 34363639937..fd8ffadf06e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -300,16 +300,12 @@ enum { enum { OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, }; @@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; @@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 13e58fdd8df..0e2d460c985 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -17,3 +17,36 @@ =20 /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" + +/* + * Integer Multiply-Accumulate Instructions + * + * MACC Multiply, accumulate, and move LO + * MACCHI Multiply, accumulate, and move HI + * MACCHIU Unsigned multiply, accumulate, and move HI + * MACCU Unsigned multiply, accumulate, and move LO + */ + +static bool trans_mult_acc(DisasContext *ctx, arg_r *a, + void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCG= v, TCGv)) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + gen_helper_mult_acc(t0, cpu_env, t0, t1); + + gen_store_gpr(t0, a->rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return false; +} + +TRANS(MACC, trans_mult_acc, gen_helper_macc); +TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); +TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); +TRANS(MACCU, trans_mult_acc, gen_helper_maccu); --=20 2.31.1