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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id d5sm16604650wre.77.2021.08.08.10.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DbONOkwC1FwLLFkqMVdsgc91Qocspy7yIt/Uw3KVeaM=; b=iDkN610G7qca7QkPxxnD7VhJp35uapWdfbjqaClo98N6Mlglg1bK52C01h6Lf8lnoa nTp1Yh3QFFdIbWk9+12/ThTTLtHNs9g1sg6QAo3d6rCStT1Ib8tOIT08q+cjRbFNUcX0 ypxMa1yzJYL/zBSPxA/GuLM2RMOgRY7bbu4iGLxXIVlQndB07f979fwB++TnYez5BZ20 Pd4+rAz1fQmcZNSTZDYYLYMyRinPGodUKa3MLG56nIU1218+h9uTW9qW+3P3I9p3GYKN 3S/sHJ4pfnm2E7ZHapfM1l1o0fWtk/yALEiN0UUmdlaOfWZK3dSZVYRN8sd3WAxBeTR1 kcIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DbONOkwC1FwLLFkqMVdsgc91Qocspy7yIt/Uw3KVeaM=; b=nzH7bdZ3kC/qPfIk+djYwizDO3VkyAc/PO6TwwYa+wIRHgSvsdNgfRZ0m4jLdmhP3j 24o3hr/YQv5rjNwSJNx4bXyFLeVw/cstX5nN2j3kIc5mVEKrPAcas4wjmId1mIwi39wi 2v/L+WNOXoE0SsVLWFhNV2wbjHclbrMofPdW0JqEg24Yj4AHIY+T268RTFOmJ7hdin03 78OeKsrH4N5QN5S9cUJ0Cl44lBLWY5o7gCzFlUYu18j4JInPRTT3v1v3kTfO1QY3xSz6 l+JQ7jZ45VMm88XnNXYBTBBv8MAhth2ipwC0qYHxuB4r/Cu5iACmtj0BtbyAYYoWuO+C hYww== X-Gm-Message-State: AOAM5338gvdnK/b34LQc5c5Xnpgxn6RTk+xi9cZEw6zAV8lykP2c7n/4 x6yKJSjkdhr6eRW91LH3AFg= X-Google-Smtp-Source: ABdhPJykCkdO0POB1v9ivPKfsM9fu0Rkwf7f4mBdj+XPPNIKijYvNv/GpbrChvPOlMzrKHgf6j0rkg== X-Received: by 2002:a7b:cc8b:: with SMTP id p11mr29838912wma.164.1628443825102; Sun, 08 Aug 2021 10:30:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 1/7] target/mips: Introduce generic TRANS() macro for decodetree helpers Date: Sun, 8 Aug 2021 19:30:12 +0200 Message-Id: <20210808173018.90960-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443827643100001 Plain copy/paste of the TRANS() macro introduced in the PPC commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer loads to decodetree") to the MIPS target. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c25fad597d5..791e3e2c7e8 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,4 +202,12 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); #endif =20 +/* + * Helpers for implementing sets of trans_* functions. + * Defer the implementation of NAME to FUNC, with optional extra arguments. + */ +#define TRANS(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { return FUNC(ctx, a, __VA_ARGS__); } + #endif --=20 2.31.1 From nobody Fri May 17 07:55:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1628443831; cv=none; d=zohomail.com; s=zohoarc; b=eRV7AVWdpcweY/mUyJAWDRbYvsDarba+0gbUG5NsM1USa2Nc5yxbtBYuZCxZQVRnZru5M9JQ4ptf6FpqXPwH2hFE4rbH/sb6ioqwkaQ2epuHhsC4ZHls1CvU8OVSG+ixTXY2HaRDf+E43qP2pjHiHEM7od25w15AnA8mwFtY11s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628443831; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/eMBnlVY7aRA5TQWaHvUi3TTkCtDi3J83ziaggVBpSU=; b=i4THvmHjVfQpTDM0/r9XkuCSBv/nTyB2vuB2yqDtpyHLeXeDnA5fehuVWSo1Ad9PuHQUW3ouCdIUUzWmHvfLMKYgFihhfZ47YxjqsxUxyHj3kva0jKKBIsURCIOgGuk+olY4bztWvgFt/LAPFT3ZimCc6D/onAILjQGnWePJzSk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1628443831751541.3919610791726; Sun, 8 Aug 2021 10:30:31 -0700 (PDT) Received: by mail-wm1-f52.google.com with SMTP id l8-20020a05600c1d08b02902b5acf7d8b5so9132821wms.2 for ; Sun, 08 Aug 2021 10:30:31 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id y14sm4832738wrs.29.2021.08.08.10.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/eMBnlVY7aRA5TQWaHvUi3TTkCtDi3J83ziaggVBpSU=; b=h1QSnXtVDIQWZKoInEV29JJ6dUCbeE/dyihvNDbd56xVYxufD1OMi8kLGnHfx8dQnV pe0l2V1Edg5Hsflc2uVwtIHAIxESqR/dPaw/V/rAC2JzxL9qr5jkR338+aqKAMH4tJTa IUV+l/gqqmHDEJOXRuTyTkvpPpavmwv7I+g6RhkTmgvXgo9fTiAmKPQalPfRqwSWwI8+ eF8vidxVnc1wtKWcKzasSthlCjkhDs19JonLiW9ir9AphYGw8y/5YK3qMlk6FhfjXq1P Xbi4cHFJHwsMGmHGOPlVac1NNuEAX27ZI3Sm6AN1OePg1Ta0Ne59W/z0XTax0/Pn3XJT xwdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/eMBnlVY7aRA5TQWaHvUi3TTkCtDi3J83ziaggVBpSU=; b=od1ZYL+tFCNdwjXyXGT5DmBr3tY67q97vvyaZ2wIre7sS1Yi/Pm6rddDFaI0uYR0+h 5tpKdNduUNzUWnW4spK5YQaQGnSCmXxfFRew9b3ytzFi53GL4lD1vONb8OTJUoAM4scQ XVoBwS41cn9OAh+K1jy75mXmGjQRZpSdDQ8MHF63/azWFOV5Bo4RCS3ikBoCTUQEsjuR MnMddxUc8/Uzl9nm6YVIw+K9IOWK3p5Ji7p+ClqIdH5p1QEH4ZWh7HSdApO7OeouagPd N6C6WPD43N6yWzgze8tiAWblCW9PABWDp4/+yw6IKMmMtOEUkzSPDXGPBpotA0M9oY3G uX6Q== X-Gm-Message-State: AOAM532yRA/zgTFPuvJ16/NL1ljhSQdNaMVvS21iMcunwtu+NXQXl/NB ydCDOkz1PBa1hQSO41awFUgcxNx86DE= X-Google-Smtp-Source: ABdhPJwvmIikUvYK1r9JI+hHjtcvb/zV2WOel8S79j4JcMIjrFxbc8SYzXgmXrI8BfEVwLhIhXhxDg== X-Received: by 2002:a7b:c14a:: with SMTP id z10mr30573136wmi.36.1628443829973; Sun, 08 Aug 2021 10:30:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 2/7] target/mips: Extract NEC Vr54xx helper definitions Date: Sun, 8 Aug 2021 19:30:13 +0200 Message-Id: <20210808173018.90960-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443833607100001 Extract the NEC Vr54xx helper definitions to 'vendor-vr54xx_helper.h'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-15-f4bug@amsat.org> --- target/mips/helper.h | 18 +++--------------- target/mips/tcg/vr54xx_helper.h.inc | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 15 deletions(-) create mode 100644 target/mips/tcg/vr54xx_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index a9c6c7d1a31..de32d82e980 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -16,21 +16,6 @@ DEF_HELPER_3(lld, tl, env, tl, int) #endif #endif =20 -DEF_HELPER_3(muls, tl, env, tl, tl) -DEF_HELPER_3(mulsu, tl, env, tl, tl) -DEF_HELPER_3(macc, tl, env, tl, tl) -DEF_HELPER_3(maccu, tl, env, tl, tl) -DEF_HELPER_3(msac, tl, env, tl, tl) -DEF_HELPER_3(msacu, tl, env, tl, tl) -DEF_HELPER_3(mulhi, tl, env, tl, tl) -DEF_HELPER_3(mulhiu, tl, env, tl, tl) -DEF_HELPER_3(mulshi, tl, env, tl, tl) -DEF_HELPER_3(mulshiu, tl, env, tl, tl) -DEF_HELPER_3(macchi, tl, env, tl, tl) -DEF_HELPER_3(macchiu, tl, env, tl, tl) -DEF_HELPER_3(msachi, tl, env, tl, tl) -DEF_HELPER_3(msachiu, tl, env, tl, tl) - DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) #ifdef TARGET_MIPS64 DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) @@ -609,3 +594,6 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #endif /* !CONFIG_USER_ONLY */ =20 #include "tcg/msa_helper.h.inc" + +/* Vendor extensions */ +#include "tcg/vr54xx_helper.h.inc" diff --git a/target/mips/tcg/vr54xx_helper.h.inc b/target/mips/tcg/vr54xx_h= elper.h.inc new file mode 100644 index 00000000000..50b1f5b818d --- /dev/null +++ b/target/mips/tcg/vr54xx_helper.h.inc @@ -0,0 +1,24 @@ +/* + * MIPS NEC Vr54xx instruction emulation helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_3(muls, tl, env, tl, tl) +DEF_HELPER_3(mulsu, tl, env, tl, tl) +DEF_HELPER_3(macc, tl, env, tl, tl) +DEF_HELPER_3(maccu, tl, env, tl, tl) +DEF_HELPER_3(msac, tl, env, tl, tl) +DEF_HELPER_3(msacu, tl, env, tl, tl) +DEF_HELPER_3(mulhi, tl, env, tl, tl) +DEF_HELPER_3(mulhiu, tl, env, tl, tl) +DEF_HELPER_3(mulshi, tl, env, tl, tl) +DEF_HELPER_3(mulshiu, tl, env, tl, tl) +DEF_HELPER_3(macchi, tl, env, tl, tl) +DEF_HELPER_3(macchiu, tl, env, tl, tl) +DEF_HELPER_3(msachi, tl, env, tl, tl) +DEF_HELPER_3(msachiu, tl, env, tl, tl) --=20 2.31.1 From nobody Fri May 17 07:55:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1628443836; cv=none; d=zohomail.com; s=zohoarc; b=i/c1SoN3mFslURKOEEajdd1Fd6Qd7xR1KqUgaeI3vqm8U01ouGYgsQAxO2Lesoo9q74xyrdbe5kB+vWBHWkCMqsgrYvggkfa2WRuIOIy8TJroHd+OLdYFG+vD3dsBFTcx7QOuq4uK3WOy88cgL84Vb2MPDnIwVhf4QMoZWoUSwQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628443836; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y+Z+wzzxvnZ3+Pd2ULhHSg80v3gwgjV2sFikCRT73jM=; b=P/czp2NnEvp4zElfeXtVW6bb2IlVdGEvuDe2F2kBSM+kjE8trSzO5xHHpg0kGjs4a3/XCH4UXKU3XfSmlVLzxBxxpf5qO0Jnw0xq94Y6R5+uZAQmbGEBVccWSYgUb0u0btrZdSPpUhq4j8leFJjb6c/ffms40jH+Cn4bZaE+hKw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1628443836711588.2593424379864; Sun, 8 Aug 2021 10:30:36 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id f5so2426866wrm.13 for ; Sun, 08 Aug 2021 10:30:36 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id j2sm17090279wrd.14.2021.08.08.10.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y+Z+wzzxvnZ3+Pd2ULhHSg80v3gwgjV2sFikCRT73jM=; b=qyWHNHGfVdtl8yZn4bfIiHtmhAEATqNpNsGxZka/LmVS51m1G3OT38k1c8DSUKQ7Li hE2diO2839pNJDeM/g4DsMXZ5XLwi8FKfSZsU5VT54OWPrCsWRTP+PKllkr1nMYgCNv/ 6SkGN6/ZDHED/SK+1RCO5BNLUQVkTNnsYwMnsq0xp05ZLSOxJxNG4y4nKtaHw2o/7hdf uxvxBghKWrH3R5w3RDozhfWKl1K9J0+Qvk6588BqtTUZzPYfJfWy4uspHgAPXdgWCKki JHoihGSL2HAa2vqllYdBoYwfJQ/ns3U6hv451JuoUKgjY6NzsHGbIt0/vI/GEG4orurA MpVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=y+Z+wzzxvnZ3+Pd2ULhHSg80v3gwgjV2sFikCRT73jM=; b=nTgoAvwV/0qstTgeeA2gEtkWCwA0pCdbgkx5150oms60cGoi0jhY34U3u6MaBuQilr /ovpjBAZ1fu3Z27BCMzy+nWPRU7z8mbHDfm2yrVxtaXXnlPYg/yjOZ+hmcBFbco4jPTu T3mcndBoKJYciRU4iJmJlqv8ifgWQIRRvyEY+MfGTL1162spBU9cifN4ILrdeNbRWA1w vRcI5XxUKLtZauXWqVzBauX1kiGxihY5MVi574o470dc8TLhxpo9iu///I91xf8dA8z7 fETE/VOiEoZQ0/wQqd1GQbGBNIDXLoGTdkp7zXOnzptM3X4dFPXVcfwBJb5BupnfuGpj QSdQ== X-Gm-Message-State: AOAM5324gD76UZhcwAIEDTDi59pXngZlWftlGgULnPKqj8HxVDkoJV0N jvAZkysynyVh4HU3DblK5TE= X-Google-Smtp-Source: ABdhPJxTlp71X0dwI4nPDLSMebllLiBFZT2GObr233lJ3Gd+U9OJx26ZAbhD8RJd4qmVsn3PxWH5/g== X-Received: by 2002:a5d:62cd:: with SMTP id o13mr13819937wrv.93.1628443834823; Sun, 08 Aug 2021 10:30:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 3/7] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c Date: Sun, 8 Aug 2021 19:30:14 +0200 Message-Id: <20210808173018.90960-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443837788100001 Extract NEC Vr54xx helpers from op_helper.c to a new file: 'vr54xx_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-14-f4bug@amsat.org> --- target/mips/tcg/op_helper.c | 118 -------------------------- target/mips/tcg/vr54xx_helper.c | 142 ++++++++++++++++++++++++++++++++ target/mips/tcg/meson.build | 1 + 3 files changed, 143 insertions(+), 118 deletions(-) create mode 100644 target/mips/tcg/vr54xx_helper.c diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index fafbf1faca7..ef3dafcbb3f 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -26,124 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO(CPUMIPSState *env) -{ - return ((uint64_t)(env->active_tc.HI[0]) << 32) | - (uint32_t)env->active_tc.LO[0]; -} - -static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) -{ - env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFFFFF); - return env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); -} - -static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) -{ - target_ulong tmp =3D env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFF= FFF); - env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); - return tmp; -} - -/* Multiplication variants of the vr54xx. */ -target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2)); -} - -target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg= 2); -} - -target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - static inline target_ulong bitswap(target_ulong v) { v =3D ((v >> 1) & (target_ulong)0x5555555555555555ULL) | diff --git a/target/mips/tcg/vr54xx_helper.c b/target/mips/tcg/vr54xx_helpe= r.c new file mode 100644 index 00000000000..2255bd11163 --- /dev/null +++ b/target/mips/tcg/vr54xx_helper.c @@ -0,0 +1,142 @@ +/* + * MIPS VR5432 emulation helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO(CPUMIPSState *env) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; +} + +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) +{ + env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFFFFF); + return env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); +} + +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) +{ + target_ulong tmp =3D env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFF= FFF); + env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); + return tmp; +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); +} + +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 70fa3dd57df..ff618a159b7 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -18,6 +18,7 @@ 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', + 'vr54xx_helper.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', --=20 2.31.1 From nobody Fri May 17 07:55:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id r133sm22450337wma.18.2021.08.08.10.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RtJHpFNb3pDGfH1hMhE0K1VwxFwp2STcaYrJ+svwAgw=; b=neHQkExMc94ttBFy+MQheltVk03Absbo/P/vZV0SpN1ouszOVFVmnBU/INuOPbtRVy b4ZWzK8tcbDyFpxv3f8tgRgGtwvdDqW490LV0PQejjr9aEP8p6KOtfx4kcadtymb2t3K Kbsu7rltc1Suqdbi4ZN1CPuJ4FOPyW38cStDeVfwQBkL5yQXLkjvkM0KF+7EYjVHplYj cBskTHTbLMkCFpQcg9KrEa6Rgj4izgBl+CYCX64ruC1onazdsYKJTmEgECe6XKlHQy3Q c/2lou5fMkQh61IC+f7xw3X60caLEhdrJbeqOEVl7yaB5vbJJtgWjo+yX3IQ4X/PQ332 zyzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RtJHpFNb3pDGfH1hMhE0K1VwxFwp2STcaYrJ+svwAgw=; b=YiTHW+EjrApLxUQjDOw0hjd4GykTDAw8Ia+IV9JtrE3BF5wuB7KHK5r9qcCKsYzm8q 03a3sxez/k3KeC4z5oZeNIQFjeTzYGxoadwwDA8vm/5mIbOipwSFwKIemUkQ8XeTjcIx 6T5o1SDkyQh9z860qquyjYNRcNeeNBwPIwLp7X5CMXRQzLxuRh6LKciYUZhtvu84h4WN qSsp8y3p60IuFk1e2stuIiPVPOKlP3p9GCpeRT4bgvmgO18zv/lLClBUKeyi359Q3rB/ OiWBgemupjHdm4nbTH6KZq6kgXuDnk3l+8To++pwH2uJcF7QKc0dcjeZEWzXJv+2yxwR 1HEg== X-Gm-Message-State: AOAM530MTBug2Kyh8AuGcFTVi1BEyIUGf2j2N8MVJam3UXm7j8Vj6un5 b3XkSOMj6EmP2aNstnLH33A= X-Google-Smtp-Source: ABdhPJx5mytG2VqTnBaSk6ybj4N3z2QhO0SzvUmrRiooOic9AIhobRqAah9RDgo7xC6+kFV90Y4jeA== X-Received: by 2002:a7b:c0c6:: with SMTP id s6mr6568888wmh.21.1628443840264; Sun, 08 Aug 2021 10:30:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 4/7] target/mips: Introduce decodetree structure for NEC Vr54xx extension Date: Sun, 8 Aug 2021 19:30:15 +0200 Message-Id: <20210808173018.90960-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443844028100001 The decoder is called but doesn't decode anything. This will ease reviewing the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210801235926.3178085-3-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 1 + target/mips/tcg/vr54xx.decode | 8 ++++++++ target/mips/tcg/translate.c | 3 +++ target/mips/tcg/vr54xx_translate.c | 19 +++++++++++++++++++ target/mips/tcg/meson.build | 2 ++ 5 files changed, 33 insertions(+) create mode 100644 target/mips/tcg/vr54xx.decode create mode 100644 target/mips/tcg/vr54xx_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 791e3e2c7e8..bb0a6b8d74f 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -201,6 +201,7 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); #endif +bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); =20 /* * Helpers for implementing sets of trans_* functions. diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode new file mode 100644 index 00000000000..f6b3e42c999 --- /dev/null +++ b/target/mips/tcg/vr54xx.decode @@ -0,0 +1,8 @@ +# MIPS VR5432 instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VR5432 Microprocessor User=E2=80=99s Manual +# (Document Number U13751EU5V0UM00) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 490add3fc15..34363639937 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16098,6 +16098,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { return; } + if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->= opcode)) { + return; + } =20 /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c new file mode 100644 index 00000000000..13e58fdd8df --- /dev/null +++ b/target/mips/tcg/vr54xx_translate.c @@ -0,0 +1,19 @@ +/* + * VR5432 extensions translation routines + * + * Reference: VR5432 Microprocessor User=E2=80=99s Manual + * (Document Number U13751EU5V0UM00) + * + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "internal.h" + +/* Include the auto-generated decoder. */ +#include "decode-vr54xx.c.inc" diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index ff618a159b7..8f6f7508b66 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -2,6 +2,7 @@ decodetree.process('rel6.decode', extra_args: ['--decode=3Ddecode_isa_re= l6']), decodetree.process('msa.decode', extra_args: '--decode=3Ddecode_ase_msa'= ), decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), + decodetree.process('vr54xx.decode', extra_args: '--decode=3Ddecode_ext_v= r54xx'), ] =20 mips_ss.add(gen) @@ -19,6 +20,7 @@ 'translate_addr_const.c', 'txx9_translate.c', 'vr54xx_helper.c', + 'vr54xx_translate.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', --=20 2.31.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id d7sm16794868wrs.39.2021.08.08.10.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Aug 2021 10:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Ip7dNqBR9CCs37W148txuk2ntTuwtUF2p4pRZfBcEc=; b=POJXZoKM49dhjifHYhA54TernPftxyeGVFHAU3EfjFjRDzLg00rmvBZvSg01EK1N0X o5BoUYVhSUHiG9DMR3BVxkhUBIKpK8sZ8tZJePTa4z/sg3zkY25KgfSDgXVcSHPkRLXx q4MkNlUuaWulBOiWW1wYXrlfXUDqqPe/eTFlxICKTScrpptE7G46gC61FyAi1AhzFOWv TlYc5lWYoxADXHQtTHFpHJAxOtKhhyV/1JEwvKDzdQhsK/yyThqGwCiEfqVUSbNoTxeR xZ/2VR44i5W7WdHAdEXdo/rEDhOFfZrd52oXPdvtEFT4fFuVIfsYD/lcnrPlmPILV3Ap UP7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2Ip7dNqBR9CCs37W148txuk2ntTuwtUF2p4pRZfBcEc=; b=mVJEZbq6R00M6Fw0YANae+J22IFcGAGN6+8WxOMklIgxxkLAsYMRdayAUEy/aaDJcL YOdlYRg9swaFtb4dJngA3l5Go4QkzoYZUyEZrZQIirpS6JU3A6nTW8zD0S+3+oyc8LLn kjPlf2wtZEAoQN7NghedZwvcX0pds47FgyA/WxnPvnkq41F1PiIcM7iM18HqlDg7Qlff Je3jmsSDOwhXXm1rCcu/3t6DJz8duc4RYI8HNgVVYkaSzcipAMwT6GAOpx3VGID0KNTX DXE4BGX1MJkaQ2H4nlSAAV7SB/YSXWrFpwTlX9UAtoB1+pPedq4Qgk2OC14PkQEQayxh HOfw== X-Gm-Message-State: AOAM530lCLngPoHOVV5LoTKn01r8VQb2PrkQzZTfwildAxYLft130X7K zBFbBAF/QXFKhDaS5K0V6os= X-Google-Smtp-Source: ABdhPJyIFEPwW3Hs9yxY4z5a1DYi+lrKoMTi8GP64+mayczuiAan5beEBxPlaFoYXvEYB4PFiNEoAQ== X-Received: by 2002:a05:6000:10c6:: with SMTP id b6mr21125723wrx.110.1628443845785; Sun, 08 Aug 2021 10:30:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Matheus Ferst , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 v3 5/7] target/mips: Convert Vr54xx MACC* opcodes to decodetree Date: Sun, 8 Aug 2021 19:30:16 +0200 Message-Id: <20210808173018.90960-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808173018.90960-1-f4bug@amsat.org> References: <20210808173018.90960-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443848486100001 Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/vr54xx.decode | 9 ++++++++ target/mips/tcg/translate.c | 16 --------------- target/mips/tcg/vr54xx_translate.c | 33 ++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index f6b3e42c999..73778f101a5 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -6,3 +6,12 @@ # # Reference: VR5432 Microprocessor User=E2=80=99s Manual # (Document Number U13751EU5V0UM00) + +&r rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r + +MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd +MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd +MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 34363639937..fd8ffadf06e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -300,16 +300,12 @@ enum { enum { OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, }; @@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; @@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 13e58fdd8df..0e2d460c985 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -17,3 +17,36 @@ =20 /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" + +/* + * Integer Multiply-Accumulate Instructions + * + * MACC Multiply, accumulate, and move LO + * MACCHI Multiply, accumulate, and move HI + * MACCHIU Unsigned multiply, accumulate, and move HI + * MACCU Unsigned multiply, accumulate, and move LO + */ + +static bool trans_mult_acc(DisasContext *ctx, arg_r *a, + void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCG= v, TCGv)) +{ + TCGv t0 =3D tcg_temp_new(); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443854443100001 Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/vr54xx.decode | 6 ++++++ target/mips/tcg/translate.c | 24 ------------------------ target/mips/tcg/vr54xx_translate.c | 12 ++++++++++++ 3 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 73778f101a5..79bb5175eab 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -11,7 +11,13 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r =20 +MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd +MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd +MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd +MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd +MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd8ffadf06e..4b7f2d9ae8b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -298,14 +298,8 @@ enum { #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) =20 enum { - OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, - OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, - OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, - OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, - OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, }; @@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint3= 2_t opc, gen_load_gpr(t1, rt); =20 switch (opc) { - case OPC_VR54XX_MULS: - gen_helper_muls(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; case OPC_VR54XX_MSACU: gen_helper_msacu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 0e2d460c985..9f35b2c7e5d 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,12 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MULHI Multiply and move HI + * MULHIU Unsigned multiply and move HI + * MULS Multiply, negate, and move LO + * MULSHI Multiply, negate, and move HI + * MULSHIU Unsigned multiply, negate, and move HI + * MULSU Unsigned multiply, negate, and move LO */ =20 static bool trans_mult_acc(DisasContext *ctx, arg_r *a, @@ -50,3 +56,9 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc); TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); TRANS(MACCU, trans_mult_acc, gen_helper_maccu); +TRANS(MULHI, trans_mult_acc, gen_helper_mulhi); +TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu); +TRANS(MULS, trans_mult_acc, gen_helper_muls); +TRANS(MULSHI, trans_mult_acc, gen_helper_mulshi); +TRANS(MULSHIU, trans_mult_acc, gen_helper_mulshiu); +TRANS(MULSU, trans_mult_acc, gen_helper_mulsu); --=20 2.31.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1628443857; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1628443858609100001 Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/vr54xx.decode | 4 +++ target/mips/tcg/translate.c | 55 ++---------------------------- target/mips/tcg/vr54xx_translate.c | 8 +++++ 3 files changed, 14 insertions(+), 53 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 79bb5175eab..4fc708d80ae 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -15,9 +15,13 @@ MULS 000000 ..... ..... ..... 00011011000 = @rs_rt_rd MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd +MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd +MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd +MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4b7f2d9ae8b..30780deb96f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -294,16 +294,6 @@ enum { R6_OPC_SDBBP =3D 0x0e | OPC_SPECIAL, }; =20 -/* Multiplication variants of the vr54xx. */ -#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) - -enum { - OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, - OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, - OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, -}; - /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16= ))) =20 @@ -3754,40 +3744,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t= opc, tcg_temp_free(t1); } =20 -static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_VR54XX_MSAC: - gen_helper_msac(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, cpu_env, t0, t1); - break; - default: - MIPS_INVAL("mul vr54xx"); - gen_reserved_instruction(ctx); - goto out; - } - gen_store_gpr(t0, rd); - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_cl(DisasContext *ctx, uint32_t opc, int rd, int rs) { @@ -14104,13 +14060,12 @@ static void decode_opc_special_tx79(CPUMIPSState = *env, DisasContext *ctx) =20 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) { - int rs, rt, rd, sa; + int rs, rt, rd; uint32_t op1; =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; rd =3D (ctx->opcode >> 11) & 0x1f; - sa =3D (ctx->opcode >> 6) & 0x1f; =20 op1 =3D MASK_SPECIAL(ctx->opcode); switch (op1) { @@ -14140,13 +14095,7 @@ static void decode_opc_special_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_MULT: case OPC_MULTU: - if (sa) { - check_insn(ctx, INSN_VR54XX); - op1 =3D MASK_MUL_VR54XX(ctx->opcode); - gen_mul_vr54xx(ctx, op1, rd, rs, rt); - } else { - gen_muldiv(ctx, op1, rd & 3, rs, rt); - } + gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_DIV: case OPC_DIVU: diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 9f35b2c7e5d..3e2c98f2c6a 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,10 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MSAC Multiply, negate, accumulate, and move LO + * MSACHI Multiply, negate, accumulate, and move HI + * MSACHIU Unsigned multiply, negate, accumulate, and move HI + * MSACU Unsigned multiply, negate, accumulate, and move LO * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO @@ -56,6 +60,10 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc); TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); TRANS(MACCU, trans_mult_acc, gen_helper_maccu); +TRANS(MSAC, trans_mult_acc, gen_helper_msac); +TRANS(MSACHI, trans_mult_acc, gen_helper_msachi); +TRANS(MSACHIU, trans_mult_acc, gen_helper_msachiu); +TRANS(MSACU, trans_mult_acc, gen_helper_msacu); TRANS(MULHI, trans_mult_acc, gen_helper_mulhi); TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu); TRANS(MULS, trans_mult_acc, gen_helper_muls); --=20 2.31.1