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[142.114.143.47]) by smtp.googlemail.com with ESMTPSA id d28sm3655195qkj.25.2021.08.05.15.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Aug 2021 15:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oINuPGEcryVgocqWb2UboVny7kYUXzklLGzq6cJvadg=; b=RzXdWhhdMc8Ib9vJMThsDDAPhXD2DlvlzJs3fYciXVdd2ZrzR+iFeBTL97XSHXBKOw e9LzkFQvwv3He4R8Gh5AYpHrrkgythrutNk3SC/s4V/9kUK96R0xWASgSpsDl/NBUEdz rtlab6C7iLD9vHgEeGBXlbqkRHwI3uNfDQWKBLXXbQyAA5w1GHn96kIJPkx+hV5soJb1 hznilmdCrJLNEcfrNXS3WJZbmAcWnsTd/0DH6hKgrqjZgkrc26pSJnnztpGkOy+IsQOF 9wBDi57v9gfqDKPKB+HzwREUXuKRKTyFuCu4wKI8gc0x9ozEuhSeS/W55jHfXkIyquwS v2YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oINuPGEcryVgocqWb2UboVny7kYUXzklLGzq6cJvadg=; b=k7CtVysFnJL34Zq9CuL+yiAMA9HeGukwqzovijcO5RKG8KriUkwVI9kgkujDKbVSNk eWGdyV5rU2hxMGg+xolzelYZ+/B1qGHAuPUAZDjy0TSQtcfd08iKQY1GKqz8Snm6UX0e dgEXkJbp8PR22g3kpCRj5gu2H+S6weaJus2hx7+o5GSNOq6wG053mPLX8fnLKsVtDhUo 7mQy3DZeiMoSQYc2H9ZCLRuQZYsnhD4MsHRCSS8bKJ7QGCUue0XRkSKBcG4c12N5o9G4 fkOr+9ot0LrsZdr5139cIwwm2muKUtzFaFXhRtSkQjX2of7iHCu0AhKwdVAG3+FWNncU psKw== X-Gm-Message-State: AOAM531Qa43kZSXzVM2mFfAC5jcHuIYQOy1xWioYdH5KQsAWWOf1X/Rf T56NZ1e/cEDuVNNHq2xtmMlX6Q== X-Google-Smtp-Source: ABdhPJydvWkuQSDiuOGsWUW+QUGUeD5Q+yQBjgb5D0x+OkFH+IajyPL6qMfYN3BAnPPKf4m0UMCEmg== X-Received: by 2002:a05:620a:5f6:: with SMTP id z22mr7191832qkg.195.1628202607012; Thu, 05 Aug 2021 15:30:07 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com, mst@redhat.com, imammedo@redhat.com Subject: [PATCH v7 05/10] hw/intc: GICv3 ITS Feature enablement Date: Thu, 5 Aug 2021 18:29:57 -0400 Message-Id: <20210805223002.144855-6-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210805223002.144855-1-shashi.mallela@linaro.org> References: <20210805223002.144855-1-shashi.mallela@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: eric.auger@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628202739928100001 Content-Type: text/plain; charset="utf-8" Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Tested-by: Neil Armstrong --- hw/intc/arm_gicv3_common.c | 12 ++++++++++++ hw/intc/arm_gicv3_dist.c | 5 ++++- hw/intc/arm_gicv3_redist.c | 12 +++++++++--- hw/intc/gicv3_internal.h | 2 ++ include/hw/intc/arm_gicv3_common.h | 1 + 5 files changed, 28 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 58ef65f589..53dea2a775 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,= Error **errp) return; } =20 + if (s->lpi_enable && !s->dma) { + error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not se= t"); + return; + } + s->cpu =3D g_new0(GICv3CPUState, s->num_cpu); =20 for (i =3D 0; i < s->num_cpu; i++) { @@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,= Error **errp) (1 << 24) | (i << 8) | (last << 4); + + if (s->lpi_enable) { + s->cpu[i].gicr_typer |=3D GICR_TYPER_PLPIS; + } } } =20 @@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), + DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), + DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, + MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index b65f56f903..43128b376d 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -371,7 +371,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, * A3V =3D=3D 1 (non-zero values of Affinity level 3 supported) * IDbits =3D=3D 0xf (we support 16-bit interrupt identifiers) * DVIS =3D=3D 0 (Direct virtual LPI injection not supported) - * LPIS =3D=3D 0 (LPIs not supported) + * LPIS =3D=3D 1 (LPIs are supported if affinity routing is enable= d) + * num_LPIs =3D=3D 0b00000 (bits [15:11],Number of LPIs as indicat= ed + * by GICD_TYPER.IDbits) * MBIS =3D=3D 0 (message-based SPIs not supported) * SecurityExtn =3D=3D 1 if security extns supported * CPUNumber =3D=3D 0 since for us ARE is always 1 @@ -386,6 +388,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr off= set, bool sec_extn =3D !(s->gicd_ctlr & GICD_CTLR_DS); =20 *data =3D (1 << 25) | (1 << 24) | (sec_extn << 10) | + (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | (0xf << 19) | itlinesnumber; return MEMTX_OK; } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 53da703ed8..2108abfe9c 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwa= ddr offset, case GICR_CTLR: /* For our implementation, GICR_TYPER.DPGS is 0 and so all * the DPG bits are RAZ/WI. We don't do anything asynchronously, - * so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't - * implement LPIs) so Enable_LPIs is RES0. So there are no writable - * bits for us. + * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we + * implement LPIs) so Enable_LPIs is programmable. */ + if (cs->gicr_typer & GICR_TYPER_PLPIS) { + if (value & GICR_CTLR_ENABLE_LPIS) { + cs->gicr_ctlr |=3D GICR_CTLR_ENABLE_LPIS; + } else { + cs->gicr_ctlr &=3D ~GICR_CTLR_ENABLE_LPIS; + } + } return MEMTX_OK; case GICR_STATUSR: /* RAZ/WI for our implementation */ diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 1966444790..530d1c1789 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -68,6 +68,8 @@ #define GICD_CTLR_E1NWF (1U << 7) #define GICD_CTLR_RWP (1U << 31) =20 +#define GICD_TYPER_LPIS_SHIFT 17 + /* 16 bits EventId */ #define GICD_TYPER_IDBITS 0xf =20 diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 0715b0bc2a..c1348cc60a 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -221,6 +221,7 @@ struct GICv3State { uint32_t num_cpu; uint32_t num_irq; uint32_t revision; + bool lpi_enable; bool security_extn; bool irq_reset_nonsecure; bool gicd_no_migration_shift_bug; --=20 2.27.0