From nobody Mon Feb 9 12:14:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628186269748245.34722784605833; Thu, 5 Aug 2021 10:57:49 -0700 (PDT) Received: from localhost ([::1]:38112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBhcq-00017z-Gr for importer@patchew.org; Thu, 05 Aug 2021 13:57:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc3-0007de-8L; Thu, 05 Aug 2021 13:56:59 -0400 Received: from exmail.andestech.com ([60.248.187.195]:49199 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhbz-0007nC-VA; Thu, 05 Aug 2021 13:56:58 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 175HuUWc055927; Fri, 6 Aug 2021 01:56:30 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 6 Aug 2021 01:56:31 +0800 From: Ruinland Chuan-Tzu Tsai To: , Subject: [RFC PATCH v4 1/4] Add options to config/meson files for custom CSR Date: Fri, 6 Aug 2021 01:56:23 +0800 Message-ID: <20210805175626.11573-2-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20210805175626.11573-1-ruinland@andestech.com> References: <20210805175626.11573-1-ruinland@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HuUWc055927 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, wangjunqiang@iscas.ac.cn, bin.meng@windriver.com, Dylan Jhong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628186272659100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ruinland ChuanTzu Tsai Adding option `riscv_custom` to configure script, meson.build and meson_options.txt so as to toggle custom CSR and will-be-upstreamed custom instructions handling logic. Signed-off-by: Dylan Jhong --- configure | 6 ++++++ meson.build | 2 ++ meson_options.txt | 2 ++ 3 files changed, 10 insertions(+) diff --git a/configure b/configure index 34fccaa..88f6584 100755 --- a/configure +++ b/configure @@ -324,6 +324,7 @@ virtiofsd=3D"auto" virtfs=3D"auto" libudev=3D"auto" mpath=3D"auto" +riscv_custom=3D"auto" vnc=3D"enabled" sparse=3D"auto" vde=3D"$default_feature" @@ -1016,6 +1017,10 @@ for opt do ;; --enable-vnc) vnc=3D"enabled" ;; + --enable-riscv-custom) riscv_custom=3D"enabled" + ;; + --disable-riscv-custom) riscv_custom=3D"disabled" + ;; --disable-gettext) gettext=3D"disabled" ;; --enable-gettext) gettext=3D"enabled" @@ -6416,6 +6421,7 @@ NINJA=3D$ninja $meson setup \ -Dcocoa=3D$cocoa -Dgtk=3D$gtk -Dmpath=3D$mpath -Dsdl=3D$sdl -Dsdl_= image=3D$sdl_image \ -Dvnc=3D$vnc -Dvnc_sasl=3D$vnc_sasl -Dvnc_jpeg=3D$vnc_jpeg -Dvnc_p= ng=3D$vnc_png \ -Dgettext=3D$gettext -Dxkbcommon=3D$xkbcommon -Du2f=3D$u2f -Dvirti= ofsd=3D$virtiofsd \ + -Driscv_custom=3D$riscv_custom \ -Dcapstone=3D$capstone -Dslirp=3D$slirp -Dfdt=3D$fdt -Dbrlapi=3D$b= rlapi \ -Dcurl=3D$curl -Dglusterfs=3D$glusterfs -Dbzip2=3D$bzip2 -Dlibiscs= i=3D$libiscsi \ -Dlibnfs=3D$libnfs -Diconv=3D$iconv -Dcurses=3D$curses -Dlibudev= =3D$libudev\ diff --git a/meson.build b/meson.build index adeec15..736810e 100644 --- a/meson.build +++ b/meson.build @@ -1151,6 +1151,7 @@ config_host_data.set('HAVE_SYS_KCOV_H', cc.has_header= ('sys/kcov.h')) config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', pre= fix: '#include ')) =20 config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#= include ')) +config_host_data.set('CONFIG_RISCV_CUSTOM', get_option('riscv_custom').ena= bled()) =20 ignored =3D ['CONFIG_QEMU_INTERP_PREFIX'] # actually per-target arrays =3D ['CONFIG_AUDIO_DRIVERS', 'CONFIG_BDRV_RW_WHITELIST', 'CONFIG_BD= RV_RO_WHITELIST'] @@ -2694,6 +2695,7 @@ summary_info +=3D {'libpmem support': config_host.h= as_key('CONFIG_LIBPMEM')} summary_info +=3D {'libdaxctl support': config_host.has_key('CONFIG_LIBDAX= CTL')} summary_info +=3D {'libudev': libudev.found()} summary_info +=3D {'FUSE lseek': fuse_lseek.found()} +summary_info +=3D {'RISC-V custom CSRs/instructions': get_option('riscv_cu= stom').enabled()} summary(summary_info, bool_yn: true, section: 'Dependencies') =20 if not supported_cpus.contains(cpu) diff --git a/meson_options.txt b/meson_options.txt index 9734019..470ef23 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -125,3 +125,5 @@ option('slirp', type: 'combo', value: 'auto', option('fdt', type: 'combo', value: 'auto', choices: ['disabled', 'enabled', 'auto', 'system', 'internal'], description: 'Whether and how to find the libfdt library') +option('riscv_custom', type: 'feature', value: 'auto', + description: 'RISC-V custom') --=20 2.32.0 From nobody Mon Feb 9 12:14:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628186327310429.147446078778; Thu, 5 Aug 2021 10:58:47 -0700 (PDT) Received: from localhost ([::1]:41758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBhdm-0003YR-5U for importer@patchew.org; Thu, 05 Aug 2021 13:58:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc3-0007df-C1; Thu, 05 Aug 2021 13:56:59 -0400 Received: from exmail.andestech.com ([60.248.187.195]:33388 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhbz-0007r5-Ui; Thu, 05 Aug 2021 13:56:58 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 175HuZhD055945; Fri, 6 Aug 2021 01:56:35 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 6 Aug 2021 01:56:37 +0800 From: Ruinland Chuan-Tzu Tsai To: , Subject: [RFC PATCH v4 2/4] Adding basic custom/vendor CSR handling mechanism Date: Fri, 6 Aug 2021 01:56:24 +0800 Message-ID: <20210805175626.11573-3-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20210805175626.11573-1-ruinland@andestech.com> References: <20210805175626.11573-1-ruinland@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HuZhD055945 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, wangjunqiang@iscas.ac.cn, bin.meng@windriver.com, Dylan Jhong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628186327853100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ruinalnd ChuanTzu Tsai For now we add a custom CSR handling mechanism to handle non-standard CSR r= ead or write. The write_stub() and read_zero() are provided for quick placeholder usage if such CSRs' behavior are expected to fail-over in its user code. Signed-off-by: Dylan Jhong --- target/riscv/cpu.c | 23 ++++++++++ target/riscv/cpu.h | 31 ++++++++++++- target/riscv/cpu_bits.h | 4 ++ target/riscv/csr.c | 83 ++++++++++++++++++++++++++++------ target/riscv/custom_cpu_bits.h | 8 ++++ 5 files changed, 134 insertions(+), 15 deletions(-) create mode 100644 target/riscv/custom_cpu_bits.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7401325..3a638b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -144,6 +144,29 @@ static void set_resetvec(CPURISCVState *env, target_ul= ong resetvec) #endif } =20 +#if defined(CONFIG_RISCV_CUSTOM) +static void setup_custom_csr(CPURISCVState *env, + riscv_custom_csr_operations csr_map_struct[] + ) { + + env->custom_csr_map =3D g_hash_table_new_full(g_direct_hash, \ + g_direct_equal, \ + NULL, NULL); + + + int i; + for (i =3D 0; i < MAX_CUSTOM_CSR_NUM; i++) { + if (csr_map_struct[i].csrno !=3D 0) { + g_hash_table_insert(env->custom_csr_map, + GINT_TO_POINTER(csr_map_struct[i].csrno), + &csr_map_struct[i].csr_opset); + } else { + break; + } + } +} +#endif + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb282..52df9bb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -239,6 +239,16 @@ struct CPURISCVState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + + /* + * The reason why we have an opset map for custom CSRs and a seperated + * storage map is that we might have heterogeneous architecture, in wh= ich + * different harts have different custom CSRs. + * Custom CSR opset map + */ + GHashTable *custom_csr_map; + /* Custom CSR val holder */ + void *custom_csr_val; }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, @@ -485,17 +495,36 @@ typedef struct { riscv_csr_op_fn op; } riscv_csr_operations; =20 +typedef struct { + int csrno; + riscv_csr_operations csr_opset; + } riscv_custom_csr_operations; + +/* + * The reason why we have an abstraction here is that : We could have CSR + * number M on hart A is an alias of CSR number N on hart B. So we make a + * CSR number to value address map. + */ +typedef struct { + int csrno; + target_ulong val; + } riscv_custom_csr_vals; + /* CSR function table constants */ enum { - CSR_TABLE_SIZE =3D 0x1000 + CSR_TABLE_SIZE =3D 0x1000, + MAX_CUSTOM_CSR_NUM =3D 100 }; =20 /* CSR function table */ +extern int andes_custom_csr_size; +extern riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_N= UM]; extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); =20 + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599..de77242 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -593,3 +593,7 @@ #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) #endif + +#if defined(CONFIG_RISCV_CUSTOM) +#include "custom_cpu_bits.h" +#endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e636..1c4dc94 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -137,7 +137,8 @@ static int ctr32(CPURISCVState *env, int csrno) return ctr(env, csrno); } =20 -#if !defined(CONFIG_USER_ONLY) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" static int any(CPURISCVState *env, int csrno) { return 0; @@ -152,6 +153,25 @@ static int any32(CPURISCVState *env, int csrno) return any(env, csrno); =20 } +#pragma GCC diagnostic pop + +/* Machine Information Registers */ +static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) +{ + return *val =3D 0; +} + +/* + * XXX: This is just a write stub for developing custom CSR handler, + * if the behavior of writting such CSR is not presentable in QEMU and doe= sn't + * affect the functionality, just stub it. + */ +static int write_stub(CPURISCVState *env, int csrno, target_ulong val) +{ + return 0; +} + +#if !defined(CONFIG_USER_ONLY) =20 static int smode(CPURISCVState *env, int csrno) { @@ -435,11 +455,6 @@ static const char valid_vm_1_10_64[16] =3D { [VM_1_10_SV57] =3D 1 }; =20 -/* Machine Information Registers */ -static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) -{ - return *val =3D 0; -} =20 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1264,6 +1279,18 @@ static int write_pmpaddr(CPURISCVState *env, int csr= no, target_ulong val) =20 #endif =20 + +#if defined(CONFIG_RISCV_CUSTOM) +/* Custom CSR related routines and data structures */ + +static gpointer is_custom_csr(CPURISCVState *env, int csrno) +{ + gpointer ret; + ret =3D g_hash_table_lookup(env->custom_csr_map, GINT_TO_POINTER(csrno= )); + return ret; +} +#endif + /* * riscv_csrrw - read and/or update control and status register * @@ -1273,12 +1300,19 @@ static int write_pmpaddr(CPURISCVState *env, int cs= rno, target_ulong val) * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); */ =20 + + int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); + #if !defined(CONFIG_RISCV_CUSTOM) + riscv_csr_operations *csrop =3D &csr_ops[csrno]; + #else + riscv_csr_operations *csrop; + #endif =20 /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) @@ -1300,6 +1334,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { return -RISCV_EXCP_ILLEGAL_INST; } + #endif =20 /* ensure the CSR extension is enabled. */ @@ -1307,27 +1342,43 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return -RISCV_EXCP_ILLEGAL_INST; } =20 + /* try handle_custom_csr */ + + #if defined(CONFIG_RISCV_CUSTOM) + if (unlikely(env->custom_csr_map !=3D NULL)) { + riscv_csr_operations *custom_csr_opset =3D (riscv_csr_operations *) + is_custom_csr(env, csrno); + if (NULL !=3D custom_csr_opset) { + csrop =3D custom_csr_opset; + } else { + csrop =3D &csr_ops[csrno]; + } + } else { + csrop =3D &csr_ops[csrno]; + } + #endif + /* check predicate */ - if (!csr_ops[csrno].predicate) { + if (!csrop->predicate) { return -RISCV_EXCP_ILLEGAL_INST; } - ret =3D csr_ops[csrno].predicate(env, csrno); + ret =3D csrop->predicate(env, csrno); if (ret < 0) { return ret; } =20 /* execute combined read/write operation if it exists */ - if (csr_ops[csrno].op) { - return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); + if (csrop->op) { + return csrop->op(env, csrno, ret_value, new_value, write_mask); } =20 /* if no accessor exists then return failure */ - if (!csr_ops[csrno].read) { + if (!csrop->read) { return -RISCV_EXCP_ILLEGAL_INST; } =20 /* read old value */ - ret =3D csr_ops[csrno].read(env, csrno, &old_value); + ret =3D csrop->read(env, csrno, &old_value); if (ret < 0) { return ret; } @@ -1335,8 +1386,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, /* write value if writable and write mask set, otherwise drop writes */ if (write_mask) { new_value =3D (old_value & ~write_mask) | (new_value & write_mask); - if (csr_ops[csrno].write) { - ret =3D csr_ops[csrno].write(env, csrno, new_value); + if (csrop->write) { + ret =3D csrop->write(env, csrno, new_value); if (ret < 0) { return ret; } @@ -1369,6 +1420,10 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno,= target_ulong *ret_value, return ret; } =20 +#if defined(CONFIG_RISCV_CUSTOM) +/* Include the custom CSR table here. */ +#endif + /* Control and Status Register function table */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ diff --git a/target/riscv/custom_cpu_bits.h b/target/riscv/custom_cpu_bits.h new file mode 100644 index 0000000..5df31f8 --- /dev/null +++ b/target/riscv/custom_cpu_bits.h @@ -0,0 +1,8 @@ +/* + * RISC-V cpu bits for custom CSR logic. + * + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This file is intentionally left blank at this commit. */ --=20 2.32.0 From nobody Mon Feb 9 12:14:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628186459911337.16512138867097; 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Fri, 6 Aug 2021 01:56:43 +0800 From: Ruinland Chuan-Tzu Tsai To: , Subject: [RFC PATCH v4 3/4] Adding Andes AX25 and A25 CPU model Date: Fri, 6 Aug 2021 01:56:25 +0800 Message-ID: <20210805175626.11573-4-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20210805175626.11573-1-ruinland@andestech.com> References: <20210805175626.11573-1-ruinland@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HuewN055963 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, wangjunqiang@iscas.ac.cn, bin.meng@windriver.com, Dylan Jhong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628186460707100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ruinalnd ChuanTzu Tsai Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without enhanced features (yet). Signed-off-by: Dylan Jhong --- target/riscv/cpu.c | 16 ++++++++++++++++ target/riscv/cpu.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3a638b5..9eb1e3a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -182,6 +182,13 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, RV64); } =20 +static void ax25_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} + static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -235,6 +242,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } + +static void a25_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -726,8 +740,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 52df9bb..bd79d63 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -37,6 +37,8 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") --=20 2.32.0 From nobody Mon Feb 9 12:14:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628186278721329.39202545057856; Thu, 5 Aug 2021 10:57:58 -0700 (PDT) Received: from localhost ([::1]:38676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBhcz-0001VR-Hz for importer@patchew.org; Thu, 05 Aug 2021 13:57:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc7-0007lR-3P; Thu, 05 Aug 2021 13:57:03 -0400 Received: from exmail.andestech.com ([60.248.187.195]:59956 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBhc3-0007xQ-P6; Thu, 05 Aug 2021 13:57:02 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 175HukI5055986; Fri, 6 Aug 2021 01:56:46 +0800 (GMT-8) (envelope-from ruinland@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 6 Aug 2021 01:56:46 +0800 From: Ruinland Chuan-Tzu Tsai To: , Subject: [RFC PATCH v4 4/4] Enable custom CSR logic for Andes AX25 and A25 Date: Fri, 6 Aug 2021 01:56:26 +0800 Message-ID: <20210805175626.11573-5-ruinland@andestech.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20210805175626.11573-1-ruinland@andestech.com> References: <20210805175626.11573-1-ruinland@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 175HukI5055986 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, wangjunqiang@iscas.ac.cn, bin.meng@windriver.com, Dylan Jhong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1628186280070100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ruinalnd ChuanTzu Tsai In this patch we enabled custom CSR logic for Andes AX25 and A25 logic. Hence csr_andes.inc.c and andes_cpu_bits.h is added. Signed-off-by: Dylan Jhong --- target/riscv/andes_cpu_bits.h | 124 +++++++++++++++++++++++++ target/riscv/cpu.c | 12 +++ target/riscv/csr.c | 2 +- target/riscv/csr_andes.inc.c | 160 +++++++++++++++++++++++++++++++++ target/riscv/custom_cpu_bits.h | 6 +- 5 files changed, 302 insertions(+), 2 deletions(-) create mode 100644 target/riscv/andes_cpu_bits.h create mode 100644 target/riscv/csr_andes.inc.c diff --git a/target/riscv/andes_cpu_bits.h b/target/riscv/andes_cpu_bits.h new file mode 100644 index 0000000..bd2b7d1 --- /dev/null +++ b/target/riscv/andes_cpu_bits.h @@ -0,0 +1,124 @@ +/* + * Andes custom CSRs bit definitions + * + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D Missing drafted/standard CSR definitions */ +/* Although TINFO is in official debug sepc, it's not in cpu_bits.h yet. */ +#define CSR_TINFO 0x7a4 + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 machine mode CSRs =3D=3D=3D=3D= =3D=3D=3D=3D=3D */ +/* Configuration Registers */ +#define CSR_MICM_CFG 0xfc0 +#define CSR_MDCM_CFG 0xfc1 +#define CSR_MMSC_CFG 0xfc2 +#define CSR_MMSC_CFG2 0xfc3 +#define CSR_MVEC_CFG 0xfc7 + +/* Crash Debug CSRs */ +#define CSR_MCRASH_STATESAVE 0xfc8 +#define CSR_MSTATUS_CRASHSAVE 0xfc9 + +/* Memory CSRs */ +#define CSR_MILMB 0x7c0 +#define CSR_MDLMB 0x7c1 +#define CSR_MECC_CODE 0x7C2 +#define CSR_MNVEC 0x7c3 +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MCCTLBEGINADDR 0x7cb +#define CSR_MCCTLCOMMAND 0x7cc +#define CSR_MCCTLDATA 0x7cd +#define CSR_MPPIB 0x7f0 +#define CSR_MFIOB 0x7f1 + +/* Hardware Stack Protection & Recording */ +#define CSR_MHSP_CTL 0x7c6 +#define CSR_MSP_BOUND 0x7c7 +#define CSR_MSP_BASE 0x7c8 +#define CSR_MXSTATUS 0x7c4 +#define CSR_MDCAUSE 0x7c9 +#define CSR_MSLIDELEG 0x7d5 +#define CSR_MSAVESTATUS 0x7d6 +#define CSR_MSAVEEPC1 0x7d7 +#define CSR_MSAVECAUSE1 0x7d8 +#define CSR_MSAVEEPC2 0x7d9 +#define CSR_MSAVECAUSE2 0x7da +#define CSR_MSAVEDCAUSE1 0x7db +#define CSR_MSAVEDCAUSE2 0x7dc + +/* Control CSRs */ +#define CSR_MPFT_CTL 0x7c5 +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MCLK_CTL 0x7df + +/* Counter related CSRs */ +#define CSR_MCOUNTERWEN 0x7ce +#define CSR_MCOUNTERINTEN 0x7cf +#define CSR_MCOUNTERMASK_M 0x7d1 +#define CSR_MCOUNTERMASK_S 0x7d2 +#define CSR_MCOUNTERMASK_U 0x7d3 +#define CSR_MCOUNTEROVF 0x7d4 + +/* Enhanced CLIC CSRs */ +#define CSR_MIRQ_ENTRY 0x7ec +#define CSR_MINTSEL_JAL 0x7ed +#define CSR_PUSHMCAUSE 0x7ee +#define CSR_PUSHMEPC 0x7ef +#define CSR_PUSHMXSTATUS 0x7eb + +/* Andes Physical Memory Attribute(PMA) CSRs */ +#define CSR_PMACFG0 0xbc0 +#define CSR_PMACFG1 0xbc1 +#define CSR_PMACFG2 0xbc2 +#define CSR_PMACFG3 0xbc3 +#define CSR_PMAADDR0 0xbd0 +#define CSR_PMAADDR1 0xbd1 +#define CSR_PMAADDR2 0xbd2 +#define CSR_PMAADDR3 0xbd2 +#define CSR_PMAADDR4 0xbd4 +#define CSR_PMAADDR5 0xbd5 +#define CSR_PMAADDR6 0xbd6 +#define CSR_PMAADDR7 0xbd7 +#define CSR_PMAADDR8 0xbd8 +#define CSR_PMAADDR9 0xbd9 +#define CSR_PMAADDR10 0xbda +#define CSR_PMAADDR11 0xbdb +#define CSR_PMAADDR12 0xbdc +#define CSR_PMAADDR13 0xbdd +#define CSR_PMAADDR14 0xbde +#define CSR_PMAADDR15 0xbdf + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 supervisor mode CSRs =3D=3D=3D= =3D=3D=3D=3D=3D=3D */ +/* Supervisor trap registers */ +#define CSR_SLIE 0x9c4 +#define CSR_SLIP 0x9c5 +#define CSR_SDCAUSE 0x9c9 + +/* Supervisor counter registers */ +#define CSR_SCOUNTERINTEN 0x9cf +#define CSR_SCOUNTERMASK_M 0x9d1 +#define CSR_SCOUNTERMASK_S 0x9d2 +#define CSR_SCOUNTERMASK_U 0x9d3 +#define CSR_SCOUNTEROVF 0x9d4 +#define CSR_SCOUNTINHIBIT 0x9e0 +#define CSR_SHPMEVENT3 0x9e3 +#define CSR_SHPMEVENT4 0x9e4 +#define CSR_SHPMEVENT5 0x9e5 +#define CSR_SHPMEVENT6 0x9e6 + +/* Supervisor control registers */ +#define CSR_SCCTLDATA 0x9cd +#define CSR_SMISC_CTL 0x9d0 + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 user mode CSRs =3D=3D=3D=3D=3D= =3D=3D=3D=3D */ +/* User mode control registers */ +#define CSR_UITB 0x800 +#define CSR_UCODE 0x801 +#define CSR_UDCAUSE 0x809 +#define CSR_UCCTLBEGINADDR 0x80b +#define CSR_UCCTLCOMMAND 0x80c +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9eb1e3a..d1d4773 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -187,6 +187,12 @@ static void ax25_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + + #if defined(CONFIG_RISCV_CUSTOM) + /* setup custom csr handler hash table */ + setup_custom_csr(env, andes_custom_csr_table); + env->custom_csr_val =3D g_malloc(andes_custom_csr_size); + #endif } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -248,6 +254,12 @@ static void a25_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + + #if defined(CONFIG_RISCV_CUSTOM) + /* setup custom csr handler hash table */ + setup_custom_csr(env, andes_custom_csr_table); + env->custom_csr_val =3D g_malloc(andes_custom_csr_size); + #endif } #endif =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1c4dc94..9c16b88 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1421,7 +1421,7 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, = target_ulong *ret_value, } =20 #if defined(CONFIG_RISCV_CUSTOM) -/* Include the custom CSR table here. */ +#include "csr_andes.inc.c" #endif =20 /* Control and Status Register function table */ diff --git a/target/riscv/csr_andes.inc.c b/target/riscv/csr_andes.inc.c new file mode 100644 index 0000000..da226b0 --- /dev/null +++ b/target/riscv/csr_andes.inc.c @@ -0,0 +1,160 @@ +/* + * Andes custom CSR table and handling functions + * + * Copyright (c) 2021 Andes Technology Corp. + * SPDX-License-Identifier: GPL-2.0+ + */ + +static int write_uitb(CPURISCVState *env, int csrno, target_ulong val); +static int read_uitb(CPURISCVState *env, int csrno, target_ulong *val); + +struct andes_csr_val { + target_long uitb; +}; + +static int read_mmsc_cfg(CPURISCVState *env, int csrno, target_ulong *val) +{ + /* enable pma probe */ + *val =3D 0x40000000; + return 0; +} + +static int write_uitb(CPURISCVState *env, int csrno, target_ulong val) +{ + struct andes_csr_val *andes_csr =3D env->custom_csr_val; + andes_csr->uitb =3D val; + return 0; +} + +static int read_uitb(CPURISCVState *env, int csrno, target_ulong *val) +{ + struct andes_csr_val *andes_csr =3D env->custom_csr_val; + *val =3D andes_csr->uitb; + return 0; +} + + +int andes_custom_csr_size =3D sizeof(struct andes_csr_val); +riscv_custom_csr_operations andes_custom_csr_table[MAX_CUSTOM_CSR_NUM] =3D= { + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D AndeSt= ar V5 machine mode CSRs =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D */ + /* Configuration Registers */ + {CSR_MICM_CFG, { "micm_cfg", any, read_zero, write_st= ub} }, + {CSR_MDCM_CFG, { "mdcm_cfg", any, read_zero, write_st= ub} }, + {CSR_MMSC_CFG, { "mmsc_cfg", any, read_mmsc_cfg, writ= e_stub} }, + {CSR_MMSC_CFG2, { "mmsc_cfg2", any, read_zero, write_st= ub} }, + {CSR_MVEC_CFG, { "mvec_cfg", any, read_zero, write_st= ub} }, + + /* Crash Debug CSRs */ + {CSR_MCRASH_STATESAVE, { "mcrash_statesave", any, read_zero, write_s= tub} }, + {CSR_MSTATUS_CRASHSAVE, { "mstatus_crashsave", any, read_zero, write_s= tub} }, + + /* Memory CSRs */ + {CSR_MILMB, { "milmb", any, read_zero, write_st= ub} }, + {CSR_MDLMB, { "mdlmb", any, read_zero, write_st= ub} }, + {CSR_MECC_CODE, { "mecc_code", any, read_zero, write_st= ub} }, + {CSR_MNVEC, { "mnvec", any, read_zero, write_st= ub} }, + {CSR_MCACHE_CTL, { "mcache_ctl", any, read_zero, write_st= ub} }, + {CSR_MCCTLBEGINADDR, { "mcctlbeginaddr", any, read_zero, write_st= ub} }, + {CSR_MCCTLCOMMAND, { "mcctlcommand", any, read_zero, write_st= ub} }, + {CSR_MCCTLDATA, { "mcctldata", any, read_zero, write_st= ub} }, + {CSR_MPPIB, { "mppib", any, read_zero, write_st= ub} }, + {CSR_MFIOB, { "mfiob", any, read_zero, write_st= ub} }, + + /* Hardware Stack Protection & Recording */ + {CSR_MHSP_CTL, { "mhsp_ctl", any, read_zero, write_st= ub} }, + {CSR_MSP_BOUND, { "msp_bound", any, read_zero, write_st= ub} }, + {CSR_MSP_BASE, { "msp_base", any, read_zero, write_st= ub} }, + {CSR_MXSTATUS, { "mxstatus", any, read_zero, write_st= ub} }, + {CSR_MDCAUSE, { "mdcause", any, read_zero, write_st= ub} }, + {CSR_MSLIDELEG, { "mslideleg", any, read_zero, write_st= ub} }, + {CSR_MSAVESTATUS, { "msavestatus", any, read_zero, write_st= ub} }, + {CSR_MSAVEEPC1, { "msaveepc1", any, read_zero, write_st= ub} }, + {CSR_MSAVECAUSE1, { "msavecause1", any, read_zero, write_st= ub} }, + {CSR_MSAVEEPC2, { "msaveepc2", any, read_zero, write_st= ub} }, + {CSR_MSAVECAUSE2, { "msavecause2", any, read_zero, write_st= ub} }, + {CSR_MSAVEDCAUSE1, { "msavedcause1", any, read_zero, write_st= ub} }, + {CSR_MSAVEDCAUSE2, { "msavedcause2", any, read_zero, write_st= ub} }, + + /* Control CSRs */ + {CSR_MPFT_CTL, { "mpft_ctl", any, read_zero, write_st= ub} }, + {CSR_MMISC_CTL, { "mmisc_ctl", any, read_zero, write_st= ub} }, + {CSR_MCLK_CTL, { "mclk_ctl", any, read_zero, write_st= ub} }, + + /* Counter related CSRs */ + {CSR_MCOUNTERWEN, { "mcounterwen", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERINTEN, { "mcounterinten", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_M, { "mcountermask_m", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_S, { "mcountermask_s", any, read_zero, write_st= ub} }, + {CSR_MCOUNTERMASK_U, { "mcountermask_u", any, read_zero, write_st= ub} }, + {CSR_MCOUNTEROVF, { "mcounterovf", any, read_zero, write_st= ub} }, + + /* Enhanced CLIC CSRs */ + {CSR_MIRQ_ENTRY, { "mirq_entry", any, read_zero, write_st= ub} }, + {CSR_MINTSEL_JAL, { "mintsel_jal", any, read_zero, write_st= ub} }, + {CSR_PUSHMCAUSE, { "pushmcause", any, read_zero, write_st= ub} }, + {CSR_PUSHMEPC, { "pushmepc", any, read_zero, write_st= ub} }, + {CSR_PUSHMXSTATUS, { "pushmxstatus", any, read_zero, write_st= ub} }, + + /* Andes Physical Memory Attribute(PMA) CSRs */ + {CSR_PMACFG0, { "pmacfg0", any, read_zero, write_st= ub} }, + {CSR_PMACFG1, { "pmacfg1", any, read_zero, write_st= ub} }, + {CSR_PMACFG2, { "pmacfg2", any, read_zero, write_st= ub} }, + {CSR_PMACFG3, { "pmacfg3", any, read_zero, write_st= ub} }, + {CSR_PMAADDR0, { "pmaaddr0", any, read_zero, write_st= ub} }, + {CSR_PMAADDR1, { "pmaaddr1", any, read_zero, write_st= ub} }, + {CSR_PMAADDR2, { "pmaaddr2", any, read_zero, write_st= ub} }, + {CSR_PMAADDR3, { "pmaaddr3", any, read_zero, write_st= ub} }, + {CSR_PMAADDR4, { "pmaaddr4", any, read_zero, write_st= ub} }, + {CSR_PMAADDR5, { "pmaaddr5", any, read_zero, write_st= ub} }, + {CSR_PMAADDR6, { "pmaaddr6", any, read_zero, write_st= ub} }, + {CSR_PMAADDR7, { "pmaaddr7", any, read_zero, write_st= ub} }, + {CSR_PMAADDR8, { "pmaaddr8", any, read_zero, write_st= ub} }, + {CSR_PMAADDR9, { "pmaaddr9", any, read_zero, write_st= ub} }, + {CSR_PMAADDR10, { "pmaaddr10", any, read_zero, write_st= ub} }, + {CSR_PMAADDR11, { "pmaaddr11", any, read_zero, write_st= ub} }, + {CSR_PMAADDR12, { "pmaaddr12", any, read_zero, write_st= ub} }, + {CSR_PMAADDR13, { "pmaaddr13", any, read_zero, write_st= ub} }, + {CSR_PMAADDR14, { "pmaaddr14", any, read_zero, write_st= ub} }, + {CSR_PMAADDR15, { "pmaaddr15", any, read_zero, write_st= ub} }, + + /* Debug/Trace Registers (shared with Debug Mode) */ + {CSR_TSELECT, { "tselect", any, read_zero, write_st= ub} }, + {CSR_TDATA1, { "tdata1", any, read_zero, write_st= ub} }, + {CSR_TDATA2, { "tdata2", any, read_zero, write_st= ub} }, + {CSR_TDATA3, { "tdata3", any, read_zero, write_st= ub} }, + {CSR_TINFO, { "tinfo", any, read_zero, write_st= ub} }, + + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D AndeStar V5 = supervisor mode CSRs =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= */ + /* Supervisor trap registers */ + {CSR_SLIE, { "slie", any, read_zero, write_st= ub} }, + {CSR_SLIP, { "slip", any, read_zero, write_st= ub} }, + {CSR_SDCAUSE, { "sdcause", any, read_zero, write_st= ub} }, + + /* Supervisor counter registers */ + {CSR_SCOUNTERINTEN, { "scounterinten", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_M, { "scountermask_m", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_S, { "scountermask_s", any, read_zero, write_st= ub} }, + {CSR_SCOUNTERMASK_U, { "scountermask_u", any, read_zero, write_st= ub} }, + {CSR_SCOUNTEROVF, { "scounterovf", any, read_zero, write_st= ub} }, + {CSR_SCOUNTINHIBIT, { "scountinhibit", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT3, { "shpmevent3", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT4, { "shpmevent4", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT5, { "shpmevent5", any, read_zero, write_st= ub} }, + {CSR_SHPMEVENT6, { "shpmevent6", any, read_zero, write_st= ub} }, + + /* Supervisor control registers */ + {CSR_SCCTLDATA, { "scctldata", any, read_zero, write_st= ub} }, + {CSR_SMISC_CTL, { "smisc_ctl", any, read_zero, write_st= ub} }, + + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D And= eStar V5 user mode CSRs =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D */ + /* User mode control registers */ + {CSR_UITB, { "uitb", any, read_uitb, write_ui= tb} }, + {CSR_UCODE, { "ucode", any, read_zero, write_st= ub} }, + {CSR_UDCAUSE, { "udcause", any, read_zero, write_st= ub} }, + {CSR_UCCTLBEGINADDR, { "ucctlbeginaddr", any, read_zero, write_st= ub} }, + {CSR_UCCTLCOMMAND, { "ucctlcommand", any, read_zero, write_st= ub} }, + {CSR_WFE, { "wfe", any, read_zero, write_st= ub} }, + {CSR_SLEEPVALUE, { "sleepvalue", any, read_zero, write_st= ub} }, + {CSR_TXEVT, { "csr_txevt", any, read_zero, write_st= ub} }, + {0, { "", NULL, NULL, NULL } }, + }; diff --git a/target/riscv/custom_cpu_bits.h b/target/riscv/custom_cpu_bits.h index 5df31f8..ba67e95 100644 --- a/target/riscv/custom_cpu_bits.h +++ b/target/riscv/custom_cpu_bits.h @@ -5,4 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ =20 -/* This file is intentionally left blank at this commit. */ +/* + * XXX: Maybe we should add a "target-list"-like option to toggle enabled + * custom CSR variations ? + */ +#include "andes_cpu_bits.h" --=20 2.32.0