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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id ns18sm12091020pjb.31.2021.08.02.21.18.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/JPMIUFwv6h1D3td4UoRXmmsJ7EdKacS0CaAIsGRkeY=; b=P02tAJI0QrHTYrjebqZfWXpAu8ksgb3klJdoqNM27KPgXMTl3uTn0Dw5u0ncEPUEVo Xdxvn2/dAalGWKpPyu1CA51lsHLtr8S0BJODq5pxnPSNdMoeSDESVAnWX1kOWqC/T1tw Zo6Fm3y3CFITiQePA3+BQoNNe2o9DcfwldKolZQcCdKF2iR5Lom8LcjMxtXgl8W2WkUh HlmLJqXg6tPlpOuLOMwUzV35WXJUtxY7Xip06pNKqHV1J7XQgVSHhFubuQoJiN7+yPR6 6LeiC/kgwPFC5r+1l2g1gH05njTKYN/7VgQFp8bCtC7L8asx2LmL8ex10fL+qjXBy4kr itHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/JPMIUFwv6h1D3td4UoRXmmsJ7EdKacS0CaAIsGRkeY=; b=Qcc4eDdURVImd3u4cDjzWPFRiY1zxOEZmzEh1G647NxZpm6Obe6YBw0AZZrSv3ExqR KDderzgPyUBjXOxJJ8tPiDHxVu6kVgV9eLjWqhwknHV3JxSB6BaO4AhhgnTQova7/GpQ hVLKJpoYnlYbpUEXB7ZkBy6I00yUZMlhiWFIRKbxvZDxnvtVjFrkmHdoc9iHl8WoPHTm RkK3lI18upMs3LoQ+EJOgcKJ2hpAqUmheAAQ0cDGnFcXs9Bvkj9mSrVNzgGpUUOEC7Ew LgAr7Zbp+MPOGYvKAjW0LI6kI9RzUbcSH1UgQlCzfPf0OCuPSmBS6wptEx8Bt/FjyBg6 79VQ== X-Gm-Message-State: AOAM530ODeLjvjiKK1QWDJlwnwIM0s6JXVKNxl465lzMlQhf4C6kuird PfJy2m+6XPnfTM5LaVi1toMB3ihkf4lWsg== X-Google-Smtp-Source: ABdhPJwzHDhEniOpl6OAFWeX9dIosuMMPE9/dB4x2Sf5ls487MSXKEfFtsUQ2tEx9Zi0TTzCtYnQCQ== X-Received: by 2002:a17:90a:8d83:: with SMTP id d3mr2349214pjo.125.1627964329170; Mon, 02 Aug 2021 21:18:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 53/55] target/alpha: Implement prctl_unalign_sigbus Date: Mon, 2 Aug 2021 18:14:41 -1000 Message-Id: <20210803041443.55452-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210803041443.55452-1-richard.henderson@linaro.org> References: <20210803041443.55452-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1627965602913100001 Content-Type: text/plain; charset="utf-8" Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 +++++ hw/core/cpu-user.c | 2 +- linux-user/syscall.c | 2 +- target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 6eb3fcc63e..d9099ea188 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -387,6 +387,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) =20 +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; @@ -469,6 +471,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, *pc =3D env->pc; *cs_base =3D 0; *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } =20 #ifdef CONFIG_USER_ONLY diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index 23786865cb..daf8ff59b5 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -24,7 +24,7 @@ static Property cpu_useronly_props[] =3D { * up its memory. The default if no link is set up is to use the * system address space. */ -#if 0 +#if defined(TARGET_ALPHA) DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, prctl_unalign_sigbus, false), #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index b2e3c28b41..15080d0539 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6644,7 +6644,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, * We only implement PR_UNALIGN_SIGBUS, and only for those targets * who have had their translator updated to insert MO_ALIGN. */ -#if 0 +#if defined(TARGET_ALPHA) case PR_GET_UNALIGN: { CPUState *cs =3D env_cpu(env); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c14c1156a0..f6ba6a1a59 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; =20 +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *c= tx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv = addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCG= v addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } =20 static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int= rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |=3D UNALIGN(ctx); } =20 dest =3D ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv a= ddr) { TCGv tmp =3D tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } =20 @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv= addr) { TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } =20 static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } =20 static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, in= t rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |=3D UNALIGN(ctx); } =20 src =3D load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) =20 #ifdef CONFIG_USER_ONLY ctx->ir =3D cpu_std_ir; + ctx->unalign =3D (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN= ); #else ctx->palbr =3D env->palbr; ctx->ir =3D (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_i= r); --=20 2.25.1