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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id l2sm9043969wru.67.2021.08.01.16.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zv+GKBWChYiL7jtN3ifnlUeQ3KYEnUk/PWHE3YGCQS4=; b=Bh6iUcjzoCSV6h2bYmHzfuXS7lqOdz9zzT+Cbtyim4vG5aYpoLCvgaonTdamSGXEk2 36uXtPkLIL6bLwk0L55/LlxnzE27h9hEon3uVWec1OohfCOcN8q8qfKKJywGxKRas9sy SPFNR5Z6pJARIaPlJYpMk7bQ2EVxT5/DyqUJSg/KzF67pxsa923M4VEJjtBOt+Z5RMpv dPUCA3ufnvGKGVmIj5RLEMWA1JLxypxtx3VnjLUUWYqSVYh2oFVw6z2UYFDNsooB4p71 2A0NPH9/vAQXdTM2e05iBbTTM4s/Gj7lpp/kfFFsIk6QU6N+va36KTf5OQlxjgCRIXJq /ZZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zv+GKBWChYiL7jtN3ifnlUeQ3KYEnUk/PWHE3YGCQS4=; b=fdGSQwlH7lWL2asJlAbcDkKPhUDJhUY3bi1lyy2h48gRHXQQKo8ZOpkLGrNyQY5gpa 0DHICpxerolZ1hWdGka0jRNolEepTYskFu9jqhXWJxU4yNCiOBzefVKlApopJQLUIQGc /mu/JW7nx+AifjKGJaIp6UWxObgmQU/smmFC79vF8brpFXn7GTLjwcUJ8LeCozwAreiP FLhU4P9YEBHgsWvUzg9B+MOwL/GGxMgM7H+Rl6x0CJcaLoDSg6Vj1TmXb0Xu73fBamuw ERe5p2XLu9M7SDhnqSrIL8WuEjJLSYoUkswIUsh0RqxlELnz6FW04dP/HQKcpUf5EFxl b98Q== X-Gm-Message-State: AOAM5311Fk7rMLuvjZG/BPvVqiYhwXYDupFtuNS2B3razvT5oSiC45O/ svKt9RDO9d5rBdMKwyBNs3o= X-Google-Smtp-Source: ABdhPJyYqXQW+cWmEVAfwRVJP83VmQrlvXxp0tkpQMN38aMoj2cUxfgEpKDPu+lHm3D115C7NHzSFw== X-Received: by 2002:adf:ea41:: with SMTP id j1mr14666025wrn.147.1627862373522; Sun, 01 Aug 2021 16:59:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson Subject: [PATCH-for-6.2 1/5] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c Date: Mon, 2 Aug 2021 01:59:22 +0200 Message-Id: <20210801235926.3178085-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801235926.3178085-1-f4bug@amsat.org> References: <20210801235926.3178085-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627862376954100001 Extract NEC Vr54xx helpers from op_helper.c to a new file: 'vr54xx_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-14-f4bug@amsat.org> --- target/mips/tcg/op_helper.c | 118 -------------------------- target/mips/tcg/vr54xx_helper.c | 142 ++++++++++++++++++++++++++++++++ target/mips/tcg/meson.build | 1 + 3 files changed, 143 insertions(+), 118 deletions(-) create mode 100644 target/mips/tcg/vr54xx_helper.c diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index fafbf1faca7..ef3dafcbb3f 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -26,124 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO(CPUMIPSState *env) -{ - return ((uint64_t)(env->active_tc.HI[0]) << 32) | - (uint32_t)env->active_tc.LO[0]; -} - -static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) -{ - env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFFFFF); - return env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); -} - -static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) -{ - target_ulong tmp =3D env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFF= FFF); - env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); - return tmp; -} - -/* Multiplication variants of the vr54xx. */ -target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2)); -} - -target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2= ); -} - -target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg= 2); -} - -target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - static inline target_ulong bitswap(target_ulong v) { v =3D ((v >> 1) & (target_ulong)0x5555555555555555ULL) | diff --git a/target/mips/tcg/vr54xx_helper.c b/target/mips/tcg/vr54xx_helpe= r.c new file mode 100644 index 00000000000..2255bd11163 --- /dev/null +++ b/target/mips/tcg/vr54xx_helper.c @@ -0,0 +1,142 @@ +/* + * MIPS VR5432 emulation helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO(CPUMIPSState *env) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; +} + +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) +{ + env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFFFFF); + return env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); +} + +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) +{ + target_ulong tmp =3D env->active_tc.LO[0] =3D (int32_t)(HILO & 0xFFFFF= FFF); + env->active_tc.HI[0] =3D (int32_t)(HILO >> 32); + return tmp; +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); +} + +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg= 1 * + (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)= arg1 * + (uint64_t)(uint32_t)= arg2); +} + +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg= 2); +} + +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index bf4001e5741..68eb284e099 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -19,6 +19,7 @@ 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', + 'vr54xx_helper.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', --=20 2.31.1 From nobody Fri May 17 09:01:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id f26sm9249423wrd.41.2021.08.01.16.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=StzvGMLMsgqPmTgAHMYz+S6poTEEwTkgQFoR1NPgVPo=; b=tpYuqU7ULMhKJXymVktl4eeLz39gZN5KbXfYL6BM8AKi1rzi2Atn7iTbUHXxEPkJVp Dco/xvctgWLneB22YkOUeP26Cnocng3QXo9/YpQG7kV1cJx4hD3WhXfR/MzS2ssiZV7v qmp0trqshTP2EKAZLtuLWS+s70HisfiG9P0n9TYR6jqsH7VC16Uxs+LJXZDyem/crhrf WJl3g/KfWY94W6MsTZvR9FGRIJ8B6CC8Xu88makD2ankr486VsO8BHGb0mSMJDS7PFsF 3SVkHJEGFgvU4WIFhiafGMai9SgMOnV2E0K0pT/HvZNU6y8io+rCZBPuI0LI2r4DY++w MktQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=StzvGMLMsgqPmTgAHMYz+S6poTEEwTkgQFoR1NPgVPo=; b=hvF4oJAQpKOPq6wtQndPHST9wpfCgcEvSP+otr/+XxcQcu/8KjgYwszH9LKGCwJkF1 AbTQK08bo1oERHnc6/tz9vpCZ9d/YTzops+EhOYuGSHldv3Bj9CLEU7DCnJOt0YK+u/a u2QZ3zJ4nuKlJvdcb2h/sbp6WZuheBGpd8GzGDiGjDhtbduVNsvt6NwsqoQ+f50fPfim Z7wqpWa5fDOMGz4KXLOozjRmnTtncbPZ5j4eBdYFJD0YhhjzmfY7H/l3CRwf/GRlo4dX 2X70lqQOjbcYDEIUDOsoQt+nI+tRU6lWeaoMwYw8zFBeySHndcN+DIUVN3olzZcMZcIX 8cjA== X-Gm-Message-State: AOAM532N9eusyQKgBSk5Wi9GpSphVCEpovnFgWamw3aSfl4niuLn0T5S yMVUqWcfDTMAjPiWzGtOjLA= X-Google-Smtp-Source: ABdhPJxliFQ5C+u6XOw8fWfQofvit45wu7tofeeO30t6iBGOxhlaC3UUpgMAMc9CBvF2AsQO3QfakA== X-Received: by 2002:adf:c3c5:: with SMTP id d5mr14764331wrg.76.1627862377969; Sun, 01 Aug 2021 16:59:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH-for-6.2 2/5] target/mips: Introduce decodetree structure for NEC Vr54xx extension Date: Mon, 2 Aug 2021 01:59:23 +0200 Message-Id: <20210801235926.3178085-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801235926.3178085-1-f4bug@amsat.org> References: <20210801235926.3178085-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627862381105100001 The decoder is called but doesn't decode anything. This will ease reviewing the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 1 + target/mips/tcg/vr54xx.decode | 8 ++++++++ target/mips/tcg/translate.c | 3 +++ target/mips/tcg/vr54xx_translate.c | 19 +++++++++++++++++++ target/mips/tcg/meson.build | 2 ++ 5 files changed, 33 insertions(+) create mode 100644 target/mips/tcg/vr54xx.decode create mode 100644 target/mips/tcg/vr54xx_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c25fad597d5..d82c78c9bdc 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -201,5 +201,6 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); #endif +bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); =20 #endif diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode new file mode 100644 index 00000000000..f6b3e42c999 --- /dev/null +++ b/target/mips/tcg/vr54xx.decode @@ -0,0 +1,8 @@ +# MIPS VR5432 instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VR5432 Microprocessor User=E2=80=99s Manual +# (Document Number U13751EU5V0UM00) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 34a96159d15..98dfcf5afd1 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16109,6 +16109,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { return; } + if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->= opcode)) { + return; + } =20 if (decode_opc_legacy(env, ctx)) { return; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c new file mode 100644 index 00000000000..13e58fdd8df --- /dev/null +++ b/target/mips/tcg/vr54xx_translate.c @@ -0,0 +1,19 @@ +/* + * VR5432 extensions translation routines + * + * Reference: VR5432 Microprocessor User=E2=80=99s Manual + * (Document Number U13751EU5V0UM00) + * + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "internal.h" + +/* Include the auto-generated decoder. */ +#include "decode-vr54xx.c.inc" diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 68eb284e099..259663a8893 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -3,6 +3,7 @@ decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), decodetree.process('msa.decode', extra_args: '--decode=3Ddecode_ase_msa'= ), decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), + decodetree.process('vr54xx.decode', extra_args: '--decode=3Ddecode_ext_v= r54xx'), ] =20 mips_ss.add(gen) @@ -20,6 +21,7 @@ 'translate_addr_const.c', 'txx9_translate.c', 'vr54xx_helper.c', + 'vr54xx_translate.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', --=20 2.31.1 From nobody Fri May 17 09:01:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1627862384; cv=none; d=zohomail.com; s=zohoarc; b=DnS1tRohC+4fm2l/FWW77s+309qiPTIjusQhK4EsKzgDc0xVMx9i2TPZ/iMtlfqLY9zdo/X8a6z2u7nz1Jh5qTnJ6hTcA+z3QyJ1l5485tem3jXKx8EP6wLp/xkwJMRFCEhiMevBQQkzlzptI8joQpRjuhupL7WvzfrZY15Y9HQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627862384; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ygTviteO4ICr+Dt5AxHx9smElVVVjf1jYJCNvq3bytw=; b=CdA2TF8B7Yp7o8/eVrxeWin3mSuID3UCNK9JFiiX1su/+ZEr4UoI7KraQ/ZQ4wncX8e/xnEqcEnNNblu3Lzu1OWvSsuTVmCcF48aV+kakErZdk7AJC7+WhzbU9EfyCyNwrJRn2N0QogVpZ4bvOyh+PFtQZzCHybw8ZBrBm3pMeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1627862384198656.3714013814533; Sun, 1 Aug 2021 16:59:44 -0700 (PDT) Received: by mail-wr1-f46.google.com with SMTP id b13so8467380wrs.3 for ; Sun, 01 Aug 2021 16:59:43 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id u11sm9647414wrt.89.2021.08.01.16.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygTviteO4ICr+Dt5AxHx9smElVVVjf1jYJCNvq3bytw=; b=PipBSvp9aZ87XDb0yLykTwnPrk78rZzJHZ6+T2bDEvRM+RbNENTm/fiLKoLfPPaim5 BS0vfP3rNiZncbKVqKQDQuY7VZWFqx07DWLbAKVb3ng2WzgLJ9/Xs8l1Ae2NEtDIbpaN WlPhzLpNqKQrJ9x5LB24wpTvjrRN4BG4UZLwTdEFPXAMXAmxUMqRo4u8ojTTS1RIsBgV RqgY+93c4/6cFThoPRG+pr23FGWwcq99Mptijzhwnc2f7ugjYkIc/ECyMe628mybVbxc szKdjvdILAL30aXE1vZpwmks+eFaJTklvUsetyrfDeLT8LgbcYElHIzGGZKTwKZmwIob Cpuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ygTviteO4ICr+Dt5AxHx9smElVVVjf1jYJCNvq3bytw=; b=ScA8DY/coPEIvbWjgtBWGeCx00YcS2NXElFoaHvn64eJc9Siz02NacwNgDn6//FzdU AY2lSmsJoCLfNmEKrUyVQiV+1vEfqY5zvxDMfUdaW+8BpKMuguafvLlsrleyqY54SKrm B0+X9Ha24sbg2nWh3FZZ61wzVPiUe+gAc7bkCs5/Xydo6Pnjup7M53ZWEIq3H2s7fvhv HmzFdjmjduoFQRyvlcI8FkM3bgyAGDhJMX/+ur+TRz3XbF/1FEFwfbPKcJDeTiMrOtp7 5BdtQHyJfyqzcUOL7mJP3RDGSy80nGMyoXV7ZlKUBQmPu3bUPdvRZuCzEDRXLXoxUIEv p6Lg== X-Gm-Message-State: AOAM530tCCPyfI9ZaEDPXuwYV+7lqjBiRAjLwbg+60Pim5Piu2r9dUp1 8HD/LsklowjkBnVZJDCK2vk= X-Google-Smtp-Source: ABdhPJzwghYsWLAQxqrLnerG9aZf8/xK3Ha068VBmZKl7nUYXzLp/dO+HI8FyIe+sck/whpj7mIt7Q== X-Received: by 2002:a5d:5147:: with SMTP id u7mr14611186wrt.181.1627862382412; Sun, 01 Aug 2021 16:59:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH-for-6.2 3/5] target/mips: Convert Vr54xx MACC* opcodes to decodetree Date: Mon, 2 Aug 2021 01:59:24 +0200 Message-Id: <20210801235926.3178085-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801235926.3178085-1-f4bug@amsat.org> References: <20210801235926.3178085-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627862385157100001 Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/vr54xx.decode | 9 +++++++ target/mips/tcg/translate.c | 16 ------------ target/mips/tcg/vr54xx_translate.c | 40 ++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index f6b3e42c999..73778f101a5 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -6,3 +6,12 @@ # # Reference: VR5432 Microprocessor User=E2=80=99s Manual # (Document Number U13751EU5V0UM00) + +&r rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r + +MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd +MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd +MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 98dfcf5afd1..8d29a0d4e4b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -300,16 +300,12 @@ enum { enum { OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, }; @@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; @@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32= _t opc, case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 13e58fdd8df..85e2ec371b9 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -17,3 +17,43 @@ =20 /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" + +/* + * Integer Multiply-Accumulate Instructions + * + * MACC Multiply, accumulate, and move LO + * MACCHI Multiply, accumulate, and move HI + * MACCHIU Unsigned multiply, accumulate, and move HI + * MACCU Unsigned multiply, accumulate, and move LO + */ + +typedef void gen_helper_mult_acc_t(TCGv, TCGv_ptr, TCGv, TCGv); + +static bool trans_mult_acc(DisasContext *ctx, arg_r *a, + gen_helper_mult_acc_t *gen_helper_mult_acc) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + gen_helper_mult_acc(t0, cpu_env, t0, t1); + + gen_store_gpr(t0, a->rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return false; +} + +#define MULT_ACC(opcode, gen_helper) \ +static bool trans_##opcode(DisasContext *ctx, arg_r *a) \ +{ \ + return trans_mult_acc(ctx, a, gen_helper); \ +} +MULT_ACC(MACC, gen_helper_macc); +MULT_ACC(MACCHI, gen_helper_macchi); +MULT_ACC(MACCHIU, gen_helper_macchiu); +MULT_ACC(MACCU, gen_helper_maccu); --=20 2.31.1 From nobody Fri May 17 09:01:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627862389293100001 Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/vr54xx.decode | 6 ++++++ target/mips/tcg/translate.c | 24 ------------------------ target/mips/tcg/vr54xx_translate.c | 12 ++++++++++++ 3 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 73778f101a5..79bb5175eab 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -11,7 +11,13 @@ =20 @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r =20 +MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd +MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd +MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd +MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd +MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8d29a0d4e4b..4196319d827 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -298,14 +298,8 @@ enum { #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) =20 enum { - OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, - OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, - OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, - OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, - OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, }; @@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint3= 2_t opc, gen_load_gpr(t1, rt); =20 switch (opc) { - case OPC_VR54XX_MULS: - gen_helper_muls(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; case OPC_VR54XX_MSACU: gen_helper_msacu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 85e2ec371b9..1e6000d3d15 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,12 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MULHI Multiply and move HI + * MULHIU Unsigned multiply and move HI + * MULS Multiply, negate, and move LO + * MULSHI Multiply, negate, and move HI + * MULSHIU Unsigned multiply, negate, and move HI + * MULSU Unsigned multiply, negate, and move LO */ =20 typedef void gen_helper_mult_acc_t(TCGv, TCGv_ptr, TCGv, TCGv); @@ -57,3 +63,9 @@ MULT_ACC(MACC, gen_helper_macc); MULT_ACC(MACCHI, gen_helper_macchi); MULT_ACC(MACCHIU, gen_helper_macchiu); MULT_ACC(MACCU, gen_helper_maccu); +MULT_ACC(MULHI, gen_helper_mulhi); +MULT_ACC(MULHIU, gen_helper_mulhiu); +MULT_ACC(MULS, gen_helper_muls); +MULT_ACC(MULSHI, gen_helper_mulshi); +MULT_ACC(MULSHIU, gen_helper_mulshiu); +MULT_ACC(MULSU, gen_helper_mulsu); --=20 2.31.1 From nobody Fri May 17 09:01:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1627862393; cv=none; d=zohomail.com; s=zohoarc; b=grRxzil+tgtCQyE+xuIuoiEDSZLC4vqcOMsyfGWDsYhMrognlRsAKNtzRravIyYa9K73HxniqxFNbngJgAZUVnUmwsbZGQiddUK8IYioe0Q9pj4CdyMdAVE5g16e1p6Qv5Rsb2Ge0LWSeSZK+ZGYi//zcNTNVzCnj6F226RCRQ8= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627862395720100001 Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/vr54xx.decode | 4 +++ target/mips/tcg/translate.c | 55 ++---------------------------- target/mips/tcg/vr54xx_translate.c | 8 +++++ 3 files changed, 14 insertions(+), 53 deletions(-) diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 79bb5175eab..4fc708d80ae 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -15,9 +15,13 @@ MULS 000000 ..... ..... ..... 00011011000 = @rs_rt_rd MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd +MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd +MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd +MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4196319d827..bdce6356c27 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -294,16 +294,6 @@ enum { R6_OPC_SDBBP =3D 0x0e | OPC_SPECIAL, }; =20 -/* Multiplication variants of the vr54xx. */ -#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) - -enum { - OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, - OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, - OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, -}; - /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16= ))) =20 @@ -3754,40 +3744,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t= opc, tcg_temp_free(t1); } =20 -static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_VR54XX_MSAC: - gen_helper_msac(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, cpu_env, t0, t1); - break; - default: - MIPS_INVAL("mul vr54xx"); - gen_reserved_instruction(ctx); - goto out; - } - gen_store_gpr(t0, rd); - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_cl(DisasContext *ctx, uint32_t opc, int rd, int rs) { @@ -14104,13 +14060,12 @@ static void decode_opc_special_tx79(CPUMIPSState = *env, DisasContext *ctx) =20 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) { - int rs, rt, rd, sa; + int rs, rt, rd; uint32_t op1; =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; rd =3D (ctx->opcode >> 11) & 0x1f; - sa =3D (ctx->opcode >> 6) & 0x1f; =20 op1 =3D MASK_SPECIAL(ctx->opcode); switch (op1) { @@ -14139,13 +14094,7 @@ static void decode_opc_special_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_MULT: case OPC_MULTU: - if (sa) { - check_insn(ctx, INSN_VR54XX); - op1 =3D MASK_MUL_VR54XX(ctx->opcode); - gen_mul_vr54xx(ctx, op1, rd, rs, rt); - } else { - gen_muldiv(ctx, op1, rd & 3, rs, rt); - } + gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_DIV: case OPC_DIVU: diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 1e6000d3d15..6661bf39eee 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,10 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MSAC Multiply, negate, accumulate, and move LO + * MSACHI Multiply, negate, accumulate, and move HI + * MSACHIU Unsigned multiply, negate, accumulate, and move HI + * MSACU Unsigned multiply, negate, accumulate, and move LO * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO @@ -63,6 +67,10 @@ MULT_ACC(MACC, gen_helper_macc); MULT_ACC(MACCHI, gen_helper_macchi); MULT_ACC(MACCHIU, gen_helper_macchiu); MULT_ACC(MACCU, gen_helper_maccu); +MULT_ACC(MSAC, gen_helper_msac); +MULT_ACC(MSACHI, gen_helper_msachi); +MULT_ACC(MSACHIU, gen_helper_msachiu); +MULT_ACC(MSACU, gen_helper_msacu); MULT_ACC(MULHI, gen_helper_mulhi); MULT_ACC(MULHIU, gen_helper_mulhiu); MULT_ACC(MULS, gen_helper_muls); --=20 2.31.1